Arithmetic circuit, memory system, and control method

Abstract

To execute a plurality of times of multiplication of a Galois field at a higher speed.SOLUTION: The arithmetic circuit executes a first operation corresponding to p multiplications executed in series, each of the p multiplications being represented by p (p is an integer of 2 or more) third order tensors that input two elements of a Galois field and output one element that is a multiplication result of the two elements, by an AND operation that calculates an AND value of a plurality of elements used in the p multiplications, and an XOR operation based on the AND value and a contraction tensor obtained by contracting a 3p tensor obtained by a direct product of the p third order tensors.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an arithmetic circuit, a memory system, and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded.

[0003] In technology related to error correcting codes, multiplication in a Galois field (finite field) may be performed. For example, in decoding a BCH (Bose-Chaudhuri-Hocquenghem) code, which is an example of an error correcting code, a syndrome is calculated from a received word (read sequence) read from a memory, and the coefficients of an error locator polynomial are calculated from the syndrome. The syndrome is an element of a Galois field. Therefore, when calculating the coefficients of the error locator polynomial, multiplication of the syndrome, i.e., Galois field multiplication, may be performed. Furthermore, when calculating the coefficients of the error locator polynomial, multiple Galois field multiplications may be performed, which may increase the calculation time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2024-080211 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the embodiments of the present invention is to provide an arithmetic circuit that can execute multiple Galois field multiplications at higher speed. [Means for solving the problem]

[0006] The arithmetic circuit of the embodiment is represented by p (p is an integer greater than or equal to 2) third-order tensors that input two elements of a Galois field and output one element that is the multiplication result of the two elements, and performs a first operation corresponding to p multiplications performed in series by an AND operation that calculates AND values ​​of the multiple elements used in the p multiplications, and an XOR operation based on the AND value and a contracted tensor obtained by contracting a 3p-order tensor obtained by the Cartesian product of the p third-order tensors. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram of a decoding unit according to the embodiment. [Figure 3] FIG. 1 is a diagram showing an overview of the procedure for calculating syndromes and error locator polynomials. [Figure 4] FIG. 10 is a diagram showing an example of the relationship between a syndrome and an error locator polynomial. [Figure 5] A diagram showing an example of a vector representation of an element of a Galois field GF(24). [Figure 6] FIG. 10 is a diagram illustrating an example of a companion matrix. [Figure 7] FIG. 10 is a diagram showing an example of how to obtain a tensor Ti. [Figure 8] FIG. 10 is a diagram showing a specific example of how to calculate tensor T0. [Figure 9] A diagram showing an example of how to calculate the tensor S(1). [Figure 10] A diagram showing a specific example of how to calculate the tensor S(1). [Figure 11] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 12] FIG. 12 is a diagram showing an example of the configuration of a circuit that embodies the arithmetic unit of FIG. 11. [Figure 13] A diagram of a matrix in which six tensors are represented as one-dimensional vectors. [Figure 14] A diagram showing an example of a diagrammatic representation of a tensor. [Figure 15]FIG. 10 shows an example of a diagrammatic representation of a Cartesian product. [Figure 16] A diagram showing an example of diagrammatic notation equivalent to contraction. [Figure 17] A diagram showing an example of diagrammatic notation equivalent to contraction. [Figure 18] FIG. 10 is a diagram showing the relationship between a calculation unit of a comparative example and a calculation unit of the embodiment. [Figure 19] FIG. 2 is a diagram showing an example of the configuration of a circuit that embodies a calculation unit. [Figure 20] FIG. 10 is a diagram showing an example of a flattening matrix. [Figure 21] FIG. 10 is a diagram for explaining an example of the number of stages to be reduced. [Figure 22] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 23] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 24] FIG. 2 is a diagram showing an example of a calculation unit. [Figure 25] FIG. 10 is a diagram showing an example of the configuration of a calculation unit that calculates an inverse element. [Figure 26] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 27] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 28] FIG. 2 is a diagram showing an example of the configuration of a calculation unit. [Figure 29] 10 is a flowchart showing an example of a decoding process. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the arithmetic circuit according to the present invention will be described in detail below with reference to the accompanying drawings. The following description will be given taking as an example a memory system including an arithmetic circuit that performs Galois field multiplication when decoding error-correcting codes. The configuration using the arithmetic circuit is not limited to this example, and may be any system (device, instrument). For example, the arithmetic circuit described below can be applied to a memory system that performs Galois field multiplication when calculating error locations, and a system that performs Galois field multiplication during cryptographic processing.

[0009] First, a memory system according to this embodiment will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration example of a memory system according to this embodiment. As shown in FIG. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and FIG. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND flash memory (hereinafter simply referred to as a NAND memory). In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistive Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0011] The memory system 1 may be any of various memory systems equipped with a nonvolatile memory 20, such as a so-called SSD (Solid State Drive) or a memory card in which a memory controller 10 and a nonvolatile memory 20 are configured as a single package.

[0012] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 is a semiconductor integrated circuit configured as, for example, an SoC (System On a Chip). The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected via an internal bus 16. Some or all of the operations of the components of the memory controller 10 described below may be implemented by a CPU (Central Processing Unit) executing firmware, or by hardware.

[0013] The host I / F 15 is a circuit that performs processing in accordance with the interface standard with the host 30 and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data that has been read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0014] The memory I / F 13 is a circuit that performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0015] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0016] Furthermore, when the control unit 11 receives a write request from the host 30, it determines a storage area (memory area) on the nonvolatile memory 20 for the user data stored in the data buffer 12. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0017] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0018] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. When the memory cells are single-level cells (SLC: Single Level Cell), one memory cell group corresponds to one page. When the memory cells are multi-level cells (MLC: Multiple Level Cell), one memory cell group corresponds to multiple pages. In this description, MLC includes triple-level cells (TLC) and quad-level cells (QLC). Each memory cell is connected to a word line and also to a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0019] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). The data buffer 12 may not be built into the memory controller 10 but may be mounted outside the memory controller 10.

[0020] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data stored in the nonvolatile memory 20 to generate code words. The encoding / decoding unit 14 also decodes received words read from the nonvolatile memory 20 to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoding unit (Encoder) 17 and a decoding unit (Decoder) 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0021] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoding unit 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the code word in the nonvolatile memory 20, and also instructs the memory I / F 13 of the determined storage location.

[0022] The encoding unit 17 generates code words by encoding user data stored in the data buffer 12 based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 instructed by the control unit 11. The following describes an example in which a BCH code that corrects errors of t bits or less (t is an integer equal to or greater than 2) is used.

[0023] Next, a description will be given of the processing performed when reading from the nonvolatile memory 20 in this embodiment. When reading from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoding unit 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads the received word from the specified address in the nonvolatile memory 20 and inputs the read received word to the decoding unit 18. The decoding unit 18 decodes the received word read from the nonvolatile memory 20.

[0024] The decoding unit 18 decodes the received word read from the nonvolatile memory 20. The decoding unit 18 calculates the error locator polynomial using, for example, the Peterson-Gorenstein-Zierler (PGZ) method. The PGZ method is a method of solving simultaneous equations that hold between the coefficients σ of the error locator polynomial and the syndromes by matrix calculation.

[0025] 2 is a block diagram showing an example of the configuration of the decoding unit 18 according to this embodiment. As shown in FIG. 2, the decoding unit 18 includes a syndrome calculation unit 101, an error position polynomial calculation unit 102, an error position calculation unit 103, and a bit flip unit 104.

[0026] The syndrome calculation unit 101 calculates a syndrome using the received word (read sequence) read from the non-volatile memory 20. The syndrome calculation unit 101 may calculate the syndrome using any conventional method. If all the syndrome values ​​are 0, it can be determined that there is no error in the received word, and the decoding unit 18 can terminate the decoding process without performing any further processing.

[0027] The error locator polynomial calculation unit 102 calculates an error locator polynomial by the PGZ algorithm using the syndromes. Some of the coefficients of the error locator polynomial are calculated by adding and multiplying the syndromes.

[0028] 3 is a diagram showing an outline of the procedure for calculating the syndrome and error locator polynomial in the case of a BCH code. A read sequence r0, r1, r2, . . . , r n-1 are read as received words. The syndrome calculation unit 101 inputs these received words and calculates syndromes S1, S3, . . . , S 2t-1 The error location polynomial calculation unit 102 calculates the coefficients σ0, σ1, . . . , σ of the t-th order error location polynomial from the syndrome. t-1 ,σ t As shown in FIG. 3, the syndrome and the coefficient σ calculated using the syndrome are elements of the Galois field.

[0029] Fig. 4 is a diagram showing an example of the relationship between syndromes and error locator polynomials. Fig. 4 shows examples of first- to fourth-order error locator polynomials (first- to fourth-order polynomials) when using a BCH code that corrects errors of 4 bits (t=4) or less. |M2|, |M3|, |M4|, and |M5| included in any of the second- to fourth-order polynomials are calculated using the equations shown at the bottom of Fig. 4.

[0030] The first- to fourth-order polynomials are equations for calculating error locations when the number of errors is 1 to 4, respectively. In the example of Fig. 4, the number of multipliers required to calculate the coefficients of each of the first- to fourth-order polynomials is, for example, 0, 1, 5, and 21, excluding squares that can be realized by simple calculations as explained in Fig. 9 and Fig. 10. In this way, as the number of bits t that can be corrected for errors increases, the number of multipliers for calculating the coefficients of the error locator polynomials increases.

[0031] Therefore, a technique has been proposed that uses an arithmetic circuit optimized to enable common calculation of at least some of the multiplications of syndromes used to calculate the coefficients of the error locator polynomial (for example, Patent Document 1). This makes it possible to suppress an increase in the circuit scale for performing Galois field multiplication. This technique is a technique for commonly calculating one multiplication that is included in multiple types of multiplication. For example, in the case of four multiplications, S1 2 S3, S1S3, S14 S3, S1S3 2 The arithmetic circuit is configured so that the multiplication S1 and S3 included in common are calculated in common.

[0032] On the other hand, the calculation of the coefficients of the error locator polynomial may include multiple multiplications executed in series (hereinafter referred to as multiple-stage multiplications). Multiple multiplications executed in series are, for example, multiplications in which the output of one multiplication included in the multiple multiplications becomes the input of another multiplication. In FIG. 4, multiplications 301 to 308 correspond to operations that can be interpreted as including multiple stages of multiplications. For example, multiplication 301 is a multiplication of S1 5 S3 = S1 × S1 4 This can be interpreted as a calculation that includes two multiplication stages, such as ×S3. As the number of multiplication stages increases, the calculation time may increase. For this reason, it is desirable to calculate multi-stage multiplications more efficiently.

[0033] Therefore, the arithmetic unit 110 of this embodiment is configured to efficiently calculate arithmetic operations including multi-stage multiplication. The following mainly describes an example in which the arithmetic unit 110 is configured to calculate multiplication 304, which is the seventh power of syndrome S1. The arithmetic unit 110 may be configured to calculate other multiplications (e.g., any of multiplications 301 to 303, or 305 to 308), or may be configured to calculate two or more multiplications (e.g., two or more of multiplications 301 to 308).

[0034] Returning to Fig. 2, the arithmetic unit 110 (an example of an arithmetic circuit) will be further described. As shown in Fig. 2, the error locator polynomial calculation unit 102 includes an arithmetic unit 110 that performs arithmetic on elements of the Galois field, including multiplication of elements of the Galois field. The arithmetic unit 110 also includes an AND calculation unit 111 and an XOR calculation unit 112.

[0035] The AND calculation unit 111 performs an AND operation for multiplying elements of the Galois field. The XOR calculation unit 112 performs an XOR operation for multiplying elements of the Galois field. The AND calculation unit 111 and the XOR calculation unit 112 will be described in detail later.

[0036] The calculation unit 110 is a component that executes at least a part of the multiplication of syndromes required to calculate the coefficients of the error locator polynomial. The multiplication of syndromes that is not executed by the calculation unit 110 is calculated, for example, by the error locator polynomial calculation unit 102. In this case, the error locator polynomial calculation unit 102 may calculate the coefficients (including the multiplication of syndromes) by any conventionally used method.

[0037] The error position calculation unit 103 calculates an error position using the error position polynomial calculated by the error position polynomial calculation unit 102. The process of calculating the error position (searching process) may be realized by any method, but for example, Chien search can be used. Chien search is a method of sequentially substituting values ​​into the error position polynomial and searching for the error position based on the value that makes the output value of the error position polynomial zero.

[0038] The bit flip unit 104 performs error correction by flipping (bit flipping) the bit at the error position calculated by the search process.

[0039] Next, the details of the calculation unit 110 (AND calculation unit 111, XOR calculation unit 112) will be described. The calculation unit 110 is configured, for example, by the following procedure. (P1) Number of elements in the Galois field: 2 m and a primitive polynomial p(x) of degree m are determined. Note that an irreducible polynomial may be used instead of the primitive polynomial. (P2) Find the companion matrix corresponding to the primitive polynomial p(x). (P3) Using a companion matrix, multiple tensors are found to be used in the multiplication of Galois field elements. When a Galois field element is expressed as an m-dimensional vector, the element that is the output of multiplying two elements is also expressed as an m-dimensional vector. A tensor is found for each component of the output element expressed as an m-dimensional vector. In other words, a total of m tensors are found, which are functions that take two vectors as input and output one value (one component of the vector). Below, the tensor defined for the ith component of an m-dimensional vector (i is an integer that satisfies 0≦i≦m-1) is called T iThe tensor T is expressed as i is sometimes called a second-order tensor because it has two input vectors, and a set of m second-order tensors is sometimes called a third-order tensor because they are characterized by three indices. (P4) Galois field element 2 u Calculates the second-order tensor S(u) representing the power of (u is an integer greater than or equal to 1). (P5) For operations including multiple multiplications to be performed by the calculation unit 110, multiple XOR operations separated by AND operations are rewritten into a single XOR operation. Specifically, the operation by the calculation unit 110 is expressed by an AND operation of an m-dimensional vector and an XOR operation expressed by a tensor obtained by the direct product and contraction. (P6) Configure the calculation unit 110 to perform an XOR calculation according to the tensor.

[0040] Each of the above steps will now be further explained.

[0041] Regarding (P1), we will explain the definition of a Galois field. A Galois field is determined by m∈{1,2,3...}, which defines the number of elements, and a primitive polynomial p(x) of degree m. A Galois field has the following characteristics: One zero element 0 and (2 m -1) non-zero elements, and a total of 2 m It has individual elements. · Any non-zero element can be expressed by raising the primitive element α, which is the root of the primitive polynomial p(x), as shown in the following equation (1).

number

[0042] Code length n=2 m -1 (m is an integer greater than or equal to 2) BCH code, for example, m Galois field GF(2 m ) is used. m ) can be represented by an m-bit vector (m-dimensional vector).

[0043] For example, in the Galois field GF(2 m ) any element a∈GF(2 m ) can be expressed as a polynomial of degree (m-1) on GF(2) with respect to the primitive element α, as shown in the following equation (2), where i is an integer satisfying 0≦i≦m-1.

number

[0044] Therefore, the element a can be expressed as an m-dimensional vector on GF(2) whose components are the coefficients of a polynomial on GF(2), as shown in the following equation (3).

number

[0045] For example, code length n=2 10 Galois field GF(2 10 ) can be represented by a 10-bit vector. 4 Galois field GF(2 4 ) can be represented by a 4-bit vector. Figure 5 shows the case where m=4 and the primitive polynomial is p(x)=x 4 +x+1 in the Galois field GF(2 4 ) is a diagram showing an example of an original vector representation.

[0046] For example, the element 0 is the polynomial 0α 0 +0α 1 +0α 2 +0α 3 and is expressed as a 4-dimensional vector (0,0,0,0) whose components are the coefficients of this polynomial. The primitive element α is expressed as the primitive polynomial p(α)=α 4 +α+1=0, in other words, α 4 = α+1, so the element α 4 can be transformed into 1+α. Therefore, for example, element α 4 is a polynomial 1α 0 +1α 1 +0α 2 +0α 3and is expressed as a four-dimensional vector (1,1,0,0) whose components are the coefficients of this polynomial.

[0047] Furthermore, addition of Galois field elements is expressed as XOR for each bit of two vectors. In this embodiment, multiplication of Galois field elements is performed by an arithmetic circuit that combines AND operations and XOR operations.

[0048] In (P1), first, m, which determines the number of elements of the Galois field to be operated on, is determined. The value of m may be determined in any way, for example, depending on the encoding method to be applied and the type of memory to be applied. For example, when the memory system 1 uses a BCH code with a code length of 1000 bits, the number of elements (2 10 =1024>1000), m is determined to be 10. In a Galois field, one or more primitive polynomials are defined for each value of m. Of these primitive polynomials, one to be used is determined.

[0049] Next, (P2) will be explained. Once the primitive polynomial p(x) is determined, a matrix called a companion matrix is ​​determined. Figure 6 is a diagram for explaining an example of a companion matrix.

[0050] Multiplication of a Galois field element a by a primitive element α can be expressed as multiplication of a companion matrix C by a vector representing the element a. Multiplication by the primitive element α can be divided into an operation equivalent to a right shift and an operation equivalent to feedback (FB). The circuit in Figure 6 shows an example of a circuit that corresponds to such right shifts and feedback. Feedback can be interpreted as processing for terms that overflow from a right shift. The companion matrix C can also be divided into columns equivalent to a right shift (columns 1 to (m-1)) and columns equivalent to feedback (column m).

[0051] For example, if the primitive polynomial is p(x)=x 4 +x+1 in the Galois field GF(2 4) can be expressed as the multiplication of the companion matrix C and the element a as shown in the lower equation of Figure 6. In this way, in step (P2), the companion matrix corresponding to the determined primitive polynomial is found.

[0052] Next, we will explain (P3). In (P3), we use a companion matrix to multiply the m tensors T i When m=10, T 0 From T 9 The 10 tensors are calculated.

[0053] Figure 7 shows the tensor T i 7 is a diagram showing an example of how to obtain the tensor T i is obtained by arranging the i-th row vector of matrices C(0) to C(m-1). Note that matrix C(p) (p is an integer satisfying 0≦p≦m-1) means the p-th power of the companion matrix C.

[0054] Also, in Figure 7, the tensor T i An example formula showing the relationship between and the multiplication of Galois field elements a and b is also provided. (a × b) i represents the ith bit of an m-bit vector that indicates the result of multiplication of element a and element b. As shown in Figure 7, (a × b) i is a vector representing element a, a vector representing element b, and a tensor T i It can be expressed by multiplying with. The symbol "T" in the upper right corner of element b represents the transpose of a vector or matrix. Also, (a × b) i is the jth (j is an integer satisfying 0≦j≦m-1) component a of a j and the kth (k is an integer satisfying 0≦k≦m-1) component b of b k It can be expressed in the form of the sum of AND operations of and.

[0055] As shown in Figure 7, the tensor T used to multiply element a and element b is i is an AND operation j b k and the XOR operation (ΣTjk i ) and the tensor T jk i represents the tensor equivalent to the XOR operation. jk i The subscripts j and k correspond to the subscripts of the elements a and b, which are the input vectors of the XOR operation. jk i The superscript i in corresponds to the subscript of a×b, which is the vector (output vector) that is the output of the XOR operation. jk i is sometimes called a circularly convolved tensor. jk i (cyclic convolution tensor) is equivalent to a third-order tensor that takes two elements of a Galois field (e.g., element a and element b) as input and outputs one element (e.g., element ab) that is the result of multiplication of the two elements.

[0056] Similarly, in the following, the subscript of a tensor corresponding to an operation may be expressed as the subscript of the input vector of the operation, and the superscript may be expressed as the subscript of the output vector of the operation. For example, the subscript of element a, which is an m-dimensional input vector, is j, and the subscript of element a, which is an m-dimensional output vector, is j. 2 If the subscript of is i, the tensor S(1) representing the square of the element a is S j i (1). The components of a vector, which is a first-order tensor, are expressed as subscripts. For example, the i-th component of element a, which is an m-dimensional vector, is a i It is expressed as:

[0057] Figure 8 shows the case where m=4 and the primitive polynomial p(x)=x 4 Tensor T for +x+1 0 First, matrices C(0) to C(3) are calculated from the companion matrix C. The tensor T 0 can be obtained by arranging the 0th row of each of these matrices C(0) to C(3). 0Using the above formula, (a×b)0 can be expressed as a0b0+a1b3+a2b2+a3b1. Similarly, the tensor T 1 , T 2 and T 3 can be obtained.

[0058] Next, we will explain (P4). The tensor S(1) representing the square of an element of a Galois field is the tensor T i FIG. 9 is a diagram showing an example of how to obtain the tensor S(1). As shown in FIG. 9, the tensor S(1) can be obtained by i It can be obtained by taking the diagonal components of the i-th row vector.

[0059] 9 also shows an example of an equation showing the relationship between the tensor S(1) and the square of the element a of the Galois field (multiplication of the element a and the element a). As shown in FIG. 9, the square of the element a (a×a) can be expressed by multiplying the vector indicating the element a by the tensor S(1).

[0060] Figure 10 shows the case where m=4 and the primitive polynomial p(x)=x 4 +x+1. The tensor S(1) is calculated by the tensor T 0 ~T 3 It can be found by arranging the diagonal elements of each. Using this tensor S(1), a 2 (=a×a) is calculated as the vector (a0+a2, a2, a1+a3, a3).

[0061] The reason for extracting only the diagonal elements is that the elements symmetric about the main diagonal line cancel each other out and become 0. For example, the tensor T 0 The corresponding (a×a)0 is a0a0+a2a2+a3a1+a1a3. In GF(2), the square of the element a, a 2 is equal to a, and addition (a+a) of the same element a is 0. For example, a0a0 and a2a2 are a0 and a2, respectively. Also, a3a1+a1a3 is 0 because it is the addition of the same element. Therefore, a0a0+a2a2+a3a1+a1a3 is expressed as a0+a2.

[0062] 2 of Galois field elements when u is 2 or greater u The second-order tensor S(u) representing a power can be calculated by raising S(1) calculated as above to the u power. For example, the second-order tensor S(2) representing the fourth power of an element of a Galois field is calculated by S(1) × S(1).

[0063] Next, we will explain (P5). Below, we will use the 7th power of Galois field a (a 7 ) will be described.

[0064] Figure 11 shows the Galois field a to the seventh power (a 7 5 shows an example of the configuration of a calculation unit 500 that calculates XOR (XOR) and multiplication units 503 and 504. The calculation unit 500 includes XOR calculation units 501 and 502 and multiplication units 503 and 504.

[0065] The XOR calculation unit 501 performs an XOR operation corresponding to the square of the Galois field. As described above, the second-order tensor representing the square of the Galois field element is expressed as S(1). The XOR calculation unit 501 performs an XOR operation corresponding to the tensor S(1) to obtain a, which is the square of the input element a. 2 Calculate.

[0066] The XOR calculation unit 502 performs an XOR operation corresponding to the fourth power of the Galois field. As described above, the second-order tensor representing the fourth power of the Galois field element is expressed as S(2). The XOR calculation unit 501 performs an XOR operation corresponding to the tensor S(2) to obtain a, which is the fourth power of the input element a. 4 Calculate.

[0067] The multiplication unit 503 multiplies the input element a by the output of the XOR calculation unit 501. 2 Multiply and and the result is a 3 Output.

[0068] The multiplication unit 504 multiplies the output of the multiplication unit 503 by a 3 and the output of the XOR calculation unit 501, a 4Multiply and and the result is a 7 Output.

[0069] 12 is a diagram showing an example of the configuration of a circuit in which the components of the arithmetic unit 500 are embodied as logic circuits. Unlike the embodiment of this embodiment, this is an example of a configuration in which two XOR calculation units are separated by an AND calculation unit. Note that FIG. 12 shows an example of the configuration of the arithmetic unit 500 when m=10.

[0070] As mentioned above, multiplication of Galois field elements is expressed by a combination of AND and XOR operations. For example, element a and element a 2 The multiplication unit 503 multiplies the element a j and the original (a 2 ) κ AND calculation part and tensor T jκ μ The XOR calculation part corresponds to the element a. 3 and former a 4 The multiplication unit 504 multiplies the element (a 3 ) μ and the original (a 4 ) λ AND calculation part and tensor T μλ i 12, i, j, k, l, κ, μ, and λ are all integers between 0 and 9.

[0071] Here, a description will be given of the amount of calculation (calculation time) performed by the calculation unit 500 of the comparative example shown in Fig. 12. First, a description will be given of the conversion of the representation of tensors used in the calculation.

[0072] In general, a tensor T jk ican be expressed by converting multiple indices j and k of the input vector into a one-dimensional vector. The process of converting a tensor into a one-dimensional vector is called flattening. The matrix obtained by flattening is called a flattened matrix. A flattened matrix is ​​equivalent to a matrix in which one-dimensional vectors, which are a collection of multiple indices corresponding to multiple inputs, are arranged in the same order as the number of elements of the indices corresponding to one output. In the following, m=6, and the primitive polynomial is p(x)=x 6 +x+1 in the Galois field GF(2 6 ) will be used as an example.

[0073] The multiplication of element a and element b is performed using the third-order tensor T jk i The 0th element (i=0) of the output vector is the second-order tensor T jk 0 It is calculated as follows.

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[0074] For example, the tensor T in equation (5) jk 0 can be converted to a one-dimensional vector (1,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1,0,0,0,0,1,0,0,0,0,1,0,0,0,0,1,0,0,0,0) by concatenating each row. jk 0 The jth row and kth column element of corresponds to the qth column element of the one-dimensional vector (q=j+6k, q is an integer satisfying 0≦q≦35). jk 1 ~T jk 5 can also be converted into a one-dimensional vector using the same procedure.

[0075] Figure 13 shows six tensors T jk 0~T jk 5 A vector 1301 is a matrix (second-order tensor) in which the tensor T jk 0 is a one-dimensional vector corresponding to

[0076] A component with a value of 1 is a corresponding AND operation value a j b k indicates that the terms are used in the XOR operation. Hereinafter, being used in the XOR operation may be referred to as contributing to the XOR operation. In the example of equation (5), the output vector (ab)0 is expressed as (ab)0 = a0b0 + a5b1 + a4b2 + a3b3 + a2b4 + a1b5. In this example, the number of terms used in the XOR operation (terms contributing to the XOR operation) is 6.

[0077] In this embodiment, as shown in the lower part of Fig. 13, a tree structure is considered in which multiple terms are leaf nodes, and XOR operations are performed using a tournament method. That is, first, three XOR operations a0b0+a5b1, a4b2+a3b 3、 a2b4+a1b5 is executed. The results of the three XOR operations are represented as operation results R01, R02, and R03. Next, an XOR operation is performed on the two operation results R01 and R02, and the operation result R11 is output. Finally, an XOR operation is performed on operation results R11 and R03, and the operation result (ab)0 is output.

[0078] In this example, the number of XOR operations executed in series until the final operation result is obtained is three. Hereinafter, this number will be referred to as the number of stages (logical stages) of XOR operations. The number of stages ns of XOR operations is calculated by ns = ceiling(log(number of XOR terms)). ceiling(x) is a ceiling function that outputs the smallest integer equal to or greater than x. In the example in Figure 13, the number of stages ns is ceiling(log(6)) = 3.

[0079] The amount of calculation by the calculation unit 500 can be evaluated by the number of stages as described above. Most of the amount of calculation by the calculation unit 500 is accounted for by the multiplication units 503 and 504 that perform multiplication, so the amount of calculation by the multiplication units 503 and 504 will be explained.

[0080] The number of stages of the AND calculation unit in multiplication unit 503 is 1. When m=10, the number of terms in the XOR calculation by the XOR calculation unit is about 10 to 28. Since ceiling(log(10))=4 and ceiling(log(28))=5, the number of stages of the XOR calculation unit in multiplication unit 503 is about 4 to 5. The number of stages in the entire multiplication unit 503 is about 5 to 6. The number of stages of the calculation in multiplication unit 504 is also about 5 to 6, the same as multiplication unit 503.

[0081] In the arithmetic unit 500 of the comparative example, multiplication by the multiplication unit 503 and multiplication by the multiplication unit 504 are performed in series. Therefore, the number of stages of operation in the arithmetic unit 500 as a whole is 10 to 12 stages (2 stages of AND calculation units, 8 to 10 stages of XOR calculation units). In this way, the number of stages of operation increases due to the inclusion of multiplications performed in series, and accordingly, the calculation time for the operations in the arithmetic unit 500 as a whole may increase.

[0082] In this embodiment, the multiple-stage multiplication included in the arithmetic unit 500 is replaced with a single-stage multiplication, thereby reducing the number of stages in the overall arithmetic operation and enabling multiple Galois field multiplications to be performed at higher speed.

[0083] Continuing the explanation of (P5), in this embodiment, multiple stages of multiplication are replaced with one stage of multiplication by the procedure of direct product and contraction of tensors. The terms used in the explanation of the replacement of multiplications are described below.

[0084] In this embodiment, the tensor T is defined as follows: It represents a transformation (multilinearity) that takes multiple input vectors as input and has linearity for each input. For example, linearity for each input can be expressed as follows: T(a+b,c)=T(a,c)+T(b,c) T(a,b+c)=T(a,b)+T(a,c) ·The number of vectors involved in a transformation is called the rank. The input vector subscripts are placed as subscripts, and the output vector subscripts are placed as superscripts.

[0085] In the following, operations in a Galois field may be expressed as a network of diagrammatically represented tensors (including vectors and matrices). Figure 14 shows an example of a diagrammatic representation of a tensor.

[0086] For example, component a of vector a i is identified by a single subscript i. Thus, the diagrammatic representation of a vector a includes the symbol a representing the vector inside the circle, and an undirected edge leaving the circle. The edge is given the subscript i.

[0087] Component C of the companion matrix C, which is a rank 2 tensor j i is specified by two subscripts i and j. Thus, the diagrammatic representation of a companion matrix C includes the symbol C representing the companion matrix within a rectangle, the edge going into the rectangle with subscript j, and the edge going out of the rectangle with subscript i.

[0088] Component T of the circularly convoluted tensor T, which is a rank 3 tensor jk i is specified by three indices i, j, and k. Thus, the diagrammatic representation of a circular convolution tensor T includes the symbol T representing the circular convolution tensor inside a rectangle, two edges entering the rectangle with indices j and k, respectively, and an edge leaving the rectangle with indices i.

[0089] Next, we will explain the Cartesian product of tensors. The Cartesian product of tensors is an operation to obtain a higher-rank tensor by multiplying the components of two tensors. For example, A jk i and a third-order tensor with B m lThe direct product of a second-order tensor with components C jkm il =A jk i B m l This corresponds to the operation of obtaining a fifth-order tensor with components. Figure 15 shows an example of a diagrammatic representation of this Cartesian product.

[0090] Next, we will explain tensor contraction. Tensor contraction is the operation of choosing two different indices for a tensor, making them the same indices, and then taking the sum. For example, C jkm il =A jk i B m l For the fifth-order tensor with components, two subscripts l and k are selected, and the sum is taken after making them the same subscript κ, to obtain the third-order tensor D shown in the following equation (6). jm i The operation of obtaining the above corresponds to contraction. Figure 16 shows an example of a diagram representation equivalent to this contraction.

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[0091] Here, we will explain the relationship between matrix (second-order tensor) multiplication and direct product and contraction. The matrix S(2) obtained by multiplying two matrices (second-order tensors) S(1) and S(1) is expressed by the following equation (7).

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[0092] The matrix S(2) corresponds to a tensor (matrix) obtained by taking the direct product of two matrices S(1) and S(1) and contracting them with subscripts that include both ends of the side in the region you want to combine into one operation. For example, the first matrix S j l The index l of the output of (1) and the second matrix S k iBy using the subscript κ that connects the subscript k of the input of (1), the two matrices S(1) can be converted into the matrix S j i (2) is a diagram showing an example of the diagram representation equivalent to this contraction.

[0093] Next, an example will be described in which the calculation unit 110 of the embodiment is configured by applying a direct product and contraction to the calculation unit 500 of the comparative example including two-stage multiplication. FIG. 18 is a diagram showing the relationship between the calculation unit 500 and the calculation unit 110.

[0094] The calculation unit 500 shown on the left side of FIG. 18 corresponds to a configuration in which the calculation of the calculation unit 500 in FIG. 12 is represented in diagram form, for example.

[0095] The arithmetic unit 500 is replaced by the arithmetic unit 110 shown on the right side of FIG. 18 through a direct product and contraction. The arithmetic unit 110 corresponds to the tensor P(111) representing the seventh power of the element a. Note that the "P" in tensor P(111) represents power. "111" corresponds to the binary representation of "7" to the seventh power. The tensor P(111) is expressed by the following equation (8) using input subscripts j, k, and l and output subscript i.

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[0096] 19 is a diagram showing an example of the configuration of a circuit that embodies the calculation unit 110. Note that FIG. 19 shows an example of the configuration of the calculation unit 110 when m=10. The AND calculation unit 111 calculates the element a j , a k , a l The XOR calculation unit 112 performs an XOR operation corresponding to the tensor P(111).

[0097] Next, (P6) will be described. In (P6), the arithmetic unit 110 is configured (designed) to perform an XOR operation according to the tensor P(111). The configuration of the arithmetic unit 110 may be performed by any conventional method. For example, a method using a tool for circuit design using a register transfer level (RTL) hardware description language can be applied.

[0098] In (P6), flattening of the tensor P(111) may be performed. Figure 20 is a diagram showing an example of a flattened matrix obtained by flattening the tensor P(111). Figure 20 is an example of a flattened matrix of the tensor P(111) when m=6.

[0099] The tensor P(111) has three input subscripts (j, k, l) and one output subscript (i), so if you simply flatten it, the flattening matrix will be 6 rows and 6 columns. 3 On the other hand, the tensor P(111) has three input vectors that are the same for all elements a. This allows the flattening matrix to be simplified.

[0100] For example, if the input subscripts (j, k, l) are (2, 1, 1), the value used in the XOR operation is a2 × a1 × a1. As mentioned above, in GF(2), the square of the element a, a 2 is equal to a. Therefore, a2 × a1 × a1 is equal to a1 × a2. Furthermore, the contribution of a2 × a1 × a1 to the XOR operation is the same as the contribution of a1 × a2. Similarly, for pairs (j, k, l) where one or two of the subscripts have a value of "2" and the remaining subscripts have a value of "1", the contribution to the XOR operation is the same as the contribution of a1 × a2. In this way, the flattened matrix can be simplified by combining terms that have the same contribution to the XOR operation into one, and by setting the contribution to zero if there is an even number of contributions.

[0101] Figure 20 shows an example of a flattened matrix obtained by such simplification. The flattened matrix in Figure 20 is the output vector of the tensor P(111) (a7 )0~(a 7 )5 corresponds to being expressed as in the following equation (9).

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[0102] At least some of the steps (P1) to (P6) above may be implemented by one or more processing units. The processing unit may be implemented, for example, by one or more processors. For example, the processing unit may be implemented by causing a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) to execute a program, i.e., by software. The processing unit may be implemented by a processor such as a dedicated IC (Integrated Circuit), i.e., by hardware. The processing unit may be implemented by a combination of software and hardware. At least some of the steps (P1) to (P6) may be implemented as functions of a tool used to configure the calculation unit 110.

[0103] The amount of calculation performed by the calculation unit 110 of this embodiment will be described. The number of stages in the AND calculation unit 111 is 2. When m=10, the number of terms in the XOR calculation by the XOR calculation unit 112 is approximately 79 to 92. Since ceiling(log(79))=7 and ceiling(log(92))=7, the number of stages in the XOR calculation unit 112 is approximately 7. The number of stages in the entire calculation unit 110 is approximately 9.

[0104] As described above, in this embodiment, the arithmetic unit 110 is configured to combine a plurality of XOR calculation units (in the example of FIG. 12, the XOR calculation units included in the multiplication unit 503 and the multiplication unit 504, and further the XOR calculation units 501 and 502). As a result, the number of stages of calculation in the arithmetic unit 110 can be suppressed to about 9 stages, compared to the 10 to 12 stages of the arithmetic unit 500 of the comparative example, for example. In other words, it becomes possible to execute a plurality of Galois field multiplications at higher speed.

[0105] Up to now, the number of stages has been compared when m=10. By applying this embodiment, the number of stages of XOR operations can be reduced even when m is other than 10. Fig. 21 is a diagram for explaining an example of the number of stages reduced when m=8 to 14.

[0106] 21 shows an example of the code length of the BCH code, the primitive polynomial, the maximum number of XOR stages in the comparative example, the maximum number of XOR stages in this embodiment, and the rate of increase in the number of transistors. For the maximum number of XOR stages in the comparative example, the left side shows an estimate ignoring the increase in the number of stages due to the XOR calculation unit 501, which corresponds to the square of the Galois field, and the right side shows an estimate including the number of stages of the XOR calculation unit 501. Note that FIG. 21 shows the maximum number of XOR stages in the comparative example, which is calculated by ignoring the increase in the number of stages due to the XOR calculation unit 501, which corresponds to the square of the Galois field, and the right side shows an estimate including the increase in the number of stages of the XOR calculation unit 501. 7 The maximum number of XOR stages corresponds to the number of stages of the XOR calculation unit 112 in the calculation unit 110, for example.

[0107] As mentioned above, the code length of the BCH code is n=2. m -1, the number of elements in the Galois field is 2 m is determined. When m is in the range of 8 to 14, the maximum number of XOR stages in the comparative example is a minimum of 10 and a maximum of 17. In contrast, in the present embodiment, the maximum number of XOR stages is in the range of 6 to 8, and the number of stages can be reduced compared to the comparative example for any value of m. The larger m is, the greater the rate of increase in circuit size (number of transistors) due to multiplication replacement (direct product and contraction). However, for example, in the decoding unit 18, if the input / output bit width of the decoding unit 18 is increased to speed up the entire decoding unit 18, the circuit size occupied by the arithmetic unit 110 (error locator polynomial calculation unit 102) is relatively small. Therefore, the impact of the increase in circuit size of the arithmetic unit 110 can be kept within an acceptable range.

[0108] So far, we have considered the Galois field a 7 We have described an example of the configuration of the calculation unit 110 that calculates the above. This calculation unit 110 is an example that is configured based on the direct product and contraction of two third-order tensors. The number of third-order tensors to be subjected to the direct product and contraction is not limited to two, and may be three or more.

[0109] That is, the calculation unit 110 can be configured to perform an operation (first operation) represented by p (p is an integer equal to or greater than 2) third-order tensors and corresponding to p multiplications executed in series, using an AND operation (AND calculation unit 111) and an XOR operation (XOR calculation unit 112). The AND operation corresponds to an operation that calculates an AND value of multiple elements used in the p multiplications. The XOR operation corresponds to an operation based on a tensor (hereinafter referred to as a contracted tensor) obtained by contracting a 3p-order tensor obtained by the Cartesian product of p third-order tensors, and an AND value that is the result of the AND operation.

[0110] A contracted tensor can be interpreted as being obtained as follows: That is, a contracted tensor corresponds to a tensor obtained by contracting a 3p-order tensor with respect to the subscripts corresponding to the output and the subscripts related to the input for one or more pairs of two third-order tensors selected from p third-order tensors, where the output of one third-order tensor is the input of the other third-order tensor.

[0111] Also, the Galois field a 7 The calculation unit 110 calculates the number of elements of the Galois field as the elements used for the p (2) multiplications. u For example, the calculation unit 110 calculates an element a corresponding to the square of the element a (u=1). 2 and the element a corresponding to the fourth power of the element a (u=2) 4 In this case, the calculation unit 110 multiplies a 3p-th order tensor and u It is configured to use one or more second-order tensors representing the multiplication of a tensor and a tensor (contracted tensor) that is a contracted direct product of the tensor.

[0112] The calculations that are the subject of the calculation unit 110 are not limited to the seventh power of an element of a Galois field. Below, a configuration example of the calculation unit 110 that executes calculations other than the seventh power will be described.

[0113] Figure 22 shows the Galois field a 622 is a diagram showing an example of the configuration of the calculation unit 110 that calculates b. Note that the upper part of Fig. 22 shows an example of the calculation unit 500 before performing the direct product and contraction of the tensors.

[0114] a calculated by the calculation unit 110 in FIG. 6 b is expressed by the following equation (10). Also, the tensor T jkl i (a 6 b) is expressed by the following equation (11): Tensor T jkl i (a 6 b) is a 6 is a fourth-order tensor for computing b.

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[0115] Fig. 23 is a diagram showing an example of the configuration of the arithmetic unit 110 that calculates the Galois field abc. The upper part of Fig. 23 shows an example of the arithmetic unit 500 before performing the direct product and contraction of the tensor.

[0116] The abc calculated by the calculation unit 110 in FIG. 23 is expressed by the following equation (12). In addition, the tensor T jkl i (abc) is expressed by the following equation (13): Tensor T jkl i (abc) is a fourth-order tensor for computing abc.

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[0117] 18, 22, and 23 are examples of the arithmetic unit 500 of the comparative example including two stages of multiplication corresponding to two tensors T. On the other hand, there are cases where an arithmetic unit includes an arithmetic operation corresponding to two tensors T, but does not perform the direct product and contraction of these tensors, resulting in one stage of multiplication.

[0118] 24 is a diagram showing an example of such a configuration of the calculation unit 600. The calculation by the calculation unit 600 is expressed by the following equation (14).

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[0119] In the arithmetic unit 600, the result of an operation using one tensor T is not used in the operation of the other tensor T. Therefore, operations using two tensors T do not need to be performed serially. That is, the arithmetic unit 600 can be configured to perform one multiplication stage. With such a arithmetic unit 600, it is not necessary to perform replacement of multiplication by direct product and contraction, as in this embodiment.

[0120] Below, another example of a calculation unit to which replacement of multiplication by direct product and contraction as in this embodiment can be applied will be described.

[0121] 25 is a diagram showing an example of the configuration of a calculation unit 500 that calculates the inverse element of an element a in a Galois field. Such a calculation unit 500 also includes multiple multiplications (hereinafter referred to as multiple-stage multiplications) that are executed in series. Therefore, the conversion to one-stage multiplication according to this embodiment can be applied.

[0122] Figure 26 shows the Galois field a 3 b 2 and a 3 b 4 27 and 28 show an example of the configuration of a calculation unit 500 for calculating the Galois field a 3 b 627 is a diagram illustrating an example of the configuration of a calculation unit 500 that calculates the following. The calculation units 500 in FIGS. 26 to 28 all include three tensors T. On the other hand, the calculation units 500 in FIGS. 26 and 28 include two stages of multiplication, while the calculation unit 500 in FIG. 27 includes three stages of multiplication. As such, the number of tensors T included may not match the number of stages of multiplication. In either case, as long as the number of stages of multiplication is two or more, the replacement of multiplication according to this embodiment is applicable.

[0123] In FIG. 26 , all tensors included in the calculation unit 500 may be combined into a single AND calculation unit and a single XOR calculation unit through a Cartesian product and contraction. Alternatively, either the pair of the left tensor and the upper right tensor or the pair of the left tensor and the lower right tensor may be combined into a single AND calculation unit and a single XOR calculation unit through a Cartesian product and contraction. In FIG. 27 , all tensors included in the calculation unit 500 may be combined into a single AND calculation unit and a single XOR calculation unit through a Cartesian product and contraction. Alternatively, either the pair of the left tensor and the middle tensor or the pair of the middle tensor and the right tensor may be combined into a single AND calculation unit and a single XOR calculation unit through a Cartesian product and contraction. In FIG. 28 , all tensors included in the calculation unit 500 may be combined into a single AND calculation unit and a single XOR calculation unit through a Cartesian product and contraction. Alternatively, either the pair of the upper left tensor and the right tensor, or the pair of the lower left tensor and the right tensor, may be combined into a single AND calculation unit and a single XOR calculation unit by Cartesian product and contraction.

[0124] Note that Fig. 28 can be interpreted as an improved configuration of Fig. 27 that employs a tournament method to perform multiplication with fewer stages. As shown in Fig. 28, the number of multiplication stages can be configured to be ceiling(log(number of tensors T)). In other words, as with the XOR operation, employing the tournament method enables faster operation.

[0125] Next, a description will be given of the flow of the decoding process performed by the memory system 1. Fig. 29 is a flowchart showing an example of the decoding process in this embodiment.

[0126] The control unit 11 reads out the error correction code from the nonvolatile memory 20 and obtains the received word (step S101). The control unit 11 also instructs the decoding unit 18 to start decoding.

[0127] The syndrome calculation unit 101 of the decoding unit 18 calculates syndromes from the received word (step S102). The decoding unit 18 determines whether or not the values ​​of all the calculated syndromes are 0 (step S103).

[0128] If all the syndromes are 0 (step S103: Yes), it can be determined that there are no errors in the received word, and the decoding unit 18 ends the decoding process. If all the syndromes are not 0 (step S103: No), the error locator polynomial calculation unit 102 calculates an error locator polynomial using the syndromes according to the PGZ algorithm (step S104). At this time, the arithmetic unit 110 calculates the multiplication of the syndromes for at least some of the coefficients of the error locator polynomial.

[0129] The error position calculation unit 103 searches for an error position using the calculated error position polynomial (step S105). The bit flip unit 104 corrects the error by inverting (bit flipping) the bit at the error position found by the search (step S106), and the decoding process ends.

[0130] As described above, according to this embodiment, multiple Galois field multiplications can be performed at higher speed.

[0131] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0132] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoding section 18 Decoding section 20 Non-volatile memory 30 hosts 101 Syndrome Calculation Unit 102 Error location polynomial calculation unit 103 Error location calculation unit 104 Bit Flip Section 110 Arithmetic section 111 AND calculation section 112 XOR calculation section

Claims

1. A first operation corresponding to p multiplications executed in series, each represented by p (p is an integer equal to or greater than 2) third-order tensors that input two elements of a Galois field and output one element that is a multiplication result of the two elements, an AND operation for calculating an AND value of the p elements used in the multiplication; and performing an XOR operation based on a contracted tensor obtained by contracting a 3p-order tensor obtained by the direct product of p number of the third-order tensors and the AND value. Arithmetic circuit.

2. The plurality of elements may be two elements of a Galois field. ｕ one or more first elements corresponding to a power (u is an integer equal to or greater than 1), The contracted tensor is a tensor of the 3pth order and a 2pth order corresponding to the first element. ｕ One or more second-order tensors representing the multiplication of and obtained by contracting the direct product of The arithmetic circuit according to claim 1 .

3. The third-order tensor is calculated using a companion matrix determined according to a Galois field, The second-order tensor is calculated using the third-order tensor. The arithmetic circuit according to claim 2 .

4. The contracted tensor is obtained by contracting the 3p-th order tensor with respect to a subscript corresponding to the output and a subscript related to the input for each of one or more pairs of pairs containing two third-order tensors selected from the p third-order tensors, in which the output of one third-order tensor is the input of the other third-order tensor. The arithmetic circuit according to claim 1 .

5. The contracted tensor is represented by a matrix in which a one-dimensional vector, which is a collection of a plurality of subscripts corresponding to a plurality of inputs, is arranged in the same number as the number of elements of the subscript corresponding to one output. The arithmetic circuit according to claim 1 .

6. a non-volatile memory that stores data encoded with an error correction code; a memory controller including the arithmetic circuit according to claim 1; The memory controller Calculating a plurality of syndromes, which are elements of a Galois field, using the received word read from the nonvolatile memory; performing the first operation using the arithmetic circuit, with any of the syndromes as the elements; Calculating an error location using an error location polynomial whose coefficients include the result of the first operation; correcting the calculated error location; Memory system.

7. A control method for controlling a nonvolatile memory, comprising: storing data encoded with an error correction code in the nonvolatile memory; reading the data from the nonvolatile memory as a received word; Calculating a plurality of syndromes, which are elements of a Galois field, using the received word read from the nonvolatile memory; 2. The arithmetic circuit according to claim 1 is used to execute the first arithmetic operation using any of the plurality of syndromes as the plurality of elements; Calculating an error location using an error location polynomial whose coefficients include the result of the first operation; correcting the calculated error location; A control method comprising:

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