Semiconductor device

Abstract

To provide a semiconductor power module capable of satisfactorily reducing an inductance component.SOLUTION: The semiconductor device includes a first substrate having one surface and the other surface, a second substrate having a facing surface facing the one surface of the first substrate, a first switching element disposed on the facing surface side of the second substrate, a second switching element and an output terminal, a first conductive pattern disposed on the facing surface of the second substrate and electrically connected to the first switching element, a second conductive pattern disposed on the facing surface of the second substrate and separated from the first conductive pattern, the second conductive pattern being electrically connected to the second switching element, and a resin sealing the first substrate, the second substrate, and the first and second switching elements.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor power module. [Background technology]

[0002] Patent Document 1 discloses an inverter module as an example of a semiconductor power module including multiple switching elements. This inverter module includes a first semiconductor element (first switching element), a second semiconductor element (second switching element), and a resin case that houses these elements.

[0003] In this inverter module, a positive terminal (power supply terminal) connected to the first semiconductor element and a negative terminal (power supply terminal) connected to the second semiconductor element are arranged at one end of the resin case with a gap between them, and a pair of output terminals connected in common to the first semiconductor element and the second semiconductor element are arranged at the other end of the resin case. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-222885 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, semiconductor power modules equipped with multiple switching elements have a problem of the risk of surge voltages occurring during switching operations. The magnitude of the surge voltage is proportional to the inductance component of the current path, such as the wiring through which the current flows, so one of the challenges is to remove the inductance component from the current path.

[0006] In the semiconductor power module disclosed in Patent Document 1, two power supply terminals to which different voltages are applied are arranged at a distance from each other at one end of a resin case.

[0007] The distance between these two power terminals is set depending on the shape of the resin case, so it is relatively large. As a result, the magnetic field generated by one power terminal and the magnetic field generated by the other power terminal cannot be effectively canceled out, which may increase the mutual inductance component between the terminals due to the mutual induction effect.

[0008] Therefore, one embodiment of the present disclosure provides a semiconductor power module that can reduce the inductance component. [Means for solving the problem]

[0009] One embodiment of the present disclosure provides a semiconductor power module including: an insulating member having one surface and another surface; a support member having an opposing surface opposing the one surface of the insulating member; a first terminal arranged on the one surface side of the insulating member; a second terminal arranged on the other surface side of the insulating member so as to face the first terminal across the insulating member and to which a voltage different from that of the first terminal is applied; a first element, a second element, and an output terminal arranged on the surface side of the support member; and a resin that partially covers the first terminal, the second terminal, and the output terminal and defines an exposed portion of the first terminal, an exposed portion of the second terminal, and an exposed portion of the output terminal.

[0010] The direction of the current flowing through the first terminal and the direction of the current flowing through the second terminal may be opposite to each other across the insulating member.

[0011] According to this semiconductor power module, it is possible to provide a semiconductor power module capable of reducing the inductance component.

[0012] The above and other objects, features, and advantages of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is an electric circuit diagram showing the electrical structure of a semiconductor power module according to one embodiment of the present invention. [Figure 2] FIG. 2 is a perspective view of the semiconductor power module of FIG. 1 as seen from above. [Figure 3] FIG. 3 is a perspective view of the semiconductor power module of FIG. 2 as viewed from below. [Figure 4] FIG. 4 is an exploded perspective view showing the internal structure of the semiconductor power module of FIG. [Figure 5] FIG. 5 is a plan view showing the internal structure of the semiconductor power module of FIG. [Figure 6] FIG. 6 is a side view showing the internal structure of the semiconductor power module of FIG. [Figure 7] FIG. 7 is an enlarged view of region VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is an electric circuit diagram showing the electrical structure of a first modified example of the semiconductor power module of FIG. [Figure 10] FIG. 10 is an electric circuit diagram showing the electrical structure of a second modified example of the semiconductor power module of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] FIG. 1 is an electric circuit diagram showing the electrical structure of a semiconductor power module 1 according to one embodiment of the present invention.

[0015] Referring to FIG. 1, the semiconductor power module 1 according to this embodiment includes an output side terminal 2, a high voltage side terminal 3 (first power supply terminal, first terminal), and a low voltage side terminal 4 (second power supply terminal, second terminal) to which a voltage lower than the voltage applied to the high voltage side terminal 3 is applied.

[0016] The semiconductor power module 1 includes a plurality (five in this embodiment) of first switching elements (first elements) 5 connected between the output side terminal 2 and the high voltage side terminal 3, and a plurality (five in this embodiment) of second switching elements (second elements) 6 connected between the output side terminal 2 and the low voltage side terminal 4.

[0017] A half-bridge circuit 7 is formed by an output side terminal 2, a high-voltage side terminal 3, a low-voltage side terminal 4, a plurality of first switching elements 5, and a plurality of second switching elements 6. The high-voltage side terminal 3 and the low-voltage side terminal 4 are arranged close to each other.

[0018] In the half-bridge circuit 7, the plurality of first switching elements 5 constitute an upper arm 8 on the high-voltage side, and the plurality of second switching elements 6 constitute a lower arm 9 on the low-voltage side.

[0019] In this embodiment, each first switching element 5 includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on a Si substrate, a SiC substrate, or a wide bandgap semiconductor substrate, and has a first source electrode 10, a first drain electrode 11, and a first gate electrode 12.

[0020] In each first switching element 5, the first source electrode 10 and the first drain electrode 11 form a pair of first main electrodes, and the first gate electrode 12 forms a first control electrode that controls the current flowing between the pair of first main electrodes. Each first switching element 5 includes a first diode 13 connected in reverse bias between the first drain electrode 11 and the first source electrode 10.

[0021] Each first switching element 5 has a first source electrode 10 electrically connected to the output terminal 2 and a first drain electrode 11 electrically connected to the high-voltage terminal 3, and is thereby connected between the high-voltage terminal 3 and the low-voltage terminal 4. The first gate electrodes 12 of each first switching element 5 are electrically connected in common to a first gate terminal 14 (first control terminal) on the high-voltage side.

[0022] The first gate terminal 14 is a terminal for driving and controlling each first switching element 5 (each first gate electrode 12). The first source electrodes 10 of each first switching element 5 are electrically connected in common to the output side terminal 2 and also to a first source sense terminal 15 on the high voltage side. The first source sense terminal 15 is a potential detection terminal for detecting the potential of the first source electrode 10.

[0023] In this embodiment, each second switching element 6 includes a MISFET formed on a Si substrate, a SiC substrate, or a wide bandgap semiconductor substrate, and has a second source electrode 16, a second drain electrode 17, and a second gate electrode 18.

[0024] In each second switching element 6, the second source electrode 16 and the second drain electrode 17 form a pair of second main electrodes, and the second gate electrode 18 forms a second control electrode that controls the current flowing between the pair of second main electrodes. Each second switching element 6 includes a second diode 19 connected in reverse bias between the second drain electrode 17 and the second source electrode 16.

[0025] Each second switching element 6 is connected between the output side terminal 2 and the low voltage side terminal 4 by having the second drain electrode 17 electrically connected to the output side terminal 2 and the second source electrode 16 electrically connected to the low voltage side terminal 4.

[0026] The output terminal 2 is also a common terminal commonly connected to the first source electrode 10 of the first switching element 5 and the second drain electrode 17 of the second switching element 6. The second gate electrodes 18 of the second switching elements 6 are commonly electrically connected to a second gate terminal 20 (second control terminal) on the low-voltage side.

[0027] The second gate terminal 20 is a terminal for driving and controlling each second switching element 6 (each second gate electrode 18). The second source electrodes 16 of each second switching element 6 are electrically connected in common to the low-voltage side terminal 4 as well as to a low-voltage side second source sense terminal 21. The second source sense terminal 21 is a potential detection terminal for detecting the potential of the second source electrode 16.

[0028] The semiconductor power module 1 according to this embodiment is configured as an inverter module for driving one of the U, V, and W phases in a three-phase motor having, for example, U, V, and W. Therefore, by providing three semiconductor power modules 1 corresponding to the U, V, and W phases, an inverter device for driving a three-phase motor can be provided.

[0029] In the inverter device, a DC power supply is connected between the high-voltage side terminal 3 and the low-voltage side terminal 4 of each semiconductor power module 1, and a three-phase motor is connected as a load to the output side terminal 2 of each semiconductor power module 1. A DC voltage of, for example, 500 V or more and 2000 V or less is applied between the high-voltage side terminal 3 and the low-voltage side terminal 4, with the low-voltage side terminal 4 side being the reference potential.

[0030] In the inverter device, the first switching element 5 and the second switching element 6 of each semiconductor power module 1 are driven and controlled according to a predetermined switching pattern. This converts the DC voltage into a three-phase AC voltage and supplies it to the three-phase motor. In this way, the three-phase motor is sinusoidally driven.

[0031] Next, the external appearance of the semiconductor power module 1 will be specifically described with reference to FIGS.

[0032] Fig. 2 is a perspective view of the semiconductor power module 1 of Fig. 1 as seen from above. Fig. 3 is a perspective view of the semiconductor power module 1 of Fig. 2 as seen from below.

[0033] The semiconductor power module 1 includes a rectangular parallelepiped package body 31. The package body 31 includes an upper surface 32 that is rectangular in plan view, a lower surface 33 that has the same shape as the upper surface 32, and four side surfaces 34 that connect the upper surface 32 and the lower surface 33.

[0034] For convenience of explanation, the +X direction and −X direction, the +Y direction and −Y direction, and the +Z direction and −Z direction shown in FIGS. 2 and 3 may be used below.

[0035] The +X direction and the -X direction are two directions along one side of the package body 31, and are collectively referred to simply as the "X direction." The +Y direction and the -Y direction are two directions along another side of the package body 31 that is perpendicular to the side, and are collectively referred to simply as the "Y direction." The +Z direction and the -Z direction are two directions along the thickness direction of the package body 31, and are collectively referred to simply as the "Z direction."

[0036] When the package main body 31 is placed on a horizontal plane, the X direction and the Y direction are two horizontal directions along two horizontal lines (X axis and Y axis) that are perpendicular to each other, and the Z direction is a vertical direction along a vertical line (Z axis).

[0037] The package body 31 is made of a resin material (thermosetting resin material) such as epoxy resin, and seals the plurality of first switching elements 5, the plurality of second switching elements 6, and the like.

[0038] The output terminals 2 are exposed along the +X direction on a side surface 34 of the package body 31. In this embodiment, the output terminals 2 are drawn out from the inside to the outside of the package body 31 in a rectangular shape in plan view.

[0039] The high-voltage side terminal 3 and low-voltage side terminal 4 are exposed along the −X direction on side surface 34, which is the direction opposite to the exposed direction of output-side terminal 2. In other words, output-side terminal 2, high-voltage side terminal 3, and low-voltage side terminal 4 are arranged in positions facing each other with package body 31 in between.

[0040] High-voltage side terminal 3 and low-voltage side terminal 4 are each joined to a portion (first extension portion 74 of insulating substrate 41) of insulating substrate 41, which will be described later. High-voltage side terminal 3 and low-voltage side terminal 4, together with a portion of insulating substrate 41, are drawn out from the inside to the outside of package body 31 in a rectangular shape in plan view.

[0041] As shown in Fig. 2, the low-voltage side terminal 4 is joined to the surface of the insulating substrate 41 on the +Z direction side (hereinafter simply referred to as "surface 42 of insulating substrate 41"). As shown in Fig. 3, the high-voltage side terminal 3 is joined to the surface of the insulating substrate 41 on the -Z direction side (hereinafter simply referred to as "rear surface 43 of insulating substrate 41").

[0042] In the package main body 31, on the side surface 34 on the +Y direction side, which is a direction different from the exposure direction (+X direction) of the output side terminal 2 and the exposure direction (-X direction) of the high voltage side terminal 3 and the low voltage side terminal 4, the aforementioned first gate terminal 14 and first source sense terminal 15, and the aforementioned second gate terminal 20 and second source sense terminal 21 are exposed along the +Y direction.

[0043] The first gate terminal 14, the first source sense terminal 15, the second gate terminal 20, and the second source sense terminal 21 are each joined to a part of an insulating substrate 41 (a second extension portion 75 of the insulating substrate 41) which will be described later.

[0044] The first gate terminal 14, the first source sense terminal 15, the second gate terminal 20 and the second source sense terminal 21, together with a part of the insulating substrate 41 (the second extension portion 75 of the insulating substrate 41), are pulled out in a strip shape (rectangular shape in plan view) from the inside to the outside of the package main body 31.

[0045] The second gate terminal 20 and the second source sense terminal 21 are bonded to a front surface 42 of the insulating substrate 41, as shown in Figure 2. The first gate terminal 14 and the first source sense terminal 15 are bonded to a rear surface 43 of the insulating substrate 41, as shown in Figure 3.

[0046] 3, a heat dissipation member 35 is exposed on the lower surface 33 of the package body 31. The heat dissipation member 35 dissipates heat generated by the plurality of first switching elements 5 and the plurality of second switching elements 6 to the outside.

[0047] Next, the internal structure of the semiconductor power module 1 will be specifically described with reference to FIGS.

[0048] Fig. 4 is an exploded perspective view showing the internal structure of the semiconductor power module 1 of Fig. 1. Fig. 5 is a plan view showing the internal structure of the semiconductor power module 1 of Fig. 1. Fig. 6 is a side view showing the internal structure of the semiconductor power module 1 of Fig. 1. Fig. 7 is an enlarged view of region VII of Fig. 6. Fig. 8 is a cross-sectional view taken along line VIII-VIII of Fig. 7.

[0049] 4 to 6, semiconductor power module 1 includes an insulating substrate (insulating member) 41. Insulating substrate 41 has a front surface 42 and a back surface 43. Low-voltage side terminals 4 are arranged on the front surface 42 side of insulating substrate 41. Output side terminals 2 are arranged on the back surface 43 side of insulating substrate 41.

[0050] High-voltage side terminal 3 is arranged on rear surface 43 of insulating substrate 41. A plurality of first switching elements 5 electrically connected to output side terminal 2 and high-voltage side terminal 3, and a plurality of second switching elements 6 electrically connected to output side terminal 2 and low-voltage side terminal 4 are arranged on rear surface 43 of insulating substrate 41.

[0051] Semiconductor power module 1 has a structure in which high-voltage side terminal 3 and low-voltage side terminal 4 face each other across insulating substrate 41. Hereinafter, high-voltage side terminal 3 and low-voltage side terminal 4 and their surrounding structure will be specifically described.

[0052] Referring to FIG. 4, the semiconductor power module 1 of this embodiment comprises a first unit U1 including a plurality of first switching elements 5, a plurality of second switching elements 6, and an output side terminal 2, and a second unit U2 including an insulating substrate 41, a high-voltage side terminal 3, and a low-voltage side terminal 4, with the second unit U2 stacked on top of the first unit U1.

[0053] 4 to 6, the first unit U1 includes a support substrate (support member) 44 having a rectangular shape in a planar view, a first conductor pattern 45 formed on the support substrate 44, a plurality of first switching elements 5 arranged on the first conductor pattern 45, a plurality of second switching elements 6 arranged on the first conductor pattern 45, and an output side terminal 2 arranged on the first conductor pattern 45.

[0054] Support substrate 44 includes a surface in the +Z direction (hereinafter simply referred to as "surface 46 of support substrate 44") and a surface in the -Z direction (hereinafter simply referred to as "rear surface 47 of support substrate 44"). Support substrate 44 is disposed on the rear surface 43 side of insulating substrate 41 at a distance from insulating substrate 41, and supports first switching element 5 and second switching element 6 on the surface 46 side.

[0055] The support substrate 44 has a thickness of, for example, 5 mm or less. The support substrate 44 may have a thickness of 0.3 mm or more and 0.7 mm or less. The support substrate 44 may be an inorganic insulating substrate such as ceramic (e.g., AlN, SiN, SiO2), or an organic insulating substrate such as resin (e.g., epoxy resin).

[0056] First conductor pattern 45 is a conductor film made of, for example, copper (Cu), and is directly bonded to surface 46 of support substrate 44. First conductor pattern 45 includes first high-voltage-side conductor pattern 48 that electrically connects high-voltage-side terminal 3 and first switching element 5, and first output-side conductor pattern 49 that electrically connects output-side terminal 2 and second switching element 6.

[0057] First high-voltage conductor pattern 48 is disposed at the end of support substrate 44 on the -X direction side, and is formed in a rectangular shape in plan view extending along the Y direction. On the other hand, first output conductor pattern 49 is disposed at the end of support substrate 44 on the +X direction side, and is formed in a rectangular shape in plan view extending along the Y direction. The width in the X direction of first output conductor pattern 49 is set to a value larger than the width in the X direction of first high-voltage conductor pattern 48.

[0058] 4 and 5, a plurality of first switching elements 5 are joined onto first high-voltage side conductor pattern 48. The plurality of first switching elements 5 are arranged so as to be aligned in a line along the Y direction.

[0059] 7 and 8, each first switching element 5 is a so-called vertical MISFET including a first element body 52 having a first element front surface 50 in the +Z direction on which the first source electrode 10 and the first gate electrode 12 are arranged, and a first element back surface 51 in the -Z direction on which the first drain electrode 11 is arranged. The first element body 52 includes a Si substrate, a SiC substrate, or a wide bandgap semiconductor substrate.

[0060] In this embodiment, four first source electrodes 10 and one first gate electrode 12 are formed on the first element surface 50. Each first switching element 5 is bonded to the first high-voltage side conductor pattern 48 with the first element back surface 51 of the first element body portion 52 facing the surface 46 of the support substrate 44.

[0061] Each first switching element 5 is joined to the first high-voltage side conductor pattern 48 by joining the first drain electrode 11 and the first high-voltage side conductor pattern 48 via a first conductive bonding material 53. The first conductive bonding material 53 may be solder.

[0062] 4 and 5, a plurality of second switching elements 6 are joined onto the first output-side conductor pattern 49. The second switching elements 6 are aligned in a row along the Y direction and arranged to face each of the first switching elements 5 in a one-to-one correspondence in the X direction.

[0063] 7 and 8, each second switching element 6 is a so-called vertical MISFET including a second element body portion 56 having a second element front surface 54 in the +Z direction on which the second source electrode 16 and the second gate electrode 18 are arranged, and a second element back surface 55 in the -Z direction on which the second drain electrode 17 is arranged. This second element body portion 56 includes a Si substrate, a SiC substrate, or a wide bandgap semiconductor substrate.

[0064] In this embodiment, four second source electrodes 16 and one second gate electrode 18 are formed on the second element surface 54. Each second switching element 6 is bonded to the first output-side conductor pattern 49 with the second element back surface 55 of the second element body portion 56 facing the surface 46 of the support substrate 44.

[0065] Each second switching element 6 is joined to the first output-side conductor pattern 49 by joining the second drain electrode 17 and the first output-side conductor pattern 49 via a second conductive bonding material 57. The second conductive bonding material 57 may be solder.

[0066] 4 and 5, the output side terminal 2 is arranged at the end side in the +X direction of the support substrate 44 with a gap therebetween from each second switching element 6, and is joined to the longitudinal center of the first output side conductor pattern 49.

[0067] Output side terminal 2 has a thickness greater than that of high voltage side terminal 3 or low voltage side terminal 4. As described above, output side terminal 2 is electrically connected in common to first switching element 5 and second switching element 6.

[0068] Therefore, from the viewpoint of suppressing an increase in resistance, it is preferable that output terminal 2 has a thickness at least equal to or greater than the total thickness of high-voltage terminal 3 and low-voltage terminal 4.

[0069] In this embodiment, the output terminal 2 is formed in the shape of a rectangular plate or block extending in the X direction in a plan view, and has a plurality of notches 59 at an end 58 on the -X direction side. In this embodiment, the plurality of notches 59 are each formed in the shape of a groove extending in the same direction (X direction).

[0070] An end portion 58 of the output terminal 2 is joined to the first output-side conductor pattern 49 via a third conductive bonding material 60. The third conductive bonding material 60 may be solder. In a state in which the end portion 58 of the output terminal 2 and the first output-side conductor pattern 49 are joined by the third conductive bonding material 60, the third conductive bonding material 60 enters into a plurality of notches 59 formed in the end portion 58.

[0071] The first unit U1 further includes the heat dissipation member 35 described above, which is disposed on the rear surface 47 side of the support substrate 44. In this embodiment, the heat dissipation member 35 is formed of a conductor film made of copper (Cu) that is directly bonded to the rear surface 47 of the support substrate 44 and has a rectangular shape in a plan view, and covers almost the entire area of ​​the rear surface 47 of the support substrate 44 except for the edge portions.

[0072] The heat generated from the plurality of first switching elements 5 and the plurality of second switching elements 6 is transferred to the heat dissipation member 35 via the first conductor pattern 45 and the support substrate 44, and is dissipated to the outside.

[0073] 4 to 6, the second unit U2 includes the aforementioned insulating substrate 41, a second conductor pattern 71 arranged on the back surface 43 side of the insulating substrate 41, and a third conductor pattern 72 arranged on the front surface 42 side of the insulating substrate 41.

[0074] Insulating substrate 41 has a thickness of, for example, 5 mm or less. Insulating substrate 41 may have a thickness of 0.3 mm or more and 0.7 mm or less. Insulating substrate 41 may be an inorganic insulating substrate such as ceramic (e.g., AlN, SiN, SiO2), or an organic insulating substrate such as resin (e.g., epoxy resin).

[0075] The insulating substrate 41 includes a main body portion 73 having a rectangular shape in plan view that faces the surface 46 of the support substrate 44 in plan view, a first extension portion 74 that extends from an end portion of the main body portion 73 in the −X direction along the −X direction to an area outside the support substrate 44, and a second extension portion 75 that extends from an end portion of the main body portion 73 in the +Y direction along the +Y direction to an area outside the support substrate 44. The main body portion 73, the first extension portion 74, and the second extension portion 75 form the insulating substrate 41 in an L-shape in plan view.

[0076] The main body 73 of the insulating substrate 41 is disposed so as to face the first high-voltage side conductor pattern 48 and the first output side conductor pattern 49 .

[0077] The main body portion 73 of the insulating substrate 41 includes a plurality of (five in this embodiment) first removal regions 76 that expose the first element surfaces 50 of each first switching element 5 in a planar view, a second removal region 77 that exposes each second switching element 6, and a plurality of (five in this embodiment) third removal regions 78 that selectively expose the ends of the first output side conductor pattern 49 on the -X direction side.

[0078] The first removal region 76, the second removal region 77, and the third removal region 78 are regions formed by selectively removing portions of the insulating substrate 41, and each exposes a component arranged on the −Z direction side of the insulating substrate 41. The first removal region 76, the second removal region 77, and the third removal region 78 each include an opening and / or a notch.

[0079] In this embodiment, each first removal region 76 consists of an opening that is rectangular in plan view and exposes each first switching element 5 one by one in a one-to-one correspondence, and is formed so as to be aligned in a row at equal intervals along the Y direction.

[0080] Instead of an opening, each first removal region 76 may be a cutout portion that is rectangular in plan view and exposes each of the first switching elements 5 in a one-to-one correspondence. Instead of multiple first removal regions 76, multiple or one first removal region 76 may be formed, each of which is made up of openings and / or cutout portions that are rectangular in plan view and extend in the Y direction so as to expose two or more first switching elements 5 or all of the first switching elements 5 collectively.

[0081] In this embodiment, the second removal region 77 is formed by the periphery of the insulating substrate 41 on the +X direction side, and in addition to exposing the multiple second switching elements 6, the end of the first output side conductor pattern 49 on the +X direction side is also exposed.

[0082] Instead of the second removal area 77 formed by the periphery of the insulating substrate 41 on the +X direction side, a plurality of second removal areas 77 may be formed, each consisting of a rectangular opening and / or cutout portion in a plan view that exposes each second switching element 6 one by one in a one-to-one correspondence, and aligned in a row along the Y direction.

[0083] Of course, multiple or one second removal regions 77 may be formed, each consisting of a rectangular opening and / or cutout extending in the Y direction in a plan view so as to expose two or more second switching elements 6 or all of the second switching elements 6 at once.

[0084] The multiple third removal regions 78 are aligned in a row along the Y direction and are formed so as to face the multiple first removal regions 76 in a one-to-one correspondence in the X direction. Multiple or one third removal regions 78 may be formed, each of which is made up of an opening and / or a cutout that is rectangular in plan view and extends in the Y direction so as to face two or more first switching elements 5 or all of the first switching elements 5 in the X direction.

[0085] The first extension portion 74 of the insulating substrate 41 is a portion that does not face the support substrate 44 in a plan view, and in this embodiment, is formed in a rectangular shape in a plan view. The width of the first extension portion 74 of the insulating substrate 41 in the Y direction is set to a value smaller than the width of the main body portion 73 in the Y direction.

[0086] The second extension portion 75 of the insulating substrate 41 is a portion that does not face the support substrate 44 in a plan view, and in this embodiment, is formed in a rectangular shape in a plan view. The width of the second extension portion 75 of the insulating substrate 41 in the X direction is set to a value smaller than the width of the main body portion 73 in the X direction.

[0087] Referring to FIG. 4, second conductor pattern 71 disposed on rear surface 43 side of insulating substrate 41 is a conductor film made of copper (Cu), for example, and is directly bonded to rear surface 43 of insulating substrate 41.

[0088] The second conductor pattern 71 integrally includes a high-voltage side terminal 3 joined to the first extension portion 74 of the insulating substrate 41, a second high-voltage side conductor pattern 79 joined to the main body portion 73 of the insulating substrate 41 and electrically connected to the high-voltage side terminal 3 and the first high-voltage side conductor pattern 48 (first switching element 5), and a second output side conductor pattern 80 electrically connected to the first output side conductor pattern 49.

[0089] High-voltage side terminal 3 is disposed in first extension portion 74 of insulating substrate 41 at a position spaced inward from the periphery of first extension portion 74, and is formed in a quadrangular shape in plan view.

[0090] The periphery of the high-voltage side terminal 3 is positioned at a position at least 2 mm away from the periphery of the first extension portion 74 of the insulating substrate 41, thereby creating an insulating region between the periphery of the high-voltage side terminal 3 and the periphery of the first extension portion 74 of the insulating substrate 41.

[0091] Second high-voltage side conductor pattern 79 is joined to the end of main body 73 on the −X direction side, and includes first high-voltage side portion 81 connected to high-voltage side terminal 3. First high-voltage side portion 81 is electrically connected to first high-voltage side conductor pattern 48 via fourth conductive bonding material 83.

[0092] The second high-voltage side conductor pattern 79 includes comb-like second high-voltage side portions 82 that are drawn out from the first high-voltage side portions 81 toward the sides of the first switching elements 5 (first removal regions 76).

[0093] The second output conductor pattern 80 is disposed at the end of the insulating substrate 41 on the +X direction side, and is formed in a rectangular shape in plan view extending in the Y direction. The second output conductor pattern 80 is electrically connected to the first output conductor pattern 49 via a fifth conductive bonding material 85 in a region between the second switching element 6 and the end of the first output conductor pattern 49 on the −X direction side.

[0094] The second output side conductor pattern 80 has multiple (five in this embodiment) fourth removal areas 84 that selectively expose the first output side conductor pattern 49 at positions corresponding to each of the multiple third removal areas 78 of the insulating substrate 41.

[0095] The end portion of the second output conductor pattern 80 on the −X direction side is formed in a comb shape by these multiple fourth removal regions 84. The fourth removal regions 84 may be openings and / or cutouts that are rectangular in plan view and extend in the Y direction.

[0096] The end of the first output conductor pattern 49 on the −X direction side is selectively exposed by the third removal area 78 of the insulating substrate 41 and the fourth removal area 84 of the second output conductor pattern 80 .

[0097] The third conductive pattern 72 disposed on the surface 42 side of the insulating substrate 41 is a conductive film made of, for example, copper (Cu), and is directly bonded to the surface 42 of the insulating substrate 41.

[0098] The third conductor pattern 72 integrally includes a low-voltage side terminal 4 joined to the second extension portion 75 of the insulating substrate 41, and a low-voltage side conductor pattern 86 joined to the main body portion 73 of the insulating substrate 41 and electrically connected to the low-voltage side terminal 4.

[0099] Low-voltage side terminal 4 is arranged in first extension portion 74 of insulating substrate 41 at a position spaced inward from the periphery of first extension portion 74, and is formed in a rectangular shape in plan view. Low-voltage side terminal 4 faces high-voltage side terminal 3 with first extension portion 74 of insulating substrate 41 in between.

[0100] In this embodiment, the low-voltage side terminal 4 is formed in a rectangular shape in plan view with the same area and shape as the high-voltage side terminal 3, and its entirety faces the high-voltage side terminal 3 across the first extension portion 74 of the insulating substrate 41.

[0101] The periphery of the low-voltage side terminal 4 is positioned at a position at least 2 mm away from the periphery of the first extension portion 74 of the insulating substrate 41, thereby creating an insulating area between the periphery of the low-voltage side terminal 4 and the periphery of the first extension portion 74 of the insulating substrate 41.

[0102] The low-voltage side conductor pattern 86 includes a first low-voltage side portion 87 joined to the end portion on the -X direction side of the main body portion 73 and connected to the low-voltage side terminal 4, a second low-voltage side portion 88 joined to the end portion on the +X direction side of the main body portion 73, and a third low-voltage side portion 89 connecting these.

[0103] The third low-voltage side portion 89 connects the first low-voltage side portion 87 and the second low-voltage side portion 88 so as to avoid the plurality of first removal regions 76 and the plurality of third removal regions 78.

[0104] Low-voltage side conductor pattern 86 faces second high-voltage side conductor pattern 79 across main body 73 of insulating substrate 41. More specifically, first low-voltage side portion 87 of low-voltage side conductor pattern 86 faces first high-voltage side portion 81 of second high-voltage side conductor pattern 79 across main body 73 of insulating substrate 41. Third low-voltage side portion 89 of low-voltage side conductor pattern 86 faces second high-voltage side portion 82 of second high-voltage side conductor pattern 79 across main body 73 of insulating substrate 41.

[0105] 4 and 5, the second conductor pattern 71 arranged on the rear surface 43 side of the insulating substrate 41 further includes the above-mentioned first gate terminal 14 on the high voltage side and first source sense terminal 15 on the high voltage side.

[0106] The first gate terminal 14 and the first source sense terminal 15 are arranged adjacent to each other between the second high-voltage side conductor pattern 79 and the second output side conductor pattern 80. In this embodiment, the first gate terminal 14 is arranged on the −X direction side, and the first source sense terminal 15 is arranged on the +X direction side.

[0107] The first gate terminal 14 and the first source sense terminal 15 are each formed in a strip shape (rectangular shape in plan view) extending along the Y direction, and are drawn out from the main body portion 73 of the insulating substrate 41 to the second extension portion 75.

[0108] In the first gate terminal 14 and the first source sense terminal 15, the portions that are extended to the second extension portion 75 of the insulating substrate 41 are each positioned at a distance inward from the periphery of the second extension portion 75.

[0109] The main body portion 73 of the insulating substrate 41 is selectively formed with a plurality (five in this embodiment) of first contact holes 92 that selectively expose the first gate terminal 14 and a plurality (five in this embodiment) of second contact holes 93 that selectively expose the first source sense terminal 15.

[0110] The plurality of first contact holes 92 are provided one for each region between the first removal region 76 and the third removal region 78. The plurality of second contact holes 93 are provided one for each region between the first removal region 76 and the third removal region 78 so as to be adjacent to the first contact holes 92.

[0111] The third conductor pattern 72 arranged on the surface 42 side of the insulating substrate 41 includes a plurality of (five in this embodiment) gate pads 94 connected to the first gate terminal 14 via each first contact hole 92, and a plurality of (five in this embodiment) source sense pads 95 connected to the first source sense terminal 15 via each second contact hole 93.

[0112] The third conductor pattern 72 includes the aforementioned low-voltage side second gate terminal 20 and low-voltage side second source sense terminal 21. The second gate terminal 20 and the second source sense terminal 21 are each arranged at the end on the +X direction side of the insulating substrate 41 (the region between the +X direction side periphery of the insulating substrate 41 and the second low-voltage side portion 88 of the low-voltage side conductor pattern 86). In this embodiment, the second gate terminal 20 is arranged on the -X direction side, and the second source sense terminal 21 is arranged on the +X direction side.

[0113] The second gate terminal 20 and the second source sense terminal 21 are formed in a strip shape (rectangular shape in plan view) extending along the Y direction, and are each drawn out from the main body portion 73 of the insulating substrate 41 to the second extension portion 75.

[0114] In the second gate terminal 20 and the second source sense terminal 21, the portions that are drawn out to the second extension portion 75 of the insulating substrate 41 are each positioned at a distance inward from the periphery of the second extension portion 75.

[0115] In this embodiment, the second gate terminal 20 and the second source sense terminal 21 are joined at positions that do not overlap with the first gate terminal 14 and the first source sense terminal 15 in a plan view (see also FIGS. 2 and 3).

[0116] The first conductor pattern 45 arranged on the surface 46 side of the support substrate 44 includes a dummy gate terminal 96 provided in correspondence with the first gate terminal 14 and a dummy source sense terminal 97 provided in correspondence with the first source sense terminal 15.

[0117] The dummy gate terminal 96 and the dummy source sense terminal 97 are disposed between the first high-voltage side conductor pattern 48 and the first output side conductor pattern 49 , and are entirely located on the surface 46 of the support substrate 44 .

[0118] Referring to Figures 5, 7 and 8, the first source electrode 10 of each first switching element 5 is electrically connected to a first output side conductor pattern 49 bonded to the surface 46 of the support substrate 44 via a first bonding wire 101 as a connecting member.

[0119] The first bonding wire 101 is arranged on the surface 42 side of the insulating substrate 41, and connects the first source electrode 10 of each first switching element 5 to the first output side conductor pattern 49 via the first removal area 76 and the third removal area 78 (the fourth removal area 84 of the second output side conductor pattern 80) of the insulating substrate 41.

[0120] Therefore, in each first switching element 5, the first source electrode 10 is electrically connected to the output terminal 2 via the first bonding wire 101 and the first output conductor pattern 49.

[0121] In each first switching element 5, first drain electrode 11 is electrically connected to high-voltage side terminal 3 via first high-voltage side conductor pattern 48 and second high-voltage side conductor pattern 79. In this way, each first switching element 5 is electrically connected between output side terminal 2 and high-voltage side terminal 3.

[0122] The first gate electrode 12 of each first switching element 5 is electrically connected to the gate pad 94 via a second bonding wire 102 serving as a connecting member, thereby electrically connecting the first gate electrode 12 of each first switching element 5 to the first gate terminal 14.

[0123] At least one first source electrode 10 of each first switching element 5 is electrically connected to the source sense pad 95 via a third bonding wire 103 serving as a connecting member, thereby electrically connecting at least one first source electrode 10 of each first switching element 5 to the first source sense terminal 15.

[0124] On the other hand, the second source electrode 16 of each second switching element 6 is electrically connected to a low-voltage side conductor pattern 86 (second low-voltage side portion 88 of the low-voltage side conductor pattern 86) joined to the surface 42 of the insulating substrate 41 via a fourth bonding wire 104 as a connecting member.

[0125] The fourth bonding wire 104 is arranged on the surface 42 side of the insulating substrate 41 and connects the second source electrode 16 of each second switching element 6 to the low-voltage side conductor pattern 86 via the second removal region 77 of the insulating substrate 41.

[0126] Therefore, in each second switching element 6, the second source electrode 16 is electrically connected to the low-voltage side terminal 4 via the fourth bonding wire 104 and the low-voltage side conductor pattern 86.

[0127] In each second switching element 6, the second drain electrode 17 is electrically connected to the output terminal 2 via the first output conductor pattern 49. In this way, each second switching element 6 is electrically connected between the output terminal 2 and the low-voltage terminal 4.

[0128] The second gate electrode 18 of each second switching element 6 is electrically connected to the second gate terminal 20 via a fifth bonding wire 105 serving as a connecting member. The fifth bonding wire 105 is disposed on the front surface 42 side of the insulating substrate 41, and connects the second gate electrode 18 of each second switching element 6 to the second gate terminal 20 via the second removed region 77 of the insulating substrate 41.

[0129] At least one second source electrode 16 of each second switching element 6 is electrically connected to the second source sense terminal 21 via a sixth bonding wire 106 serving as a connecting member.

[0130] The sixth bonding wire 106 is arranged on the surface 42 side of the insulating substrate 41 and connects at least one second source electrode 16 of each second switching element 6 to the second source sense terminal 21 via the second removal region 77 of the insulating substrate 41.

[0131] The package main body 31 seals the insulating substrate 41 and the support substrate 44 so as to selectively expose a portion of the output side terminal 2, a portion of the high-voltage side terminal 3, a portion of the low-voltage side terminal 4, a portion of the first gate terminal 14, a portion of the first source sense terminal 15, a portion of the second gate terminal 20, a portion of the second source sense terminal 21, and the heat dissipation member 35.

[0132] A portion of the high-voltage side terminal 3 and a portion of the low-voltage side terminal 4 are drawn out to the outside of the package body 31 together with a first extension portion 74 of the insulating substrate 41. A portion of the first gate terminal 14, a portion of the first source sense terminal 15, a portion of the second gate terminal 20, and a portion of the second source sense terminal 21 are drawn out to the outside of the package body 31 together with a second extension portion 75 of the insulating substrate 41.

[0133] The package body 31 may be formed by transfer molding or compression molding.

[0134] In the transfer molding method, resin is poured into a mold having a cavity of a predetermined shape in which the insulating substrate 41, etc. are accommodated, thereby forming the package body 31 that selectively seals the insulating substrate 41, etc. Specifically, the insulating substrate 41, etc. means the internal structure of the semiconductor power module 1 excluding the package body 31 (the same applies hereinafter).

[0135] In the compression molding method, resin is immersed in a mold having a cavity of a predetermined shape, and then the insulating substrate 41, etc. is immersed in the resin, or the insulating substrate 41, etc. is accommodated and placed in a mold having a cavity of a predetermined shape, and then resin is immersed in the mold to form the package main body 31 that selectively seals the insulating substrate 41, etc.

[0136] The package body 31 may have a resin housing (resin case) having an internal space, and the insulating substrate 41 and the like may be housed in the internal space of the housing.

[0137] As described above, according to the semiconductor power module 1, one half-bridge circuit 7 is formed by the output side terminal 2, the high-voltage side terminal 3, the low-voltage side terminal 4, a plurality of first switching elements 5 connected to the output side terminal 2 and the high-voltage side terminal 3, and a plurality of second switching elements 6 connected to the output side terminal 2 and the low-voltage side terminal 4.

[0138] In this half-bridge circuit 7, the plurality of first switching elements 5 constitute an upper arm 8 on the high-voltage side, and the plurality of second switching elements 6 constitute a lower arm 9 on the low-voltage side.

[0139] In this semiconductor power module 1, a current path from the high-voltage side terminal 3 to the output side terminal 2 via each first switching element 5 is formed on the back surface 43 side of the insulating substrate 41, and a current path from the output side terminal 2 to the low-voltage side terminal 4 via each second switching element 6 is formed on the front surface 42 side of the insulating substrate 41.

[0140] Therefore, the direction of current flowing through high-voltage side terminal 3 and the direction of current flowing through low-voltage side terminal 4 are opposite to each other across insulating substrate 41.

[0141] Furthermore, the distance between the high-voltage side terminal 3 and the low-voltage side terminal 4 can be set based on the thickness (5 mm or less in this embodiment) of the insulating substrate 41 on which the high-voltage side terminal 3 and the low-voltage side terminal 4 are arranged opposite each other, so that the high-voltage side terminal 3 and the low-voltage side terminal 4 can be arranged close to each other while maintaining insulation.

[0142] This allows the magnetic field generated at high-voltage side terminal 3 and the magnetic field generated at low-voltage side terminal 4 to be effectively offset, thereby effectively reducing the mutual inductance component between high-voltage side terminal 3 and low-voltage side terminal 4. Therefore, it is possible to provide a semiconductor power module 1 that can effectively reduce the inductance component.

[0143] In the semiconductor power module 1 according to this embodiment, the insulating substrate 41 selectively includes, in a plan view, a first removal region 76 that exposes the first switching element 5 and a second removal region 77 that exposes the second switching element 6.

[0144] Therefore, the heat generated by the first switching element 5 can be dissipated from the back surface 43 side to the front surface 42 side of the insulating substrate 41 via the first removal area 76, and the heat generated by the second switching element 6 can be dissipated from the back surface 43 side to the front surface 42 side of the insulating substrate 41 via the second removal area 77.

[0145] This effectively suppresses temperature rises in the first switching element 5 and the second switching element 6. In particular, in a configuration in which the support substrate 44 is disposed on the −Z direction side of the insulating substrate 41, as in the semiconductor power module 1 according to this embodiment, by providing the insulating substrate 41 with the first removal region 76 and the second removal region 77, it is possible to effectively suppress heat buildup between the insulating substrate 41 and the support substrate 44.

[0146] In addition, in the semiconductor power module 1 according to this embodiment, the heat dissipation member 35 is provided on the rear surface 47 side of the support substrate 44. Therefore, the heat generated in the first switching element 5 and the heat generated in the second switching element 6 can be efficiently dissipated to the outside via the support substrate 44 and the heat dissipation member 35. Therefore, it is possible to provide a semiconductor power module 1 that can effectively suppress temperature rises in the first switching element 5 and the second switching element 6.

[0147] Although the embodiment of the present invention has been described above, the present invention can also be embodied in other forms.

[0148] For example, in the above-described embodiment, an example has been described in which one half-bridge circuit 7 is configured by a plurality of first switching elements 5 and a plurality of second switching elements 6. However, the number of first switching elements 5 and the number of second switching elements 6 are not limited to this.

[0149] Therefore, one half-bridge circuit 7 may be configured by one first switching element 5 and one second switching element 6. One half-bridge circuit 7 may be configured by two or more first switching elements 5 and two or more second switching elements 6.

[0150] In the above embodiment, an example was described in which MISFETs were used as the first switching element 5 and the second switching element 6, but the configuration shown in FIG. 9 or FIG. 10 may also be used.

[0151] Below, the configuration of Fig. 9 will be explained, followed by the configuration of Fig. 10. Fig. 9 is an electric circuit diagram showing the electrical structure of a first modified example of the semiconductor power module 1 of Fig. 1. In Fig. 9, the same reference numerals are used for the components shown in Fig. 1 and the like, and their explanations will be omitted.

[0152] In the embodiment shown in FIG. 9, an IGBT (Insulated Gate Bipolar Transistor) is used as the first switching element 5 and the second switching element 6 instead of the MISFET.

[0153] That is, the half-bridge circuit 7 is configured by IGBTs. The first switching element 5 and the second switching element 6 may include IGBTs formed on a Si substrate, a SiC substrate, or a wide bandgap type semiconductor substrate.

[0154] In this case, the first switching element 5 has a first emitter electrode 110 instead of the aforementioned first source electrode 10, a first collector electrode 111 instead of the aforementioned first drain electrode 11, and a first gate electrode 112 instead of the aforementioned first gate electrode 12.

[0155] In each first switching element 5, the first emitter electrode 110 and the first collector electrode 111 constitute a pair of first main electrodes, and the first gate electrode 112 constitutes a first control electrode that controls the current flowing between the pair of first main electrodes.

[0156] The second switching element 6 has a second emitter electrode 113 instead of the second source electrode 16 described above, a second collector electrode 114 instead of the second drain electrode 17 described above, and a second gate electrode 115 instead of the second gate electrode 18 described above.

[0157] In each second switching element 6, the second emitter electrode 113 and the second collector electrode 114 form a pair of first main electrodes, and the second gate electrode 115 forms a first control electrode that controls the current flowing between the pair of first main electrodes.

[0158] In the configuration shown in FIG. 9, the first gate electrode 112 is electrically connected to the first gate terminal 116 instead of the first gate terminal 14, and the first emitter electrode 110 is electrically connected to the first emitter sense terminal 117 instead of the first source sense terminal 15.

[0159] The second gate electrode 115 is electrically connected to the second gate terminal 118 instead of the second gate terminal 20, and the second emitter electrode 113 is electrically connected to the second emitter sense terminal 119 instead of the second source sense terminal 21. Even with this configuration, it is possible to achieve the same effects as those described in the above-mentioned embodiments.

[0160] Fig. 10 is an electric circuit diagram showing the electrical structure of a second modified example of the semiconductor power module 1 of Fig. 1. In Fig. 10, the same reference numerals are used for the components shown in Fig. 1 and the like, and the description thereof will be omitted.

[0161] In the embodiment shown in FIG. 10, a BJT (Bipolar Junction Transistor) is used as the first switching element 5 and the second switching element 6 instead of the MISFET.

[0162] That is, the half-bridge circuit 7 is configured by BJTs. The first switching element 5 and the second switching element 6 may include BJTs formed on a Si substrate, a SiC substrate, or a wide bandgap type semiconductor substrate.

[0163] In this case, the first switching element 5 has a first emitter electrode 120 instead of the aforementioned first source electrode 10, a first collector electrode 121 instead of the aforementioned first drain electrode 11, and a first base electrode 122 instead of the aforementioned first gate electrode 12.

[0164] In each first switching element 5, the first emitter electrode 120 and the first collector electrode 121 constitute a pair of first main electrodes, and the first base electrode 122 constitutes a first control electrode that controls the current flowing between the pair of first main electrodes.

[0165] The second switching element 6 has a second emitter electrode 123 instead of the second source electrode 16 described above, a second collector electrode 124 instead of the second drain electrode 17 described above, and a second base electrode 125 instead of the second gate electrode 18 described above.

[0166] In each second switching element 6, the second emitter electrode 123 and the second collector electrode 124 form a pair of first main electrodes, and the second base electrode 125 forms a first control electrode that controls the current flowing between the pair of first main electrodes.

[0167] In the configuration shown in FIG. 10, the first base electrode 122 is electrically connected to the first base terminal 126 instead of the first gate terminal 14, and the first emitter electrode 120 is electrically connected to the first emitter sense terminal 127 instead of the first source sense terminal 15.

[0168] The second base electrode 125 is electrically connected to the second base terminal 128 instead of the second gate terminal 20, and the second emitter electrode 123 is electrically connected to the second emitter sense terminal 129 instead of the second source sense terminal 21. Even with this configuration, it is possible to achieve the same effects as those described in the above-mentioned embodiments.

[0169] The above-mentioned MISFET, IGBT, and BJT are preferably formed on a SiC substrate or a wide bandgap semiconductor substrate out of the above-mentioned Si substrate, SiC substrate, or wide bandgap semiconductor substrate. The following provides additional information about wide bandgap semiconductor substrates.

[0170] More specifically, a wide bandgap semiconductor substrate means a substrate formed from a semiconductor material having a bandgap larger than that of silicon (=approximately 1.0 eV to 1.2 eV).

[0171] Examples of semiconductor materials for wide bandgap semiconductor substrates include III-V group semiconductors containing group III and V elements, nitride semiconductors (e.g., gallium nitride), diamond, etc. The aforementioned SiC substrate is also an example of a wide bandgap semiconductor substrate.

[0172] Below are presented example features extracted from this specification and the accompanying drawings.

[0173] [A1] A semiconductor power module including: an insulating substrate having one surface and another surface; a support substrate having an opposing surface opposing the one surface of the insulating substrate; a first switching element, a second switching element, and an output terminal arranged on the opposing surface of the support substrate; a first power supply terminal arranged on the one surface of the insulating substrate; and a second power supply terminal arranged on the other surface of the insulating substrate so as to face the first power supply terminal across the insulating substrate, the second power supply terminal being applied with a voltage of a magnitude different from that applied to the first power supply terminal, wherein the first power supply terminal, the first switching element, and the output terminal are electrically connected, and the second power supply terminal, the second switching element, and the output terminal are electrically connected, and the output terminal has a thickness greater than a thickness of the first power supply terminal or a thickness of the second power supply terminal.

[0174] [A2] The semiconductor power module according to A1, wherein the thickness of the output side terminal is equal to or greater than the sum of the thickness of the first power terminal and the thickness of the second power terminal.

[0175] [A3] The semiconductor power module according to A1 or A2, wherein a half-bridge circuit is formed by the output side terminal, the first power supply terminal, the second power supply terminal, the first switching element, and the second switching element.

[0176] [A4] The semiconductor power module according to any one of A1 to A3, wherein the direction of current flowing through the first power supply terminal and the direction of current flowing through the second power supply terminal are opposite to each other across the insulating substrate.

[0177] [A5] A semiconductor power module according to any one of A1 to A4, wherein the first power supply terminal is a high-voltage side terminal, and the second power supply terminal is a low-voltage side terminal to which a voltage lower than the voltage applied to the first power supply terminal is applied.

[0178] [A6] The semiconductor power module according to any one of A1 to A5, wherein the support substrate has a back surface opposite to the opposing surface, and the back surface has a removal area for dissipating heat generated from the first switching element and the second switching element.

[0179] [A7] The semiconductor power module according to any one of A1 to A6, wherein a conductor pattern is formed on the opposing surface of the support substrate.

[0180] [A8] The semiconductor power module according to A6, wherein a heat dissipation member is provided on the rear surface of the support substrate.

[0181] [A9] The semiconductor power module according to any one of A1 to A8, wherein the insulating substrate has a thickness of 5 mm or less.

[0182] [A10] A semiconductor power module according to any one of A1 to A9, wherein a conductor pattern is provided on the opposing surface of the support substrate, and a plurality of the first switching elements and a plurality of the second switching elements are arranged on the conductor pattern.

[0183] [A11] The semiconductor power module according to any one of A10, wherein the conductor pattern and the first switching element are electrically connected by a wire.

[0184] [A12] The semiconductor power module according to any one of A1 to A11, further including a resin that seals the insulating substrate and the support substrate so as to selectively expose the output side terminal, the first power supply terminal, and the second power supply terminal, and the first power supply terminal and the second power supply terminal are exposed from the resin together with the insulating substrate.

[0185] [A13] A semiconductor power module according to A12, wherein the first power terminal exposed from the resin is positioned at a position spaced apart inward from the periphery of the insulating substrate exposed from the resin, and the second power terminal exposed from the resin is positioned at a position spaced apart inward from the periphery of the insulating substrate exposed from the resin.

[0186] [A14] A semiconductor power module according to A13, wherein the distance between the periphery of the first power terminal exposed from the resin and the periphery of the insulating substrate exposed from the resin is set to 2 mm or more, and the distance between the periphery of the second power terminal exposed from the resin and the periphery of the insulating substrate exposed from the resin is set to 2 mm or more.

[0187] [A15] The semiconductor power module according to any one of A12 to A14, wherein the output side terminal is arranged in a position facing the first power supply terminal and the second power supply terminal across the resin in a plan view.

[0188] [A16] A semiconductor power module according to any one of A12 to A15, further including a first control terminal that drives and controls the first switching element and a second control terminal that drives and controls the second switching element, and the resin seals the insulating substrate so as to selectively expose the first control terminal and the second control terminal.

[0189] [A17] A semiconductor power module according to A16, wherein the first control terminal and the second control terminal are exposed from the resin in a direction different from the direction in which the output side terminal is exposed from the resin and the direction in which the first power supply terminal and the second power supply terminal are exposed from the resin.

[0190] [A18] A semiconductor power module described in A16 or 17, wherein the first switching element includes a pair of first main electrodes and a first control electrode that controls the current flowing between the pair of first main electrodes, the second switching element includes a pair of second main electrodes and a second control electrode that controls the current flowing between the pair of second main electrodes, the first control terminal is electrically connected to the first control electrode of the first switching element, and the second control terminal is electrically connected to the second control electrode of the second switching element.

[0191] [A19] The semiconductor power module according to any one of A1 to A18, wherein the first switching element and the second switching element include a MISFET, an IGBT, or a BJT.

[0192] [A20] The semiconductor power module according to A19, wherein the MISFET, the IGBT, or the BJT is formed on a Si substrate, a SiC substrate, or a wide bandgap type semiconductor substrate.

[0193] [A21] The semiconductor power module according to any one of A1 to A20, wherein a voltage of 500 V or more is applied between the first power supply terminal and the second power supply terminal.

[0194] [B1] A semiconductor power module comprising: an insulating substrate having one surface and another surface; a support substrate having an opposing surface opposing the one surface of the insulating substrate; a first switching element, a second switching element, and an output terminal arranged on the opposing surface of the support substrate; a first power supply terminal arranged on the one surface of the insulating substrate; a second power supply terminal arranged on the other surface of the insulating substrate so as to face the first power supply terminal across the insulating substrate, the second power supply terminal being applied with a voltage of a magnitude different from that applied to the first power supply terminal; and a resin sealing a portion of each of the terminals, wherein the first power supply terminal, the first switching element, and the output terminal are electrically connected via a wire that exceeds the one surface of the insulating substrate and a conductor pattern formed on the opposing surface of the support substrate, and the second power supply terminal, the second switching element, and the output terminal are electrically connected, and the first power supply terminal and the second power supply terminal that are exposed from the resin are arranged at a distance from a periphery of the insulating substrate that is exposed from the resin.

[0195] [B2] The semiconductor power module according to B1, wherein the insulating substrate has a removal region for dissipating heat generated from the first switching element and the second switching element arranged on the one surface side of the support substrate to the other surface side of the insulating substrate.

[0196] [B3] The semiconductor power module according to B1, wherein the distance between the periphery of the first power terminal exposed from the resin and the periphery of the insulating substrate exposed from the resin is set to 2 mm or more, and the distance between the periphery of the second power terminal exposed from the resin and the periphery of the insulating substrate exposed from the resin is set to 2 mm or more.

[0197] [B4] A semiconductor power module according to any one of B1 to B3, wherein the second power supply terminal and the second switching element are connected via a wire whose height exceeds the one surface of the insulating substrate, and a back electrode of the second switching element is electrically connected to the output side terminal via a conductor pattern formed on the opposing surface of the support substrate.

[0198] [B5] The semiconductor power module according to B1, wherein a half-bridge circuit is formed by the output side terminal, the first power supply terminal, the second power supply terminal, the first switching element, and the second switching element.

[0199] [B6] The semiconductor power module according to B5, wherein the direction of current flowing through the first power supply terminal and the direction of current flowing through the second power supply terminal are opposite to each other across the insulating substrate.

[0200] [B7] A semiconductor power module according to any one of B1 to B6, wherein the first power supply terminal is a high-voltage side terminal, and the second power supply terminal is a low-voltage side terminal to which a voltage lower than the voltage applied to the first power supply terminal is applied.

[0201] [B8] The semiconductor power module according to any one of B1 to B4, wherein the insulating substrate has a thickness of 5 mm or less.

[0202] [B9] The semiconductor power module according to any one of B1 to B8, wherein a plurality of the first switching elements and a plurality of the second switching elements are arranged on the opposing surface of the support substrate.

[0203] [B10] The semiconductor power module according to B1, wherein the output-side terminal is disposed in a position facing the first power supply terminal and the second power supply terminal across the resin in a plan view.

[0204] [B11] The semiconductor power module according to B10, wherein the output side terminal has a thickness greater than a thickness of the first power supply terminal or a thickness of the second power supply terminal.

[0205] [B12] The semiconductor power module according to B11, wherein the output-side terminal has a thickness equal to or greater than the sum of the thickness of the first power supply terminal and the thickness of the second power supply terminal.

[0206] [B13] The semiconductor power module according to B10, further including a first control terminal that drives and controls the first switching element and a second control terminal that drives and controls the second switching element, wherein the resin seals the insulating substrate so as to selectively expose the first control terminal and the second control terminal.

[0207] [B14] The semiconductor power module according to B13, wherein the first control terminal and the second control terminal are exposed from the resin in a direction different from the direction in which the output side terminal is exposed from the resin and the direction in which the first power supply terminal and the second power supply terminal are exposed from the resin.

[0208] [B15] The semiconductor power module according to B1, wherein the first switching element and the second switching element include a MISFET, an IGBT, or a BJT.

[0209] [B16] The semiconductor power module according to B15, wherein the MISFET, the IGBT, or the BJT is formed on a Si substrate, a SiC substrate, or a wide bandgap type semiconductor substrate.

[0210] [B17] The semiconductor power module according to B1, wherein a voltage of 500 V or more is applied between the first power supply terminal and the second power supply terminal.

[0211] [C1] An insulating substrate having one surface and another surface; a support substrate having an opposing surface facing the one surface of the insulating substrate; a first switching element, a second switching element, and an output terminal disposed on the opposing surface of the support substrate; a first power terminal disposed on the one surface side of the insulating substrate; a second power supply terminal that is disposed on the other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, and to which a voltage different from that of the first power supply terminal is applied; a resin that selectively covers the first power supply terminal, the second power supply terminal, and the insulating substrate so as to expose a portion of the first power supply terminal and a portion of the second power supply terminal together with a peripheral edge of the insulating substrate; the first power supply terminal, the first switching element, and the output terminal are electrically connected via conductors to a conductor pattern disposed on the one surface of the insulating substrate and a conductor pattern formed on the opposing surface of the support substrate; the second power supply terminal and the second switching element are electrically connected to a conductor pattern disposed on the other surface of the insulating substrate via a conductor; a portion of the first power terminal exposed from the resin is disposed at a distance from a portion of the periphery of the insulating substrate exposed from the resin; a portion of the second power terminal exposed from the resin is disposed at a distance from a portion of the periphery of the insulating substrate exposed from the resin; a direction of a current flowing through the first power supply terminal and a direction of a current flowing through the second power supply terminal are opposite to each other across the insulating substrate; The semiconductor power module, wherein the output side terminal has a thickness greater than either or both of the first power supply terminal and the second power supply terminal.

[0212] [C2] The semiconductor power module according to C1, wherein the insulating substrate has a removed region that dissipates heat generated on the support substrate side to the other surface side of the insulating substrate.

[0213] [C3] The semiconductor power module according to C1 or C2, wherein the distance between the periphery of the first power terminal exposed from the resin and the periphery of the second power terminal exposed from the resin is set to 2 mm or more via the periphery of the insulating substrate exposed from the resin.

[0214] [C4] A semiconductor power module according to any one of C1 to C3, wherein a half-bridge circuit is configured including the output side terminal, the first power supply terminal, the second power supply terminal, the first switching element, and the second switching element.

[0215] [C5] The first power supply terminal is a high-voltage terminal, The semiconductor power module according to any one of C1 to C4, wherein the second power supply terminal is a low-voltage side terminal.

[0216] [C6] The semiconductor power module according to any one of C1 to C5, wherein the insulating substrate has a thickness of 5 mm or less.

[0217] [C7] The semiconductor power module according to any one of C1 to C6, wherein a plurality of the first switching elements and a plurality of the second switching elements are arranged on the opposing surface of the support substrate.

[0218] [C8] The semiconductor power module according to any one of C1 to C7, wherein the output-side terminal faces the first power supply terminal and the second power supply terminal across the resin in plan view.

[0219] [C9] The semiconductor power module according to any one of C1 to C8, wherein the output side terminal has a thickness equal to or greater than the sum of the thickness of the first power supply terminal and the thickness of the second power supply terminal.

[0220] [C10] A first control terminal that controls driving of the first switching element; The semiconductor power module according to any one of C1 to C9, further comprising: a second control terminal that controls driving of the second switching element.

[0221] [C11] The semiconductor power module according to C10, wherein the resin selectively covers the first control terminal and the second control terminal so as to expose a portion of the first control terminal and a portion of the second control terminal.

[0222] [C12] The semiconductor power module according to C11, wherein the first control terminal and the second control terminal are exposed from the resin in a direction different from the exposure direction of the first power supply terminal from the resin, the exposure direction of the second power supply terminal from the resin, and the exposure direction of the output side terminal from the resin.

[0223] [C13] The first switching element has a Si substrate, The semiconductor power module according to any one of C1 to C12, wherein the second switching element has a Si substrate.

[0224] [C14] The first switching element has a wide bandgap semiconductor substrate, The semiconductor power module according to any one of C1 to C12, wherein the second switching element has a wide bandgap semiconductor substrate.

[0225] [C15] The first switching element has a SiC substrate, The semiconductor power module according to C14, wherein the second switching element has a SiC substrate.

[0226] [C16] The first switching element includes a MISFET, an IGBT, or a BJT, The semiconductor power module according to any one of C1 to C15, wherein the second switching element includes a MISFET, an IGBT, or a BJT.

[0227] [C17] The semiconductor power module according to any one of C1 to C16, wherein a voltage of 500 V or more is applied between the first power supply terminal and the second power supply terminal.

[0228] [C18] A semiconductor power module according to any one of C1 to C17, wherein the periphery of the first power terminal exposed from the resin has a size smaller than the periphery of the insulating substrate exposed from the resin.

[0229] [C19] A semiconductor power module according to any one of C1 to C18, wherein the periphery of the second power terminal exposed from the resin has a size smaller than the periphery of the insulating substrate exposed from the resin.

[0230] This application corresponds to Patent Application No. 2016-110383 filed with the Japan Patent Office on June 1, 2016, the entire disclosure of which is incorporated herein by reference.

[0231] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0232] 1: semiconductor power module, 2: output side terminal, 3: high voltage side terminal, 4: low voltage side terminal, 5: first switching element, 6: second switching element, 7: half bridge circuit, 31: package main body, 35: heat dissipation member, 41: insulating substrate, 42: front surface of insulating substrate, 43: rear surface of insulating substrate, 44: support substrate, 46: front surface of support substrate, 47: rear surface of support substrate, 76: first removal region of insulating substrate, 77: second removal region of insulating substrate

Claims

1. a first substrate having one surface and another surface; a second substrate having an opposing surface facing the one surface of the first substrate; a first switching element disposed on the opposing surface side of the second substrate; a second switching element disposed on the opposing surface side of the second substrate; an output terminal disposed on the opposing surface side of the second substrate; a first conductor pattern disposed on the opposing surface of the second substrate and electrically connected to the first switching element; a second conductor pattern disposed on the opposing surface of the second substrate at a distance from the first conductor pattern and electrically connected to the second switching element and the output terminal; a first input terminal electrically connected to the first conductor pattern and the first switching element; a second input terminal electrically connected to the second switching element; a resin that seals the first substrate, the second substrate, the first switching element, and the second switching element.

2. further including an insulating member interposed between the first input terminal and the second input terminal; the second input terminal is disposed opposite the first input terminal with the insulating member interposed therebetween, 2. The semiconductor power module according to claim 1, wherein the resin seals the first input terminal, the second input terminal, and the insulating member so as to selectively expose the first input terminal, the second input terminal, and the insulating member.

3. 3. The semiconductor power module according to claim 2, wherein the direction of current flowing through said first input terminal and the direction of current flowing through said second input terminal are opposite to each other across said insulating member.

4. 2. The semiconductor power module according to claim 1, wherein the second switching element faces the first switching element on the opposing surface of the second substrate.

5. a plurality of the first switching elements are arranged on the opposing surface side of the second substrate, 2. The semiconductor power module according to claim 1, wherein a plurality of said second switching elements are arranged on said opposing surface side of said second substrate.

6. 6. The semiconductor power module according to claim 5, wherein the output terminal, the first input terminal, the second input terminal, the first switching element, and the second switching element form a half-bridge circuit.

7. 2. The semiconductor power module according to claim 1, wherein the output terminal is formed in a plate or block shape and has at least one notch at an end portion on the second conductor pattern side.

8. 2. The semiconductor power module according to claim 1, wherein the output terminal is arranged on the same straight line as the first input terminal and the second input terminal in a plan view.

9. 2. The semiconductor power module according to claim 1, wherein the output terminal is disposed at a position facing the first input terminal and the second input terminal across the resin in a plan view.

10. 2. The semiconductor power module according to claim 1, wherein the output terminal has a thickness greater than a thickness of the first input terminal or a thickness of the second input terminal.

11. 11. The semiconductor power module according to claim 10, wherein the output terminal has a thickness equal to or greater than the sum of the thicknesses of the first input terminal and the second input terminal.

12. a first control terminal that transmits an electrical signal that controls the first switching element; a second control terminal for transmitting an electrical signal for controlling the second switching element, 2. The semiconductor power module according to claim 1, wherein the resin seals the first control terminal and the second control terminal so as to selectively expose the first control terminal and the second control terminal.

13. the first control terminal is exposed from the resin in a direction different from a direction in which the first input terminal and the second input terminal are exposed from the resin, 13. The semiconductor power module according to claim 12, wherein the second control terminal is exposed from the resin in a direction different from a direction in which the first input terminal and the second input terminal are exposed from the resin.

14. a first unit including a plurality of first switching elements, a plurality of second switching elements, and an output terminal; a second unit including a substrate, a first input terminal, and a second input terminal, the second unit being stacked on the first unit.

15. an insulating member interposed between the first input terminal and the second input terminal; a resin that seals the first input terminal, the second input terminal, and the insulating member so as to selectively expose the first input terminal, the second input terminal, and the insulating member, the second input terminal is disposed opposite the first input terminal with the insulating member interposed therebetween, 15. The semiconductor power module according to claim 14, wherein a direction of a current flowing through the first input terminal and a direction of a current flowing through the second input terminal are opposite to each other across the insulating member.

16. 15. The semiconductor power module according to claim 14, wherein the output terminal, the first input terminal, the second input terminal, the first switching element, and the second switching element form a half-bridge circuit.

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