Multilayer ceramic electronic component and mounting structure

Abstract

To reduce a manufacturing load of a laminated ceramic electronic component while reducing acoustic noise of a substrate.SOLUTION: The multilayer ceramic electronic component 1 includes an element body 2 and an external electrode 8. The element body 2 includes a capacitance portion 3, a base portion 4, and a connecting portion 5. The capacitive part 3 has a first surface 3a and a second surface 3b opposed to each other in the laminating direction, a first end-surface 3c and a second end-surface 3d opposed to each other in the lengthwise direction, and a first side-surface 3e and a second side-surface 3f opposed to each other in the widthwise direction. The base portion 4 has a third surface 4a and a fourth surface 4b opposed to each other in the laminating direction, a third end surface 4c and a fourth end surface 4d opposed to each other in the lengthwise direction, and a third side surface 4e and a fourth side surface 4f opposed to each other in the widthwise direction. The connecting portion 5 connects the second surface 3b and the third surface 4a. The connecting portion 5 is included in the capacitive portion 3 and the base portion 4 when viewed in the stacking direction, and has a smaller length in the length direction or the width direction than the capacitive portion 3 and the base portion 4.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a multilayer ceramic electronic component and a mounting structure. [Background technology]

[0002] A multilayer ceramic capacitor, an example of a multilayer ceramic electronic component, includes a laminate formed by alternately stacking dielectric layers and internal electrodes, and a main body composed of external electrodes. Multilayer ceramic capacitors are typically mounted on a circuit board for use. When a voltage is applied between the external electrodes, the dielectric layers expand and contract due to the electrostrictive effect in response to the applied voltage, causing electrostrictive vibration of the laminate. When the electrostrictive vibration of the laminate is transmitted to the circuit board, an audible sound is generated from the circuit board, i.e., the circuit board may produce squealing noise.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor comprising an interposer and a main body mounted on the interposer. When the multilayer ceramic capacitor is mounted on a circuit board, the interposer is positioned between the main body and the circuit board, and prevents electrostrictive vibrations of the laminate from being transmitted to the circuit board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-204572 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional multilayer ceramic capacitors require the main body to be mounted on an interposer, which can increase the manufacturing burden. [Means for solving the problem]

[0006] The multilayer ceramic electronic component of the present disclosure includes an element body having a capacitance portion, a base portion, and a connection portion; an external electrode; the capacitance section is sandwiched between protective layers in a stacking direction and is formed by alternately stacking a plurality of dielectric layers and a plurality of internal electrodes, and has a first surface and a second surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction, and the plurality of internal electrodes are exposed at the first end surface or the second end surface according to polarity, the pedestal portion has a third surface and a fourth surface facing each other in the stacking direction, a third end surface and a fourth end surface facing each other in the length direction, and a third side surface and a fourth side surface facing each other in the width direction, the third surface facing the second surface of the capacitance portion, the connection portion connects the second surface of the capacitance portion and the third surface of the base portion, the external electrodes include a first external electrode located at least on the first end surface and a second external electrode located at least on the second end surface, When viewed in the stacking direction, the connection portion is included in the capacitance portion and the pedestal portion, and has a length in the length direction or the width direction that is smaller than that of the capacitance portion and the pedestal portion.

[0007] The mounting structure of the present disclosure includes the above-described multilayer ceramic electronic component, a circuit board having a mounting surface, The multilayer ceramic electronic component is mounted on the circuit board so that the fourth surface of the base faces the mounting surface. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to reduce the manufacturing burden of multilayer ceramic electronic components while suppressing noise from circuit boards. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a perspective view showing a configuration of an element body in a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 3] 3 is a diagram showing an example of a cross section taken along the cross-sectional line III-III in FIG. 1. FIG. [Figure 4] 3 is a diagram showing another example of a cross section taken along the cross-sectional line III-III in FIG. 1. FIG. [Figure 5] 1 is a plan view showing an example of an element body of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 6] FIG. 10 is a plan view showing another example of an element body of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 7] 1 is a cross-sectional view showing an example of a mounting structure including a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 8] FIG. 10 is a cross-sectional view showing another example of a mounting structure including a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 9] FIG. 10 is a cross-sectional view showing another example of a mounting structure including a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 10] FIG. 2 is an enlarged cross-sectional view showing an example of the configuration of a bridge portion in the multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 11] FIG. 4 is an enlarged cross-sectional view showing another example of the configuration of the bridge portion in the multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 12] FIG. 10 is a cross-sectional view showing a multilayer ceramic capacitor according to another embodiment of the present disclosure. [Figure 13] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 14] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 15] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 16] FIG. 2 is a perspective view showing an element precursor obtained by dividing a base laminate. [Figure 17] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 18] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 19] 1A to 1C are diagrams illustrating a process for producing a base laminate. [Figure 20] FIG. 2 is a perspective view showing an element precursor obtained by dividing a base laminate. [Figure 21] FIG. [Figure 22] FIG. 1 is a perspective view showing a multilayer ceramic capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of a multilayer ceramic electronic component and a mounting structure according to the present disclosure will be described with reference to the drawings. Hereinafter, a multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component. However, the multilayer ceramic electronic component according to the present disclosure is not limited to a multilayer ceramic capacitor and may be a multilayer piezoelectric element, a multilayer thermistor element, a multilayer chip coil, a ceramic multilayer substrate, or the like. The drawings referred to below are schematic, and the shapes, dimensional ratios, and the like shown in the drawings are not necessarily accurately depicted. For convenience, a Cartesian coordinate system XYZ is defined in this specification. The X-axis direction is also referred to as the length direction. The Y-axis direction is also referred to as the width direction. The Z-axis direction is also referred to as the height direction or stacking direction. In the following description, a planar view refers to a view in the Z-axis direction.

[0011] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 2 is a perspective view showing a configuration of an element body of the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 3 is a diagram showing an example of a cross section taken along the section line III-III in FIG. 1 . FIG. 4 is a diagram showing another example of a cross section taken along the section line III-III in FIG. 1 . FIG. 5 is a plan view showing an example of an element body of the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 6 is a plan view showing another example of an element body of the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing an example of a mounting structure including the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIGS. 8 and 9 are cross-sectional views showing another example of a mounting structure including the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 10 is an enlarged cross-sectional view showing an example of a configuration of a bridge portion in the multilayer ceramic capacitor according to an embodiment of the present disclosure. FIG. 11 is an enlarged cross-sectional view showing another example of a configuration of a bridge portion in the multilayer ceramic capacitor according to an embodiment of the present disclosure. In FIG. 2 , for ease of illustration, the ends of the internal electrodes exposed on the surface of the element body are hatched.

[0012] As shown in Fig. 1, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure includes an element body 2 and external electrodes 8. As shown in Fig. 2, the element body 2 has a capacitive portion 3, a base portion 4, and a connecting portion 5. As shown in Fig. 1, the external electrodes 8 have a first external electrode 8a and a second external electrode 8b.

[0013] The capacitor 3 is formed by alternately stacking a plurality of dielectric layers 6 and a plurality of internal electrodes 7 between protective layers 31. The capacitor 3 forms a capacitance. The capacitor 3 may be substantially rectangular. The capacitor 3 has a first surface 3a and a second surface 3b facing each other in the stacking direction (Z-axis direction), a first end surface 3c and a second end surface 3d facing each other in the length direction (X-axis direction), and a first side surface 3e and a second side surface 3f facing each other in the width direction (Y-axis direction). Hereinafter, when the first surface 3a and the second surface 3b are not distinguished from each other, they may be referred to as main surfaces 3a and 3b. Hereinafter, the first end surface 3c and the second end surface 3d may be collectively referred to as end surfaces 3c and 3d, and the first side surface 3e and the second side surface 3f may be collectively referred to as side surfaces 3e and 3f.

[0014] The dielectric layer 6 may be made of a ceramic material containing as a main component BaTiO3 (barium titanate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (barium zirconate), CaZrO3 (calcium zirconate), etc. The dielectric layer 6 may have a thickness of, for example, about 0.1 to 1.0 μm.

[0015] As shown in Figures 2 and 3, the multiple internal electrodes 7 include multiple first internal electrodes 7a and multiple second internal electrodes 7b. The first internal electrodes 7a and the second internal electrodes 7b have mutually different polarities. When the first internal electrode 7a has a first polarity, the second internal electrode 7b has a second polarity different from the first polarity. The first internal electrode 7a has an end exposed at the first end surface 3c, and the second internal electrode 7b has an end exposed at the second end surface 3d.

[0016] The internal electrodes 7 may be made of a metal material containing Ni (nickel), Cu (copper), Sn (tin), etc. as a main component. The internal electrodes 7 may contain a ceramic material such as BaTiO3, CaTiO3, SrTiO3, BaZrO3, CaZrO3, etc. The internal electrodes 7 may have a thickness of, for example, about 0.1 to 1.0 μm.

[0017] The pedestal portion 4 is located away from the capacitive portion 3 in the height direction (Z-axis direction). The pedestal portion 4 does not form a capacitance. The pedestal portion 4 may be substantially rectangular parallelepiped. The pedestal portion 4 has a third surface 4a and a fourth surface 4b facing each other in the height direction (Z-axis direction), a third end surface 4c and a fourth end surface 4d facing each other in the length direction (X-axis direction), and a third side surface 4e and a fourth side surface 4f facing each other in the width direction (Y-axis direction). The third surface 4a of the pedestal portion 4 faces the second surface 3b of the capacitive portion 3. Hereinafter, the third end surface 4c and the fourth end surface 4d may be collectively referred to as end surfaces 4c and 4d, and the third side surface 4e and the fourth side surface 4f may be collectively referred to as side surfaces 4e and 4f. In addition, the end faces 3c, 3d of the capacitance portion 3 and the end faces 4c, 4d of the base portion 4 may be collectively referred to as end faces 3c, 3d, 4c, 4d, and the side faces 3e, 3f of the capacitance portion 3 and the side faces 4e, 4f of the base portion 4 may be collectively referred to as side faces 3e, 3f, 4e, 4f.

[0018] The base 4 may be made of a ceramic material whose main component is BaTiO3, CaTiO3, SrTiO3, BaZrO3, CaZrO3, etc. The ceramic material that makes up the base 4 may be the same as the ceramic material that makes up the dielectric layer 6.

[0019] The base portion 4 is a non-vibration portion that does not substantially exhibit an electrostrictive effect, unlike the capacitive portion 3 in which dielectric layers 6 and internal electrodes 7 are alternately laminated. The base portion 4 may have a plurality of dummy electrodes connected to the external electrodes 8, but the dummy electrodes do not substantially exhibit an electrostrictive effect.

[0020] As shown in FIG. 5, the first end face 3c and the second end face 3d may be substantially flush with the third end face 4c and the fourth end face 4d, respectively, and the first side face 3e and the second side face 3f may be substantially flush with the third side face 4e and the fourth side face 4f, respectively. As shown in FIG. 5, the capacitive portion 3 and the pedestal portion 4 may have substantially the same outer shape in a plan view. As shown in FIGS. 3 and 4, the third face 4a of the pedestal portion 4 may be substantially parallel to the second face 3b of the capacitive portion 3. Note that the first end face 3c and the third end face 4c being substantially flush with each other may include cases where the first end face 3c and the third end face 4c form an angle of a predetermined angle (e.g., 5°) or less and where the distance between the first end face 3c and the third end face 4c in the longitudinal direction (X-axis direction) is a predetermined distance (e.g., 5 μm) or less. The same applies to the second end face 3d and the fourth end face 4d. Furthermore, the phrase "the first side surface 3e and the third side surface 4e are substantially flush" may include cases where the first side surface 3e and the third side surface 4e form an angle of a predetermined value (e.g., 5°) or less, and where the distance between the first side surface 3e and the third side surface 4e in the width direction (Y-axis direction) is a predetermined distance (e.g., 5 μm) or less. The same applies to the second side surface 3f and the fourth side surface 4f. The phrase "the second surface 3b and the third surface 4a are substantially parallel" may include cases where the second surface 3b and the third surface 4a form an angle of a predetermined value (e.g., 5°) or less.

[0021] The connection portion 5 connects the capacitive portion 3 and the base portion 4. The connection portion 5 is located between the second surface 3b of the capacitive portion 3 and the third surface 4a of the base portion 4, and connects a part of the second surface 3b to a part of the third surface 4a. The connection portion 5 may connect the center of the second surface 3b in a plan view to the center of the third surface 4a in a plan view.

[0022] 5 and 6, the connection portion 5 is included in the capacitive portion 3 and the base portion 4 in a plan view. In other words, the connection portion 5 does not protrude from the outer shapes of the capacitive portion 3 and the base portion 4 in a plan view. The outer shapes of the connection portion 5 may partially substantially coincide with the outer shapes of the capacitive portion 3 and the base portion 4 in a plan view.

[0023] As shown in FIGS. 5 and 6 , the connection portion 5 is shorter in the length direction (X-axis direction) or width direction (Y-axis direction) than the capacitive portion 3 and the base portion 4. In other words, the element body 2 has a gap around the connection portion 5 between the second surface 3b of the capacitive portion 3 and the third surface 4a of the base portion 4. It can also be said that the element body 2 has a slit between the capacitive portion 3 and the base portion 4, cut out from both ends in the length direction (X-axis direction) or width direction (Y-axis direction) along a direction perpendicular to the stacking direction (Z-axis direction). Below, we will explain the case where the connection portion 5 is shorter in the length direction (X-axis direction) than the capacitive portion 3 and the base portion 4. Furthermore, below, the gap around the connection portion 5 may be referred to as the gap portion G of the element body 2.

[0024] The connecting portion 5 may be made of a ceramic material whose main component is BaTiO3, CaTiO3, SrTiO3, BaZrO3, CaZrO3, etc. The ceramic material that makes up the connecting portion 5 may be the same as the ceramic material that makes up the dielectric layer 6.

[0025] As shown in Figures 3 and 4, both ends of the capacitive section 3 in the stacking direction (Z-axis direction) may be provided with protective layers 31 made of a ceramic material. In this case, the main parts of the capacitive section 3 (i.e., the parts that form the capacitance) can be protected from external environments such as moisture. The ceramic material may be a ceramic material whose main component is BaTiO3, CaTiO3, SrTiO3, BaZrO3, CaZrO3, etc. The protective layer 31 may be made of a plurality of dielectric layers 6 stacked in the stacking direction (Z-axis direction).

[0026] The first external electrode 8a is located at least on the first end face 3c of the capacitive section 3, and is connected to the multiple first internal electrodes 7a whose ends are exposed at the first end face 3c. The first external electrode 8a may be located from the first end face 3c of the capacitive section 3 to the third end face 4c and the fourth face 4b of the base section 4. Even if the gap G is located between the first end face 3c and the third end face 4c, the first external electrode 8a can be formed to be continuous from the first end face 3c to the third end face 4c, as long as the dimension of the gap G in the height direction (Z-axis direction) is equal to or less than a predetermined value (e.g., 20 μm).

[0027] The first external electrode 8a may further be located on the first surface 3a of the capacitive portion 3. The first external electrode 8a may further be located on the first surface 3a and side surfaces 3e and 3f of the capacitive portion 3, and side surfaces 4e and 4f of the base portion 4.

[0028] The second external electrode 8b is located at least on the second end face 3d of the capacitive section 3, and is connected to the plurality of second internal electrodes 7b whose ends are exposed at the second end face 3d. The second external electrode 8b may be located from the second end face 3d of the capacitive section 3 to the fourth end face 4d and the fourth surface 4b of the base section 4. Even if the gap G is located between the second end face 3d and the fourth end face 4d, the second external electrode 8b can be formed to be continuous from the second end face 3d to the fourth end face 4d, as long as the dimension of the gap G in the height direction (Z-axis direction) is equal to or less than a predetermined value (e.g., 20 μm).

[0029] The second external electrode 8b may further be located on the first surface 3a of the capacitive portion 3. The second external electrode 8b may further be located on the first surface 3a and side surfaces 3e and 3f of the capacitive portion 3, and on side surfaces 4e and 4f of the base portion 4.

[0030] The external electrode 8 may be composed of a first layer 81 and a second layer 82, as shown in FIG.

[0031] The first layer 81 is located at least on the end faces 3c and 3d and is connected to the multiple internal electrodes 7 whose ends are exposed on the end faces 3c and 3d. The first layer 81 may be made of a metal such as Cu, Ni, Sn, Ag (silver), Pd (palladium), or Au (gold), or an alloy containing these metals. The first layer 81 may be formed using a thick film formation technique such as dipping (immersion coating), screen printing, or gravure printing.

[0032] The second layer 82 is located on the surface of the first layer 81. The second layer 82 may be made of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The second layer 82 may be formed using a thin film formation technique such as electroless plating or electrolytic plating. The second layer 82 may be made of two or more plating layers. The second layer 82 may be made of, for example, a Ni plating layer located on the surface of the first layer 81 and a Sn plating layer located on the surface of the Ni plating layer.

[0033] By configuring the external electrode 8 with the first layer 81 and the second layer 82, it is possible to improve the adhesion between the external electrode 8 and the element body 2, and also improve the wettability of the external electrode 8 with a conductive bonding material such as solder. As a result, the reliability of the multilayer ceramic capacitor 1 and the mounting structure including the multilayer ceramic capacitor 1 can be improved.

[0034] The external electrode 8 may be composed of a first layer 83, a second layer 84, and a third layer 85, as shown in FIG.

[0035] The first layer 83 is located at least on the end faces 3c and 3d and is connected to the ends of the internal electrodes 7 exposed on the end faces 3c and 3d. The first layer 83 may be made of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The first layer 83 may be formed using a thin film formation technique such as electroless plating or electrolytic plating. The first layer 83 only needs to be connected to the ends of the internal electrodes 7 exposed on the end faces 3c and 3d, and does not have to be located over the entire area of ​​the end faces 3c and 3d.

[0036] The second layer 84 is located on the surface of the first layer 83. The second layer 84 may be made of a conductive resin. The conductive resin may be made of a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, or polyimide resin, and a plurality of metal particles made of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The second layer 84 may be formed using a thick film formation technique such as a dipping (immersion coating) method, a screen printing method, or a gravure printing method.

[0037] The third layer 85 is located on the surface of the second layer 84. The third layer 85 may be composed of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The third layer 85 may be formed using a thin film formation technique such as electroless plating or electrolytic plating. The third layer 85 may be composed of two or more plating layers. For example, the third layer 85 may be composed of a Ni plating layer located on the surface of the second layer 84 and a Sn plating layer located on the surface of the Ni plating layer.

[0038] By configuring the external electrode 8 with the first layer 83, the second layer 84, and the third layer 85, it is possible to improve the adhesion between the external electrode 8 and the element body 2 and also improve the wettability of the external electrode 8 with a conductive bonding material such as solder. As a result, it is possible to improve the reliability of the multilayer ceramic capacitor 1 and the mounting structure including the multilayer ceramic capacitor 1. Furthermore, because the second layer 84 is made of a conductive resin (a material with a relatively low Young's modulus), it is possible to reduce the transmission of electrostrictive vibration of the capacitive section 3 to the circuit board via the external electrode 8. As a result, it is possible to reduce noise on the circuit board.

[0039] The multilayer ceramic capacitor 1 may be mounted on a circuit board 10 as shown in FIG. 7 . In this specification, a structure including the circuit board 10 and the multilayer ceramic capacitor 1 mounted on the circuit board 10 is referred to as a mounting structure 100. The circuit board 10 has a mounting surface 10a. The circuit board 10 has a first substrate electrode 11, a second substrate electrode 12, and wiring conductors (not shown) located on the mounting surface 10a. The multilayer ceramic capacitor 1 is mounted on the circuit board 10 using a conductive bonding material such as solder S so that the fourth surface 4b of the base portion 4 faces the mounting surface 10a and the first external electrode 8a and the second external electrode 8b are electrically connected to the first substrate electrode 11 and the second substrate electrode 12, respectively.

[0040] In the multilayer ceramic capacitor 1, the capacitive portion 3 and the base portion 4 are connected by a connecting portion 5. The connecting portion 5 is shorter in length (X-axis direction) or width (Y-axis direction) than the capacitive portion 3 and the base portion 4, and a gap G is formed around the connecting portion 5 between the capacitive portion 3 and the base portion 4. In the multilayer ceramic capacitor 1, the capacitive portion 3 and the base portion 4 are not firmly (rigidly) connected, so that even if the capacitive portion 3 undergoes electrostrictive vibration, transmission of the electrostrictive vibration of the capacitive portion 3 to the base portion 4 can be reduced. As a result, acoustic noise of the circuit board 10 can be reduced. Furthermore, the multilayer ceramic capacitor 1 does not need to be mounted on the circuit board 10 via an interposer, and can be directly mounted on the circuit board 10, thereby minimizing the increase in manufacturing burden.

[0041] Furthermore, as will be described in detail later, the multilayer ceramic capacitor 1 can be manufactured by adding a sub-process of applying a slit paste or ceramic slurry to the base laminate manufacturing process in the manufacturing method of a conventional multilayer ceramic capacitor (i.e., a multilayer ceramic capacitor that does not have a base portion 4 and a connecting portion 5), thereby reducing the burden of manufacturing the multilayer ceramic capacitor 1.

[0042] The height of the pedestal portion 4 (dimension in the Z-axis direction) may be, for example, 50 μm or more and 300 μm or less. If the height of the pedestal portion 4 is less than 50 μm, the pedestal portion 4 may be damaged during the manufacturing process of the multilayer ceramic capacitor 1. If the height of the pedestal portion 4 exceeds 300 μm, the multilayer ceramic capacitor 1 will become larger even though the capacitance will not increase. By setting the height of the pedestal portion 4 to 50 μm or more and 300 μm or less, the risk of the pedestal portion 4 being damaged can be reduced, and the multilayer ceramic capacitor 1 can be prevented from becoming larger.

[0043] The height of the connection portion 5 (the dimension in the Z-axis direction) may be, for example, 2 μm or more and 20 μm or less. If the height of the connection portion 5 is less than 2 μm, it may be impossible to ensure a gap between the second surface 3 b and the third surface 4 a due to dimensional tolerances. If the height of the connection portion 5 exceeds 20 μm, the connection portion 5 may be easily damaged during the manufacturing process of the multilayer ceramic capacitor 1 or during operation of the multilayer ceramic capacitor 1, or it may be difficult to form the external electrodes 8 by direct plating. By setting the height of the connection portion 5 to 2 μm or more and 20 μm or less, it becomes easier to form a gap (gap portion G) between the second surface 3 b and the third surface 4 a, and the risk of damage to the connection portion 5 can be reduced. Furthermore, since it becomes easier to form the external electrodes 8 by direct plating, the multilayer ceramic capacitor 1 can be made smaller.

[0044] At least a portion of the external electrode 8 may enter the gap G. In this case, the adhesion between the element body 2 and the external electrode 8 can be improved. The external electrode 8 may enter a portion of the gap G. Even if the external electrode 8 enters a portion of the gap G, the function of the gap G of making it difficult for the electrostrictive vibration of the capacitance section 3 to be transmitted to the base section 4 is not lost.

[0045] 1, the gap G may not be completely covered by the external electrode 8, but may be partially exposed from the external electrode 8. In this case, the capacitance part 3 and the base part 4 are not firmly fixed to each other, and therefore, transmission of electrostrictive vibration of the capacitance part 3 to the base part 4 can be reduced.

[0046] 5, the connection portion 5 may have a substantially square outer shape in a plan view. In this case, it is possible to reduce the risk of undesired amplification of the electrostrictive vibration of the capacitance portion 3 and a decrease in the mechanical strength of the multilayer ceramic capacitor 1. As a result, it is possible to reduce acoustic noise of the circuit board 10 and improve the reliability of the multilayer ceramic capacitor 1. The length (dimension in the X-axis direction) of the connection portion 5 may be equal to or greater than the width (dimension in the Y-axis direction) of the element body 2 and may be equal to or less than the length (dimension in the X-axis direction) of the element body 2.

[0047] The centroids (centers of gravity) of the capacitive portion 3, the base portion 4, and the connecting portion 5 may be substantially aligned with one another in a plan view. In this case, it is possible to reduce the risk of undesired amplification of the electrostrictive vibration of the capacitive portion 3 and a decrease in the mechanical strength of the multilayer ceramic capacitor 1. As a result, it is possible to reduce the acoustic noise of the circuit board 10 and improve the reliability of the multilayer ceramic capacitor 1. Note that the centroids of the capacitive portion 3, the base portion 4, and the connecting portion 5 being substantially aligned with one another may include the case where the distance between them is equal to or less than a predetermined distance. The predetermined distance may be set appropriately depending on, for example, the size of the multilayer ceramic capacitor 1.

[0048] When the multilayer ceramic capacitor 1 is mounted on the circuit board 10, if a large amount of solder S is attached to the external electrodes 8, the electrostrictive vibration of the capacitive section 3 is likely to be transmitted to the circuit board 10 via the solder S, making the circuit board 10 more susceptible to squealing. As shown in FIG. 8 , the external electrodes 8 may be formed only on the end faces 3c, 3d, 4c, and 4d and the fourth surface 4b. In this case, when the multilayer ceramic capacitor 1 is mounted on the circuit board 10, the solder S creeps up onto the first surface 3a, reducing the amount of solder S adhering to the external electrodes 8. As a result, the transmission of the electrostrictive vibration of the capacitive section 3 to the circuit board 10 via the solder S is reduced, reducing the squealing of the circuit board 10.

[0049] 9, the external electrodes 8 may have restricting portions 13 that block the flow of solder S when the multilayer ceramic capacitor 1 is mounted on a circuit board 10. In this case, even if the external electrodes 8 are formed on the end faces 3c, 3d, 4c, 4d, the first surface 3a, and the fourth surface 4b, it is possible to prevent the solder S from creeping up to the portion of the external electrodes 8 on the first surface 3a, and to prevent a large amount of solder S from adhering to the external electrodes 8. As a result, it is possible to reduce the transmission of electrostrictive vibrations of the capacitive portion 3 to the circuit board 10 via the solder S, and to reduce noise from the circuit board 10.

[0050] The restricting portions 13 may be provided on the end faces 3c, 3d of the external electrode 8. In this case, the risk of the amount of solder S adhering to the external electrode 8 being too small can be reduced, and the mounting strength of the multilayer ceramic capacitor 1 on the circuit board 10 can be ensured. The restricting portions 13 may be, for example, strip-shaped members extending substantially parallel to the first surface 3a. The strip-shaped members may be made of resin, such as epoxy resin or urethane resin. The restricting portions 13 may be ridges or grooves formed on the external electrode 8 and extending substantially parallel to the first surface 3a. The ridges and grooves may be formed, for example, by irradiating the surface of the external electrode 8 with laser light. The external electrode 8 may also be formed on the side faces 3e, 3f, 4e, 4f. In this case, the restricting portions 13 may be further provided on the external electrode 8 at positions on the side faces 3e, 3f.

[0051] When the external electrode 8 has a conductive resin layer (e.g., the second layer 84) made of conductive resin, the conductive resin layer has a relatively small Young's modulus, so even if solder S is attached to the external electrode 8, the electrostrictive vibration of the capacitive section 3 is unlikely to be transmitted to the solder S and the circuit board 10 via the external electrode 8. As a result, it is possible to reduce the noise of the circuit board 10. The conductive resin may be made of a thermosetting resin such as epoxy resin, phenol resin, urethane resin, silicone resin, or polyimide resin, and a plurality of metal particles made of a metal such as Ag (silver), Cu, Ni, or Sn. When the external electrode 8 has a conductive resin layer, the external electrode 8 may be formed on the end faces 3c, 3d, 4c, 4d and the fourth surface 4b, or on the end faces 3c, 3d, 4c, 4d, the fourth surface 4b and the first surface 3a, or on the end faces 3c, 3d, 4c, 4d, the fourth surface 4b, the first surface 3a and the side surfaces 3e, 3f, 4e, 4f.

[0052] As shown in FIGS. 10 and 11 , the multilayer ceramic capacitor 1 may include bridge portions 9 located in the voids G. At least a portion of the external electrodes 8 may enter the voids G, but the external electrodes 8 are not shown in FIGS. 10 and 11 . The bridge portions 9 bridge the second surface 3 b of the capacitive portion 3 and the third surface 4 a of the base portion 4. This reduces the risk of damage to the base portion 4 and the connection portions 5 during the manufacturing process of the multilayer ceramic capacitor 1. The bridge portions 9 do not need to densely fill the voids G. In this case, the transmission of electrostrictive vibrations of the capacitive portion 3 to the base portion 4 via the bridge portions 9 can be reduced, resulting in reduced noise from the circuit board.

[0053] The bridge portions 9 may be made of a ceramic material containing BaTiO3, ZrO2 (zirconia) as a main component, etc. In this case, the element body 2 and the bridge portions 9 can be produced by co-firing.

[0054] As shown in FIG. 10, the bridge portion 9 may include a plurality of ceramic particles 9a. The plurality of ceramic particles 9a may be composed of a ceramic material whose main component is BaTiO3, ZrO2, or the like. The plurality of ceramic particles 9a may have a relatively large particle size. In this case, the plurality of ceramic particles 9a are less likely to be densely packed into the void portion G, which reduces the transmission of electrostrictive vibrations of the capacitance portion 3 to the base portion 4. As a result, noise from the circuit board can be reduced. The plurality of ceramic particles 9a may have a larger average particle size than the plurality of ceramic particles contained in the dielectric layer 6, for example.

[0055] As shown in Fig. 10, the plurality of ceramic particles 9a may be out of contact with at least one of the second surface 3b and the third surface 4a. In other words, the second surface 3b and the third surface 4a do not need to be bridged by a single ceramic particle 9a that contacts both the second surface 3b and the third surface 4a. In this case, the second surface 3b and the third surface 4a are less likely to be firmly bridged by the ceramic particle 9a. As a result, transmission of electrostrictive vibrations of the capacitive portion 3 to the base portion 4 can be reduced, and noise from the circuit board 10 can be reduced.

[0056] 11, the bridge portion 9 may include a plurality of metal particles 9b located between a plurality of ceramic particles 9a. When a plurality of metal particles 9b are located in the void portion G, it becomes easier to form a continuous plating layer from the end faces 3c, 3d of the capacitance portion 3 to the end faces 4c, 4d of the base portion 4 by direct plating in the manufacturing process of the multilayer ceramic capacitor 1. As a result, it becomes possible to thin the external electrodes 8, and it becomes possible to miniaturize the multilayer ceramic capacitor 1 without miniaturizing the capacitance portion 3 (i.e., without reducing the capacitance of the multilayer ceramic capacitor 1).

[0057] The plurality of metal particles 9b may be composed of a metal whose main component is Ni, Cu, or the like, or an alloy containing such a metal. The plurality of metal particles 9b may have a relatively large particle size. In this case, the metal particles 9b are less likely to be densely packed into the voids G, which reduces the transmission of electrostrictive vibrations of the capacitance section 3 to the base section 4. As a result, acoustic noise of the circuit board 10 can be reduced. The plurality of metal particles 9b may have a larger average particle size than the plurality of metal particles contained in the internal electrode 7, for example.

[0058] 11, the plurality of metal particles 9b may be unevenly distributed in the region of the bridge portion 9 closer to the end faces 3c, 3d, 4c, and 4d. In other words, the plurality of metal particles 9b may be present in greater numbers in the region of the bridge portion 9 closer to the end faces 3c, 3d, 4c, and 4d than in the region of the bridge portion 9 closer to the connection portion 5. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, it becomes easier to form a continuous plating layer from the end faces 3c and 3d of the capacitance portion 3 to the end faces 4c and 4d of the base portion 4 by a direct plating method, which makes it possible to reduce the thickness of the external electrode 8. As a result, the multilayer ceramic capacitor 1 can be miniaturized without reducing the capacitance of the multilayer ceramic capacitor 1.

[0059] As shown in FIG. 11 , some of the metal particles 9b may be exposed on the surfaces of the bridge portions 9 facing the end faces 3c, 3d, 4c, and 4d. In this case, in the manufacturing process of the multilayer ceramic capacitor 1, it becomes easier to form a continuous plating layer from the end faces 3c and 3d of the capacitance portion 3 to the end faces 4c and 4d of the base portion 4 by direct plating, making it possible to reduce the thickness of the external electrodes 8. As a result, it is possible to reduce the size of the multilayer ceramic capacitor 1 without reducing the capacitance of the multilayer ceramic capacitor 1. To expose the metal particles 9b on the surfaces of the bridge portions 9 facing the end faces 3c, 3d, 4c, and 4d, for example, the amount of metal particles 9b added to the slit paste 18 (see FIG. 14 ) used to form the gaps G and the bridge portions 9 located in the gaps G may be increased.

[0060] Next, a multilayer ceramic capacitor according to another embodiment of the present disclosure will be described. Fig. 12 is a cross-sectional view showing a multilayer ceramic capacitor according to another embodiment of the present disclosure. The cross-sectional view shown in Fig. 12 corresponds to the cross-sectional view shown in Fig. 3. A multilayer ceramic capacitor 1A of this embodiment differs from the multilayer ceramic capacitor 1 of the above embodiment in the configurations of the protective layer 31 and the external electrodes 8, but is otherwise similar in configuration. Therefore, the same reference numerals as those in the multilayer ceramic capacitor 1 will be used for similar configurations, and description thereof will be omitted.

[0061] In this embodiment, of the protective layers 31 located at both ends of the capacitor 3 in the stacking direction (Z-axis direction), the protective layer 31 located on the second surface 3b side has multiple dummy electrodes (hereinafter also referred to as multiple capacitor dummy electrodes) 14. The multiple dummy electrodes 14 include multiple first dummy electrodes 14a whose ends are exposed on the first end surface 3c and multiple second dummy electrodes 14b whose ends are exposed on the second end surface 3d. The multiple first dummy electrodes 14a may be connected to the first external electrodes 8a, and the multiple second dummy electrodes 14b may be connected to the second external electrodes 8b. As shown in FIG. 12 , the multiple first dummy electrodes 14a do not overlap the multiple second dummy electrodes 14b when viewed in the stacking direction (Z-axis direction). Therefore, the multiple dummy electrodes 14 do not substantially form a capacitance.

[0062] Of the protective layers 31 located at both ends of the capacitance section 3 in the stacking direction (Z-axis direction), the protective layer 31 located on the first surface 3a side may also have a plurality of dummy electrodes.

[0063] The base 4 has a plurality of dummy electrodes (hereinafter also referred to as a plurality of base dummy electrodes) 15. The plurality of dummy electrodes 15 includes a plurality of third dummy electrodes 15a whose ends are exposed on the third end surface 4c and a plurality of fourth dummy electrodes 15b whose ends are exposed on the fourth end surface 4d. One of the plurality of third dummy electrodes 15a and one of the plurality of fourth dummy electrodes 15b may be exposed on the fourth surface 4b. As shown in FIG. 12, the plurality of third dummy electrodes 15a do not overlap with the plurality of fourth dummy electrodes 15b when viewed in the stacking direction (Z-axis direction). Therefore, the plurality of dummy electrodes 15 do not substantially form a capacitance.

[0064] In the element body 2 of the multilayer ceramic capacitor 1A, the capacitive portion 3 has a dummy electrode 14, and the base portion has a dummy electrode 15. Therefore, in the external electrode formation step of the manufacturing method of the multilayer ceramic capacitor 1A, it is easy to form a plating layer located from the end faces 3c and 3d of the capacitive portion 3 to the end faces 4c and 4d of the base portion 4 and the fourth surface 4b (by direct plating). As a result, the external electrode 8 can be made thinner, and the multilayer ceramic capacitor 1A can be made smaller.

[0065] The bridge portion 9 may include a plurality of ceramic particles 9a and a plurality of metal particles 9b located between the plurality of ceramic particles 9a. The plurality of metal particles 9b may be unevenly distributed in a region of the bridge portion 9 closer to the end faces 3c, 3d, 4c, and 4d. In this case, in the manufacturing process of the multilayer ceramic capacitor 1A, it is easier to form a plating layer located from the end faces 3c and 3d to the end faces 4c and 4d and the fourth surface 4b by a direct plating method. Some of the plurality of metal particles 9b may be located on the surface of the bridge portion 9 facing the end faces 3c, 3d, 4c, and 4d. In this case, it is easier to form a plating layer located from the end faces 3c and 3d to the end faces 4c and 4d and the fourth surface 4b by a direct plating method in the manufacturing process of the multilayer ceramic capacitor 1A.

[0066] As shown in FIG. 12 , the external electrode 8 may be composed of a first layer 86 and a second layer 87. The first layer 86 is located at least on the end faces 3c and 3d and is connected to multiple internal electrodes 7 whose ends are exposed on the end faces 3c and 3d. The first layer 86 may be located from the end faces 3c and 3d to the end faces 4c and 4d and the fourth surface 4b. The first layer 86 may be composed of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The first layer 86 may be formed using a thin-film formation technique such as electroless plating or electrolytic plating.

[0067] The second layer 87 is located on the outer surface of the first layer 86 and covers the outer surface of the first layer 86. The second layer 87 may be composed of a metal such as Cu, Ni, Sn, Ag, Pd, or Au, or an alloy containing these metals. The second layer 87 may be formed using a thin film formation technique such as electroless plating or electrolytic plating. The second layer 87 may be composed of two or more plating layers. For example, the second layer 87 may be composed of a Ni plating layer covering the surface of the first layer 86 and a Sn plating layer covering the surface of the Ni plating layer.

[0068] In this embodiment, the capacitive portion 3 has the dummy electrode 14, the base portion has the dummy electrode 15, and the bridge portion 9 contains metal particles 9b, so that the first layer 86 of the external electrode 8 can be formed by direct plating. As a result, the external electrode 8 can be made thinner, and the multilayer ceramic capacitor 1A can be made smaller.

[0069] An embodiment of the present disclosure may be implemented as a mounting structure 100 (see FIGS. 7 to 9) in which a multilayer ceramic capacitor 1, 1A is mounted on a circuit board 10. The mounting structure 100 of the present disclosure can reduce acoustic noise from the circuit board 10. Furthermore, the mounting structure 100 of the present disclosure can reduce a decrease in the mounting density of the multilayer ceramic capacitor 1.

[0070] Next, a method for manufacturing the multilayer ceramic capacitor 1 will be described. Figures 13 to 15 are views illustrating the steps of producing a base laminate, and Figure 16 is a perspective view showing an element precursor obtained by dividing the base laminate. In Figures 13 to 16, for ease of illustration, the internal electrode patterns, the slit paste, and the ends of the internal electrode patterns exposed on the surface of the element precursor are hatched.

[0071] The method for manufacturing the multilayer ceramic capacitor 1 includes a preparation step, a base laminate preparation step, a cutting step, a firing step, and an external electrode formation step.

[0072] <Preparation process> A powder containing BaTiO as the main component is prepared as the material for the dielectric layer 6, and an organic vehicle, a sintering aid, etc. are added to the powder to prepare a ceramic slurry. Next, a ceramic green sheet 16 that will become the dielectric layer 6 is formed on a carrier film using a sheet forming method such as a doctor blade method or a die coater method.

[0073] Furthermore, a powder containing Ni as a main component is prepared as the material for the internal electrodes 7, and an organic vehicle, a dispersant, etc. are added to the powder to prepare a conductive paste. Next, using the conductive paste, an internal electrode pattern that will become the internal electrodes 7 is printed on one main surface of the ceramic green sheet 16 to form an internal electrode pattern sheet 17. For printing the internal electrode pattern, a printing method such as screen printing or gravure printing can be used.

[0074] In the preparation step, a slit paste 18 for forming the voids G is prepared. The slit paste 18 may be prepared by dissolving a resin that is easily burned away by firing in an organic solvent. In this case, empty voids G (where no crosslinked portions 9 are located) can be formed. The slit paste 18 may be an organic resin such as an acrylic resin, a cellulose resin, or a polyvinyl alcohol resin.

[0075] The slit paste 18 may be prepared by adding ceramic particles made of a ceramic material such as BaTiO3 or ZrO2 to an organic resin such as acrylic resin, cellulose resin, or polyvinyl alcohol resin. In this case, it is possible to form bridge portions 9 composed of a plurality of ceramic particles 9a. The slit paste 18 may contain relatively large ceramic particles and may not contain a sintering aid. In this case, it is possible to form bridge portions 9 composed of a plurality of ceramic particles 9a. The slit paste 18 may be prepared by dissolving an organic resin such as acrylic resin, cellulose resin, or polyvinyl alcohol resin in an organic solvent and adding ceramic particles made of a ceramic material such as BaTiO3 or ZrO2 and metal particles made of a metal such as Ni or Cu or an alloy containing these metals. In this case, it is possible to form bridge portions 9 composed of a plurality of ceramic particles 9a and a plurality of metal particles 9b. The slit paste 18 may contain relatively large ceramic particles and metal particles. In this case, it is possible to form bridge portions 9 composed of a plurality of ceramic particles 9a and a plurality of metal particles 9b.

[0076] <Master laminate manufacturing process> Next, as shown in FIG. 13 , a predetermined number of internal electrode pattern sheets 17 are laminated on top of a predetermined number of laminated ceramic green sheets 16, and a predetermined number of ceramic green sheets 16 are further laminated to produce a capacitor temporary laminate 19 that constitutes multiple capacitor sections 3. The upper surface of the capacitor temporary laminate 19 corresponds to the second surface 3b of the capacitor section 3. Next, as shown in FIG. 14 , slit paste 18 is printed in areas on the upper surface of the capacitor temporary laminate 19 that will become voids G, and a predetermined number of ceramic green sheets 16 are further laminated to produce a temporary laminate 20. Before printing the slit paste 18 on the capacitor temporary laminate 19, the capacitor temporary laminate 19 may be pressed in the stacking direction. In this case, printing of the slit paste 18 is facilitated, enabling the voids G and bridge sections 9 to be formed favorably.

[0077] Next, the temporary laminate 20 is pressed in the stacking direction to obtain a base laminate 21 as shown in FIG. 15. The temporary laminate 20 can be pressed using, for example, a hydrostatic press. The predetermined number of ceramic green sheets 16 stacked on the upper surface of the capacity portion temporary laminate 19 will become the base portion 4 after firing, and a portion of them will enter the gaps between the slit paste 18 to become the connection portion 5 after firing. After printing the slit paste 18 on the upper surface of the capacity portion temporary laminate 19, a ceramic slurry to become the connection portion 5 may be printed or applied into the gaps between the slit paste 18.

[0078] <Cutting process> Next, the base laminate 21 is cut along imaginary parting lines 22 to produce a plurality of unsintered element bodies 2 (hereinafter also referred to as element body precursors 2p) as shown in Fig. 16. The base laminate 21 can be cut using, for example, a press cutter or a dicing saw. Because the element body precursors 2p have substantially the same structure as the element body 2, hereinafter, the terms and reference numerals such as the capacitance portion 3, the base portion 4, and the connection portion 5 may also be used for the element body precursors 2p.

[0079] <Firing process> The element precursor 2p is degreased in air, an inert gas, or a reducing atmosphere under atmospheric pressure or reduced pressure, and then fired in the reducing atmosphere. The firing temperature may be, for example, about 1100°C to 1300°C. This sinters the element precursor 2p and burns off the organic resin contained in the slit paste 18.

[0080] Next, the fired element precursor 2p is subjected to a re-oxidation treatment in a nitrogen atmosphere. The element precursor 2p after the re-oxidation treatment is barrel polished to obtain an element 2 with chamfered corners and deburred as shown in FIG.

[0081] <External electrode formation process> Next, the external electrode 8 is formed on the surface of the element body 2. The external electrode 8 may have a two-layer structure (see FIG. 3) or a three-layer structure (see FIG. 4).

[0082] (Example 1) A method for forming an external electrode 8 with a two-layer structure (see FIG. 3) will be described. First, an organic vehicle is added to a metal such as Ni or Cu, or an alloy containing these metals, to prepare a metal paste for baking. Next, the metal paste for baking is applied by dip coating or printing to each end of the element body 2 in the longitudinal direction (X-axis direction), and then baked to form a first layer 81. A Ni plating layer is formed on the surface of the first layer 81, and a Sn plating layer is formed on the surface of the Ni plating layer to form a second layer 82. In this manner, a multilayer ceramic capacitor 1 having an external electrode 8 with a two-layer structure, as shown in FIG. 1, can be manufactured.

[0083] (Example 2) A method for forming the external electrode 8 having a three-layer structure (see FIG. 4) will be described. First, a first layer 83 is formed by forming a Cu plating layer connected to the ends of the internal electrodes 7 exposed on the end faces 3c and 3d. Next, a conductive resin paste is prepared by adding metal particles made of metals such as Cu, Ni, Sn, Ag, Pd, and Au, or alloys containing these metals, to a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, or polyimide resin. Next, the conductive resin paste is applied by dip coating or printing to both ends of the element body 2 in the longitudinal direction and then cured to form the second layer 84. Next, a Ni plating layer is formed on the outer surface of the second layer 84, and a Sn plating layer is formed on the outer surface of the Ni plating layer to form the third layer 85. In this manner, a multilayer ceramic capacitor 1 having a three-layer external electrode 8 as shown in FIG. 1 can be manufactured.

[0084] A method for manufacturing the multilayer ceramic capacitor 1A will be described below. Figures 17 to 19 are views illustrating the steps of producing a base laminate, Figure 20 is a perspective view showing an element precursor obtained by dividing the base laminate, Figure 21 is a perspective view showing an element, and Figure 22 is a perspective view showing a multilayer ceramic capacitor. In Figures 17 to 21, for ease of illustration, the internal electrode patterns, dummy electrode patterns, slit paste, ends of the internal electrode patterns and dummy electrode patterns exposed on the surface of the element precursor, and ends of the internal electrodes and dummy electrodes exposed on the surface of the element are hatched.

[0085] The manufacturing method of the multilayer ceramic capacitor 1A differs from the manufacturing method of the multilayer ceramic capacitor 1 in the preparation step, the base laminate manufacturing step, and the external electrode forming step, but the other steps are the same, so detailed explanations of the similar steps will be omitted.

[0086] In the preparation step, a dummy electrode pattern that will become the capacitive portion dummy electrode 14 is printed on one main surface of the ceramic green sheet 16 using a conductive paste to produce a dummy electrode pattern sheet 23. Also in the preparation step, a dummy electrode pattern that will become the pedestal portion dummy electrode 15 is printed on one main surface of the ceramic green sheet 16 using a conductive paste to produce a dummy electrode pattern sheet 24. The conductive paste may be the conductive paste that was produced to produce the internal electrode pattern sheet 17. The dummy electrode pattern can be printed using a printing method such as screen printing or gravure printing.

[0087] In the preparation process, ceramic particles made of ceramic materials such as BaTiO3 and ZrO2, and metal particles made of metals such as Ni and Cu or alloys containing these metals are added to an organic resin such as acrylic resin, cellulose resin, or polyvinyl alcohol resin to prepare slit paste 18.

[0088] In the base laminate preparation process, as shown in FIG. 17 , a predetermined number of internal electrode pattern sheets 17 are laminated on a predetermined number of laminated ceramic green sheets 16, a predetermined number of dummy electrode pattern sheets 23 are laminated, and a predetermined number of ceramic green sheets 16 are further laminated to prepare a capacitor temporary laminate 25. One or more ceramic green sheets 16 may be disposed between the internal electrode pattern sheet 17 and the dummy electrode pattern sheet 23. The upper surface of the capacitor temporary laminate 25 corresponds to the second surface 3b of the capacitor 3. Next, as shown in FIG. 18 , a slit paste 18 is printed in the areas that will become the voids G on the upper surface of the capacitor temporary laminate 25, and a predetermined number of dummy electrode pattern sheets 24 are further laminated to prepare a temporary laminate 26. The temporary laminate 26 is pressed in the stacking direction to obtain a base laminate 27 as shown in FIG. 19 . Note that the capacitor temporary laminate 25 may be pressed in the stacking direction before printing the slit paste 18 on the capacitor temporary laminate 25. In this case, printing of the slit paste 18 becomes easy, and the gap G can be formed well.

[0089] Next, the base laminate 27 is cut along imaginary parting lines 28 to produce a plurality of element body precursors 2p as shown in FIG. 20. The element body precursors 2p are degreased and fired. The fired element body precursors 2p are then reoxidized and barrel polished to obtain an element body 2 having bridge portions 9 composed of ceramic particles 9a and metal particles 9b, capacitive portion dummy electrodes 14, and pedestal portion dummy electrodes 15 as shown in FIG. 21.

[0090] A method for forming the external electrode 8 having a two-layer structure (see FIG. 12 ) will be described. In the external electrode formation process, a Cu plating layer connected to the end of the internal electrode 7 exposed on the end faces 3 c, 3 d of the capacitive portion 3 is formed by direct electroless plating to form a first layer 86. In this process, the first layer 86 may be formed extending from the end faces 3 c, 3 d of the capacitive portion 3 to the end faces 4 c, 4 d and the fourth surface 4 b of the pedestal portion 4. In the multilayer ceramic capacitor 1A, the element body 2 includes the bridge portions 9, the capacitive portion dummy electrode 14, and the pedestal portion dummy electrode 15, each of which is composed of ceramic particles 9 a and metal particles 9 b. This allows the first layer 86 (plating layer) to be formed extending from the end faces 3 c, 3 d of the capacitive portion 3 to the end faces 4 c, 4 d and the fourth surface 4 b of the pedestal portion 4. Next, a Ni plating layer is formed on the surface of the first layer 86, and a Sn plating layer is formed on the surface of the Ni plating layer to form a second layer 87. In this manner, a multilayer ceramic capacitor 1A as shown in FIG. 22 can be manufactured.

[0091] The above describes in detail the embodiments of the present disclosure, but the present disclosure is not limited to the above-described embodiments, and various modifications, improvements, etc. are possible within the scope that does not deviate from the gist of the present disclosure.

[0092] The present disclosure can be implemented in the following aspects (1) to (14).

[0093] (1) an element body having a capacitance portion, a base portion, and a connection portion; an external electrode; the capacitance section is sandwiched between protective layers in a stacking direction and is formed by alternately stacking a plurality of dielectric layers and a plurality of internal electrodes, and has a first surface and a second surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction, and the plurality of internal electrodes are exposed at the first end surface or the second end surface according to polarity, the pedestal portion has a third surface and a fourth surface facing each other in the stacking direction, a third end surface and a fourth end surface facing each other in the length direction, and a third side surface and a fourth side surface facing each other in the width direction, the third surface facing the second surface of the capacitance portion, the connection portion connects the second surface of the capacitance portion and the third surface of the base portion, the external electrodes include a first external electrode located at least on the first end surface and a second external electrode located at least on the second end surface, the connection portion is included in the capacitance portion and the base portion when viewed in the stacking direction, and has a length in the length direction or the width direction that is smaller than that of the capacitance portion and the base portion.

[0094] (2) the first end surface and the second end surface are substantially flush with the third end surface and the fourth end surface, respectively; The multilayer ceramic electronic component according to (1) above, wherein the first side surface and the second side surface are substantially flush with the third side surface and the fourth side surface, respectively.

[0095] (3) The multilayer ceramic electronic component according to (1) or (2) above, wherein the base portion is a non-vibration portion that does not exhibit an electrostrictive effect.

[0096] (4) The multilayer ceramic electronic component according to any one of (1) to (3) above, further comprising a bridging portion located around the connecting portion between the second surface and the third surface, bridging the second surface and the third surface.

[0097] (5) The multilayer ceramic electronic component according to (4) above, wherein the bridge portion includes a plurality of ceramic particles.

[0098] (6) The multilayer ceramic electronic component according to (5) above, wherein the plurality of ceramic particles are not in contact with at least one of the second surface and the third surface.

[0099] (7) The multilayer ceramic electronic component according to (5) or (6) above, wherein the bridge portion includes a plurality of metal particles positioned between the plurality of ceramic particles.

[0100] (8) The multilayer ceramic electronic component according to any one of (1) to (7) above, wherein at least a portion of the external electrode is located between the second surface and the third surface.

[0101] (9) The multilayer ceramic electronic component according to (8) above, wherein the external electrodes contain a conductive resin.

[0102] (10) The multilayer ceramic electronic component according to any one of (1) to (9) above, wherein the connecting portion has an outer shape that is substantially square when viewed in the stacking direction.

[0103] (11) The multilayer ceramic electronic component according to any one of (1) to (10), wherein, when viewed in the stacking direction, the centroid of the capacitance section, the centroid of the base section, and the centroid of the connection section are substantially aligned.

[0104] (12) A multilayer ceramic electronic component according to any one of (1) to (11), wherein the element body has a plurality of capacitive section dummy electrodes embedded in a portion of the capacitive section on the second surface side, the plurality of capacitive section dummy electrodes having a plurality of first dummy electrodes whose ends are exposed on the first end surface and a plurality of second dummy electrodes whose ends are exposed on the second end surface, and the plurality of first dummy electrodes do not overlap the plurality of second dummy electrodes when viewed in the stacking direction.

[0105] (13) A multilayer ceramic electronic component according to any one of (1) to (12) above, wherein the base body has a plurality of pedestal dummy electrodes embedded in the pedestal, the plurality of pedestal dummy electrodes having a plurality of third dummy electrodes with ends exposed at the third end face and a plurality of fourth dummy electrodes with ends exposed at the fourth end face, and the plurality of third dummy electrodes do not overlap the plurality of fourth dummy electrodes when viewed in the stacking direction.

[0106] (14) A multilayer ceramic electronic component according to any one of (1) to (13) above, a circuit board having a mounting surface, The laminated ceramic electronic component is mounted on the circuit board so that the fourth surface of the base faces the mounting surface. [Explanation of symbols]

[0107] 1.1A multilayer ceramic electronic component (multilayer ceramic capacitor) 2 Base 2p element precursor 3 Capacity part 3a 1st page 3b 2nd side 3c 1st end face 3d second end face 3e 1st side 3f 2nd side 31 Protective layer 4 Base 4a 3rd page 4b Side 4 4c 3rd end face 4d 4th end face 4e 3rd aspect 4f 4th side 5 Connection 6 Dielectric Layer 7 Internal electrode 7a 1st internal electrode 7b 2nd internal electrode 8 External electrode 8a 1st external electrode 8b 2nd external electrode 81 1st layer 82 2nd layer 83 1st layer 84 2nd layer 85 3rd layer 86 1st layer 87 2nd layer 9 Crosslinked part 9a Ceramic particles 9b Metal particles 10 Circuit Board 10a Mounting surface 11 1st substrate electrode 12 2nd substrate electrode 13 Regulatory Department 14 Dummy electrode (capacitor dummy electrode) 14a First dummy electrode 14b Second dummy electrode 15 Dummy electrode (base dummy electrode) 15a Third dummy electrode 15b Fourth dummy electrode 16 Ceramic green sheet 17 Internal electrode pattern sheet 18 Slit Paste 19 Capacitor temporary laminate 20 Temporary laminate 21 Mother laminate 22 Virtual dividing line 23,24 Dummy electrode pattern sheet 25 Capacitor temporary laminate 26 Temporary laminate 27 Mother laminate 28 Virtual dividing line 100 Mounting Structure G void area S solder

Claims

1. an element body having a capacitance portion, a base portion, and a connection portion; an external electrode; the capacitance section is sandwiched between protective layers in a stacking direction and is formed by alternately stacking a plurality of dielectric layers and a plurality of internal electrodes, and has a first surface and a second surface opposing each other in the stacking direction, a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction, and a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction and the length direction, and the plurality of internal electrodes are exposed at the first end surface or the second end surface according to polarity, the pedestal portion has a third surface and a fourth surface facing each other in the stacking direction, a third end surface and a fourth end surface facing each other in the length direction, and a third side surface and a fourth side surface facing each other in the width direction, the third surface facing the second surface of the capacitance portion, the connection portion connects the second surface of the capacitance portion and the third surface of the base portion, the external electrodes include a first external electrode located at least on the first end surface and a second external electrode located at least on the second end surface, the connection portion is included in the capacitance portion and the base portion when viewed in the stacking direction, and has a length in the length direction or the width direction that is smaller than that of the capacitance portion and the base portion.

2. the first end surface and the second end surface are substantially flush with the third end surface and the fourth end surface, respectively; 2. The multilayer ceramic electronic component according to claim 1, wherein the first side surface and the second side surface are substantially flush with the third side surface and the fourth side surface, respectively.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein the base portion is a non-vibration portion that does not exhibit an electrostrictive effect.

4. 3. The multilayer ceramic electronic component according to claim 1, further comprising a bridge portion located around the connection portion between the second surface and the third surface, bridging the second surface and the third surface.

5. The multilayer ceramic electronic component according to claim 4 , wherein the bridge portion includes a plurality of ceramic particles.

6. The multilayer ceramic electronic component according to claim 5 , wherein the plurality of ceramic particles are not in contact with at least one of the second surface and the third surface.

7. The multilayer ceramic electronic component according to claim 5 , wherein the bridge portion includes a plurality of metal particles located between the plurality of ceramic particles.

8. 3. The multilayer ceramic electronic component according to claim 1, wherein at least a portion of the external electrode is located between the second surface and the third surface.

9. The multilayer ceramic electronic component according to claim 8 , wherein the external electrodes contain a conductive resin.

10. 3. The multilayer ceramic electronic component according to claim 1, wherein the connecting portion has an outer shape of a substantially square when viewed in the stacking direction.

11. 3. The multilayer ceramic electronic component according to claim 1, wherein the centroids of the capacitance portion, the pedestal portion, and the connection portion are substantially aligned when viewed in the stacking direction.

12. 3. The multilayer ceramic electronic component according to claim 1, wherein the base body has a plurality of capacitive section dummy electrodes embedded in a portion of the capacitive section on the second surface side, the plurality of capacitive section dummy electrodes including a plurality of first dummy electrodes having ends exposed at the first end surface and a plurality of second dummy electrodes having ends exposed at the second end surface, and when viewed in the stacking direction, the plurality of first dummy electrodes do not overlap with the plurality of second dummy electrodes.

13. 3. The multilayer ceramic electronic component according to claim 1, wherein the base body has a plurality of pedestal dummy electrodes embedded in the pedestal, the plurality of pedestal dummy electrodes including a plurality of third dummy electrodes having ends exposed at the third end surface and a plurality of fourth dummy electrodes having ends exposed at the fourth end surface, and when viewed in the stacking direction, the plurality of third dummy electrodes do not overlap with the plurality of fourth dummy electrodes.

14. The multilayer ceramic electronic component according to claim 1 or 2; a circuit board having a mounting surface, The laminated ceramic electronic component is mounted on the circuit board so that the fourth surface of the base faces the mounting surface.

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