Semiconductor device

Abstract

To provide a semiconductor device which performs product-sum operation in parallel while suppressing signal delay.SOLUTION: An operation circuit MA including first to fourth registers RG1 to 4, an adder AD, a multiplier MP, a selector SLC, and a storage section OMS, wherein an output-terminal OT1 of the first register is electrically coupled to an input-terminal IT2 of the second register, an output-terminal OT2 of the second register is electrically coupled to a second input-terminal XI of the multiplier, an output-terminal ZO of the multiplier is electrically coupled to a first input-terminal FT of the adder, and an output-terminal TT of the adder is electrically coupled to an input-terminal IT3 of the third register; The output node OT3 of the third register is electrically coupled to the first input node of the selector, and the output node of the selector is electrically coupled to the input node IT4 of the fourth register. The memory portion is electrically connected to a first input terminal WI of the multiplier, and first data corresponding to a context signal input from a wiring CTX is read and input to the first input terminal of the multiplier.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to an arithmetic circuit, a semiconductor device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a driving method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one embodiment of the present invention disclosed in this specification more specifically relates to The technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, and imaging devices. Devices, storage devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, These manufacturing methods and inspection methods can be cited as examples. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the larger von Neumann architecture, parallel processing can be performed with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. Artificial neural networks (ANNs) are used to This makes it possible to make inferences with accuracy comparable to or even exceeding that of humans. In this network, the main operation is the sum of weighted neuron outputs, i.e., the sum of products operation. do.

[0005] Depending on the problem that the artificial neural network is trying to solve, The optimal values ​​for the depth of the network hierarchy, the number of neuron elements, etc. vary, so it is necessary to select the optimal values ​​that are suitable for the problem. It is preferable to construct an artificial neural network so that has programmable logic elements and allows multiple contexts to be used to communicate between circuits. By switching between conductive and non-conductive states, it is possible to create a suitable artificial neural network. A semiconductor device that performs product-sum operations with a small circuit scale is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2018-110386 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, the development of artificial intelligence has been actively promoted, and the "inference" (cognition) that artificial intelligence performs has become increasingly important. The results of the computation of artificial neural networks are used to generate the information. To solve complex problems, the size of the artificial neural network must be increased. In other words, it is necessary to deepen the hierarchy of the artificial neural network, Measures such as increasing the number of neuron elements will be necessary.

[0008] When implementing a multiply-and-accumulate circuit as an operation of an artificial neural network, it is necessary to increase the degree of parallelism. On the other hand, it is preferable to place a multiply-and-accumulate circuit in the arithmetic block. When the model becomes larger, the number of parallel sum-of-products circuits increases. The input and output terminals of the circuit, and the buffer memory that stores the calculation results are used to determine the arrangement of the This can result in long wiring distances in the circuit layout. As the routing distance becomes longer, the parasitic resistance of the wiring and the parasitic resistance of other surrounding wiring or elements may increase. Since the raw capacitance also increases, the signal transmitted through the wiring is delayed, and the operating speed of the sum-of-products circuit is slowed down. may be reduced.

[0009] An object of one embodiment of the present invention is to provide a novel arithmetic circuit. In one aspect, by including the above-mentioned arithmetic circuit, signal delay is suppressed and multiplication and accumulation operations are performed in parallel. It is an object of the present invention to provide a semiconductor device that can perform this.

[0010] Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like. An object of one embodiment of the present invention is to provide an electronic device including the semiconductor device. do.

[0011] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0012] (1) One aspect of the present invention is a first register, a second register, a third register, and a fourth register. The first level is an arithmetic circuit having an adder, a multiplier, a selector, and a first storage unit. The output terminal of the second register is electrically connected to the input terminal of the second register. The terminal is electrically connected to a first input terminal of the multiplier. The output terminal of the multiplier is electrically connected to a first input terminal of the adder. The output terminal of the adder is electrically connected to the first input terminal of the third register. an output terminal of the third register electrically connected to a first input terminal of the selector; The output terminal of the selector is electrically connected to the input terminal of the fourth register. The first storage unit is electrically connected to the second input terminal of the multiplier, and the first storage unit stores The first data corresponding to the input context signal is read out and input to the second input terminal of the multiplier. It has the function to input.

[0013] (2) Another embodiment of the present invention is a semiconductor device including a first operational circuit and a second operational circuit. The second arithmetic circuit has the same circuit configuration as the first arithmetic circuit. a first resistor, a second resistor, a third resistor, a first terminal, a second terminal, and a third terminal; In the first operational circuit, the input terminal of the first register is an output terminal of the first resistor electrically connected to the first terminal, and an input terminal of the second resistor; The output terminal of the third resistor is electrically connected to the second terminal, and the output terminal of the third resistor is electrically connected to the fourth terminal. In addition, the first arithmetic circuit receives a context signal from the first storage unit. The first storage unit has a function of reading out first data corresponding to the context signal from the first storage unit. The first arithmetic circuit stores the second data input to the first terminal in the first register or the second register. The first arithmetic circuit has a function of storing the first data and the second data stored in the second register. The function to multiply the first data by the second data to generate the third data and the function to multiply the third data by the third terminal. a function of adding the fourth data stored in the third register to generate added data; The first arithmetic circuit has a function of storing the second data stored in the first register. The function of outputting to the second terminal and inputting to the first terminal of the second calculation circuit and the function of storing the data in the third register. The sum data is output to the fourth terminal and added to the third terminal of the second calculation circuit as the fourth data. It has the function of inputting data.

[0014] (3) Alternatively, one aspect of the present invention is the above-mentioned configuration (2), further comprising: an input register; a second storage unit; The second storage unit is electrically connected to the input terminal of the input register. The second storage unit reads out the second data and stores it in the input register via the input register. It has a function of inputting from the output terminal to the first terminal of the first arithmetic circuit.

[0015] (4) Alternatively, one embodiment of the present invention is a circuit configuration in which the first arithmetic circuit in the configuration (3) has the same circuit configuration as the first arithmetic circuit. The first and third arithmetic circuits each have a selector and a The first operation circuit and the third operation circuit may have a fourth register, a fifth terminal, and a sixth terminal. In each of the circuits, the first input terminal of the selector is electrically connected to the output terminal of the third register. The second input terminal of the selector is electrically connected to the fifth terminal, and the output terminal of the selector is electrically connected to the fifth terminal. The terminal is electrically connected to the input terminal of the fourth register, and the output terminal of the fourth register is electrically connected to the sixth the fifth terminal of the first arithmetic circuit is electrically connected to the sixth terminal of the third arithmetic circuit. is connected to.

[0016] (5) Alternatively, one aspect of the present invention is to provide a circuit for calculating the activation function in the configuration (4). The circuit may include a circuit for converting data output from the sixth terminal of the first arithmetic circuit or the third arithmetic circuit. The activation function is calculated for the vectors, and the result of the calculation is stored in the second storage unit.

[0017] (6) Alternatively, one aspect of the present invention is a semiconductor device according to any one of the above (2) to (5), wherein a plurality of first switches and a plurality of second switches. The first terminal of the second arithmetic circuit is electrically connected to the first terminal of the second arithmetic circuit through a switch. is electrically connected to the fourth terminal of the second arithmetic circuit via a plurality of second switches.

[0018] (7) Another embodiment of the present invention is a semiconductor device including any one of the semiconductor devices (2) to (6) above and a housing. The electronic device is an electronic device having a neural network. It has the function of performing calculations.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0020] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0021] An example of the case where X and Y are electrically connected is The elements that function as One or more devices (diode, display device, light-emitting device, load, etc.) are connected between X and Y. The switch has a function to control on / off. This means that the switch is either in a conducting state (ON state) or a non-conducting state (OFF state), and the current It has the function of controlling whether or not to let water flow.

[0022] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0023] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are directly connected (i.e., there is no other This includes cases where the device is connected without any element or other circuit in between.

[0024] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0026] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the term "resistance element" can be used as a circuit element, wiring, etc. " refers to wiring with resistance, transistors with current flowing between the source and drain, and diodes. Therefore, the term "resistive element" is used to refer to "resistor," "Load" or "area with a resistance value" and conversely, "resistance" or The terms "load" and "area having a resistive value" can be replaced with terms such as "resistive element." The resistance value is preferably, for example, 1 mΩ or more and 10 Ω or less, and more preferably The resistance can be set to 5 mΩ or more and 5 Ω or less, and more preferably 10 mΩ or more and 1 Ω or less. , for example, 1 Ω or more, 1×10 9 It may be set to Ω or less.

[0027] In this specification, the term "capacitance element" refers to a capacitance element having a capacitance value higher than 0 F. a circuit element having a capacitance value, a wiring area having a capacitance value, a parasitic capacitance, a gate of a transistor Therefore, in this specification, a "capacitive element" refers to a pair of Not only circuit elements including electrodes and dielectrics included between the electrodes, but also wiring and wiring The parasitic capacitance that appears between the gate and the source or drain of the transistor. Also, the term "capacitance element," "parasitic capacitance," and "gate capacitance" are included. Terms such as "amount" can be replaced with terms such as "capacity" and vice versa. The term "capacitance element," "parasitic capacitance," "gate capacitance," etc. In addition, the term "pair of electrodes" in "capacitance" can be used to refer to "pair of conductors" or "pair of The capacitance value can be expressed as: For example, the capacitance can be set to 0.05 fF or more and 10 pF or less. It may be set to 10 μF or more.

[0028] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0029] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0030] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the earth potential (ground potential), then "voltage" can be rephrased as "potential." Round potential does not necessarily mean 0V. Also, potential is relative. By changing the reference potential, the potential applied to the wiring, the potential applied to the circuit, etc. The potential, the potential output from the circuit, etc. also changes.

[0031] In addition, in this specification, the terms "high level potential" and "low level potential" are used to refer to For example, if two wires are both at a high level potential, When it says "acts as a wire supplying the The high level potentials do not have to be equal to each other. If both are described as "functioning as wiring that supplies low-level potential," The low level potentials provided by the respective switches may not be equal to each other.

[0032] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element This can be rephrased as "current flows through element A" or "current flows through element A." A statement such as "current is input" can be rephrased as "current is output from element A" Let's say.

[0033] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0034] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0035] The terms "above" and "below" mean that the positional relationship of the components is directly above or directly below, and For example, the expression "electrode B on insulating layer A" does not necessarily mean that the electrodes are in contact with each other. In this case, electrode B does not need to be formed directly on insulating layer A. This does not exclude the inclusion of other components between the two.

[0036] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to

[0037] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. It does not limit the function of the element. For example, "electrode" is used as part of "wiring." Furthermore, the terms "electrode" and "wiring" may be used interchangeably, and vice versa. This also includes cases where the "electrodes" and "wiring" are integrally formed. "Terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" refers to a combination of multiple "electrodes," "wiring," "terminals," etc. For example, "electrode" is a "wiring" or "terminal." For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably with "area." " may be replaced with terms such as "

[0038] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" have been changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". In addition, the opposite is also true, and terms such as "signal line" can be used to refer to "power line". In some cases, it may be possible to change the term to "potential" or "voltage" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change the term to something like this.

[0039] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This leads to, for example, an increase in defect level density in semiconductors and a decrease in carrier mobility. When the semiconductor is an oxide semiconductor, the crystallinity may be reduced. Impurities that change the properties of semiconductors include, for example, Group 1 elements, Group 2 elements, and Group 13 elements. Group elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, , hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen Specifically, when the semiconductor is a silicon layer, there are impurities that change the properties of the semiconductor. As the pure substance, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements (however, (oxygen and hydrogen not included)

[0040] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0041] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction.

[0043] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "roughly perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. This refers to a state in which something is happening. [Effects of the Invention]

[0044] According to one embodiment of the present invention, a novel arithmetic circuit can be provided. In some embodiments, by providing the above-described arithmetic circuit, it is possible to suppress signal delay and perform multiply-and-add operations in parallel. It is possible to provide a semiconductor device capable of performing calculations.

[0045] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0046] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0047] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 6]FIG. 6 is a diagram illustrating an example of the configuration of a CNN. [Figure 7] FIG. 7 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9A is a diagram for explaining filter values ​​included in a filter, and FIG. 9B is a block diagram showing the filter values ​​read into the arithmetic circuit. [Figure 10] FIG. 10A is a diagram illustrating pixel data included in image data, and FIG. 10B is a diagram illustrating pixel data input to an arithmetic circuit. [Figure 11] FIG. 11 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 12] 12A and 12B are diagrams for explaining pixel data input to the arithmetic circuit. [Figure 13] FIG. 13 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 14] FIG. 14 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 15] FIG. 15 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 16] FIG. 16 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 17] FIG. 17 is a diagram illustrating the calculation results output from the calculation circuit. [Figure 18] FIG. 18 is a diagram illustrating image data (feature map) in which only characteristic parts are extracted by a filter. [Figure 19] 19A and 19B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 21] FIG. 21 is a timing chart showing an example of the operation of the semiconductor device. [Figure 22]22A and 22B are diagrams for explaining pixel data input to the arithmetic circuit. [Figure 23] FIG. 23 is a diagram illustrating the filter value read out to the arithmetic circuit. [Figure 24] 24A to 24C are diagrams for explaining the calculation results output from the calculation circuit. [Figure 25] FIG. 25 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a diagram for explaining neuron signals input to the arithmetic circuit and weighting coefficients read out to the arithmetic circuit. [Figure 27] 27A to 27C are circuit diagrams showing examples of the configuration of a memory cell included in a memory circuit. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] 30A to 30C are cross-sectional views showing examples of the structure of a transistor. [Figure 31] 31A and 31B are cross-sectional views showing examples of the structure of a transistor. [Figure 32] FIG. 32 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 33] 33A and 33B are cross-sectional views showing examples of the structure of a transistor. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35] FIG. 35A is a top view showing an example of the configuration of a capacitor, and FIGS. 35B and 35C are cross-sectional perspective views showing the example of the configuration of a capacitor. [Figure 36] FIG. 36A is a top view showing an example of the configuration of a capacitor, FIG. 36B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 36C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 37]FIG. 37A is a diagram illustrating the classification of IGZO crystal structures, FIG. 37B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 37C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 38] FIG. 38A is a perspective view showing an example of a semiconductor wafer, FIG. 38B is a perspective view showing an example of a chip, and FIGS. 38C and 38D are perspective views showing an example of an electronic component. [Figure 39] FIG. 39 is a perspective view showing an example of an electronic device. [Figure 40] 40A to 40C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0048] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0049] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information from the input is sometimes called "inference" or "cognition."

[0050] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0051] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can also be called an OS FET or an OS transistor. When a transistor is described as a metal oxide or oxide semiconductor, it is replaced with a transistor having a metal oxide or oxide semiconductor. It can be said.

[0052] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0053] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0054] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0055] The contents described in the embodiments refer to the following in each embodiment (or example): The content described using various figures or the text in the specification be.

[0056] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0057] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0058] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0059] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0060] (Embodiment 1) In this embodiment, a configuration of a digital arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described. and explain.

[0061] FIG. 1 is a block diagram showing an example of the configuration of a computing device 100. The computing device 100 includes a control circuit. A path CTLR, a MAC (Multiply-Accumulate) array MAR, and a record The memory unit MEMD and the circuits AF[1] to AF[v] (v is an integer of 2 or more) are included. do.

[0062] The MAC array MAR includes, for example, a plurality of arithmetic circuits MA. In the AC array MAR, the AC array is arranged in a matrix of u×v (u is an integer of 2 or more). That is, the MAC array MAR has u×v arithmetic circuits MA. In FIG. 1, symbols [, ] are added to indicate the location where the arithmetic circuit MA is provided. For example, the arithmetic circuit MA located in row 1, column 1 is written as arithmetic circuit MA[1,1]. For example, the arithmetic circuit MA located in row u and column v is called arithmetic circuit MA[u,v]. It is written.

[0063] The arithmetic circuit MA has, for example, the function of MAC. Specifically, the arithmetic circuit MA has: First data (for example, w[1] to w[m], where m is a positive integer) It has a function of performing a product-sum operation with the second data (for example, x[1] to x[m]). For example, the first data is either multiplier data or multiplicand data, and the second data is , can be the other of the multiplier data and the multiplicand data. When performing calculations on a hierarchical neural network, the first data is used as a weighting coefficient The second data is the value of the neuron's output signal, and the weight coefficient and the neuron's output are The sum of products with the value of the force signal can be calculated.

[0064] The MAC array MAR is composed of multiple programmable switches PR and multiple programmable In FIG. 1, the programmable switches PR are One of the plurality of programmable logic circuits is electrically connected to one of the plurality of arithmetic circuits MA. One of the matrix switches PC is electrically connected to one of the plurality of arithmetic circuits MA. Therefore, in Fig. 1, the programmable switch PR, The symbols for the programmable switches PC are followed by brackets [,] to indicate their positions.

[0065] The number of wires electrically connected between the arithmetic circuit MA and the programmable switch PR The number of lines may be one or more. The number of wires electrically connected between the switch PC may be one or more. That is, the programmable switch PR and the programmable switch PC may be The number of wires electrically connecting the arithmetic circuit MA and the arithmetic circuit MA is determined according to the number of terminals of the arithmetic circuit MA. It can be done.

[0066] The programmable switches PR[1,1] to PR[2,3] located in the first row of the MAC array MAR Each of the programmable switches PR[1,v] is electrically connected in series. Similarly, the programmable switch PR[2,1 ] to the programmable switch PR[2,v] are electrically connected in series, The programmable switches PR[u,1] to PR[u,2] located in the u-th row of the MAC array MAR Each of the programmable switches PR[u,v] is electrically connected in series.

[0067] In addition, the programmable switch PC[1,1 ] to the programmable switch PC[u,1] are electrically connected in series. Similarly, the programmable switch PC[ Each of the programmable switches PC[u,2] to PC[u,2] is electrically connected in series. The programmable switch PC[1,v] located in the v-th column of the MAC array MAR Each of the programmable switches PC[u,v] is electrically connected in series. do.

[0068] Programmable switches PR[1,1] to PR[u,1] As an example, they are electrically connected to wirings XL[1] to XL[u]. In addition, the programmable switches PC[u,1] to PC[u, For example, each of the wirings YL[1] to YL[v] is electrically connected to the wirings YL[1] to YL[v]. are.

[0069] Each of the wirings XL[1] to XL[u] may, for example, be connected to a plurality of registers RG. The wiring YL[1] to the wiring YL Each of [v] is, for example, electrically connected to the memory unit MEMD.

[0070] The memory unit MEMD performs a multiplication and addition operation on the first data and the second data in the MAC array MAR. In order to perform the calculation, for example, MAC It has a function to hold second data to be input to the array MAR. The first signal transmitted from the MAC array MAR via the wires YL[1] to YL[v] The second data has a function of holding the result of a multiplication and accumulation operation between the first data and the second data.

[0071] A plurality of resistors electrically connected to the wirings XL[1] to XL[u] The data RG is provided to perform pipeline processing in the arithmetic device 100. Specifically, the register RG is, for example, a programmable access control register (MAC) array MAR in FIG. The wiring XL[1] between the matrix switch PR[1,1] and the memory unit MEMD is Registers RG[1,1] to RG[1,p] (p is an integer equal to or greater than 1) are provided. The registers RG[1,1] to RG[1,p] are adjacent registers. In RG, the input terminal and the output terminal are electrically connected, and the resistor RG[ The input terminal of the register RG[1,p] is electrically connected to the memory unit MEMD. The output terminal is electrically connected to the programmable switch PR[1,1].

[0072] Similarly, the programmable switch PR[2,1] of the MAC array MAR and the memory unit The wiring XL[2] between MEMD and the registers RG[2,1] to RG[2, The registers RG[2,1] to RG[2,p] are In the adjacent registers RG, the input terminals and the output terminals are electrically connected to each other, and The input terminal of the register RG[2,1] is electrically connected to the memory unit MEMD. The output terminal of RG[2,p] is electrically connected to the programmable switch PR[2,1]. In addition, the programmable switch PR[u,1] and the memory unit The wiring XL[u] between MEMD and the registers RG[u,1] to RG[u, The registers RG[u,1] to RG[u,p] are In the adjacent registers RG, the input terminals and the output terminals are electrically connected to each other, and The input terminal of the register RG[u,1] is electrically connected to the memory unit MEMD. The output terminal of RG[u,p] is electrically connected to the programmable switch PR[u,1]. It is being done.

[0073] As an example, the register RG receives a pulse as a clock signal. When a voltage is applied, the data (for example, It can be digital data or it can be an electric potential) The register RG has a function to automatically hold the data stored in the register RG. The data stored in the register RG is output to the output terminal of the register RG. When a high level potential is applied as a clock signal, the register RG The data given to the input terminal of the register RG is temporarily held, and the output terminal of the register RG is held Therefore, the register RG outputs the first data to the MAC array MAR. The first data is transmitted to the input register.

[0074] The clock signal is, for example, a signal sent via a wiring CKL, which will be described later. It is possible.

[0075] The register RG preferably holds, for example, 8-bit data, and It is more preferable to hold data, and even more preferable to hold data of 32 bits or more. I wish.

[0076] By the way, for example, between the programmable switch PR[1,1] and the memory unit MEMD, The registers RG[1,1] to RG[1,p] are shifted into one register. Similarly, for example, the programmable switch PR[2,1] and the memory unit M The registers RG[2,1] to RG[2,p] between the EMD and the The programmable switch PR[u,1] and the memory unit ME The registers RG[u,1] to RG[u,p] between MD and This may be replaced with a register.

[0077] As described above, as shown in FIG. 1, a register is provided between the memory unit MEMD and the MAC array MAR. By electrically connecting multiple starter RGs in series, data can be transferred from the memory unit MEMD to the MAC array. The data transfer to the MAR can be pipelined. By connecting several of them in series, the problem of data transmission caused by parasitic resistance and capacitance can be reduced. This can reduce the signal delay required for transmission.

[0078] The control circuit CTLR is electrically connected to the MAC array MAR. The CTLR and the MAC array MAR are electrically connected to a wiring CKL.

[0079] The wiring CKL functions as a wiring for supplying a clock signal, for example. The clock signal may be, for example, a pulse voltage.

[0080] The control circuit CTLR is, for example, an arithmetic circuit MA[ 1,1] to the arithmetic circuit MA[u,v]. The control circuit CTLR is a memory unit included in the arithmetic circuit MA (corresponding to the memory unit OSM etc. described later). A function to send a selection signal to write data to the memory card, and a function to send the data. For example, the control circuit CTLR includes a register included in the arithmetic circuit MA. It transmits signals to control the registers (such as registers RG2 to RG4 described later). In addition, the control circuit CTLR performs the following functions based on the clock signal from the wiring CKL: It may have the ability to generate different clock signals.

[0081] The circuits AF[1] to AF[v] are connected to the wirings YL[1] to YL[v], respectively. In addition, each of the circuits AF[1] to AF[v] is electrically connected to the The memory is electrically connected to the memory module MEMD.

[0082] The circuits AF[1] to AF[v] are, for example, wirings YL[1] to YL[v]. The function that outputs the value of the activation function using the result of the product-sum operation sent from the wiring YL[v]. The activation function can be, for example, a step function, ReL It can be a U function, a sigmoid function, a tanh function, etc.

[0083] In addition, each of the circuits AF[1] to AF[v] may be implemented, for example, as a pooling process. The pooling process may be, for example, a maximum pooling process, It can be average pooling, Lp pooling, etc.

[0084] Each of the circuits AF[1] to AF[v] outputs a value of the activation function. The circuit may include a circuit for performing a multiplication process, a circuit for performing a pooling process, etc.

[0085] In other words, by using the arithmetic device 100, it is possible to perform the calculation of a hierarchical neural network. It can perform computations such as convolutional neural network (CNN) calculations.

[0086] However, one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. The semiconductor device shown in FIG. 1 may be modified depending on the situation. For example, the semiconductor device shown in FIG. As shown in the arithmetic device 100A, circuits AF[1] to A are provided in the arithmetic device 100 shown in FIG. A configuration without F[v] may also be adopted.

[0087] <Configuration example of arithmetic circuit MA> Next, an example of the configuration of the arithmetic circuit MA will be described.

[0088] 3 is a block diagram showing an example of an arithmetic circuit MA. , register RG1, register RG2, register RG3, register RG4, and multiplier The clock generator 100 includes an MP, an adder AD, a selector SLC, and a storage unit OSM.

[0089] The arithmetic circuit MA shown in FIG. 3 has, as an example, terminals SI, SO, and MI. , a terminal MO, a terminal AI, and a terminal AO.

[0090] The register RG1 has a terminal IT1 corresponding to the input terminal and a terminal OT1 corresponding to the output terminal. The register RG2 has a terminal IT2 corresponding to an input terminal and an output terminal The terminal OT2 corresponds to a voltage input terminal, and the terminal CT2 corresponds to an enable input terminal. The register RG3 has a terminal IT3 corresponding to an input terminal, a terminal OT3 corresponding to an output terminal, The register RG4 has a terminal CT3 corresponding to an enable input terminal. The input terminal has a terminal IT4 corresponding to an input terminal, and a terminal OT4 corresponding to an output terminal. Although not shown in the figure, each of the registers RG1 to RG4 is connected to the wiring CKL. It is assumed that they are electrically connected and receive a clock signal from the wiring CKL.

[0091] The multiplier MP has a terminal WI corresponding to the first input terminal and a terminal WI corresponding to the second input terminal. The adder AD has a first input terminal XI and a terminal ZO corresponding to an output terminal. terminal FT corresponding to the first input terminal, terminal ST corresponding to the second input terminal, and terminal It has a child TT.

[0092] The terminal IT1 of the resistor RG1 is electrically connected to the terminal SI, and the terminal OT1 is electrically connected to the terminal IT2 of the resistor RG2 and the terminal SO. The terminal OT2 of the register RG2 is electrically connected to the terminal XI of the multiplier MP. The terminal CT2 of No. 2 is electrically connected to the wiring SLT.

[0093] The memory unit OSM is electrically connected to the wiring CF, the wiring WDT, and the wiring CTX. Moreover, the storage unit OSM is electrically connected to the terminal WI of the multiplier MP.

[0094] The terminal ZO of the multiplier MP is electrically connected to the terminal FT of the adder AD. The terminal ST of the calculator AD is electrically connected to the terminal AI.

[0095] The terminal IT3 of the register RG3 is electrically connected to the terminal TT of the adder AD. The terminal OT3 of RG3 is electrically connected to the terminal AO and the first input terminal of the selector SLC. In addition, the terminal CT3 of the resistor RG3 is electrically connected to the wiring URST. There are.

[0096] The terminal IT4 of the register RG4 is electrically connected to the output terminal of the selector SLC. The terminal OT4 of the star RG4 is electrically connected to the terminal MO.

[0097] The second input terminal of the selector SLC is electrically connected to the terminal MI. The control terminal of the transistor SLC is electrically connected to the wiring SEL.

[0098] For example, when a pulse voltage is applied as a clock signal, the register RG1 The data provided to the terminal IT1 (for example, digital data) In this specification, In the document, the register RG1 receives a clock signal, for example, from a low level potential to a high level. When a potential change occurs in the potential, the data given to the input terminal of register RG1 is temporarily stored and the data is output from the output terminal of register RG1. In addition, the register RG1 stores the data stored in the register RG1 as an example. It has the function of outputting to terminal OT1.

[0099] As an example, the register RG2 outputs an enable signal to the terminal CT2, which is an enable input terminal. When a pulse voltage is applied as a clock signal, the voltage applied to terminal IT2 is The data (for example, digital data) stored in the For example, when a high level potential is input to the enable input terminal of the register RG2, When a potential change occurs from a low level potential to a high level potential as a lock signal, the register The data given to the input terminal of RG2 is temporarily held. As an example, the data held in the register RG2 is transmitted to the terminal OT2. It has the function to output to.

[0100] When a low-level potential is input to the terminal CT2 of the register RG2, the clock signal Even if a potential change occurs from a low level potential to a high level potential as a signal, the resistor RG2 The data input to the IT2 register is not retained. However, the data input to the RG2 register is not retained. Even when a low-level potential is input to the terminal CT2, the The data will be output.

[0101] The wiring SLT functions as a wiring that supplies an enable signal to the register RG2, for example. It works.

[0102] The resistor RG1 is configured to change the potential given by the wiring CKL from a low level potential to a high level potential, for example. By changing to the register potential, the data input to the terminal IT1 is held and the register RG1 The data is transmitted from the terminal OT1 of the register RG2 to the terminal IT2 of the register RG2. When a high level potential is applied to T, the resistor RG2 is connected to the potential applied by the wiring CKL. For example, when the potential changes from low to high, the resistor RG2 The data input to the terminal IT2 is held, and the data is output from the terminal OT2 of the register RG2 to the multiplier The data is sent to terminal XI of the MP.

[0103] The storage unit OSM has a function of storing data according to the context, for example. The data according to the context in this case is, for example, the first data used in the operation of the multiplier MP. The memory unit OSM can obtain the context signal from the wiring CTX. , a data set according to the context signal is selected, and a plurality of data sets are input to the terminals WI of the multiplier MP. The context signal is a digital signal. Alternatively, it may be an analog signal.

[0104] In addition, the memory unit OSM receives a write signal from the wiring WDT, and The configuration data sent from the routing CF for the context according to the signal It has the function of writing to the data.

[0105] The context signal, write signal, and configuration data are, for example, It can be supplied from the control circuit CTLR. In this case, the wiring CTX, wiring WDT, wiring CF may be electrically connected to a control circuit CTLR.

[0106] The multiplier MP multiplies, for example, the first data input to the terminal WI and the second data input to the terminal XI. The result of the multiplication (hereafter referred to as the multiplied data) is output to the terminal For example, if the first data w is input to the terminal WI, When x is input as the second data to the terminal XI, the terminal ZO of the multiplier MP receives the multiplication signal. The calculation data is output as w×x.

[0107] The adder AD, for example, multiplies the multiplication data input to the terminal ZO and the data input to the terminal ST. The result of the addition (hereafter referred to as the added data) is output to the terminal TT. It has the function of providing

[0108] As an example, the register RG3 outputs an enable signal to the terminal CT3, which is an enable input terminal. When a pulse voltage is applied as a clock signal, the voltage applied to terminal IT3 It has the function of temporarily storing the added data. For example, the starter RG3 receives a high level potential at the enable input terminal and a clock signal. When a potential change occurs from a low level potential to a high level potential, the The data given to the input terminal is temporarily stored in the register R. As an example, G3 outputs the data held in register RG3 to terminal OT3. It has the function of

[0109] When a low-level potential is input to the terminal CT3 of the register RG3, the clock signal Even if a potential change occurs from a low level potential to a high level potential as a signal, the resistor RG3 The data input to the IT3 register is not retained. However, the data input to the RG3 register is not retained. Even when a low-level potential is input to the terminal CT3, the The data will be output.

[0110] The wiring URST is, for example, a wiring that supplies an enable signal to the register RG3. It works.

[0111] The selector SLC conducts between either the first input terminal or the second input terminal and the output terminal. and a non-conductive state is established between the other of the first input terminal or the second input terminal and the output terminal. The selector SLC has the function of connecting the first input terminal to the output terminal. The selection of either the first or second input terminal is determined by the potential of the wiring SEL input to the control terminal. Here, as an example, when a high level potential is input to the control terminal, The SLC establishes a conductive state between the first input terminal and the output terminal, and a low-level potential is applied to the control terminal. When input, the selector SLC establishes a conductive state between the second input terminal and the output terminal. Let's say.

[0112] In the selector SLC, the first input terminal and the output terminal are in a conductive state, and the second When there is no conduction between the input terminal and the output terminal, the terminal OT3 of the resistor RG3 The addition data from the selector SLC is input to the terminal IT4 of the register RG4. In this case, the second input terminal and the output terminal are in a conductive state, and the first input terminal and the output terminal are in a conductive state. When there is no electrical continuity between the terminals, data from the terminal MI is input to the terminal It is input to child IT4.

[0113] The wiring SEL is, for example, a wiring for supplying a signal for controlling the selector SLC. It works like this.

[0114] For example, when a pulse voltage is applied as a clock signal, the register RG4 The data provided to the terminal IT4 (for example, digital data) In this specification, the register RG4 receives, for example, a clock signal from a low level potential When a potential change occurs in the high-level potential, the corresponding The register RG4 temporarily stores the data. The data held in the RG4 is output to the terminal OT4.

[0115] <Programmable switch configuration> Next, referring to Figures 4 and 5, the programmable switch PR and the programmable This article explains about the Lu Switch PC.

[0116] The programmable switch PR[ located on the sth row (s is an integer between 1 and u) s,1] to programmable switch PR[s,v] (not shown in Figures 1 and 2) In each of the arithmetic circuits MA[s,1] to MA[s,v], It has the function of controlling the conductive and non-conductive states.

[0117] For example, the programmable switch PR can have a circuit configuration shown in FIG. In Figure 4, the programmable switch PR[s,g] (g is an integer between 1 and v-1) ) and programmable switch PR[s,h] (h is an integer greater than g and less than v) ) as well as the configuration example of the arithmetic circuit MA[s,g] and the arithmetic circuit MA[s,h] are also shown. is doing.

[0118] In addition, in FIG. 4, the arithmetic circuit MA[s, g] and the arithmetic circuit MA[s, h] are As the terminals, terminal SI, terminal SO, terminal AI, and terminal AO are shown.

[0119] The programmable switches PR[s,g] and PR[s,h] are , electrically connected to a plurality of wirings SL. Also, the programmable switches PR[s, g] and programmable switches PR[s, h] are electrically connected to multiple wirings ALX. It is being done.

[0120] The plurality of wirings SL and the plurality of wirings ALX are, for example, arranged in the row direction of the MAC array MAR. The wiring is extended to the

[0121] In addition, the wirings SL are electrically connected to the wiring XL[s]. Although the wiring XL[s] is illustrated as multiple lines, the wiring XL[s] is treated as a single wiring. In this case, the wiring SL may be electrically connected to one of the wirings SL.

[0122] Programmable switch PR[s,g] and programmable switch PR[s,h] Each of them has, for example, a plurality of switches. For example, in FIG. The switch PR[s,g] is composed of multiple switches SW_SI[s,g] and multiple switches S W_SO[s,g], multiple switches SW_AIX[s,g], and multiple switches SW AOX[s,g] and a programmable switch PR[s,h] are a plurality of switches. switch SW_SI[s,h], multiple switches SW_SO[s,h], and multiple switches SW_AIX[s,h] and a plurality of switches SW_AOX[s,h]. This shows the progress.

[0123] The terminal SI of the arithmetic circuit MA[s,g] is connected to each of the multiple switches SW_SI[s,g]. a second terminal of one of the plurality of switches SW_SI[s, g] electrically connected to the first terminal of the is electrically connected to one of the wirings SL. The output SO is electrically connected to the first terminal of each of the switches SW_SO[s,g]. The second terminal of one of the switches SW_SO[s, g] is electrically connected to one of the lines SL. The terminals AI of the arithmetic circuit MA[s, g] are connected to multiple switches SW_AI X[s, g] are electrically connected to the first terminals of the plurality of switches SW_AIX[ The second terminal of one of the plurality of wirings ALX is electrically connected to one of the plurality of wirings ALX. The terminal AO of the calculation circuit MA[s,g] is connected to each of the multiple switches SW_AOX[s,g]. and a second terminal of one of the plurality of switches SW_AOX[s,g] electrically connected to the first terminal of the is electrically connected to one of the plurality of wirings ALX.

[0124] The terminal SI of the arithmetic circuit MA[s,h] is connected to each of the multiple switches SW_SI[s,h]. a second terminal of one of the plurality of switches SW_SI[s,h] electrically connected to the first terminal of the is electrically connected to one of the wirings SL. The slave SO is electrically connected to the first terminal of each of the multiple switches SW_SO[s,h]. The second terminal of one of the switches SW_SO[s,h] is electrically connected to one of the wirings SL. The terminals AI of the arithmetic circuit MA[s,h] are connected to multiple switches SW_AI X[s,h] are electrically connected to the first terminals of the plurality of switches SW_AIX[ The second terminal of one of the plurality of wirings ALX is electrically connected to one of the plurality of wirings ALX. The terminal AO of the calculation circuit MA[s,h] is connected to each of the multiple switches SW_AOX[s,h]. and a second terminal of one of the plurality of switches SW_AOX[s,h] is electrically connected to the first terminal of the is electrically connected to one of the plurality of wirings ALX.

[0125] For example, the terminal SO of the arithmetic circuit MA[s,g] and the terminal SI of the arithmetic circuit MA[s,h] , one of the multiple wirings SL is selected and directly connected to that wiring. The relationship between the connected switch SW_SO[s,g] and the switch SW_SI[s,h] The remaining switches SW_SO[s,g] and the remaining switches SW_SO[s,g] are turned on. Switch SW_SI[s,h] should be turned off.

[0126] As with the programmable switch PR, in the t-th column (t is an integer between 1 and v), The programmable switches PC[1,t] to PC[u, 1 and 2) are the arithmetic circuits MA[1,t] to MA[ Each of the transistors [u, t] has a function of controlling the conductive state or non-conductive state of the other.

[0127] For example, the programmable switch PC can have the circuit configuration shown in FIG. In Figure 5, the programmable switch PC[e,t] (e is an integer between 1 and u-1) ) and programmable switch PC[f,t] (f is an integer greater than e and less than u) ) as well as the configuration example of the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t] are also shown in Figure 1. It shows.

[0128] In addition, in FIG. 5, the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t] are As the terminals, terminals AI, AO, MI, and MO are shown.

[0129] The programmable switches PC[e,t] and PC[f,t] are , and are electrically connected to a plurality of wirings ML and a plurality of wirings ALY.

[0130] The plurality of wirings ML and the plurality of wirings ALY are, for example, arranged in the column direction of the MAC array MAR. The wiring is extended to the

[0131] In addition, the multiple wirings ML are electrically connected to the wiring YL[t]. Although the wiring YL[t] is illustrated as multiple lines, the wiring YL[t] is treated as a single line. In this case, the wiring ML may be electrically connected to one of the wirings ML.

[0132] Programmable switch PC[e,t] and programmable switch PC[f,t] Each of them has, for example, a plurality of switches. For example, in FIG. A switch PC[e,t] is composed of multiple switches SW_MI[e,t] and multiple switches S W_MO[e,t], multiple switches SW_AIY[e,t], and multiple switches SW AOY[e,t] and the programmable switch PC[f,t] has a plurality of switches. switch SW_MI[f,t], multiple switches SW_MO[f,t], and multiple switches SW_AIY[f,t] and a plurality of switches SW_AOY[f,t]. This shows the progress.

[0133] The terminal MI of the arithmetic circuit MA[e,t] is connected to each of the multiple switches SW_MI[e,t]. a second terminal of one of the plurality of switches SW_MI[e,t] electrically connected to the first terminal of the is electrically connected to one of the wirings ML. The slave MO is electrically connected to the first terminal of each of the multiple switches SW_MO[e,t]. The second terminal of one of the switches SW_MO[e,t] is electrically connected to one of the wirings ML. The terminals AI of the arithmetic circuit MA[e,t] are connected to multiple switches SW_AI Y[e,t] are electrically connected to the first terminals of the plurality of switches SW_AIY[ The second terminal of one of the elements [e, t] is electrically connected to one of the plurality of wirings ALY. The terminal AO of the calculation circuit MA[e,t] is connected to each of the multiple switches SW_AOY[e,t]. and a second terminal of one of the plurality of switches SW_AOY[e,t] electrically connected to the first terminal of the is electrically connected to one of the plurality of wirings ALY.

[0134] The terminal MI of the arithmetic circuit MA[f,t] is connected to each of the multiple switches SW_MI[f,t]. The second terminal of one of the switches SW_MI[f,t] is electrically connected to the first terminal of the other switch SW_MI[f,t]. , is electrically connected to one of the wirings ML. Also, the terminal of the arithmetic circuit MA[f,t] MO is electrically connected to the first terminal of each of the multiple switches SW_MO[f,t]. A second terminal of one of the switches SW_MO[f,t] is electrically connected to one of the wirings ML. The terminal AI of the arithmetic circuit MA[f,t] is connected to multiple switches SW_AIY [f, t], and a plurality of switches SW_AIY[f , t] is electrically connected to one of the plurality of wirings ALY. The terminal AO of the circuit MA[f,t] is connected to each of the multiple switches SW_AOY[f,t]. a second terminal of one of the switches SW_AOY[f,t] electrically connected to the first terminal; , is electrically connected to one of the plurality of wirings ALY.

[0135] For example, the terminal MO of the arithmetic circuit MA[e,t] and the terminal MI of the arithmetic circuit MA[f,t] , select one of the multiple wirings ML and connect it directly to The relationship between the connected switches SW_MO[e,t] and SW_MI[f,t] Each of the switches is turned on, and the remaining switches SW_MO[e,t] and In addition, for example, the arithmetic circuit The terminal AO of MA[e,t] and the terminal AI of the arithmetic circuit MA[f,t] are connected to each other. When doing so, select one of the multiple wiring ALYs and connect the switches directly to that wiring. switch SW_AOY[e,t] and switch SW_SI[f,t] are in the ON state. and the remaining multiple switches SW_AOY[e,t] and the remaining multiple switches SW_AI Y[f,t] should be set to the off state.

[0136] In FIG. 4, the programmable switch PR and the terminals SI and SO of the arithmetic circuit MA are , terminals AI and AO are electrically connected. a pull switch PC, terminals AI, AO, MI, and MO of an arithmetic circuit MA, However, one embodiment of the present invention is not limited to this. , the arithmetic device 100 is configured such that the programmable switch PR is connected to the terminals SI, SO, AI, and terminal AO, and also as a configuration electrically connected to terminal MI and terminal MO. Then, the programmable switch PC is connected to the terminals AI, AO, MI, and MO. In addition, the terminals SI and SO may also be electrically connected.

[0137] The MAC array MAR includes programmable switches PR[1,1] to PR[1,2]. programmable switch PR[u,v] and programmable switch PC[1,1] or programmable switch The scale of the circuit related to the multiplication and accumulation operation can be changed by the switch PC[u,v]. For example, when a multiply-and-accumulate operation is performed using the MAC array MAR, the arithmetic circuit MA[ 1,t] or the arithmetic circuit MA[u,t] alone is sufficient for the calculation. PR[1,t] to programmable switch PR[u,t] and programmable switch PC[1,t] to the programmable switch PC[u,t], and All the other programmable switches should be turned off.

[0138] <How it works> Next, an example of the operation of the arithmetic device 100 will be described. In this operation method, This section explains an example of the operation of a neural network (CNN).

[0139] CNN is a computational model used to extract features from images. Figure 6 shows an example of the CNN configuration. The CNN consists of a convolutional layer CL, a pooling layer PL, and a fully connected layer In this operation method, for example, The image data IPD is input to the MAC array MAR, and feature extraction is performed. do.

[0140] The convolution layer CL has the function of performing convolution processing on image data. The process involves repeating product-sum operations between a part of the image data and the filter value of the weighting filter. The image features are extracted by convolution in the convolution layer CL.

[0141] The convolution process can use one or more weight filters. When using a filter, it is possible to extract multiple features contained in the image data. The filter has multiple weight filters, filter fil1, filter fil2, and filter fil Although three filters are shown in Figure 6, only three filters are used for convolution processing. The number of filters used may be one, two, four or more. The image data input to L is filtered using filters fil1, fil2, and fil3. 10 shows an example in which data processing is performed to generate image data D1, D2, and D3.

[0142] The convolved image data D1, D2, and D3 are calculated using activation functions, for example. As an example of an activation function, ReLU (Rectified Logarithm) ReLU is a linear unit (RLU) that is used when the input value is negative. If the input value is "0" or greater, the function outputs the input value as is. In addition, other activation functions such as sigmoid function and tanh function can be used. It can also be done as follows.

[0143] Regardless of whether or not the activation function is used, the image data D1, D2, and D3 are, for example, pooled. The pooling layer PL receives the image data from the convolution layer CL and outputs it to the pooling layer PL. It has a function to pool the image data. Pooling is done by dividing the image data into multiple regions. This is a process of dividing the image into parts, extracting predetermined data for each part, and arranging it in a new matrix. Pooling allows us to extract the image data while retaining the features extracted by the convolution layer CL. The pooling is performed by max pooling, average pooling, Lp pooling, A ring or the like can be used.

[0144] CNN extracts features by, for example, the above-mentioned convolution processing, pooling processing, etc. Note that a CNN may have multiple convolutional layers CL and / or multiple pooling layers PL. In FIG. 6, as an example, a convolutional layer CL and a pooling layer PL are used. The layer L is provided in z layers (where z is an integer of 1 or more) (layers L1 to L z ), folding In this case, in each layer L, This allows for more advanced feature extraction. 1, layer L2, layer L z The other layers L are omitted.

[0145] The fully connected layer FCL includes, for example, layers L1 to L z Using the image data obtained through The fully connected layer FCL has the function of determining the image. In other words, the fully connected layer FCL is a fully connected neural network. The computation is performed by the network (FNN). It is either a convolution layer CL or a pooling layer PL. The image data output from the FCL is a two-dimensional feature map, and when input to the FCL, Then, the image data OP obtained by inference using the fully connected layer FCL is D is output.

[0146] <<Convolutional Layer CL Operation 1>> Here, a method of computing the convolution layer CL using the computing device 100 will be described. The arithmetic circuit MA included in the MAC array MAR of the arithmetic device 100 is, for example, It is assumed that the MAs are arranged in a matrix of 9 rows and 10 columns. The C array MAR includes arithmetic circuits MA[1,1] to MA[9,10]. It shall be.

[0147] In addition, the MAC array MAR in this operation method includes a programmable switch PR The programmable switch PC creates a circuit configuration as shown in Figure 7. is the number of the end of the arithmetic circuit MA in one row of the MAC array MAR. The terminal SO is connected to the terminal SI of the adjacent arithmetic circuit MA by a programmable switch. For example, the terminal SO of the arithmetic circuit MA[1,1] is set to The programmable switches PR[1, 1] and programmable switch PR[1,2] are set, and the arithmetic circuit MA[1, The terminal SO of the arithmetic circuit MA[1,3] is programmed to be in a conductive state with the terminal SI of the arithmetic circuit MA[1,3]. The programmable switch PR[1,2] and the programmable switch PR[1,3] are set. The wiring XL[1] is connected to the programmable switch PR[1,1]. The terminal SI of the calculation circuit MA[1,1] is in a conductive state. In each row of the MAC array MAR, the arithmetic circuits MA are serially connected to each other so that they are in a conducting state. It is assumed that the programmable switch PR is set.

[0148] In addition, the MAC array MAR in this operation method is specifically In the arithmetic circuit MA included in one column, the terminal AO of the arithmetic circuit MA is connected to the adjacent arithmetic circuit The programmable switch PC is set so that it is in a conductive state with the terminal AI of the circuit MA. For example, the terminal AO of the arithmetic circuit MA[1,1] is connected to the terminal AI of the arithmetic circuit MA[2,1]. The programmable switch PC[1,1] and the programmable switch PC[1,1] are connected to each other. The wire YL[1] is set to the programmable switch PC[2,1]. The terminal AO of the arithmetic circuit MA[9,1] is in a conductive state via the switch PC[9,1]. In this way, in this operation method, in each column of the MAC array MAR, the arithmetic circuit MA Assume that the programmable switch PC is set to be in a continuous state in series. .

[0149] FIG. 8 shows the operation of the arithmetic circuit MA from time T1 to time T9 and the time around them. [2,1] has terminals SI, SO, XI, WI, and AI (terminal ST). 1 is a timing chart showing changes in data input to terminals TT and AO. FIG. 8 also shows the potential changes of the wiring CKL, wiring SLT, wiring SEL, and wiring URST. In Figure 8, "high" indicates a high level potential, and "low" indicates a low level potential. represents the potential of the coil.

[0150] In this operation method, it is assumed that a high-level potential is always input to the wiring SLT. Therefore, register RG2 is enabled during this operation method.

[0151] In this operation method, a low level potential is always input to the wiring SEL. Therefore, the selector SLC always keeps the first input terminal and the output terminal in a non-conductive state. The second input terminal and the output terminal are brought into a conductive state.

[0152] The following describes the operations performed by the MAC array MAR using the timing chart in Figure 8. The method will be explained.

[0153] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, before time T1 In this case, the terminals SI of the arithmetic circuits MA[1,1] to MA[9,10] , terminal SO, terminal XT, terminal WT, terminal AI (terminal ST), terminal TT, and terminal AO It is preferable that initialization data is input (not shown in FIG. 8). The data can be, for example, data with a value of "0". The potential of the terminal AO is changed from low level potential to high level potential by resistor RG3. The potential of the terminal AO at this time is set to the potential corresponding to the value of "0", for example. It is preferable to set the following.

[0154] [Step 1: Read filter value] After step 0 and before time T1, the MAC array MA of the arithmetic device 100 In each of the arithmetic circuits MA[1,1] to MA[9,10] of R, the memory unit The filter value is read from the OSM. Specifically, the context signal is sent from the CTX line. and retrieves data from the OSM storage according to the desired context, i.e., filter values. Here, as an example, the t-th column (where t is 1 or more and 10 or less) is read. The integers of the arithmetic circuits MA[1,t] to MA[9,t] located at Each storage unit OSM contains a filter fil t The filter value of the filter fi is read out. l t For example, let us consider a 3-row, 3-column matrix shown in FIG. 9A, and the filter fil t is the composition of the matrix Minutes as fil t [1,1] to fil t Let us have [3,3]. For example, Then, the memory section OSM of the arithmetic circuit MA[1,t] is fil t Read [1,1] and calculate The memory part OSM of the path MA[2,t] is fil t [1,2] is read and the calculation circuit MA[3, t]'s memory part OSM is fil t [1,3] is read and the memory area of ​​the arithmetic circuit MA[4,t] OSM is fil t [2,1] is read, and the memory unit OSM of the arithmetic circuit MA[5,t] is fi l t [2,2] is read, and the memory unit OSM of the arithmetic circuit MA[6,t] is fil t [2,3 ] is read out, and the storage unit OSM of the arithmetic circuit MA[7,t] is t Read [3,1] , the storage unit OSM of the arithmetic circuit MA[8,t] is fil t [3,2] is read and the calculation circuit M The storage part OSM of A[9,t] is fil t Let's read [3,3].

[0155] Therefore, the arithmetic circuit MA of the MAC array MAR has the first to second columns as shown in FIG. 9B. In each of the 0th columns, filters fil1 to fil 10 is read out.

[0156] In each of the arithmetic circuits MA[1,1] to MA[9,10], a memory unit O The filter value read from SM is input to a terminal WI of the multiplier MP.

[0157] [Step 2: Input image data] Next, the operation of inputting image data IPD to the MAC array MAR will be described.

[0158] The image data IPD here has, for example, m rows and n columns (here, as shown in FIG. 10A). The m and n are integers of 1 or more. It is assumed to be composed of pix[m,n].

[0159] In addition, the image data IPD is read from the memory unit MEMD of the arithmetic device 100, for example. will be done.

[0160] The arithmetic circuits MA of the MAC array MAR are arranged in a matrix of 9 rows and 10 columns. Therefore, the MAC array MAR has registers RG[1,p] to RG[9 , p] are electrically connected. where s is an integer between 1 and 9.) [s, p] are electrically connected. In other words, the pixel data read out from the memory unit MEMD When data pix is ​​input to the arithmetic circuit MA[s,1] of the MAC array MAR, This is done via registers RG[s,1] to RG[s,p].

[0161] The registers RG[s,1] to RG[s,p] receive a clock signal via the wiring CKL. For example, every time a potential change from a low level potential to a high level potential is input, The multiple pixel data pix read from MEMD are transmitted sequentially.

[0162] FIG. 10B shows the state of registers RG[1, p] to RG[1, p] between time T1 and time T9. The images stored in the registers RG[9, p] and input to the MAC array MAR are FIG. 1 is a block diagram showing raw data pix.

[0163] For example, in FIG. 10B, at time T1, the potential of the wiring CKL changes from a low level to a high level. A potential change to the potential occurs, and the potentials of the registers RG[1,p] to RG[3,p] are The pixel data pix[1,1] is stored in the arithmetic circuit The signals are input to the terminals SI of the arithmetic circuits MA[1,1] to MA[3,1]. Also, for example, in FIG. 10B, at time T2, the line CKL is at a low level. A potential change from low to high level occurs, and registers RG[1,p] to RG The pixel data pix[1,2] is stored in each of [3,p], and the pixel data pix[ 1,2] are connected to the terminals SI of the arithmetic circuits MA[1,1] to MA[3,1]. Also, for example, in FIG. 10B, at time T3, A potential change from low level to high level occurs on the line CKL, and the register RG[1,p ] to register RG[3,p], pixel data pix[1,3] is stored, The pixel data pix[1,3] is at the end of the arithmetic circuit MA[1,1] to the arithmetic circuit MA[1,3]. Indicates that it has been entered into a child SI.

[0164] Also, for example, in FIG. 10B, at time T4, the potential of the wiring CKL changes from a low level to a high level. A potential change to the bell potential occurs, and the registers RG[1,p] to RG[3,p] Pixel data pix[1,4] is stored in each, and pixel data pix[1,4] is The inputs to the terminals SI of the arithmetic circuits MA[1,1] to MA[3,1] are Pixel data pix[2, 1] is stored, and pixel data pix[2,1] is stored in the arithmetic circuit MA[4,1] through the arithmetic circuit This indicates that the signal is input to terminal SI of MA[6,1].

[0165] Also, for example, in FIG. 10B, at time T7, the potential of the wiring CKL changes from a low level to a high level. A potential change to the bell potential occurs, and the registers RG[1,p] to RG[3,p] Pixel data pix[1,7] is stored in each, and pixel data pix[1,7] is The signal is input to the terminal SI of each of the arithmetic circuits MA[1,1] to MA[3,1]. Pixel data pix[2,4] is stored in registers RG[4,p] to RG[6,p] The pixel data pix[2,4] is input to the arithmetic circuits MA[4,1] to MA[6, 1] are input to the terminal SI, and pixel data pix[3 ,1] is stored, and the pixel data pix[3,1] is input to the terminal SI of the arithmetic circuit MA[7,1]. This indicates that the data has been entered in

[0166] As described above, the arithmetic circuits MA[1,1] to MA[3,1] are connected to the wiring CKL. Each time a potential change occurs from a low level to a high level as a clock signal, pixel data is Pixel data pix[1,1] to pix[1,n] are input sequentially. The arithmetic circuits MA[4,1] to MA[6,1] include the arithmetic circuits MA[1,1] to MA[6,1]. After data is input to MA[3,1], a low-level voltage is output as a clock signal on the CKL line. After three potential changes from low to high level, pixel data pix[2,1] to The raw data pix[2,n] is input sequentially. The path MA[9,1] is connected to the arithmetic circuits MA[4,1] to MA[6,1]. After input, the voltage changes from low level potential to high level potential as a clock signal on the wiring CKL. After three position changes, pixel data pix[3,1] to pixel data pix[3,n] are input sequentially.

[0167] The pixel data pix[1 , n] is input, for example, pixel data pix[4, 1] to pixel data pix[ Similarly, the calculation circuits MA[4,1] to M After pixel data pix[2,n] is input to A[6,1], for example, pixel data p Pixel data ix[5,1] to pix[5,n] are input sequentially, and the calculation circuit MA[7,1] After pixel data pix[3,n] is input to the arithmetic circuit MA[9,1], for example, Alternatively, pixel data pix[6,1] to pixel data pix[6,n] may be input in sequence. In this way, pixel data pix for one row is input to the arithmetic circuits MA[1,1] to MA[9]. After inputting the pixel data in [1], the next row of pixel data pix can be input to continue the calculation process. It can be done.

[0168] As will be described in detail later, in FIG. 10B, pixel data pix (for example, For example, at time T1, the values ​​stored in registers RG[2,p] and RG[3,p] are , the pixels input to the arithmetic circuit MA[2,1] and the arithmetic circuit MA[3,1] pix[1,1], etc.) is data that is not used in CNN calculations. When performing calculations with Ray MAR, only the data of the pixels enclosed by the solid lines is used in the MAC array M However, when actually configuring a calculation device, the solid line Rather than inputting only the data of the pixels surrounded by the dotted line to the MAC array MAR, The pixel pix is ​​sent as dummy data along with the pixel pix surrounded by the black line. In some cases, it may be easier to construct a computing device using a 3D model.

[0169] The pixel data pix is ​​input to the MAC array MAR using the filter fil 1 to filter fil 10 This can only be applied when the filter fi l1 to filter fil 10 If is a matrix other than 3 rows and 3 columns, the above MAC array It is necessary to change the way pixel data pix is ​​input to the MAR. For example, the MAC array The filter read into the calculation circuit MA of MAR is a row, b column (a is an integer greater than or equal to 1, and b is an integer equal to or greater than 1), the MA inputs pixel data pix from the register RG. The C array MAR should have a × b rows (i.e., the rows of the arithmetic circuit MA of the MAC array MAR). (The number of pixels is a × b.) The input of pixel data pix to the MAC array MAR is , a clock signal difference of a is added and the process is divided into a rows. When the filter read into the calculation circuit MA of the ray MAR has 2 rows and 3 columns, The pixel data and timing input to the MAC array MAR from the CLK1 / CLK2 / CLK3 / CLK4 / CLK5 / CLK6 / CLK7 / CLK8 / CLK9 / CLK1 / CLK1 / CLK2 / CLK1 / CLK2 / CLK3 / CLK4 / CLK5 / CLK6 / CLK1 / CLK1 / CLK2 / CLK1 / CLK1 / CLK2 / CLK1 / CLK1 / CLK2 / CLK3 / CLK1 / CLK1 / CLK2 / CLK1 ... That's fine.

[0170] Next, referring to FIG. 3, pixel data pix is ​​input to the terminal SI of the arithmetic circuit MA. The pixel data pix input to the terminal SI of the arithmetic circuit MA is The register RG1 is connected to the terminal IT1 of the register RG1. For example, when a signal changes from a low level potential to a high level potential, the signal input to terminal IT1 is The input pixel data pix is ​​held and output from the terminal OT1.

[0171] The register RG1 is electrically connected to the wiring CKL, so the MAC array The pixel data pix is ​​output to the terminal OT1 in synchronization with the external register RG of the MAR. The pixel data pix output from the terminal OT1 is input to the terminal of the arithmetic circuit MA. The terminal SO of the arithmetic circuit MA is connected to the terminal SI of the adjacent arithmetic circuit MA. Therefore, the arithmetic circuit M included in one row of the MAC array MAR is in a conductive state. A is a resistor connected in series, with terminal SI as the input terminal and terminal SO as the output terminal. Therefore, the number of operations included in one row of the MAC array MAR can be regarded as The register MA operates in response to a clock signal in the same manner as the register RG outside the MAC array MAR. For example, the pixel data pix can be transmitted sequentially from register RG[s,1] to register RG[s,2]. The pixel data pix sequentially transmitted to the register RG[s,p] is then sent to the MAC array MA R's arithmetic circuits MA[s,1] to MA[s,v] (in this example, v=10) ) are sent sequentially.

[0172] In this operation method, a high level potential is always applied to the terminal CT2 of the register RG2. In other words, a high level potential is always applied to the wiring SLT. It shall be.

[0173] The pixel data pix output from the terminal OT1 of the register RG1 is The resistor RG2 is electrically connected to the wiring CKL. , synchronized with the register RG and register RG1 outside the MAC array MAR described above, The pixel data pix can be output to the terminal OT2. For this reason, the register RG2 is The pixel data pix input to the terminal IT2 is held and the pixel data pix is ​​output to the terminal OT2. The pixel data pix output to terminal OT2 is input to terminal XI of multiplier MP. can be.

[0174] In other words, the pixel data pix input to the terminal IT1 of the register RG1 is output to the line CKL. The input clock signal changes potential from low level to high level twice. When this occurs, the signal is output to the terminal OT2 of the register RG2.

[0175] [Step 3: Multiply and accumulate the filter value and pixel data pix] In step 2, pixel data pix is ​​input to the arithmetic circuit MA. In MA, pixel data pix and the filter read from the memory unit OSM of the arithmetic circuit MA are The value is multiplied by .

[0176] [Time T1] FIG. 12A shows, as an example, the state of a part of the arithmetic circuit M of the MAC array MAR at time T1. 12A is a block diagram illustrating data output to a terminal AO of a Registers RG[1,p] to RG[5,p], arithmetic circuits MA[1,1] to MA[5,p], Only the path MA[5,1] is shown in the figure.

[0177] At time T1, the following is read from each of the registers RG[1,p] to RG[9,p]: Pixel data is input to the MAC array MAR. At time T1, the arithmetic circuit MA Pixel data pix[1,1] is input to the calculation circuits MA[1,1] to MA[3,1], and calculation is performed. No pixel data is input to the circuit MA[4,1] through the arithmetic circuit MA[9,1]. Therefore, in FIG. 12A, the arithmetic circuits MA[4,1] to MA[9,1] have the pixel BLK is shown, which indicates that no data has been input.

[0178] In addition, the registers RG of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,1] is input to terminal IT1.

[0179] At time T1, all the arithmetic circuits MA of the MAC array MAR perform the arithmetic operation. Therefore, in FIG. 12A, the arithmetic circuits MA[1,1] to MA[9] are not used. , 1], the terminals AO are marked with BLK, which indicates that there is no output of the calculation result. There are.

[0180] [Time T2] FIG. 12B shows, as an example, the state of a part of the arithmetic circuit M of the MAC array MAR at time T2. 1 is a block diagram illustrating the data output to terminals AO and SI of A. In 2B, registers RG[1,p] to RG[5,p], an arithmetic circuit MA[1,1 ] to arithmetic circuit MA[5,1], arithmetic circuit MA[1,3] to arithmetic circuit MA[5,3] Only excerpts are shown in the figures.

[0181] At time T2, pixel data p is read from registers RG[1,p] to RG[3,p]. ix[1,2] is output, and the image is output from the arithmetic circuits MA[4,1] to MA[9,1]. As mentioned above, the arithmetic circuit MA of the MAC array MAR is not input. Since the arithmetic circuits MA[1,1] and MA[2,2] also function as registers, at time T2, the arithmetic circuits MA[1,1] and MA[2,2] Pixel data pix[1,1] is output from each terminal SO of the path MA[3,1]. Furthermore, the terminals SO of the arithmetic circuits MA[4,1] to MA[9,1] are , pixel data pix is ​​not output.

[0182] At this time, the registers of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,1] is input to terminal IT2 of RG2. The pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,1] to MA[3,1]. The data pix[1,2] is input.

[0183] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] Pixel data pix[1,1] is input to terminal IT1.

[0184] At time T2, the calculation results are performed in all the calculation circuits MA of the MAC array MAR. Therefore, in FIG. 12B, the arithmetic circuit MA[1,1] is not included, as in FIG. 12A. This indicates that there is no output of the calculation result at each terminal AO of the calculation circuit MA[9,1]. The BLK shown is

[0185] [Time T3] Next, consider the operation of the MAC array MAR at time T3. At time T3, the terminals AO and MA of the arithmetic circuit MA of the MAC array MAR are 13 is a block diagram illustrating data output to SI. [1,p] to register RG[5,p], arithmetic circuits MA[1,1] to MA[5 ,1], arithmetic circuits MA[1,2] to MA[5,2], arithmetic circuits MA[1,3] Only the arithmetic circuit MA[5,3] is shown in the figure.

[0186] At time T3, the registers RG[1,p] to RG[3,p] are read from the arithmetic circuit MA Pixel data pix[1,3] is input to the calculation circuits MA[1,1] to MA[3,1], and calculation is performed. No pixel data is input to the circuit MA[4,1] through the arithmetic circuit MA[9,1]. As mentioned above, the arithmetic circuit MA of the MAC array MAR also functions as a register. Therefore, at time T3, the terminals of the arithmetic circuits MA[1,1] to MA[3,1] The pixel data pix[1,2] is output from the child SO, and the calculation circuit MA[1,2] and the calculation circuit Pixel data pix[1,1] is output from each terminal SO of the path MA[3,2]. In addition, the arithmetic circuits MA[4,1] to MA[9,1] and the arithmetic circuits MA[4,2 ] to the arithmetic circuit MA[9,2], pixel data pix is ​​output from each terminal SO. I can't.

[0187] At this time, the registers of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,2] is input to terminal IT2 of RG2. The pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,1] to MA[3,1]. The data pix[1,3] is input.

[0188] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] Pixel data pix[1,1] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,2] to MA[3,2]. pix[1,2] is input.

[0189] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] Pixel data pix[1,1] is input to terminal IT1.

[0190] In addition, the registers RG of the arithmetic circuits MA[1,1] to MA[3,1] The pixel data pix[1,1] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 1] is input to terminal XI of multiplier MP.

[0191] Here, the calculations performed by the calculation circuits MA[1,1] to MA[9,1] are as follows: explain.

[0192] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP receives the filter value fi l1[1,1] is input, and pixel pix[1,1] is input to terminal XI of multiplier MP. As a result, the terminal ZO of the multiplier MP is set to fil1[1,1]×pix[1,1 ] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is , the value of "0" is input. This causes the terminal TT of the adder AD to be filled with fil 1[1,1]×pix[1,1] is output. In this example, F1 [1,1] [ 1] = fil1[1,1] × pix[1,1]. F1 [1,1] [1] is the number of operations The signal is input to the terminal IT3 of the register RG3 of the path MA[1,1].

[0193] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2] is input to the multiplier, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,2]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil1[1,2]×pix[1,1] is output to the terminal TT. However, this calculation result Since it is not used in the CNN calculation, it will be referred to as FD from now on. This FD is 2,1] is input to terminal IT3 of register RG3.

[0194] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives the filter value fil1[1,3] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,3]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil1[1,3]×pix[1,1] is output to the terminal TT. However, this calculation result As with the previous calculation circuit MA[2,1], this is not used in CNN calculations, so it will be referred to as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1]. can be.

[0195] In the arithmetic circuits MA[4,1] to MA[9,1], the multiplier MP Since no pixel data pix is ​​input to the terminal XI, no operation is performed.

[0196] [Time T4] Next, consider the operation of the MAC array MAR at time T4. At time T4, the terminals AO and MA of the arithmetic circuit MA of the MAC array MAR are 14 is a block diagram illustrating the data output to the SI. [1,p] to register RG[5,p], arithmetic circuits MA[1,1] to MA[5 ,1], arithmetic circuits MA[1,2] to MA[5,2], arithmetic circuits MA[1,3] Only the arithmetic circuit MA[5,3] is shown in the figure.

[0197] In this operation method, each of the arithmetic circuits MA[1,1] to MA[9,10] It is assumed that a high level potential is always applied to the terminal CT3 of the register RG3. In other words, it is assumed that a high level potential is always applied to the wiring URST.

[0198] In the arithmetic circuit MA[1,1], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, the terminal OT3 to F1 [1,1] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1]. In addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal MA[2,1] Since there is a connection between the AI ​​and F1 [1,1] [1] is the arithmetic circuit MA[2, 1] is input to terminal AI.

[0199] Similarly, in each of the arithmetic circuits MA[2,1] and MA[3,1], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[2,1] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[2,1] via the terminal AO of the arithmetic circuit MA[3,1]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[2,1] is F D is input to the terminal AI of the circuit MA[3,1]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[3,1]. Since the terminal AI of A[4,1] is in a conductive state, the calculation is performed by the arithmetic circuit MA[3,1]. The result of the calculation FD is input to the terminal AI of the circuit MA[4,1].

[0200] At time T4, the registers RG[1,p] to RG[3,p] are read from the arithmetic circuit MA Pixel data pix[1,4] is input to the registers [1,1] to MA[3,1]. Registers RG[4,p] to RG[6,p] are connected to the arithmetic circuits MA[4,1] to MA[6,p]. Pixel data pix[2,1] is input to the circuit MA[6,1], and the calculation circuit MA[7,1] No pixel data is input to the arithmetic circuit MA[9,1]. Since the arithmetic circuit MA of the AC array MAR also functions as a register, at time T4, Pixel data is output from the terminals SO of the arithmetic circuits MA[1,1] to MA[3,1]. pix[1,3] is output, and the calculation circuits MA[1,2] to MA[3,2] The pixel data pix[1,2] is output from each terminal SO and is input to the arithmetic circuit MA[1,3]. The pixel data pix[1,1] is output from each terminal SO of the arithmetic circuit MA[3,3]. In addition, the arithmetic circuits MA[4,1] to MA[9,1], the arithmetic circuits MA[ 4,2] to arithmetic circuit MA[9,2], and arithmetic circuit MA[4,3] to arithmetic circuit MA[ 9, 3], pixel data pix is ​​not output from the terminals SO.

[0201] At this time, the registers of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,3] is input to terminal IT2 of RG2. The pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,1] to MA[3,1]. The data pix[1,4] is input.

[0202] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] Pixel data pix[1,2] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,2] to MA[3,2]. pix[1,3] is input.

[0203] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] Pixel data pix[1,1] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,3] to MA[3,3]. pix[1,2] is input.

[0204] In addition, the registers RG of the arithmetic circuits MA[4,1] to MA[6,1] Pixel data pix[2,1] is input to terminal IT1 of 1.

[0205] In addition, the registers RG of the arithmetic circuits MA[1,1] to MA[3,1] The pixel data pix[1,2] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 2] is input to terminal XI of multiplier MP.

[0206] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] The pixel data pix[1,1] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 1] is input to terminal XI of multiplier MP.

[0207] Here, the arithmetic circuits MA[1,1] to MA[9,1] and the arithmetic circuit MA[1 The calculations performed by the calculation circuits MA[9,2] to MA[9,2] will be described.

[0208] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP receives the filter value fi l1[1,1] is input, and pixel pix[1,2] is input to terminal XI of multiplier MP. As a result, the terminal ZO of the multiplier MP is connected to fil1[1,1]×pix[1,2 ] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is , the value of "0" is input. This causes the terminal TT of the adder AD to be filled with fil 1[1,1]×pix[1,2] is output. In this example, F1 [1,2] [ 1] = fil1[1,1] × pix[1,2]. F1 [1,2] [1] is the number of operations The signal is input to the terminal IT3 of the register RG3 of the path MA[1,1].

[0209] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,2]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F1 [1,1] The value [1] is input. This causes the terminal T of the adder AD to T to F1 [1,1] [1]+fil1[1,1]×pix[1,2] is output. In this example, F1 [1,1] [2]=F1 [1,1] [1]+fil1[1,1]× pix[1,2]. F1 [1,1] [2] is the register of the arithmetic circuit MA[2,1] Input to terminal IT3 of RG3.

[0210] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives the filter value fil1[1,3] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,3]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T is assumed to have input FD output from terminal AO of arithmetic circuit MA[2,1]. However, since the results of this calculation are not used in CNN calculations, they will be referred to as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0211] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP receives the filter value fil2[1,1] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,1]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD The value "0" is input to T. This causes the terminal TT of the adder AD to fil2[1,1]×pix[1,1] is output. In this example, F2 [1, 1] [1] = fil2[1,1] × pix[1,1]. F2 [1,1] [1] is, The signal is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,2].

[0212] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives the filter value fil2[1,2] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,2]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil2[1,2]×pix[1,1] is output to the terminal TT. However, this calculation result Since it is not used in the CNN calculation, it will be referred to as FD from now on. This FD is 2,2] is input to terminal IT3 of register RG3.

[0213] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP receives the filter value fil2[1,3] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,3]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil2[1,3]×pix[1,1] is output to the terminal TT. However, this calculation result As with the previous arithmetic circuit MA[2,2], this is not used in CNN calculations, so we will refer to it as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2]. can be.

[0214] Note that the arithmetic circuits MA[4,1] to MA[9,1] and MA[4,2] In the arithmetic circuit MA[9,2], pixel data pix is ​​input to the terminal XI of the multiplier MP. Since no input has been made, no calculation is performed.

[0215] [Time T5] Next, consider the operation of the MAC array MAR at time T5. At time T5, the terminals AO and MA of the arithmetic circuit MA of the MAC array MAR are 15 is a block diagram illustrating data output to SI. [1,p] to register RG[5,p], arithmetic circuits MA[1,1] to MA[5 ,1], arithmetic circuits MA[1,2] to MA[5,2], arithmetic circuits MA[1,3] Only the arithmetic circuit MA[5,3] is shown in the figure.

[0216] In the arithmetic circuit MA[1,1], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, the terminal OT3 to F1 [1,2] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1]. In addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal MA[2,1] Since there is a connection between the AI ​​and F1 [1,2] [1] is the arithmetic circuit MA[2, Similarly, in the arithmetic circuit MA[2,1], the register RG 3 is the terminal when a potential change occurs from a low level potential to a high level potential as a clock signal. Child OT3 to F1 [1,1] [2] is output. The terminal OT3 of the register RG3 is the arithmetic circuit It is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and also to the terminal Since there is a continuity between AO and the terminal AI of the arithmetic circuit MA[3,1], F1 [1 ,1] [2] is input to the terminal AI of the arithmetic circuit MA[3,1].

[0217] Similarly, in each of the arithmetic circuits MA[3,1] and MA[4,1], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[3,1] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[3,1] via the terminal AO of the arithmetic circuit MA[4,1]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[3,1] is F D is input to the terminal AI of the circuit MA[4,1]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[4,1]. Since the terminal AI of A[5,1] is in a conductive state, the calculation is performed by the arithmetic circuit MA[4,1]. The result of the calculation FD is input to a terminal AI of the circuit MA[5,1].

[0218] In the arithmetic circuit MA[1,2], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, the terminals OT3 to F2 [1,1] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2]. In addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal MA[2,2] Since there is a connection between AI and F2 [1,1] [1] is the arithmetic circuit MA[2, 2] is input to terminal AI.

[0219] Similarly, in each of the arithmetic circuits MA[2,2] and MA[3,2], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[2,2] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[2,2] via the terminal AO of the arithmetic circuit MA[3,2]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[2,2] is F D is input to the terminal AI of the circuit MA[3,2]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[3,2]. Since the terminal AI of A[4,2] is in a conductive state, the calculation is performed by the arithmetic circuit MA[3,2]. The result of the calculation FD is input to the terminal AI of the circuit MA[4,2].

[0220] At time T5, the registers RG[1,p] to RG[3,p] are read from the arithmetic circuit MA Pixel data pix[1,5] is input to the registers [1,1] to MA[3,1]. Registers RG[3,p] to RG[6,p] are connected to the arithmetic circuits MA[4,1] to MA[6,p]. Pixel data pix[2,2] is input to the circuit MA[6,1], and the calculation circuit MA[7,1] No pixel data is input to the arithmetic circuit MA[9,1]. The arithmetic circuit MA of the AC array MAR also functions as a register, so at time T5, Pixel data is output from the terminals SO of the arithmetic circuits MA[1,1] to MA[3,1]. pix[1,4] is output, and the calculation circuits MA[1,2] to MA[3,2] The pixel data pix[1,3] is output from each terminal SO and is input to the arithmetic circuit MA[1,3]. The pixel data pix[1,2] is output from each terminal SO of the arithmetic circuit MA[3,3]. Also, the terminals of the arithmetic circuits MA[4,1] to MA[6,1] are input. Pixel data pix[2,1] is output from SO. Arithmetic circuit MA[9,1], arithmetic circuit MA[4,2] to arithmetic circuit MA[9,2], and The terminals SO of the arithmetic circuits MA[4,3] to MA[9,3] are connected to the pixel data. No data pix is ​​output.

[0221] At this time, the registers of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,4] is input to terminal IT2 of RG2. The pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,1] to MA[3,1]. The data pix[1,5] is input.

[0222] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] Pixel data pix[1,3] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,2] to MA[3,2]. pix[1,4] is input.

[0223] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] Pixel data pix[1,2] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,3] to MA[3,3]. pix[1,3] is input.

[0224] In addition, the registers RG of the arithmetic circuits MA[4,1] to MA[6,1] Pixel data pix[2,1] is input to terminal IT2 of arithmetic circuit MA[4, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[6,1] to MA[6,1]. pix[2,2] is input.

[0225] In addition, the registers RG of the arithmetic circuits MA[4,2] to MA[6,2] Pixel data pix[2,1] is input to terminal IT1 of 1.

[0226] In addition, the registers RG of the arithmetic circuits MA[1,1] to MA[3,1] The pixel data pix[1,3] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 3] is input to terminal XI of multiplier MP.

[0227] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] The pixel data pix[1,2] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 2] is input to terminal XI of multiplier MP.

[0228] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] The pixel data pix[1,1] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 1] is input to terminal XI of multiplier MP.

[0229] Here, the arithmetic circuits MA[1,1] to MA[9,1] and the arithmetic circuits MA[1,2 ] to arithmetic circuit MA[9,2], and arithmetic circuit MA[1,3] to arithmetic circuit MA[9,3 ] will be explained.

[0230] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP receives the filter value fi l1[1,1] is input, and pixel pix[1,3] is input to terminal XI of multiplier MP. As a result, the terminal ZO of the multiplier MP is connected to fil1[1,1]×pix[1,3 ] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is , the value of "0" is input. This causes the terminal TT of the adder AD to be filled with fil 1[1,1]×pix[1,3] is output. In this example, F1 [1,3] [ 1] = fil1[1,1] × pix[1,3]. F1 [1,3] [1] is the number of operations The signal is input to the terminal IT3 of the register RG3 of the path MA[1,1].

[0231] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2] is input to the multiplier, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,2]×pix[ 1,3] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F1 [1,2] The value [1] is input. This causes the terminal T of the adder AD to T to F1 [1,2] [1]+fil1[1,2]×pix[1,3] is output. In this example, F1 [1,2] [2]=F1 [1,2] [1]+fil1[1,2]× pix[1,3]. F1 [1,2] [2] is the register of the arithmetic circuit MA[2,1] Input to terminal IT3 of RG3.

[0232] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives the filter value fil1[1,3] is input to the multiplier MP, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,3]×pix[ 1,3] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F1 [1,1] The value of [2] is input. This causes the terminal T of the adder AD to T to F1 [1,1] [2]+fil1[1,3]×pix[1,3] is output. In this example, F1 [1,1] [3]=F1 [1,1] [2]+fil1[1,3]× pix[1,3]. F1 [1,1] [3] is the register of the arithmetic circuit MA[3,1] Input to terminal IT3 of RG3.

[0233] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP receives the filter value fil2[1,1] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,1]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD The value "0" is input to T. This causes the terminal TT of the adder AD to fil2[1,1]×pix[1,2] is output. In this example, F2 [1, 2] [1] = fil2[1,1] × pix[1,2]. F2 [1,2] [1] is, The signal is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,2].

[0234] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives the filter value fil2[1,2] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,2]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F2 [1,1] The value [1] is input. This causes the terminal T of the adder AD to T to F2 [1,1] [1] + fil2[1,2] × pix[1,2] is output. In this example, F2 [1,1] [2]=F2 [1,1] [1]+fil2[1,2]× pix[1,2]. F2 [1,1] [2] is the register of the arithmetic circuit MA[2,2] Input to terminal IT3 of RG3.

[0235] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP receives the filter value fil2[1,3] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,3]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T is assumed to have input FD output from terminal AO of arithmetic circuit MA[2,2]. However, since the results of this calculation are not used in CNN calculations, they will be referred to as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2].

[0236] In the arithmetic circuit MA[1,3], the terminal WI of the multiplier MP receives the filter value fil3[1,1] is input to the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil3[1,1]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD The value "0" is input to T. This causes the terminal TT of the adder AD to fil3[1,1]×pix[1,1] is output. In this example, F3 [1, 1] [1] = fil3[1,1] × pix[1,1]. F3 [1,1] [1] is, The signal is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,3].

[0237] In the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP receives the filter value fil3[1,2] is input to the multiplier, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil3[1,2]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil3[1,2]×pix[1,1] is output to the terminal TT. However, this calculation result Since it is not used in the CNN calculation, it will be referred to as FD from now on. This FD is 2, 3] is input to terminal IT3 of register RG3.

[0238] In the arithmetic circuit MA[3,3], the terminal WI of the multiplier MP receives the filter value fil3[1,3] is input to the multiplier, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil3[1,3]×pix[ 1,1] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD For example, the value of "0" is input to T. This causes the adder AD fil3[1,3]×pix[1,1] is output to the terminal TT. However, this calculation result As with the previous calculation circuit MA[2,3], is not used in CNN calculations, so from now on, it will be referred to as FD. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,3]. can be.

[0239] Note that the arithmetic circuits MA[4,1] to MA[9,1] and MA[4,2] to arithmetic circuit MA[9,2], and arithmetic circuit MA[4,3] to arithmetic circuit MA[9,3] In this case, pixel data pix is ​​not input to the terminal XI of the multiplier MP, so the operation is not executed.

[0240] [Time T6] Next, consider the operation of the MAC array MAR at time T6. At time T6, the terminals AO and MA of the arithmetic circuit MA of the MAC array MAR are 16 is a block diagram illustrating data output to SI. [1,p] to register RG[5,p], arithmetic circuits MA[1,1] to MA[5 ,1], arithmetic circuits MA[1,2] to MA[5,2], arithmetic circuits MA[1,3] Only the arithmetic circuit MA[5,3] is shown in the figure.

[0241] In the arithmetic circuit MA[1,1], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, the terminal OT3 to F1 [1,3] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1]. In addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal MA[2,1] Since there is a connection between the AI ​​and F1 [1,3] [1] is the arithmetic circuit MA[2, Similarly, in the arithmetic circuit MA[2,1], the register RG 3 is the terminal when a potential change occurs from a low level potential to a high level potential as a clock signal. Child OT3 to F1 [1,2] [2] is output. The terminal OT3 of the register RG3 is the arithmetic circuit It is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and also to the terminal Since there is a continuity between AO and the terminal AI of the arithmetic circuit MA[3,1], F1 [1 ,2] [2] is input to the terminal AI of the arithmetic circuit MA[3,1]. In [3,1], the register RG3 changes from a low level potential to a high level potential as a clock signal. When a potential change occurs in the potential, the voltage from terminal OT3 to F1 [1,1] Output [3]. The terminal OT3 of the master RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[3,1]. Therefore, there is a conduction between the terminal AO of the arithmetic circuit MA[3,1] and the terminal AI of the arithmetic circuit MA[4,1]. Since it is in normal condition, F1 [1,1] [3] is the terminal AI of the arithmetic circuit MA[3,1] is entered into

[0242] Similarly, in each of the arithmetic circuits MA[4,1] and MA[5,1], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[4,1] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[4,1] via the terminal AO of the arithmetic circuit MA[5,1]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[4,1] is F D is input to the terminal AI of the circuit MA[5,1]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[5,1]. Since the terminal AI of A[6,1] is in a conductive state, the calculation is performed by the arithmetic circuit MA[5,1]. The result of the calculation FD is input to a terminal AI of the circuit MA[6,1].

[0243] In the arithmetic circuit MA[1,2], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, the terminals OT3 to F2 [1,2] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2]. In addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal MA[2,2] Since there is a connection between AI and F2 [1,2] [1] is the arithmetic circuit MA[2, 2]. Similarly, in the arithmetic circuit MA[2,2], the register RG 3 is the terminal when a potential change occurs from a low level potential to a high level potential as a clock signal. Child OT3 to F2 [1,1] [2] is output. The terminal OT3 of the register RG3 is the arithmetic circuit It is electrically connected to the terminal AO of the arithmetic circuit MA[2,2], and also to the terminal Since there is a continuity between AO and the terminal AI of the arithmetic circuit MA[3,2], F2 [1 ,1] [2] is input to the terminal AI of the arithmetic circuit MA[3,2].

[0244] Similarly, in each of the arithmetic circuits MA[3,2] and MA[4,2], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[3,2] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[3,2] via the terminal AO of the arithmetic circuit MA[4,2]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[3,2] is F D is input to the terminal AI of the circuit MA[4,2]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[4,2]. Since the terminal AI of A[5,2] is in a conductive state, the calculation is performed by the arithmetic circuit MA[4,2]. The result of the calculation FD is input to a terminal AI of the circuit MA[5,2].

[0245] In the arithmetic circuit MA[1,3], the register RG3 receives a low-level voltage as a clock signal. When a potential change occurs from low to high level, terminals OT3 to F3 [1,1] [1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,3]. In addition, the terminal AO of the arithmetic circuit MA[1,3] and the terminal MA[2,3] Since there is a connection between the AI ​​and F3 [1,1] [1] is the arithmetic circuit MA[2, 3] is input to terminal AI.

[0246] Similarly, in each of the arithmetic circuits MA[2,3] and MA[3,3], Register RG3 receives a potential change from low level potential to high level potential as a clock signal. When the register RG3 of the arithmetic circuit MA[2,3] is set to 0, the FD is output from the terminal OT3. The terminal OT3 is connected to the terminal AO of the arithmetic circuit MA[2,3] via the terminal AO of the arithmetic circuit MA[3,3]. Since the terminal AI is in a conductive state, the result of the operation performed in the arithmetic circuit MA[2,3] is F D is input to the terminal AI of the circuit MA[3,3]. The terminal OT3 of the register RG3 is connected to the terminal AO of the arithmetic circuit MA[3,3]. Since the terminal AI of A[4,3] is in a conductive state, the calculation is performed by the arithmetic circuit MA[3,3]. The result of the calculation FD is input to a terminal AI of the circuit MA[4,3].

[0247] At time T6, the registers RG[1,p] to RG[3,p] are read from the arithmetic circuit MA Pixel data pix[1,6] is input to the registers [1,1] to MA[3,1]. Registers RG[4,p] to RG[6,p] are connected to the arithmetic circuits MA[4,1] to MA[6,p]. Pixel data pix[2,3] is input to the circuit MA[6,1], and the calculation circuit MA[7,1] No pixel data is input to the arithmetic circuit MA[9,1]. Since the arithmetic circuit MA of the AC array MAR also functions as a register, at time T6, Pixel data is output from the terminals SO of the arithmetic circuits MA[1,1] to MA[3,1]. pix[1,5] is output, and the calculation circuits MA[1,2] to MA[3,2] The pixel data pix[1,4] is output from each terminal SO and is input to the arithmetic circuit MA[1,3]. The pixel data pix[1,3] is output from each terminal SO of the arithmetic circuit MA[3,3]. Also, the terminals of the arithmetic circuits MA[4,1] to MA[6,1] are input. Pixel data pix[2,2] is output from SO, and the arithmetic circuits MA[4,2] to MA[4,2] are Pixel data pix[2,1] is output from each terminal SO of MA[6,2]. In addition, the arithmetic circuits MA[7,1] to MA[9,1], the arithmetic circuits MA[4,2] to The arithmetic circuit MA[9,2] and the arithmetic circuits MA[4,3] to MA[9,3] No pixel data pix is ​​output from each terminal SO.

[0248] At this time, the registers of the arithmetic circuits MA[1,1] to MA[3,1] Pixel data pix[1,5] is input to terminal IT2 of RG2. The pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,1] to MA[3,1]. The data pix[1,6] is input.

[0249] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] Pixel data pix[1,4] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,2] to MA[3,2]. pix[1,5] is input.

[0250] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] Pixel data pix[1,3] is input to terminal IT2 of arithmetic circuit MA[1, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[3,3] to MA[3,3]. pix[1,4] is input.

[0251] In addition, the registers RG of the arithmetic circuits MA[4,1] to MA[6,1] Pixel data pix[2,2] is input to terminal IT2 of arithmetic circuit MA[4, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[6,1] to MA[6,1]. pix[2,3] is input.

[0252] In addition, the registers RG of the arithmetic circuits MA[4,2] to MA[6,2] Pixel data pix[2,1] is input to terminal IT2 of arithmetic circuit MA[4, Pixel data is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[6,2] to MA[6,2]. pix[2,2] is input.

[0253] In addition, the registers RG of the arithmetic circuits MA[4,3] to MA[6,3] Pixel data pix[2,1] is input to terminal IT1 of 1.

[0254] In addition, the registers RG of the arithmetic circuits MA[1,1] to MA[3,1] The pixel data pix[1,4] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 4] is input to terminal XI of multiplier MP.

[0255] In addition, the registers RG of the arithmetic circuits MA[1,2] to MA[3,2] The pixel data pix[1,3] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 3] is input to terminal XI of multiplier MP.

[0256] In addition, the registers RG of the arithmetic circuits MA[1,3] to MA[3,3] The pixel data pix[1,2] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, and therefore the pixel data pix[1, 2] is input to terminal XI of multiplier MP.

[0257] In addition, the registers RG of the arithmetic circuits MA[4,1] to MA[6,1] The pixel data pix[2,1] is output from the terminal OT2 of register RG2. T2 is electrically connected to the terminal XI of the multiplier MP, so that the pixel data pix[2, 1] is input to terminal XI of multiplier MP.

[0258] Here, the arithmetic circuits MA[1,1] to MA[9,1] and the arithmetic circuits MA[1,2 ] to arithmetic circuit MA[9,2], and arithmetic circuit MA[1,3] to arithmetic circuit MA[9,3 ] will be explained.

[0259] In the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP receives the filter value fi l1[1,1] is input, and pixel pix[1,4] is input to terminal XI of multiplier MP. As a result, the terminal ZO of the multiplier MP is connected to fil1[1,1]×pix[1,4 ] is output and input to the terminal FT of the adder AD. Also, the terminal ST of the adder AD is , the value of "0" is input. This causes the terminal TT of the adder AD to be filled with fil 1[1,1]×pix[1,4] is output. In this example, F1 [1,4] [ 1] = fil1[1,1] × pix[1,4]. F1 [1,4] [1] is the number of operations The signal is input to the terminal IT3 of the register RG3 of the path MA[1,1].

[0260] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2] is input to the multiplier, and pixel pix[1,4] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,2]×pix[ 1,4] is output and input to the terminal FT of the adder AD. T has F1 [1,3] The value [1] is input. This causes the terminal T of the adder AD to T to F1 [1,3] [1]+fil1[1,2]×pix[1,4] is output. In this example, F1 [1,3] [2]=F1 [1,3] [1]+fil1[1,2]× pix[1,4]. F1 [1,3] [2] is the register of the arithmetic circuit MA[2,1] Input to terminal IT3 of RG3.

[0261] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives the filter value fil1[1,3] is input to the multiplier, and pixel pix[1,4] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[1,3]×pix[ 1,4] is output and input to the terminal FT of the adder AD. T has F1 [1,2] The value of [2] is input. This causes the terminal T of the adder AD to T to F1 [1,2] [2]+fil1[1,3]×pix[1,4] is output. In this example, F1 [1,2] [3]=F1 [1,2] [2]+fil1[1,3]× pix[1,4]. F1 [1,2] [3] is the register of the arithmetic circuit MA[3,1] Input to terminal IT3 of RG3.

[0262] In the arithmetic circuit MA[4,1], the terminal WI of the multiplier MP receives the filter value fil1[2,1] is input to the multiplier MP, and pixel pix[2,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[2,1]×pix[ 2,1] is output and input to the terminal FT of the adder AD. T has F1 [1,1]The value of [3] is input. This causes the terminal T of the adder AD to T to F1 [1,1] [3]+fil1[2,1]×pix[2,1] is output. In this example, F1 [1,1] [4]=F1 [1,1] [3]+fil1[2,1]× Let pix[2,1]. F1 [1,1] [4] is the register of the arithmetic circuit MA[4,1] Input to terminal IT3 of RG3.

[0263] In the arithmetic circuit MA[5,1], the terminal WI of the multiplier MP receives the filter value fil1[2,2] is input to the multiplier, and pixel pix[2,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil1[2,2]×pix[ 2,1] is output and input to the terminal FT of the adder AD. T is assumed to have input FD output from terminal AO of arithmetic circuit MA[4,1]. However, since the results of this calculation are not used in CNN calculations, they will be referred to as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[5,1].

[0264] In the arithmetic circuit MA[1,2], the terminal WI of the multiplier MP receives the filter value fil2[1,1] is input to the multiplier, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,1]×pix[ 1,3] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD The value "0" is input to T. This causes the terminal TT of the adder AD to fil2[1,1]×pix[1,3] is output. In this example, F2 [1, 3] [1] = fil2[1,1] × pix[1,3]. F2 [1,3] [1] is, It is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0265] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives the filter value fil2[1,2] is input to the multiplier MP, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,2]×pix[ 1,3] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F2 [1,2] The value [1] is input. This causes the terminal T of the adder AD to T to F2 [1,2] [1] + fil2[1,2] × pix[1,3] is output. In this example, F2 [1,2] [2]=F2 [1,2] [1]+fil2[1,2]× pix[1,3]. F2 [1,2] [2] is the register of the arithmetic circuit MA[2,2] Input to terminal IT3 of RG3.

[0266] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP receives the filter value fil1[1,3] is input to the multiplier MP, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,3]×pix[ 1,3] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F2 [1,1] The value of [2] is input. This causes the terminal T of the adder AD to T to F2 [1,1] [2]+fil2[1,3]×pix[1,3] is output. In this example, F2 [1,1] [3]=F2 [1,1] [2]+fil2[1,3]× pix[1,3]. F2 [1,1] [3] is the register of the arithmetic circuit MA[3,2] Input to terminal IT3 of RG3.

[0267] In the arithmetic circuit MA[1,3], the terminal WI of the multiplier MP receives the filter value fil3[1,1] is input to the multiplier, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil3[1,1]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD The value "0" is input to T. This causes the terminal TT of the adder AD to fil3[1,1]×pix[1,2] is output. In this example, F3 [1, 2] [1] = fil3[1,1] × pix[1,2]. F3 [1,2] [1] is, The signal is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,3].

[0268] In the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP receives the filter value fil3[1,2] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil3[1,2]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T has F3 [1,1] The value [1] is input. This causes the terminal T of the adder AD to F3 on T [1,1] [1] + fil3[1,2] × pix[1,2] is output. In this example, F3 [1,1] [2]=F3 [1,1] [1]+fil3[1,2]× pix[1,2]. F3 [1,1] [2] is the register of the arithmetic circuit MA[2,3] Input to terminal IT3 of RG3.

[0269] In the arithmetic circuit MA[3,3], the terminal WI of the multiplier MP receives the filter value fil3[1,3] is input to the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP is input with fil2[1,3]×pix[ 1,2] is output and input to the terminal FT of the adder AD. Also, the terminal S of the adder AD T is assumed to have input FD output from terminal AO of arithmetic circuit MA[2,3]. However, since the results of this calculation are not used in CNN calculations, they will be referred to as FD from now on. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,3].

[0270] Note that the arithmetic circuits MA[6,1] to MA[9,1] and MA[4,2] to arithmetic circuit MA[9,2], and arithmetic circuit MA[4,3] to arithmetic circuit MA[9,3] In this case, pixel data pix is ​​not input to the terminal XI of the multiplier MP, so the operation is not executed.

[0271] The above-mentioned operation is performed at a certain time (here, for example, at time T 11 If we continue until From the terminal AO of the arithmetic circuit MA[9,1], F1 [1,1] [9] is output. F1 [1 ,1] [9] is the above-mentioned operation, F1 [1,1] [9]=fil1[1,1]×pi x[1,1]+fil1[1,2]×pix[1,2]+fil1[1,3]×pix[ 1,3]+fil1[2,1]×pix[2,1]+fil1[2,2]×pix[2, 2]+fil1[2,3]×pix[2,3]+fil1[3,1]×pix[3,1] +fil1[3,2]×pix[3,2]+fil1[3,3]×pix[3,3] do.

[0272] In other words, F1 [1,1] [9] is the pixel data pix[1,1] of the image data IPD. Pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2 ,3], and the area of ​​pixel data pix[3,1] to pixel data pix[3,3] This is the value obtained by performing convolution using filter fil1.

[0273] Also, at time T 11 Therefore, the clock signal on the wiring CKL changes from low level potential to high level potential. The time when a potential change to the potential occurs once (here, for example, time T 12 (Let us assume that) From the terminal AO of the arithmetic circuit MA[9,1], F1 [1,2] [9] is output. F1 [1 ,2] [9] is the above-mentioned operation, F1 [1,2] [9]=fil1[1,1]×pi x[1,2]+fil1[1,2]×pix[1,3]+fil1[1,3]×pix[ 1,4]+fil1[2,1]×pix[2,2]+fil1[2,2]×pix[2, 3]+fil1[2,3]×pix[2,4]+fil1[3,1]×pix[3,2] +fil1[3,2]×pix[3,3]+fil1[3,3]×pix[3,4] do.

[0274] In other words, F1 [1,2] [9] is the pixel data pix[1,2] of the image data IPD. Up to pixel data pix[1,4], pixel data pix[2,2] to pixel data pix[2 , 4], and the pixel data pix[3,2] to pixel data pix[3,4] are This is the value obtained by performing convolution using filter fil1.

[0275] Also, at time T 12 Now, from the terminal AO of the arithmetic circuit MA[9,2], F2 [1,1] [9 ] is output. F2 [1,1] [9] is the F2 [1,1] [9]= fil2[1,1]×pix[1,1]+fil2[1,2]×pix[1,2]+fi l2[1,3]×pix[1,3]+fil2[2,1]×pix[2,1]+fil2 [2,2]×pix[2,2]+fil2[2,3]×pix[2,3]+fil2[3 ,1]×pix[3,1]+fil2[3,2]×pix[3,2]+fil2[3,3 ]×pix[3,3].

[0276] In other words, F2 [1,1] [9] is the pixel data pix[1,1] of the image data IPD. Pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2 ,3], and the area of ​​pixel data pix[3,1] to pixel data pix[3,3] This is the value obtained by performing convolution using filter fil2.

[0277] In this way, by inputting image data IPD to the MAC array MAR, the calculation The filters fil1 to fil2 are output from the circuits MA[9,1] to MA[9,10], respectively. To filter fil10 The results of the convolution operations performed by The calculation result obtained by the convolution can be expressed as shown in FIG. 17, for example. In the MAC array MAR shown in FIG. The arithmetic circuits MA[1,9], MA[9,1] and MA[9,9] are shown. Also, at time T 12 to time T 20 Each of these is at time T 11 In the wiring CK L has a potential change from low level potential to high level potential one to nine times as a clock signal. The time is the time when the

[0278] For example, at time T 18 In this case, the clock signal is transmitted from the low level potential to the high level potential on the wiring CKL. The potential change to the Bell potential occurs, and the arithmetic circuit MA[9,1] to the arithmetic circuit MA[9, 8], the convolutions performed by the filters fil1 to fil8 As a result of the calculation, F1 [1,8] [9], F2 [1,7] [9], F3 [1,6] [9 ], F4 [1,5] [9], F5 [1,4] [9], F6 [1,3] [9], F7 [1, 2] [9], F8 [1,1] [9] is output. Note that the arithmetic circuit MA[9,9] and From the arithmetic circuit MA[9,10], in the 9th and 10th columns of the MAC array MAR, ,Since the convolution operation has not been completed, the operation result has not been output.

[0279] In addition, the convolutions output from the arithmetic circuits MA[9,1] to MA[9,10] The calculation results are calculated by circuits AF[1] to AF

[10] as activation functions and pooling functions. Here, as an example, the entire image data IPD may be processed. For all pixel data pix[1,1] to pix[m,n], the filter fil t F obtained by convolution of t [1,1] [9]~F t [m-2,n-2] [9], we apply the activation function to each of them to obtain F At [1,1] ~F At [m -2,n-2] It is assumed that the following can be obtained.

[0280] where F At [1,1] ~F At [m-2,n-2] to a matrix of m-2 rows and n-2 columns. The image data IPD-F is a t Image data IPD-F t For example, the filter fil is applied to the image data IPD. t The convolution process is performed by The filter fil is obtained by calculating the result of the convolution process using the activation function. t Image data (sometimes called a feature map) that extracts only the characteristic parts that depend on ) can be used. In addition, the image data IPD-F t For example, the following is shown in Figure 18: It is possible.

[0281] <<Convolutional Layer CL Operation 2>> Next, a convolution layer CL and a pool using the calculation device 100, which is different from the above-mentioned method, are The calculation method of the ring layer PL will be explained. The arithmetic circuit MA included in R is, for example, 9 rows and 10 rows, similar to the above-mentioned arithmetic method. It is assumed that the pixels are arranged in a matrix of columns.

[0282] In addition, the MAC array MAR in this operation method includes a programmable switch PR , the programmable switch PC is used to configure the circuits shown in Figs. 19A, 19B, and 20. Specifically, as shown in FIG. 19A, the sth row of the MAC array MAR (here In the above, s is an integer between 1 and 9. The terminal SO of MA is programmed to be in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. The MA[s,1] terminal is set as follows: The programmable switch P is connected to the terminal SI of the arithmetic circuit MA[s,2]. R[s,1] and the programmable switch PR[s,2] are set, and the arithmetic circuit M The terminal SO of A[s,2] is connected to the terminal SI of the arithmetic circuit MA[s,3]. , programmable switch PR[s,2] and programmable switch PR[s,3] The wiring XL[s] is set via the programmable switch PR[s,1]. As a result, the terminal SI of the arithmetic circuit MA[s,1] is in a conductive state. In this method, in each row of the MAC array MAR, the arithmetic circuits MA are serially connected to each other so as to be in a conductive state. Assume that the programmable switch PR is set as follows:

[0283] In addition, the MAC array MAR in this operation method is specifically as shown in FIG. 19B. , the arithmetic circuit MA[s,1] to the arithmetic circuit MA[ s, 9], the terminal AO of the arithmetic circuit MA is in a conductive state with the terminal AI of another arithmetic circuit MA. and the data output from the terminal AO of a certain arithmetic circuit MA is different. The programmable switch is set to input the signal to the terminal AI of the original arithmetic circuit MA via MA. For example, the terminal AO of the arithmetic circuit MA[s,9] is set to Programmable switch PR[s,9] is connected to terminal AI of [s,8]. and the programmable switch PR[s,8] are set. The terminal AO of MA[s,8] is connected to the terminal AI of the arithmetic circuit MA[s,7]. Then, programmable switch PR[s,8] and programmable switch PR[s,7] Furthermore, the terminal AO of the arithmetic circuit MA[s,1] is set to the terminal AO of the arithmetic circuit MA[s,9]. ] terminal AI, the programmable switch PR[s,1] and the programmable In other words, in this operation method, MAC In the arithmetic circuit MA of each row of the array MAR, the data output from the arithmetic circuit MA is the same. The programmable switches PR[s,1] to PR[s,2] are used to cycle to other arithmetic circuits MA in the row. It is assumed that the programmable switch PR[s, 9] is set. Since the arithmetic circuit MA[s,10] is not used, the arithmetic circuit MA[s,10] is The programmable switch PR[s,10] is in a non-conductive state with other arithmetic circuits MA. do.

[0284] In addition, the MAC array MAR in this operation method is specifically as shown in FIG. The MAC array MAR contains the t-th column (where t is an integer between 1 and 10). In the arithmetic circuit MA, the terminal MO of the arithmetic circuit MA is connected to the terminal M of the adjacent arithmetic circuit MA. The programmable switch PC is set to be in a conductive state with I. The terminal MO of the arithmetic circuit MA[1,t] is in a conductive state with the terminal MI of the arithmetic circuit MA[2,t]. As shown, the programmable switch PC[1,t] and the programmable switch PC[2, For example, the terminal MO of the arithmetic circuit MA[2,t] is set to The programmable switch PC[2 ,t] and programmable switch PC[3,t] are set. t] is connected to the end of the arithmetic circuit MA[9,t] via the programmable switch PC[9,t]. In this way, in this operation method, each In the column, the programmable switch PC is connected so that the arithmetic circuit MA is in a serial conducting state. is assumed to be set.

[0285] Figure 21 shows the time T 21 From time T 41 The number of calculations during and around the time The path MA[1,1] has terminals SI, SO, AI (terminal ST of the adder), and AO, terminal MO, terminals XI and WI of the multiplier MP, terminal TT of the adder, and register 10 is a timing chart showing changes in data input to terminal IT4 of RG4. 21 also shows the changes in the potentials of the wiring CKL, wiring SLT, wiring SEL, and wiring URST. In FIG. 21, "high" indicates a high level potential, and "low" indicates a low level potential. represents the electric potential.

[0286] The following describes the operations performed in the MAC array MAR using the timing chart of FIG. The calculation method will be described below. Unless otherwise specified, the calculation method is performed by the calculation circuit MA[ It is assumed that this is performed by the arithmetic circuits MA[1,1] to MA[1,9].

[0287] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, at time T 21 twist In the above, the terminals S of the arithmetic circuits MA[1,1] to MA[9,10] I, terminal SO, terminal XT, terminal WT, terminal AI (terminal ST), terminal TT, and terminal AO It is preferable that initialization data is input (not shown in FIG. 21). The data for the wiring URS can be, for example, data with a value of "0". The potential of T is changed from low level potential to high level potential, and terminal A is connected by resistor RG3. The potential of terminal AO at this time is set to the appropriate value, for example, When the potential of the wiring URST is at a low level, the potential of the wiring S The potential of EL is set to high level potential, and the potential of terminal MO is set to the appropriate level by resistor RG4. At this time, the potential of the terminal MO is preferably set to a potential corresponding to the value of "0", for example. It's nice.

[0288] [Step 1: Input image data] Next, the arithmetic circuits MA[1,1] to M Pixel data pix of the image data IPD is input to each of A[9,10]. Here, the image data IPD is, for example, calculated as shown in FIG. 10A in the same manner as in the above-mentioned calculation method. As shown, a plurality of pixel data pix[1,1] to pix[m,n] in m rows and n columns ] shall be composed of the following.

[0289] The image data IPD is read from the memory unit MEMD of the arithmetic device 100, for example. .

[0290] As in the above-described calculation method, in this operation method, the MAC array MAR also has a register The registers RG[1,p] to RG[9,p] are electrically connected. The s-th row of the AC array MAR contains registers RG[s,1] to RG[s,p]. Pixel data pix is ​​input via

[0291] The registers RG[s,1] to RG[s,p] are connected to the clock line CKL. For example, every time a potential change from a low level potential to a high level potential is input as a clock signal, The pixel data pix read from the memory unit MEMD is transmitted in sequence. As described above, the arithmetic circuits MA[s,1] to MA[s,10] in the sth row have terminals S I is the input terminal and SO is the output terminal. The pixel data pix sent to the register RG[s,p] is calculated sequentially according to the clock signal. The signals are transmitted to the circuits MA[s,1] through the arithmetic circuits MA[s,10].

[0292] In this operation method, pixel data pix is ​​transmitted to the MAC array MAR as shown in FIG. As shown in the figure, the same pixel data pi x is input. In FIG. 22A, the time T 23 Pixel data pi in x to the MAC array MAR. Specifically, for example, pixel data pix [1,1] is the register of each of the arithmetic circuits MA[1,2] to MA[9,2]. The values ​​of the arithmetic circuits MA[1,2] to MA[9,2] are held by the counter RG1. Similarly, pixel data pix[1,2] is output to the respective terminals SO. The values ​​held by the registers RG1 of the arithmetic circuits MA[1,1] to MA[9,1] are The registers RG[1,p] to RG[1,p] outside the MAC array MAR are [9,p] holds pixel data pix[1,3] and calculates pixel data pix[1,3]. The inputs are input to the arithmetic circuits MA[1,1] to MA[9,1]. , arithmetic circuits MA[1,10] to MA[9,10], etc. are not shown.

[0293] From the stage shown in FIG. 22A, the potential of the clock signal changes from a low level potential to a high level potential. By making six changes, the pixel data pix[3,3] becomes as shown in Figure 22B. , are input to the terminals SI of the arithmetic circuits MA[1,1] to MA[9,1]. The time at this time is called time T 29 Let's say.

[0294] Note that pixel data pix[1,1] is input to the arithmetic circuits MA[1,9] to MA[9, A low level potential is input to the wiring SLT until it is held in the register RG1 in [9]. In other words, the pixel data pix[1,1] is input to the MAC array MAR and then calculated. Until the registers RG1 of the circuits MA[1,1] to MA[9,9] are held register RG2 does not acquire pixel data pix from terminal IT2.

[0295] By the way, the registers RG1 of the arithmetic circuits MA[1,9] to MA[9,9] are After the raw data pix[1,1] is held, a high level potential is temporarily input to the wiring SLT. (The time at this time is called time T 31 At this time, the clock signal is at a low level. When a potential change occurs from low to high level, the register RG2 The inputs to the terminals IT2 of the registers RG2 of the arithmetic circuits MA[1,9] to MA[9,9] are The pixel data pix[1,1] stored in the OT1 pin is held and the pixel data pix[1, 1]. Note that each of the arithmetic circuits MA[1,9] to MA[9,9] outputs After the pixel data pix[1,1] is held in the register RG2, the line SLT is set to a low level. This is a clock signal that changes from a low level potential to a high level potential. When a potential change occurs, the pixel data pix[1,1] stored in register RG2 becomes This is done to prevent rewriting.

[0296] In the MAC array MAR, the arithmetic circuits MA[1,9] to MA[9,9] are Similarly, for the other arithmetic circuits, at time T 31 Then, a high level potential is temporarily applied to the wiring SLT. This causes the time T 31 In the arithmetic circuit MA[1,1] to the arithmetic circuit MA The pixel data pix input to the terminal IT2 of each register RG2 [9,8] For example, the arithmetic circuit MA[9,1 ], pixel data pix[3,3] is input to terminal IT2 of register RG2. Therefore, at this time, a high level potential is input to the line SLT, and the pixel data p ix[3,3] is output.

[0297] [Step 2: Read filter values] Also, at time T 31 At this time, the arithmetic circuit MA[1 , 1] to the arithmetic circuit MA[1, 9], the filter value is input from the storage unit OSM. The filter value is read out. Ct A component of the matrix contained in In addition, the matrix is ​​the fil t A 3-by-3 matrix similar to As an example, the arithmetic circuits MA[1,1] to MA[1,1] in the first row of the MAC array MAR are From each memory unit OSM of the arithmetic circuit MA[1,10], the context CTEX1 The corresponding filter value shall be read.

[0298] The filter value corresponding to the context CTEX1 is the value of the arithmetic circuit MA[ The calculation circuits MA[1,1] to MA[1,9] are read from the respective storage units OSM. The value in the block indicated by the text CTEX1 is used. Not only the context CTEX1, but also the contexts CTEX2 to CTEX9 The corresponding filter values ​​for each are also shown.

[0299] Specifically, the memory units of the arithmetic circuits MA[1,1] to MA[1,9] When the signal of the context CTEX1 is given to OSM, the operation circuit MA[1,9] From the storage OSM, fil C1 [1,1] is read and the memory of the arithmetic circuit MA[1,8] Part of OSM is fil C2 [1,2] is read out and the memory part OS of the arithmetic circuit MA[1,7] From M to fil C3 [1,3] is read out and stored in the memory OSM of the arithmetic circuit MA[1,6]. They are fil C4 [2,1] is read out, and from the memory unit OSM of the arithmetic circuit MA[1,5] fil C5 [2,2] is read out, and fi is read out from the memory unit OSM of the arithmetic circuit MA[1,4]. l C6 [2,3] is read out and fil is read out from the memory part OSM of the arithmetic circuit MA[1,3]. C7 [3,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,2]. C8 [3 ,2] is read out, and fil is read out from the storage unit OSM of the arithmetic circuit MA[1,1]. C9 [3,3 ] is read out.

[0300] [Step 3: Multiplying pixel data by filter value] Next, the arithmetic circuits MA[1,1] to MA[1, 9], the pixel data and the filter value are explained.

[0301] For example, in the arithmetic circuit MA[1,9], the terminal WI of the multiplier MP receives the filter value and fil C1 [1,1] is input. Also, the register RG2 contains pixel data p Since ix[1,1] is held, the pixel data pix[ 1,1] is input to the terminal ZO of the multiplier MP. C1 [1, 1] × pix[1,1] is output. Also, the terminal ST of the adder AD has the initial value Assume that data "0" is input. This causes the terminal FT of the adder AD to C1 By inputting [1,1]×pix[1,1], the terminal TT of the adder AD is il C1 [1,1] x pix[1,1] is output. In this example, A1[1] =fil C1 [1,1]×pix[1,1]. A1[1] is the arithmetic circuit MA[1, 9] is input to the terminal IT3 of the register RG3.

[0302] Also, for example, in the arithmetic circuit MA[1,1], a filter is connected to the terminal WI of the multiplier MP. fil as the data value C9 [3,3] is input. Also, the pixel data is input to register RG2. Since the pixel data pix[3,3] is held, the pixel data p ix[3,3] is input. This causes the terminal ZO of the multiplier MP to receive fil C1 [3,3] × pix[3,3] is output. Also, the initial value is As a result, the terminal FT of the adder AD is set to "0". fil C9 When [3,3] × pix[3,3] is input, the terminal TT of the adder AD fil C9 [3,3] x pix[3,3] is output. In this example, A9 [1]=fil C9 [3,3]×pix[3,3]. A9[1] is the arithmetic circuit MA [1,1] is input to terminal IT3 of register RG3.

[0303] Regarding the arithmetic circuits MA[1,2] to MA[1,8], 9] and the arithmetic circuit MA[1,1] perform the same operation. At this time, each adder The multiplication results output from AD are input to the terminal IT3 of each register RG3. The following table shows the registers of each of the arithmetic circuits MA[1,1] to MA[1,9]. The multiplication results input to the terminal IT3 of RG3 are shown. A9[1], A8[1], A7[1], A6[1], A5[1], A4[1], A3[1 ], A2[1].

[0304] [Table 1]

[0305] [Step 4: Switching filter values ​​and adding the calculation results] Here, when a potential change from a low level potential to a high level occurs as a clock signal, The registers RG3 of the arithmetic circuits MA[1,1] to MA[1,9] are The addition data input to terminal IT3 is held and the addition data is output to terminal OT3 of register RG3. The data is output (the time at which this occurs is called time T 32 This results in the As shown in the figure, the terminals AO of the arithmetic circuits MA[1,1] to MA[1,9] et al., A9[1], A8[1], A7[1], A6[1], A5[1], A4[1], A3 [1], A2[1], A1[1] are output.

[0306] A1[1] is input to the terminal AI of the arithmetic circuit MA[1,8], and A2[1] is input to the terminal AI of the arithmetic circuit M A3[1] is input to the terminal AI of the arithmetic circuit MA[1,6]. A4[1] is input to the terminal AI of the arithmetic circuit MA[1,5], and A5[1] is input to the terminal AI of the arithmetic circuit MA[1,5]. A6[1] is input to the terminal AI of the arithmetic circuit MA[1,4], and A6[1] is input to the terminal AI of the arithmetic circuit MA[1,3]. A7[1] is input to the terminal AI of the arithmetic circuit MA[1,2], and A8[ 1] is input to the terminal AI of the arithmetic circuit MA[1,1], and A9[1] is input to the arithmetic circuit MA[1, 9] is input to terminal AI.

[0307] At this time, in each of the arithmetic circuits MA[1,1] to MA[1,9], In this case, the storage unit OSM stores a filter value corresponding to the context CNTX2 shown in FIG. is read out.

[0308] Specifically, the storage unit OSM of the arithmetic circuit MA[1,8] stores fil C1 [1,2] is readable The storage unit OSM of the arithmetic circuit MA[1,7] is filled with fil C2 [1,3] is read The storage unit OSM of the arithmetic circuit MA[1,6] stores fil C3 [2,1] is read, The storage unit OSM of the arithmetic circuit MA[1,5] is C4 [2,2] is read and the operation From the memory part OSM of the circuit MA[1,4], fil C5 [2,3] is read out and the calculation circuit M From the memory part OSM of A[1,3], fil C6 [3,1] is read out and the arithmetic circuit MA[ 1,2] from the storage part OSM C7 [3,2] is read out and the calculation circuit MA[1, 1] from the storage section of OSM C8 [3,3] is read and the calculation circuit MA[1,9] The storage part of OSM is fil C9 Assume that [1,1] is read out.

[0309] As a result, similarly to step 3, the arithmetic circuits MA[1,1] to MA[1,9] ], the image held by the register RG2 is input to the terminal XI of the multiplier MP. The raw data pix is ​​input, and the modified filter value is input to the terminal WI of the multiplier MP. Therefore, the multiplication result of the pixel data and the filter value is output from the terminal ZO of the multiplier MP. .

[0310] Furthermore, the adders AD In this case, the multiplication result is input to the terminal FT of the adder AD, and the terminal ST of the adder AD is , the data input to the terminal AI is input. Therefore, the output from the terminal TT of the adder AD is The data to be added is as shown in the following table. The results of each multiplication are shown in A8[2] , A7[2], A6[2], A5[2], A4[2], A3[2], A2[2], A1[ 2], A9[2].

[0311] [Table 2]

[0312] The registers R of the arithmetic circuits MA[1,1] to MA[1,9] To terminal IT3 of G3, A8[2], A7[2], A6[2], A5[2], A4[2], A3[2], A2[2], A1[2], and A9[2] are input.

[0313] Here, a potential change from a low level potential to a high level potential occurs as a clock signal. When this occurs, the registers RG of the arithmetic circuits MA[1,1] to MA[1,9] are 3 is the same as that of the arithmetic circuits MA[1,1] to MA[1,9] as shown in FIG. 24B. From each terminal AO, A8[2], A7[2], A6[2], A5[2], A4[2] , A3[2], A2[2], A1[2], A9[2] are output.

[0314] [Step 5: Repeat step 4] The operation of step 4, that of the arithmetic circuits MA[1,1] to MA[1,9] The data input to each register RG3 is held and the corresponding data is output to the terminal OT3 of register RG3. The output of the data, the memory units O of the arithmetic circuits MA[1,1] to MA[1,9] Read the corresponding filter value from SM and multiply it by the pixel data pix. The calculation results are repeatedly added to the data. The filter values ​​read from the respective storage units OSM of the arithmetic circuit MA[1,9] are , the contexts CNTX3 to CNTX9 in FIG. 23 may be selected in order.

[0315] For example, in the arithmetic circuit MA[1,1], at time T 33 From time T 40 In the meantime, The filter values ​​read from the memory unit OSM are the context CNTX3 in Figure 23. Select the context CNTX9 in order and then C7 [3,3], fil C6 [3 ,3],fil C5 [3,3], fil C4 [3,3], fil C3 [3,3], fil C2 [3,3], fil C1 [3,3] and the arithmetic circuit MA[1 , 1] is the operation in each of the contexts CNTX3 to CNTX9. From terminal AO to A7[3], A6[4], A5[5], A4[6], A3[7] , A2[8], A1[9] are output.

[0316] From the above, time T 40 At this stage, the arithmetic circuits MA[1,1] to MA[1,9] ] to the terminal IT3 of the register RG3 of each of A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], A2[9] are entered. do.

[0317] As an example, A1[9] is calculated by the arithmetic circuits MA[1,1] to MA[1,9]. That is, it is the value resulting from the multiplication and addition of the filter value and the pixel data pix. A1[9] is, by the above operation, A1[9]=fil C1 [1,1]×pix[1,1] +fil C1 [1,2]×pix[1,2]+fil C1 [1,3]×pix[1,3] +fil C1 [2,1]×pix[2,1]+fil C1 [2,2]×pix[2,2] +fil C1 [2,3]×pix[2,3]+fil C1 [3,1]×pix[3,1] +fil C1 [3,2]×pix[3,2]+fil C1 [3,3]×pix[3,3] This becomes:

[0318] That is, A1[9] is the pixel data pix[1,1] to pixel data pix[1,1] of the image data IPD. pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and The area of ​​pixel data pix[3,1] to pixel data pix[3,3] is filtered by the filter fi l C1 The value is obtained by convolution with

[0319] Similarly, A9[9] is calculated as follows: A9[9]=fil C9 [3,3]× pix[3,3]+fil C9 [1,1]×pix[1,1]+filC9 [1,2]× pix[1,2]+fil C9 [1,3]×pix[1,3]+fil C9 [2,1]× pix[2,1]+fil C9 [2,2]×pix[2,2]+fil C9 [2,3]× pix[2,3]+fil C9 [3,1]×pix[3,1]+fil C9 [3,2]× The result is pix[3,2].

[0320] That is, A9[9] is the pixel data pix[1,1] to pixel data pix[1,1] of the image data IPD. pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and The area of ​​pixel data pix[3,1] to pixel data pix[3,3] is filtered by the filter fi l C9 The value is obtained by convolution with

[0321] Therefore, each of A2[9] to A8[9] is the same as A1[9] and A9[9]. Similarly, pixel data pix[1,1] to pixel data pix[1,3] of the image data IPD , pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix The area from [3,1] to pixel data pix[3,3] is filtered by the filter fil C2 or filter fil C8 The value is obtained by convolution with

[0322] [Step 6: Output the result of the multiply-and-accumulate operation] In step 6, the terminals of the arithmetic circuits MA[1,1] to MA[1,9] are The value of the sum of products is output from the child MO. Specifically, at time T 40 In the calculation circuit MA A high level is applied to the control terminal of each selector SLC of the arithmetic circuit MA[1,1] to the arithmetic circuit MA[1,9]. Since the voltage of the capacitor is input, the first input terminal and the output terminal are in a conductive state, and the second input terminal This causes a non-conduction state between the input terminal and the output terminal of resistor RG3. and the terminal IT4 of the resistor RG4 are brought into a conductive state.

[0323] At this time, a potential change from a low level potential to a high level potential occurs as a clock signal. By this, the registers of the arithmetic circuits MA[1,1] to MA[1,9] are The data input to the IT3 terminal of the register RG3 is held and output to the OT3 terminal of the register RG3. The data is output. Therefore, the data is input to the terminal IT4 of the register RG4. will be done.

[0324] That is, the registers R of the arithmetic circuits MA[1,1] to MA[1,9] A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A to G3 A4[9], A3[9], A2[9] are held, and the respective data is stored in register RG4 The signal is input to terminal IT4.

[0325] Furthermore, a potential change from a low level potential to a high level potential occurs as a clock signal. (The time at this time is T 41 The data input to terminal IT4 of register RG4 is The data is held by register RG4 and is output to terminal OT4 of register RG4. Therefore, each of the arithmetic circuits MA[1,1] to MA[1,9] is output. A1[9], A9[9], A8[9], A7[9] are output from each register RG4. , A6[9], A5[9], A4[9], A3[9], A2[9] are the arithmetic circuits MA[1 ,1] to the terminal MO of the arithmetic circuit MA[1,9].

[0326] In step 6, the arithmetic circuits MA[1,1] to M In each selector SLC of the arithmetic circuit MA other than A[1,9], A bell potential is input. This causes a non-conductive state between the first input terminal and the output terminal. The second input terminal and the output terminal are brought into a conductive state. The state between the terminal MI and the terminal IT4 of the resistor RG4 is brought into conduction.

[0327] As mentioned above, the programmable switches of the MAC array MAR in this operation method Each of the programmable switches PC[1,t] to PC[9,t] is shown in FIG. Therefore, in the first column of the MAC array MAR, the arithmetic circuit MA[1,1 ] is connected to the arithmetic circuit MA[2,1] through the arithmetic circuit MA[8,1]. The terminal MI of MA[9,1] is in a conductive state. Similarly, for other columns, In the same column of the array MAR, the terminal MO of the arithmetic circuit MA located in the first row is A state of conduction is established with the terminal MI of the arithmetic circuit MA on the ninth row via the arithmetic circuit MA on the eighth row.

[0328] Therefore, the terminals MO of the arithmetic circuits MA[1,1] to MA[1,9] From A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4 [9], A3[9], A2[9] are output, and then the clock signal is As shown in FIG. 24C, the potential changes from low to high level eight times. 9,1] to the terminals MO of the arithmetic circuits MA[9,9], A1[9], A9[9 ], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], A2 [9] is output.

[0329] On the other hand, other than the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR, In the arithmetic circuit MA, in each selector SLC, a low level potential is applied to the control terminal. is input, there is no conduction between the first input terminal and the output terminal. Therefore, the MAC array MAR includes the arithmetic circuits MA[1,1] to MA[1,9]. The arithmetic circuit MA is the above-mentioned A1[9], A9[9], A8[9], A7[9], A6[9 ], A5[9], A4[9], A3[9], A2[9], etc. Therefore, the MAC array MAR can be operated on in all rows except the first row. The arithmetic circuit MA includes, for example, pixel data pix of the image data IPD. Pixel data pix[1,1] to pix[1,3], pixel data pix[2,1] to pix[3,1] pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] Convolution may be performed on areas other than the above.

[0330] As shown in the timing chart of FIG. 21, the multiplier MP and the adder AD Specifically, at time T 30 From time T 39 Meanwhile, the cashier The following operations are performed from register RG[1,p] to register RG[9,p] to MAC array MAR. Pixel data pix[1,2] to pixel data pix[1,4], pixel data p Pixel data ix[2,2] to pix[2,4], and pixel data pix[3,2] to The pixel data pix[3,4] may be transmitted sequentially. Pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] Pixel data pix[2,3] and pixel data pix[3,1] to pixel data pix After the convolution operation for [3,3] is completed, the pixel data pix[1,2] is Pixel data pix[1,4], pixel data pix[2,2], and pixel data pix[ 2,4], and convolution for pixel data pix[3,2] to pixel data pix[3,4] The calculation of the pixel data can be performed in the same way. This reduces the time spent waiting for data transfer, thereby improving the efficiency of calculations.

[0331] Convolution calculation output from the arithmetic circuit MA[9,1] to the arithmetic circuit MA[9,10] The results are shown in Circuit AF[1] to Circuit AF

[10] , which are used to calculate activation functions, pooling layers, etc. The processing may be performed by the above-mentioned operation method. Please take into consideration the following.

[0332] In this operation method, as in the above-described operation method, filtering is performed on the image data IPD. Rutafil Ct By performing convolution processing using Ct Features that depend on It is possible to generate image data (feature map) that extracts only the important parts.

[0333] The above-mentioned operation method is applicable not only to the convolution calculation of image data but also to the calculation of FNN. can also be applied.

[0334] For example, m neurons (where m is an integer equal to or greater than 1) in the (k-1)th layer N (k-1) 1 to neuron N (k-1) m From the kth layer, n (where n is 1 or more) (N) of neurons (k) 1 to neuron N (k) n If a signal is sent to Consider the (k-1)th layer neuron N (k-1) i (where i is an integer between 1 and m. The signal sent from z (k-1) i Let N be the neuron in the (k-1)th layer. (k-1) i and the k-th layer neuron N (k) j The weighting coefficient between (k-1) i (k) j Then, the (k-1)th layer neuron N (k-1) 1 to neuron N (k-1) m to the k-th layer neuron N (k) j The sum of the products of the signals input to and the weighting coefficients is S (k ) j =Σw (k-1) i (k) j ×z (k-1) i (Σ is the sum of 1 to m for i )

[0335] Here, the kth layer neuron N (k) 1 to neuron N (k) n Regarding each of S (k) jA method for calculating the MAC address included in the calculation device 100 will be described. Register RG2 of the arithmetic circuit MA in one row of the ray MAR (k-1) i Keep specific For example, in FIG. 26, the operation circuits MA[1,1] to MA[1,10] are Each register RG2 contains (k-1) 10 ~z (k-1) It holds 1.

[0336] Next, the memory units OS As an example, the data read from M is used as a weighting factor. Set context CNTXF1 to context CNTXF10. CNTXF10 may be set as shown in FIG. The registers RG2 of the arithmetic circuits MA[1,1] to MA[1,10] are set to z (k-1) 10 ~z (k-1) 1 and the weight coefficients read from the memory OSM are shown in Figure 2. 6. Setting contexts CNTXF1 to CNTXF10 By this, the FNN calculation can be performed in the same way as the above-mentioned convolution calculation.

[0337] Note that FIG. 26 shows the case where the number of neurons in the k-th layer is n=10. However, if n is not 10, the number of contexts should be set to the number n. 26 shows the case where the number of neurons in the (k-1)th layer is m=10. However, if m is smaller than 10, the number of arithmetic circuits MA used for the calculation may be reduced. Also, if m is greater than 10, the neuron's signal z (k-1)1 to z (k-1) 10 When the sum of products of the weighting coefficients is calculated, the calculation circuit MA[1,1] to the calculation circuit The signal of the neuron to be operated next is stored in each register RG1 of MA[1,10]. Just keep it in advance.

[0338] The method for operating the semiconductor device according to one embodiment of the present invention is not limited to the above-described method. The method of operating the semiconductor device according to one embodiment of the present invention can be changed depending on the situation. For example, The MAC array MAR set by the programmable switch PR shown in FIG. The configuration is shown in FIG. 25, which is a MAC array M configured by a programmable switch PR. It may be changed to an AR configuration.

[0339] The configuration of the MAC array MAR shown in FIG. 25 is such that the terminal AO of the arithmetic circuit MA is connected to the arithmetic circuit two steps away. The programmable switch PR[s,1] is connected to the terminal AI of the circuit MA. The programmable switch PR[s,9] is set. 1] and the arithmetic circuit MA[s,2], the terminal AO of the arithmetic circuit MA[s,2] and the terminal AO of the arithmetic circuit MA[s,2] The programmable switch P is turned on so that the terminal AI of the path MA[s,1] is in a conductive state. R[s,2] and the programmable switch PR[s,1] are set, and the arithmetic circuit MA[s ,8] and the arithmetic circuit MA[s,9], the terminal AO of the arithmetic circuit MA[s,9] and the arithmetic circuit MA[s,9] are The programmable switch is connected to the terminal AI of the circuit MA[s,8]. The programmable switch PR[s,9] and the programmable switch PR[s,8] are set.

[0340] In the configuration shown in FIG. 19B, the terminal AO of the arithmetic circuit MA[s,1] and the terminal AO of the arithmetic circuit MA[s,9] ] terminal AI becomes longer, which may cause signal delay. In the configuration shown in Fig. 1, the distance between the arithmetic circuits MA can be shortened on average, so the signal delay can be reduced. This can suppress the spread of the disease.

[0341] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0342] (Embodiment 2) In this embodiment, a memory circuit that can be applied to the memory unit OSM described in the above embodiment is This article explains:

[0343] The storage unit OSM may be, for example, a register, a flip-flop, an SRAM (Static RAM), or the like. c Random Access Memory) can be applied. For example, a flash memory may be used.

[0344] The storage unit OSM may be, for example, a DOSRAM (Dynamic Oxide Random Access Memory). Semiconductor Random Access Memory (registered trademark) ), or NOSRAM (Dynamic Oxide Semiconductor R The Remote Access Memory (R) may be applied.

[0345] FIG. 27A shows an example of the circuit configuration of a DOSRAM memory cell. 21 includes a transistor M1 and a capacitance element CA. The transistor M1 is It has a front gate (sometimes simply called the gate) and a back gate.

[0346] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CVL.

[0347] Transistor M1 functions as a write transistor in memory cell 221. The write transistor is preferably an OS transistor, which will be described later. .

[0348] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, the line CVL is set to a low level potential (reference voltage It is preferable to apply a voltage of 0.1 V.

[0349] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 The voltage can be increased or decreased.

[0350] Data is written and read by applying a high-level potential to the wiring WOL and M1 is turned on, and a state of conduction is established between the wiring BIL and the first terminal of the capacitance element CA. This is done by:

[0351] Specifically, data is written by applying a potential corresponding to the data to be written to the wiring BIL. This is done by writing the potential to the first terminal of the capacitance element CA via the transistor M1. After writing the data, a low-level potential is applied to the wiring WOL to turn on the transistor M1. By turning off the potential, the potential can be held in the memory cell 221.

[0352] In addition, to read data, first, the wiring BIL is set to an appropriate potential, for example, a low level potential. and high-level potential, and then the wiring BIL is electrically floating. After that, a high-level potential is applied to the wiring WOL to turn on the transistor M1. The potential of the wiring BIL is changed by turning on the capacitor C Since it is determined by the potential written to the first terminal of A, from the changed potential of the wiring BIL, The data stored in the memory cell 221 can be read out.

[0353] Furthermore, the above-described memory cell 221 is not limited to the circuit configuration shown in FIG. 27A. The circuit configuration of the recell 221 may be changed as appropriate.

[0354] FIG. 27B shows an example of the circuit configuration of a NOSRAM memory cell. 31 includes a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 has a front gate (sometimes simply referred to as a gate) and a back gate. It has a route.

[0355] Transistor M2 functions as a write transistor in memory cell 231. The write transistor is preferably an OS transistor, which will be described later. .

[0356] Also, transistor M3 functions as a read transistor in memory cell 231. The readout transistor is an OS transistor (described later) or a semiconductor layer having a silicon layer. In this example of operation, the transistor Unless otherwise specified, the transistor M3 operates in the saturation region. The gate voltage, source voltage, and drain voltage of transistor M3 are set to a value within the range in which it operates in the saturation region. It is assumed that the voltage is appropriately biased to

[0357] The first terminal of the transistor M2 is connected to the first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of transistor B is connected to the line CAL. The first terminal of transistor M3 is connected to the line R BL, the second terminal of the transistor M3 is connected to the line SOL, and the second terminal of the transistor M4 is connected to the line SOL. The gate of M3 is connected to the first terminal of the capacitive element CB.

[0358] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL functions as the second wiring of the capacitance element CB. It functions as a wiring for applying a predetermined potential to the terminal. It is preferable to apply a low level potential (sometimes called a reference potential) to the line CAL. When writing data or reading data, a high-level potential is applied to the wiring CAL. It is preferable to do so.

[0359] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 The voltage can be increased or decreased.

[0360] To write data, a high-level potential is applied to the wiring WOL to turn on the transistor M2. This is achieved by bringing the line WBL and the first terminal of the capacitance element CB into a conductive state. Specifically, when the transistor M2 is in an on state, the information to be recorded in the wiring WBL is A corresponding potential is applied to the first terminal of the capacitance element CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WOL to turn off the transistor M2. By switching the capacitor CB to the ON state, the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3 are The potential is maintained at .

[0361] Data is read by applying a predetermined potential to the wiring SOL. The current flowing between the source and drain of the transistor M3 and the voltage at the first terminal of the transistor M3 The potential is determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential of the wiring RBL connected to the first terminal of the transistor M3 is read out. By this, a current is held at the first terminal of the capacitance element CB (or the gate of the transistor M3). In other words, the potential at the first terminal of the capacitance element CB (or the transistor The information written in this memory cell is stored in the potential held at the gate of the It can be read out.

[0362] Furthermore, the above-described memory cell 231 is not limited to the circuit configuration shown in FIG. 27B. The circuit configuration of the rechargeable battery 231 may be changed as appropriate. For example, the wiring WBL and the wiring RBL may be connected together. The memory cells may be arranged as a single wiring BIL. 7C. The memory cell 232 has the wiring WBL and the wiring RBL of the memory cell 231 connected together. The second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. The memory cell 232 is connected to the wiring BIL. The bit line and the read bit line are configured to operate as a single wiring BIL. .

[0363] As mentioned above, DOSRAM and NOSRAM use OS transistors as write transistors. The semiconductor layer of the OS transistor is the same as that described in Embodiment 3. The metal oxide includes, for example, indium, element M (aluminum), Sodium, Gallium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from zinc, hafnium, tantalum, tungsten, magnesium, etc., or The material may be one or more selected from the group consisting of indium, zinc, and a plurality of other elements. The semiconductor layer contains a metal oxide made of aluminum, gallium, and zinc. The band gap of the semiconductor layer can be increased. The current can be reduced.

[0364] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0365] (Embodiment 3) In this embodiment, a configuration example of the semiconductor device described in the above embodiment and a semiconductor device An example of the structure of an applicable transistor will be described.

[0366] <Configuration example of semiconductor device> The semiconductor device shown in FIG. 28 includes a transistor 300, a transistor 500, and a capacitor element 30A is a cross-sectional view of the transistor 500 in the channel length direction. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 30C is a cross-sectional view of the transistor 500 in the channel width direction. 1 is a cross-sectional view of a transistor 300 in the channel width direction.

[0367] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). The transistor 500 has a small off-state current and a low field effect even at high temperatures. The transistor 500 has a characteristic that the resultant mobility does not change. The transistors included in the arithmetic device 100, arithmetic device 100A, etc. described in the embodiment By applying this, it is possible to realize a semiconductor device whose operating capability does not decrease even at high temperatures. By utilizing the characteristics of a small off-state current, the transistor 500 is By applying this to the memory cell M2, the memory cell 221, the memory cell 231, and the memory cell 2 The potential written to 32 or the like can be maintained for a long period of time.

[0368] The semiconductor device described in this embodiment is, for example, a transistor as shown in FIG. 300, a transistor 500, and a capacitor element 600. The transistor 500 is, for example, , the capacitor element 600 is provided above the transistor 300, for example. 0 and the transistor 500. Note that the capacitor 600 is The capacitances included in the memory cells 231 and 232 described in the embodiment are Depending on the circuit configuration, the capacitance element 600 shown in FIG. It's not necessary.

[0369] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the transistors included in the arithmetic device 100, the arithmetic device 100A, etc., described in the above embodiments It can be applied to transistors, etc.

[0370] The substrate 311 is a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). It is preferable that

[0371] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 30C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0372] The transistor 300 may be either a p-channel type or an n-channel type. .

[0373] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Nitride), GaAlAs (Gallium Aluminum Arsenide), GaN (Gallium Nitride), etc. The effective mass can be increased by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, a structure using silicon with controlled conductivity may be used. This allows the transistor 300 to be a HEMT (High Electron Mobilit y Transistor).

[0374] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0375] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0376] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0377] The transistor 300 shown in FIG. 28 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure and driving method. A unipolar circuit consisting of only transistors (in this specification, only n-channel transistors, etc.) As shown in Figure 29, when the term "transistor circuit" is used, the The transistor 300 has a structure similar to that of a transistor 500 using an oxide semiconductor. The transistor 500 will be described in detail later.

[0378] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0379] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0380] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0381] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0382] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the capacitor 500 is provided. It is preferable that

[0383] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0384] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0385] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. It can be reduced.

[0386] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0387] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring board from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0388] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0389] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0390] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0391] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0392] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0393] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0394] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0395] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0396] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0397] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0398] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0399] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the capacitor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0400] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0401] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0402] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0403] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the film 516 .

[0404] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0405] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0406] Above the insulator 516 is the transistor 500 .

[0407] As shown in FIGS. 30A and 30B, the transistor 500 includes an insulator 514 and an insulator 516. The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the insulator 522, and an oxide 53 is disposed on the insulator 524. 530a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart, and conductor 542a and conductor 54 2b, and an opening is formed between the conductors 542a and 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c an insulator 550 disposed on the forming surface; and a conductor 560 disposed on the forming surface of the insulator 550; It has.

[0408] As shown in FIGS. 30A and 30B, the oxide 530a, the oxide 530b, and the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580, and the conductor 542b. As shown in FIGS. 30A and 30B, the conductor 560 is preferably made of an insulator 560. 50, and a conductor 560a provided inside the conductor 560a. It is preferable that the conductive material 560b is provided. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0409] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0410] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, one embodiment of the present invention is not limited thereto. a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c The transistor 500 may have a layer structure or a stacked structure of four or more layers. Although the conductor 560 has a two-layer structure in the example, one embodiment of the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminate of three or more layers. 28, 30A, and 30B. 0 is an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method. Just use the .

[0411] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0412] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the conductive material 560 is not formed between the conductive material 542a and the conductive material 542b. Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0413] The conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the conductor 560 This can reduce the drain current when the potential applied to is 0V.

[0414] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0415] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. Although a layered structure is shown, one embodiment of the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.

[0416] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the above-mentioned function (i.e., that is difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0417] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0418] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In this case, the conductor 503a is not necessarily provided. However, it may have a laminated structure, for example, titanium or titanium nitride and the above conductive material. It may also be laminated with other materials.

[0419] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0420] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. In this specification and the like, oxygen vacancies in the metal oxide are referred to as V. O It is sometimes called oxygen vacancy. The area where the holes are formed is impurities or oxygen vacancies (V O ) is present, the electrical characteristics tend to fluctuate. In particular, oxygen deficiency (V O ) hydrogen near the oxygen vacancy ( V O ) with hydrogen (hereinafter referred to as V O It is sometimes called H.) This may cause the transistor 500 to This makes it more likely to have negative characteristics.

[0421] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0422] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may diffuse into the conductor 542a and the conductor 542b. The electrons may be trapped or captured (also called gettered).

[0423] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The microwave treatment may be performed at a pressure of 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0424] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. The heat treatment is preferably performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to compensate for the oxygen that was released. The treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of an oxidizing gas. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0425] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, "V O +O→null reaction Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in the substance 530 recombines with the oxygen vacancy to form V. O inhibits the formation of H It is possible.

[0426] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0427] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0428] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0429] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. The layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0430] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0431] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Furthermore, it is possible to obtain the insulator 520 having a laminated structure with a high relative dielectric constant.

[0432] 30A and 30B, the transistor 500 has a three-layer stack structure. As the second gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. Good too.

[0433] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. The In-M-Zn oxide that can be applied as a C-Axis Alignment Oxide (CAAC-OS) is ned Crystalline Oxide Semiconductor), CAC -OS(Cloud-Aligned Composite Oxide Semico The oxide 530 is preferably an In-Ga oxide. , In-Zn oxide, In oxide, etc. may also be used.

[0434] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, Examples include silicon and silicon dioxide.

[0435] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna It functions as a carrier and electrons are generated. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides containing a large amount of silicon tend to be normally on. In addition, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one aspect of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V is substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain the oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, This is sometimes referred to as oxidation treatment.) and oxygen deficiency is compensated for by supplying oxygen to the metal oxide. It is important to note that this is sometimes referred to as oxygenation treatment. O Impurities such as H are not enough By using a metal oxide that has been reduced to a low level in the channel formation region of a transistor, stable current can be obtained. It can be given a special characteristic.

[0436] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, metal As a parameter of the oxide, instead of donor concentration, we use the capacitance assuming a state where no electric field is applied. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "energy concentration."

[0437] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0438] In addition, when a metal oxide is used for the oxide 530, the metal oxide has a band gap of It is a semiconductor that is intrinsic (also called type I) or substantially intrinsic, and has a channel The carrier concentration of the metal oxide in the formation region is 1×10 18 cm -3It is preferable that it is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 Less than More preferably, 1×10 13 cm -3 More preferably, it is less than 1 x10 12 cm -3 It is more preferable that the metal oxide in the channel forming region is less than 1000 nm. The lower limit of the carrier concentration of the oxide is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0439] When a metal oxide is used for the oxide 530, the conductors 542a and 542b When the oxide 530 comes into contact with the conductor 542a, the oxygen in the oxide 530 is transferred to the conductor 542a and the conductor 542b. 2b, and the conductors 542a and 542b may be oxidized. The oxidization of the conductors 542a and 542b reduces the conductivity of the conductors 542a and 542b. It is highly likely that the oxygen in the oxide 530 will decrease. The conductors 542a and 542b absorb oxygen in the oxide 530 and diffuse into the oxide 530. This can be rephrased as ``to do.''

[0440] Furthermore, oxygen in the oxide 530 diffuses into the conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductor 542a and the conductor 542b. Since the conductor 54 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the conductor 542b, the hetero layer, and the oxide 530b is a metal-insulator structure. -It can be considered as a three-layer structure consisting of semiconductors, and is MIS (Metal-Insulator Diodes that are mainly called MIS (metal-semiconductor) structures or MIS structures This is sometimes called a bonded structure.

[0441] The different layer is formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. For example, the different layers may be a conductor 542a and a conductor 542b and an oxide 542b. 30c, or between the conductor 542a and the conductor 542b and the oxide 530b. and between the conductor 542a and the oxide 530c. be.

[0442] The metal oxide that functions as the channel forming region in the oxide 530 is a band gap metal oxide. It is preferable to use a material with a peak voltage of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. It is possible.

[0443] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0444] The oxide 530 has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, it is preferable to use The atomic ratio of element M in the metal oxide used for oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of element M to In is In the oxide 530b, the atomic ratio of the element M to In is preferably larger than that of the element M. In the metal oxide used for the oxide 530a, the atomic ratio of In to the element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. , oxide 530c can be oxide 530a or oxide 530b. Things can be used.

[0445] Specifically, the oxide 530a has an atomic ratio of In, Ga, and Zn of In:Ga:Z. Metal oxides with n=1:3:4 or 1:1:0.5 may be used. 0b, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=4:2:3, or 1 In addition, a metal oxide of In, Ga, and Zn may be used as the oxide 530c. The atomic ratio of In:Ga:Zn is 1:3:4, and the atomic ratio of Ga and Zn is Ga:Zn Metal oxides with a ratio of Ga:Zn=2:1 or Ga:Zn=2:5 may be used. As a specific example of the case where c is a laminated structure, the atomic ratio of In, Ga, and Zn is In:Ga Zn=4:2:3 and In:Ga:Zn=1:3:4, and Ga and Zn The atomic ratio of Ga:Zn is 2:1, and the atomic ratio of In, Ga, and Zn is In:Ga:Zn= The atomic ratio of Ga and Zn is 4:2:3, and the atomic ratio of In and Ga is 2:5. The atomic ratio of In to Zn is 4:2:3. and a layered structure with an atomic ratio of Ga to Zn of In:Ga:Zn=4:2:3. do.

[0446] In addition, for example, the ratio of In atoms to element M in the metal oxide used for the oxide 530a The atomic ratio of In to element M in the metal oxide used for oxide 530b is When the atomic ratio of In, Ga, and Zn in the oxide 530b is In:Ga:Zn = 5:1:6 or nearby, In:Ga:Zn = 5:1:3 or nearby, In:G In-Ga-Zn oxide with a composition of a:Zn=10:1:3 or similar is used. It is possible.

[0447] In addition to the above, the oxide 530b may have a composition of, for example, In:Zn=2: 1 composition, In:Zn=5:1 composition, In:Zn=10:1 composition, any of these Metal oxides having compositions close to one another can be used.

[0448] These oxides 530a, 530b, and 530c are formed by the above atomic ratio. For example, oxide 530a and oxide 530c are preferably filled and combined. The metal oxides and oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to the composition The compound 530b has a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition in the vicinity thereof. It is preferable that the metal oxide has the following composition. The atomic ratio in the substance or the sputtering target. By increasing the In ratio in the 0b composition, the on-current or field effect of the transistor can be improved. This is preferable because it can increase the fruit mobility and the like.

[0449] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of the oxide. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0450] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The oxide 530a is formed at the interface between the oxide 530a and the oxide 530b, and at the interface between the oxide 530b and the oxide 530c. It is preferable to lower the defect level density of the resulting mixed layer.

[0451] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0452] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0453] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride have low resistance to hydrogen or oxygen. It is preferable because it has barrier properties.

[0454] In addition, in FIGS. 30A and 30B, the conductor 542a and the conductor 542b are formed in a single layer structure. However, it may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten It is also possible to laminate a titanium film and an aluminum film. Two-layer structure with aluminum film laminated on copper-magnesium-aluminum film Two-layer structure with copper film laminated on alloy film, two-layer structure with copper film laminated on titanium film, tungsten Alternatively, a two-layer structure may be used in which a copper film is laminated on an aluminum film.

[0455] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A three-layer structure in which a titanium film or a copper film is laminated and a titanium film or a titanium nitride film is further formed on top of that. Molybdenum film or molybdenum nitride film and a An aluminum film or a copper film is laminated on top of it, and a molybdenum film or a molybdenum nitride film is further laminated on top of it. There are three-layer structures that form a transparent film. Transparent conductive materials may also be used.

[0456] As shown in FIG. 30A, the conductor 542a (conductor 542b) of the oxide 530 At the interface and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a functions as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between 3a and region 543b.

[0457] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0458] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 30 and may be provided so as to be in contact with the insulator 524.

[0459] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc. may be used. Alternatively, silicon nitride oxide or silicon nitride may be used as the insulator 544. You can be there.

[0460] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators including aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during the treatment. If b is a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, it is an insulating material. The insulator 544 is not an essential component and may be appropriately designed depending on the desired transistor characteristics. stomach.

[0461] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. The oxide 530c is prevented from diffusing into the oxide 530b through the insulator 550. In addition, the excess oxygen contained in the insulator 580 can prevent the conductor 560 from being oxidized. It is possible.

[0462] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is disposed in contact with the inside (top and side surfaces) of the insulating member 550. Similar to the insulator 524, an insulator containing excess oxygen and releasing oxygen when heated is used. It is preferable to form it using a

[0463] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0464] An insulator that releases oxygen when heated is used as the insulator 550, and is placed on the top surface of the oxide 530c. By providing the oxide 530b in contact with the insulator 550, the oxide 530c passes through the oxide 530b. In addition, oxygen can be effectively supplied to the channel formation region of the insulator 524. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0465] In addition, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, A metal oxide may be provided between the insulating material 550 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 550 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0466] Note that the insulator 550 may have a stacked structure similar to the second gate insulating film. As transistors become smaller and more highly integrated, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a thermally stable material and a thin film of a thin film, It is possible to reduce the gate potential during transistor operation. It may have a laminated structure.

[0467] The conductor 560 functioning as the first gate electrode has a two-layer structure in FIGS. 30A and 30B. Although the structure is shown as a single layer structure, it may also be a laminated structure of three or more layers.

[0468] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 550 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 560a. An oxide semiconductor that can be used for the oxide 530 can be used. In that case, the conductor 560 By forming the conductive layer 560b by sputtering, the electrical resistance of the conductive layer 560a is reduced, and the conductive layer 560b is This is called an OC (Oxide Conductor) electrode. It is possible.

[0469] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. A conductive material containing rubber as a main component can be used. For example, it may be a laminated structure of titanium or titanium nitride and the above conductive material. stomach.

[0470] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material contains silicon, silicon oxide having pores, or resin. Silicon nitride and silicon oxynitride are preferred because they are thermally stable. However, silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it can

[0471] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. The oxide 530 can be efficiently supplied through the insulator 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0472] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0473] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductor 560 may have a shape with a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0474] The insulator 574 is connected to the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. The insulator 574 is preferably provided in contact with the , insulator 550, and insulator 580. This allows for the provision of excess oxygen regions. Oxygen can be supplied into the oxide 530 from the excess oxygen region.

[0475] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of sodium, .

[0476] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0477] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0478] In addition, the openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the opening. The conductors 540a and 540b are provided facing each other with the conductor 560 in between. It has the same structure as the conductor 546 and the conductor 548 described later.

[0479] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0480] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0481] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using insulating materials, it is possible to reduce the parasitic capacitance that occurs between wiring. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0482] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The edge 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and Conductors 548 and the like are embedded.

[0483] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 functions as a plug or wiring that connects to the transistor 300. The conductor 548 can be formed using the same material as the conductor 328 and the conductor 330. Cut.

[0484] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture, In addition, it is possible to prevent hydrogen from penetrating the transistors 500. The whole may be wrapped in an insulator that has high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 514 or the insulator An opening is formed that reaches the insulator 522, and the above-mentioned barrier is formed so as to contact the insulator 514 or the insulator 522. If a highly flexible insulator is formed, the manufacturing process of the transistor 500 can be performed simultaneously. In addition, examples of insulators with high barrier properties against hydrogen or water include The same material as the insulator 522 may be used.

[0485] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0486] Moreover, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 12 functions as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0487] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Indium tin oxide, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible.

[0488] In FIG. 28, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high adhesion to highly conductive conductors A thin conductor may be formed.

[0489] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0490] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0491] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This can suppress the fluctuation of electrical characteristics and improve reliability. In semiconductor devices using transistors having compound semiconductors, miniaturization or high integration is being attempted. It is possible.

[0492] Next, another example of the structure of an OS transistor will be described, which is shown in FIGS. 28 and 29. do.

[0493] 31A and 31B are variations of the transistor 500 shown in FIGS. 30A and 30B. 31A is a cross-sectional view of a transistor 500 in the channel length direction, and FIG. 31A and 31B are cross-sectional views of the transistor 500 in the channel width direction. The structure shown in FIG. 1B is similar to that of the transistor 300 or other transistors included in the semiconductor device of one embodiment of the present invention. The present invention can also be applied to transistors.

[0494] The transistor 500 having the configuration shown in FIGS. 31A and 31B includes an insulator 402 and an insulator 30A and 30B in that it has a transistor 404. An insulator 552 is provided in contact with the side surface of the conductor 540a, and an insulator 552 is provided in contact with the side surface of the conductor 540b. The insulator 552 is provided in contact with the transistor shown in FIGS. 30A and 30B. 30A and 30B in that it does not have an insulator 520. This differs from the transistor 500 shown in FIG.

[0495] The transistor 500 shown in FIGS. 31A and 31B has an insulator 512 on an insulator 512. In addition, an insulator 404 is provided on the insulator 574 and on the insulator 402. It is provided.

[0496] In the transistor 500 having the configuration shown in FIGS. 31A and 31B, the insulator 514, the insulator 516, insulator 522, insulator 524, insulator 544, insulator 580, and insulator 574 The insulator 404 covers these. 4 is the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the Side, side of insulator 524, side of insulator 522, side of insulator 516, side of insulator 514 The oxide 530 and the like are in contact with the side surface and the top surface of the insulator 402, respectively. 04 and is isolated from the outside by an insulator 402.

[0497] The insulators 402 and 404 are made of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 402 and the insulator 403 have a high function of suppressing the diffusion of water molecules. The insulator 404 is made of silicon nitride or silicon nitride oxide, which has a high hydrogen barrier property. It is preferable to use a material such as a silicon dioxide film, which prevents hydrogen and other impurities from diffusing into the oxide 530. Therefore, the deterioration of the characteristics of the transistor 500 can be suppressed. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0498] The insulator 552 includes the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 574. The insulator 552 is provided in contact with the insulator 544. The insulator 552 has a function of suppressing the diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably made of a material with a high hydrogen barrier property. Insulators such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used. In particular, silicon nitride is a material with high hydrogen barrier properties, and is therefore suitable as the insulator 552. By using a material with a high hydrogen barrier property as the insulator 552, Impurities such as water or hydrogen pass through the insulator 580 and the like and the conductors 540a and 540b. In addition, the diffusion of the silicon dioxide into the oxide 530 can be suppressed. This can prevent oxygen from being absorbed by the conductors 540a and 540b. As described above, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0499] FIG. 32 shows the transistor 500 and the transistor 300 shown in FIGS. 31A and 31B. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device in which the conductor 546 is An insulator 552 is provided on the surface.

[0500] Also, the transistor 500 shown in FIGS. 31A and 31B may be configured as a transistor The transistor configuration may be changed. For example, transistor 500 in FIGS. 31A and 31B may be As a modification, the transistors shown in FIGS. 33A and 33B can be used. 3A is a cross-sectional view of the transistor in the channel length direction, and FIG. 3B is a cross-sectional view of the transistor in the channel length direction. The transistor shown in FIGS. 33A and 33B is a cross-sectional view in the width direction of the transistor. 31A and 31C, in that the oxide 530c has a two-layer structure of the oxide 530c1 and the oxide 530c2. This is different from the transistor shown in 1B.

[0501] The oxide 530c1 is formed on the top surface of the insulator 524, the side surface of the oxide 530a, and the side surface of the oxide 530b. The top surface and side surfaces, the side surfaces of the conductors 542a and 542b, the side surfaces of the insulator 544, and the insulating The oxide 530c2 contacts the side of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0502] The oxide 530c1 may be, for example, an In-Zn oxide. When the oxide 530c has a single layer structure, the oxide 530c can be used as the material 530c2. For example, the oxide 530c2 may be made of a material similar to the material that can be used for the oxide 530c2. In:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or A metal oxide with an atomic ratio of Ga:Zn=2:5 can be used.

[0503] By forming the oxide 530c into a two-layer structure of the oxide 530c1 and the oxide 530c2, In this case, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as a power MOS transistor, for example. Note that the oxide 53 included in the transistor having the structure shown in FIGS. 0c can also have a two-layer structure of oxide 530c1 and oxide 530c2.

[0504] The transistors having the configurations shown in FIGS. 33A and 33B may be, for example, This can be applied to the transistor 300. Also, the transistor 300 is The semiconductor device described in the above embodiment, for example, the arithmetic device described in the above embodiment, The present invention can be applied to transistors included in the arithmetic device 100, the arithmetic device 100A, etc. The transistors illustrated in FIGS. 33A and 33B are included in the semiconductor device of one embodiment of the present invention. The present invention can be applied to transistors other than the transistor 300 and the transistor 500. can.

[0505] FIG. 34 shows a transistor 500 having the configuration shown in FIG. 30A. 33A shows an example of the configuration of a semiconductor device in which the transistor 300 has the transistor configuration shown in FIG. 32, an insulator 552 is provided on the side surface of the conductor 546. As shown in FIG. 34, the semiconductor device of one embodiment of the present invention has a transistor 3 00 and transistor 500 are both OS transistors, while transistors 300 and Each of the transistors 500 can be configured differently.

[0506] Next, regarding the capacitance elements applicable to the semiconductor devices of FIGS. 28, 29, 32, and 34, I will explain.

[0507] FIG. 35 shows a capacitance that can be applied to the semiconductor devices shown in FIGS. A capacitor element 600A is shown as an example of the element 600. FIG. 35A is a top view of the capacitance element 600A, and FIG. 35B is a cross section taken along dashed line L3-L4 of the capacitance element 600A. 35C is a cross-sectional view of the capacitor element 600A taken along the dashed line W3-L4. FIG.

[0508] The conductor 610 serves as one of a pair of electrodes of the capacitor 600A, and the conductor 620 serves as The insulator 630 functions as the other of the pair of electrodes of the capacitor 600A. It functions as a dielectric sandwiched between the electrodes.

[0509] The insulator 630 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The insulating layer may be formed of a single layer or a multilayer structure.

[0510] In this specification, hafnium oxynitride refers to a compound containing more oxygen than nitrogen as its composition. Hafnium nitride refers to a material with a high content of nitrogen rather than oxygen. Indicates materials with a high content of

[0511] For example, the insulator 630 may be made of a material with high dielectric strength, such as silicon oxynitride. A laminated structure with a high dielectric constant (high-k) material may also be used. 600A has a high dielectric constant (high-k) insulator, ensuring sufficient capacity. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the capacitance element 600A is Destruction can be suppressed.

[0512] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, or oxide nitrides having silicon and hafnium Nitrides containing fluorine are also included.

[0513] Alternatively, the insulator 630 may be, for example, aluminum oxide, hafnium oxide, or tantalum oxide. , zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulators containing high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) For example, when the insulator 630 is a laminate, the insulating material may be a silicon dioxide. a three-layer laminate in which zirconium, aluminum oxide, and zirconium oxide are formed in this order; Zirconium oxide, aluminum oxide, zirconium oxide, aluminum oxide, In addition, the insulator 630 may be a four-layer laminate in which the following layers are formed in order. Compounds containing tungsten and zirconium may also be used. As integration density increases, the gate insulator and the dielectric used in the capacitor element become thinner, resulting in a This can cause problems such as leakage current in transistors and capacitors. By using high-k materials as insulators that function as dielectrics for the capacitor elements, While maintaining the thickness of the film, the gate potential during transistor operation is reduced and the capacitance of the capacitor element is reduced. It becomes possible to secure it.

[0514] The capacitance element 600 is connected to the conductor 546 and the conductor 548 below the conductor 610. Electrical conductors 546 and 548 are electrically connected to other circuit elements. 35A to 35C, the conductor 546 functions as a plug or wiring. , conductor 548 are collectively referred to as conductor 540.

[0515] Also, in FIG. 35, for clarity of illustration, the conductors 546 and 548 are embedded. an insulator 586 covering the conductor 620 and the insulator 630; and an insulator 650 covering the conductor 620 and the insulator 630. is omitted.

[0516] 28, 29, 32, 34, 35A, 35B, and 35C. The capacitor 600 is a planar type, but the shape of the capacitor is not limited to this. The capacitor 600 may be a cylindrical capacitor 600B shown in FIGS. 36A to 36C. stomach.

[0517] FIG. 36A is a top view of the capacitance element 600B, and FIG. 36B is a dashed line view of the capacitance element 600B. 36C is a cross-sectional view taken along the dashed line W3-L4 of the capacitance element 600B. FIG.

[0518] In FIG. 36B, a capacitive element 600B is formed by an insulator 58 having a conductor 540 embedded therein. 6, an insulator 631 having an opening, and an insulator 651 which functions as one of a pair of electrodes. The pair of electrodes includes a conductor 610 that functions as the other of the pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0519] Also, in FIG. 36C, for clarity, the insulators 586, 650, and The body 651 and are omitted.

[0520] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0521] In addition, the insulator 631 is filled with a conductor 611 so as to be electrically connected to the conductor 540. The conductor 611 is made of the same material as the conductors 330 and 518, for example. It can be used.

[0522] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0523] As described above, the insulator 651 has an opening that overlaps with the conductor 611. is doing.

[0524] The conductor 610 is formed on the bottom and side of the opening. 21 overlaps the conductor 611 and is electrically connected to the conductor 611.

[0525] The conductor 610 can be formed by etching the insulator 651. A mouth is formed, and then a conductor 610 is formed by sputtering, ALD, or the like. Then, CMP (Chemical Mechanical Polishing) The conductor 610 is left in the opening by a method such as a method of forming a film on the insulator 651. The conductor 610 can then be removed.

[0526] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor.

[0527] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled. There are.

[0528] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0529] The cylindrical capacitor element 600B shown in FIG. 36 has a larger capacitance than the planar capacitor element 600A. The capacitance value can be increased.

[0530] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0531] (Fourth embodiment) In this embodiment, the semiconductor device can be used for the OS transistor described in the above embodiment. The metal oxide (hereinafter also referred to as an oxide semiconductor) will be described.

[0532] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the material contains yttrium, tin, etc. Also, boron, silicon, titanium, etc. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Selected from among odymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. One or more of these may be included.

[0533] <Classification of crystal structures> First, the classification of crystal structures in oxide semiconductors will be explained with reference to FIG. 37A. FIG. 37A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metal oxides.

[0534] As shown in FIG. 37A, oxide semiconductors are broadly divided into "amorphous" and "non-amorphous" oxide semiconductors. ) and "Crystalline" and "Crystal" Also, among "Amorphous" there are those that are completely amorphous. Also, "Crystalline" contains CAAC (ca xis-aligned crystalline), nc(nanocrystall ine), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal al). The classification of "Crystalline" includes single crystal , poly crystal, and completely amorphous are excluded. Also, "Crystal" includes single crystal and poly Contains crystals.

[0535] The structures within the bold frame in Figure 37A are "Amorphous" and "Cr It is an intermediate state between "crystal" and "new crystal" In other words, the structure is in the It is completely different from the unstable "Amorphous" and "Crystal" This can be rephrased as a structure in which:

[0536] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). The crystallinity can be evaluated using the crystallinity spectrum. The GIXD (Grazing-Incidence) of CAAC-IGZO films The XRD spectrum obtained by the GIXD measurement is shown in Figure 37B. This is also called the membrane method or the Seemann-Bohlin method. The XRD spectrum obtained by the measurement is simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 37B is 500 nm.

[0537] As shown in Figure 37B, the XRD spectrum of the CAAC-IGZO film shows clear crystalline Specifically, in the XRD spectrum of the CAAC-IGZO film, A peak indicating the c-axis orientation is detected near 2θ=31°. The peak intensity at 2θ=31° is detected at the angle It is asymmetrical about the axis.

[0538] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns (ultra-small) observed by electron diffraction It can be evaluated by the electron diffraction pattern. The folding pattern is shown in Figure 37C. Figure 37C shows the NB method in which the electron beam is incident parallel to the substrate. The diffraction pattern observed by ED is shown in Figure 37C. The composition of the film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0539] As shown in Figure 37C, the diffraction pattern of the CAAC-IGZO film shows multiple patterns indicating c-axis orientation. Several spots are observed.

[0540] <<Oxide semiconductor structure>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in FIG. 37A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, the above-mentioned CAAC-OS Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-crystalline oxide semiconductors, and nc-OS. Amorphous-like oxide semiconductor (a-like OS) semiconductor), amorphous oxide semiconductor, etc.

[0541] Here, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, , and provide an explanation.

[0542] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. , in the normal direction to the surface on which the CAAC-OS film is formed, or in the normal direction to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as a crystal arrangement, the crystalline region is also a region with a uniform lattice arrangement. The OS has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion may occur in a region where multiple crystal regions are connected. The area where the orientation of the lattice arrangement changes between a region with one lattice arrangement and a region with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that has not been

[0543] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10 When a crystalline region is made up of a single microcrystal (crystals less than nanometers in size), The maximum diameter of the crystalline region is less than 10 nm. When such crystal regions are formed, the size of the crystal regions may be on the order of several tens of nanometers.

[0544] In-M-Zn oxide (element M is aluminum, gallium, yttrium, sulphur, CAAC-OS is a material selected from the group consisting of aluminum, titanium, and other materials. A layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the O layer) are formed. A layered crystal structure (also called a layered structure) is formed by stacking a layer having an element (hereinafter referred to as an (M, Zn) layer) and a layer having an element (hereinafter referred to as an (M, Zn) layer). Indium and element M are mutually substitutable. The (M,Zn) layer may contain indium. The In layer contains the element M. The In layer may contain Zn. In high-resolution TEM images, this is observed as a lattice pattern.

[0545] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ phase In the out-of-plane XRD measurement using a can, two peaks indicating the c-axis orientation were observed. The peak indicating the c-axis orientation is detected at or near θ=31°. ) may vary depending on the type and composition of the metal elements that make up the CAAC-OS.

[0546] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) Note that one spot and another spot are the incident electron beams that have passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at positions that are point-symmetric. can be.

[0547] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. However, the unit cell is not necessarily a regular hexagon, and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. -In OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is close-packed in the ab-plane direction. The bond distance between atoms changes when metal atoms are substituted. , it is believed that this is because distortion can be tolerated.

[0548] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming transistors. It is highly likely that this will cause a decrease in on-state current and a decrease in field effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystal structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides containing Zn to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are made of In oxide. This is preferable because it can suppress the generation of grain boundaries more effectively than oxides.

[0549] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of oxide semiconductors may be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having a CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. C-OS is stable even under high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using CAAC-OS for OS transistors increases the flexibility of the manufacturing process. It becomes possible to

[0550] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). In other words, nc-OS has a periodic atomic arrangement in the region of 3 nm or less. It has small crystals. The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. Since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be considered as a-like In some cases, it is difficult to distinguish between an OS and an amorphous oxide semiconductor. For example, in the case of an nc-OS film, , Structural analysis was performed using an XRD instrument, and out-of-plane analysis using θ / 2θ scan was performed. In the XRD measurement, no peaks indicating crystallinity were detected. However, electron beam circuits using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or larger) are being used. When electron diffraction (also called selected area electron diffraction) is performed, a diffraction pattern resembling a halo pattern is observed. On the other hand, for the nc-OS film, the size of the nanocrystals is close to or smaller than that of the nanocrystals. Electron beam diffraction (nanobeam) using an electron beam with a probe diameter (for example, 1 nm to 30 nm) When electron diffraction is performed, a ring-shaped region is formed around the direct spot. An electron diffraction pattern may be obtained in which multiple spots are observed.

[0551] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has pores or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0552] <<Oxide semiconductor structure>> Next, the details of the above-mentioned CAC-OS will be explained. Regarding the formation of

[0553] [CAC-OS] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in size. Preferably, the material is unevenly distributed in a size range of 1 nm to 3 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A mixed state of particles with sizes of less than 1 m or close to that size is called a mosaic or patch state. .

[0554] Furthermore, CAC-OS is a material that is separated into a first region and a second region. The first regions are in a shape of a cloud, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud shape). ) In other words, the CAC-OS is a mixture of the first area and the second area. It is a composite metal oxide having a structure in which

[0555] Here, the I ratio of the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of n, Ga, and Zn are defined as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has [In] higher than the [In] in the second region. In this region, [Ga] is larger than [Ga] in the first region. In addition, the second region has a larger [Ga] than the [Ga] in the first region and a smaller [I [n] is smaller than [In] in the first region.

[0556] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region containing gallium oxide, gallium zinc oxide, etc. In other words, the first region is called a region in which In is the main component. The second region can be rephrased as a region containing Ga as the main component. It is possible.

[0557] Note that there are cases where a clear boundary between the first region and the second region cannot be observed. .

[0558] For example, in the case of CAC-OS in In-Ga-Zn oxide, energy dispersive X-ray diffraction (EDX) Optical method (EDX:Energy Dispersive X-ray spectrosc) The EDX mapping obtained using the opy revealed a region containing In as the main component (the first region). The structure has a structure in which a Ga-based region (first region) and a Ga-based region (second region) are unevenly distributed and mixed. It can be confirmed that

[0559] When CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties due to the region act complementary to each other to provide a switching function (On In other words, the CAC-OS and has a conductive function in a part of the material and an insulating function in a part of the material, and By separating the conductive function from the insulating function, Therefore, by using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching This allows for realizing a switching operation.

[0560] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductors in Two or more of AC-OS, nc-OS, and CAAC-OS may be included.

[0561] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0562] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be obtained. Furthermore, a highly reliable transistor can be realized.

[0563] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. , the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 c m -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm - 3 In order to reduce the carrier concentration of the oxide semiconductor film, The impurity concentration in the semiconductor film may be reduced to reduce the defect state density. A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. The oxide semiconductor having a low carrier concentration is preferably a high-purity intrinsic or substantially high-purity intrinsic oxide. These are sometimes called nitride semiconductors.

[0564] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0565] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. This may be the case.

[0566] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0567] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0568] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0569] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may be included. Transistors using oxide semiconductors, which are widely used in semiconductors, tend to be normally on. Therefore, the concentration of alkali metals or alkaline earth metals in oxide semiconductors obtained by SIMS Degrees, 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0570] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor becomes a semiconductor. The transistors used for the oxide semiconductors tend to be normally on. Therefore, if nitrogen is contained, trap levels may be formed. Therefore, the electrical properties of the oxide semiconductor obtained by SIMS may become unstable. The nitrogen concentration in 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following are more preferred: Kuha 5 x 10 17 atoms / cm 3 Do the following:

[0571] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, resulting in the formation of chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm3 Make it less than.

[0572] By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0573] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0574] (Embodiment 5) This embodiment mode is directed to a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, and 1 and 2 show an example of an electronic component incorporating the semiconductor device.

[0575] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 38A. .

[0576] The semiconductor wafer 4800 shown in FIG. 38A includes a wafer 4801 and a The wafer 4801 has a plurality of circuit portions 4802. The area without the circuit portion 4802 is a spacing 4803, which is an area for dicing. .

[0577] The semiconductor wafer 4800 has a plurality of circuits formed on the surface of the wafer 4801 by a previous process. The wafer 4801 can be fabricated by forming a portion 4802. The surface opposite to the surface on which the plurality of circuit portions 4802 are formed is ground to thin the wafer 4801. This process reduces warpage of the wafer 4801 and allows for miniaturization of the components. This can be achieved.

[0578] The next step is the dicing process. Scribe line SCL1 and scribe line SCL2 (dicing line or cutting line) The spacing 4803 is To facilitate the scribe process, multiple scribe lines SCL1 are arranged in parallel. The multiple scribe lines SCL2 are arranged parallel to each other, and the scribe lines SCL1 and SCL2 are arranged parallel to each other. It is preferable that the scribe line SCL2 be provided so as to be vertical.

[0579] By performing a dicing process, a chip 4800a as shown in FIG. 38B is obtained. The chip 4800a can be cut from the wafer 4800. The chip 4800a is made of a wafer 4801a and The circuit portion 4802 and the spacing 4803a are included. It is preferable that a is as small as possible. The width of the spacing 4803 between the scribe lines SCL1 and the scribe line SCL2 is It should be approximately the same length as the cutting allowance of Eveline SCL2.

[0580] The shape of the element substrate according to one embodiment of the present invention is the same as that of the semiconductor wafer 4800 shown in FIG. 38A. ...

Claims

1. The device includes a control circuit, a product-sum operation circuit, a function circuit, a plurality of registers, and a storage unit, the control circuit is electrically connected to the product-sum operation circuit; the product-sum operation circuit is electrically connected to the storage unit via the function circuit; the storage unit is electrically connected to the product-sum operation circuit via the plurality of registers; The function circuit is a semiconductor device having a function of outputting a value of an activation function using the result of the product-sum operation output from the product-sum operation circuit.

2. The device includes a control circuit, a product-sum operation circuit, a function circuit, a plurality of registers, and a storage unit, the control circuit is electrically connected to the product-sum operation circuit; the sum-of-products operation circuit includes an operation circuit, a first programmable switch, and a second programmable switch; the arithmetic circuit is electrically connected to the first programmable switch; the arithmetic circuit is electrically connected to the second programmable switch; the first programmable switch is electrically connected to the storage unit via the function circuit; the storage unit is electrically connected to the second programmable switch via the plurality of registers; The function circuit is a semiconductor device having a function of outputting a value of an activation function using the result of the product-sum operation output from the product-sum operation circuit.

Images