Semiconductor module

Abstract

To provide a semiconductor module having a module structure preferable for performance improvement and miniaturization.SOLUTION: A semiconductor element module A1 includes a conductive substrate, semiconductor elements, control terminals 45, and a sealing synthetic resin 8. The conductive substrate has a main surface and a back surface spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the main surface and has a switching function. The control terminal 45 controls the semiconductor element. The sealing resin 8 has a resin obverse face 81 and a resin reverse face, and covers the conductive substrate, the semiconductor elements, and part of the control terminals 45. The control terminals 45 protrude from the resin main surface 81 and extend in the thickness direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] Conventionally, semiconductor modules equipped with power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor modules are installed in a wide variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in Patent Document 1 includes a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and conductor layers stacked on both sides of the base material. The base material is made of, for example, ceramic. Each conductor layer is made of, for example, Cu (copper), and a semiconductor element is bonded to one of the conductor layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-220382 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a demand for electronic devices to be more energy-efficient, perform better, and be more compact. To achieve this, it is necessary to improve the performance and reduce the size of the semiconductor modules installed in the electronic devices.

[0005] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a semiconductor module having a module structure that is favorable for improving performance and miniaturization. [Means for solving the problem]

[0006] The semiconductor module of the present disclosure includes a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing the opposite side from the main surface, a semiconductor element electrically connected to the main surface and having a switching function, a control terminal for controlling the semiconductor element, and a sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side from the resin main surface, the sealing resin covering the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin main surface and extends along the thickness direction. [Effects of the Invention]

[0007] According to the above-described configuration, it is possible to provide a semiconductor module structure that is preferable for improving performance and miniaturization, for example. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view of a semiconductor module according to a first embodiment. [Figure 2] 2 is a perspective view of FIG. 1 in which the sealing resin, the resin portion, and the resin filling portion are omitted. [Figure 3] FIG. 3 is a perspective view of FIG. 2 in which the conductive member is omitted. [Figure 4] FIG. 1 is a plan view showing a semiconductor module according to a first embodiment. [Figure 5] 5 is a plan view of FIG. 4 in which the sealing resin, the resin portion, and the resin filling portion are indicated by imaginary lines. [Figure 6] FIG. 6 is a partially enlarged view of a part of FIG. 5, in which imaginary lines for the sealing resin, the resin portion, and the resin filling portion are omitted. [Figure 7] FIG. 7 is a partially enlarged view of a part of FIG. 6. [Figure 8] 6 is a plan view of FIG. 5, in which a part of the conductive member is shown by an imaginary line. [Figure 9] FIG. 1 is a front view showing a semiconductor module according to a first embodiment. [Figure 10] FIG. 2 is a bottom view showing the semiconductor module according to the first embodiment. [Figure 11] FIG. 1 is a left side view showing a semiconductor module according to a first embodiment. [Figure 12] FIG. 2 is a right side view showing the semiconductor module according to the first embodiment. [Figure 13] FIG. 6 is a cross-sectional view taken along line XIII-XIII in FIG. 5. [Figure 14] FIG. 6 is a cross-sectional view taken along line XIV-XIV in FIG. 5. [Figure 15] FIG. 15 is a partially enlarged view of a part of FIG. [Figure 16] FIG. 6 is a cross-sectional view taken along line XVI-XVI in FIG. 5. [Figure 17] FIG. 6 is a cross-sectional view taken along line XVII-XVII in FIG. 5. [Figure 18] FIG. 6 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. [Figure 19] FIG. 6 is a cross-sectional view taken along line XIX-XIX in FIG. 5. [Figure 20] 2 is an example of a circuit configuration of a semiconductor module according to a first embodiment. [Figure 21] FIG. 2 is a plan view showing a step of the method for manufacturing the semiconductor module according to the first embodiment. [Figure 22] 2 is a cross-sectional view schematically illustrating a step of a method for manufacturing the semiconductor module according to the first embodiment. FIG. [Figure 23] FIG. 2 is a plan view showing a step of the method for manufacturing the semiconductor module according to the first embodiment. [Figure 24] 14 is a cross-sectional end view showing one step of the manufacturing method according to the first embodiment, corresponding to the cross section shown in FIG. 13. FIG. [Figure 25]14 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 13. [Figure 26] 15 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Figure 27] 15 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Figure 28] 14 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 13. [Figure 29] 15 is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to an enlarged view of a part of the cross section shown in FIG. 14. [Figure 30] FIG. 10 is a front view of a semiconductor module according to a second embodiment. [Figure 31] FIG. 10 is a right side view showing a semiconductor module according to a second embodiment. [Figure 32] 19 is a cross-sectional view similar to FIG. 18, showing a semiconductor module according to a second embodiment. [Figure 33] FIG. 10 is a front view of a semiconductor module according to a third embodiment. [Figure 34] FIG. 10 is a right side view showing a semiconductor module according to a third embodiment. [Figure 35] 19 is a cross-sectional view similar to FIG. 18, showing a semiconductor module according to a third embodiment. [Figure 36] FIG. 10 is a perspective view of a semiconductor module according to a fourth embodiment. [Figure 37] FIG. 10 is a right side view showing a semiconductor module according to a fourth embodiment. [Figure 38] 10 is a plan view similar to FIG. 5, showing a semiconductor module according to a fifth embodiment. [Figure 39]FIG. 39 is a partially enlarged view of a part of FIG. 38, in which imaginary lines for the sealing resin, the resin portion, and the resin filling portion are omitted. [Figure 40] FIG. 40 is a partially enlarged view of a part of FIG. 39. [Figure 41] 10 is a plan view similar to FIG. 5, showing a semiconductor module according to a sixth embodiment. [Figure 42] FIG. 42 is a cross-sectional view taken along line XLII-XLII in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the semiconductor module of the present disclosure will be described below with reference to the drawings. In the following description, identical or similar components will be designated by the same reference numerals and redundant description will be omitted.

[0010] 1 to 20 show a semiconductor module A1 according to the first embodiment. The semiconductor module A1 includes a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conductive member 6, a first conductive bonding material 71, a second conductive bonding material 72, a plurality of wires 731 to 735, a sealing resin 8, a resin portion 87, and a resin filling portion 88.

[0011] FIG. 1 is a perspective view of a semiconductor module A1. FIG. 2 is a perspective view of FIG. 1 in which the sealing resin 8, the resin portion 87, and the resin filling portion 88 are omitted. FIG. 3 is a perspective view of FIG. 2 in which the conductive member 6 is omitted. FIG. 4 is a plan view of the semiconductor module A1. FIG. 5 is a diagram in which the sealing resin 8, the resin portion 87, and the resin filling portion 88 are shown by imaginary lines in the plan view of FIG. 4. FIG. 6 is a partial enlarged view of FIG. 5. In FIG. 6, the imaginary lines of the sealing resin 8, the resin portion 87, and the resin filling portion 88 are omitted. FIG. 7 is a partial enlarged view of FIG. 6. FIG. 8 is a diagram in which a part of the conductive member 6 (a second conductive member 62 described later) is shown by imaginary lines in the plan view of FIG. 5. FIG. 9 is a front view of the semiconductor module A1. FIG. 10 is a bottom view of the semiconductor module A1. FIG. 11 is a left side view of the semiconductor module A1. FIG. 12 is a right side view of the semiconductor module A1. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 5. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 5. FIG. 15 is a partially enlarged view of FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 5. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 5. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 5. Note that multiple wires 731 to 735 are omitted in FIGS. 2, 3, 7, 14, and 18. FIG. 20 shows an example of a circuit configuration of a semiconductor module A1. In the circuit diagram of FIG. 20, only one each of multiple first semiconductor elements 10A (described below) and multiple second semiconductor elements 10B (described below) is shown, and the other first semiconductor elements 10A and the other second semiconductor elements 10B are omitted.

[0012] For convenience of explanation, three mutually perpendicular directions, namely, the x direction, the y direction, and the z direction, will be referred to. As an example, the z direction is the thickness direction of the semiconductor module A1. The x direction is the left-right direction in the plan view of the semiconductor module A1 (see FIG. 4). The y direction is the up-down direction in the plan view of the semiconductor module A1 (see FIG. 4). One of the x directions is the x1 direction, and the other of the x directions is the x2 direction. Similarly, one of the y directions is the y1 direction, the other of the y directions is the y2 direction, one of the z directions is the z1 direction, and the other of the z directions is the z2 direction. In the following explanation, "plan view" refers to the view in the z direction. The z direction is an example of a "thickness direction," the x direction is an example of a "first direction," and the y direction is an example of a "second direction."

[0013] Each of the multiple semiconductor elements 10 is the functional core of the semiconductor module A1. The constituent material of each semiconductor element 10 is a semiconductor material primarily composed of, for example, SiC (silicon carbide). This semiconductor material is not limited to SiC, but may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. Each semiconductor element 10 has a switching function unit Q1 (see FIG. 20 ) configured, for example, by a MOSFET (metal-oxide-semiconductor field-effect transistor). The switching function unit Q1 is not limited to a MOSFET, but may be other transistors such as a field-effect transistor including a MISFET (metal-insulator-semiconductor FET) or a bipolar transistor such as an IGBT. Each semiconductor element 10 is the same element. Each semiconductor element 10 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0014] 15, each semiconductor element 10 has an element main surface 101 and an element back surface 102. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are spaced apart in the z direction. The element main surface 101 faces the z2 direction, and the element back surface 102 faces the z1 direction.

[0015] The multiple semiconductor elements 10 include multiple first semiconductor elements 10A and multiple second semiconductor elements 10B. In this embodiment, the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B. However, the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this configuration and may be changed as appropriate depending on the performance required of the semiconductor module A1. In the example of FIG. 8, three first semiconductor elements 10A and three second semiconductor elements 10B are disposed. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be one, two, or four or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B is determined by the current capacity handled by the semiconductor module A1.

[0016] As shown in Fig. 20, the semiconductor module A1 is configured as, for example, a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A configure an upper arm circuit of the semiconductor module A1, and a plurality of second semiconductor elements 10B configure a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to configure a bridge layer.

[0017] As shown in FIGS. 8 and 16, each of the multiple first semiconductor elements 10A is mounted on a conductive substrate 2. In the example shown in FIG. 8, the multiple first semiconductor elements 10A are lined up, for example, in the y direction and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the conductive substrate 2 (a first conductive portion 2A described below) via a second conductive bonding material 72. When each first semiconductor element 10A is bonded to the first conductive portion 2A, the element back surface 102 faces the first conductive portion 2A.

[0018] As shown in FIGS. 8 and 17, the multiple second semiconductor elements 10B are mounted on the conductive substrate 2. In the example shown in FIG. 8, the multiple second semiconductor elements 10B are lined up, for example, in the y direction and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the conductive substrate 2 (a second conductive portion 2B described below) via a second conductive bonding material 72. When each second semiconductor element 10B is bonded to the second conductive portion 2B, the element back surface 102 faces the second conductive portion 2B. As can be seen from FIG. 8, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the x direction, but they do not have to overlap.

[0019] Each of the multiple semiconductor elements 10 (multiple first semiconductor elements 10A and multiple second semiconductor elements 10B) has a first principal surface electrode 11, a second principal surface electrode 12, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15 described below are common to all semiconductor elements 10. The first principal surface electrode 11 and the second principal surface electrode 12 are provided on the element principal surface 101. The first principal surface electrode 11 and the second principal surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0020] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the semiconductor element 10 is input. In each semiconductor element 10, the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the back surface 102 of the element. The back surface electrode 15 is, for example, formed by Ag plating.

[0021] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode) by the switching function unit Q1, each semiconductor element 10 switches between a conductive state and a cutoff state in response to the drive signal. This operation of switching between the conductive state and the cutoff state is called a switching operation. In the conductive state, a current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the cutoff state, this current does not flow. That is, each semiconductor element 10 performs a switching operation by the switching function unit Q1. In the semiconductor module A1, the switching function units Q1 of the multiple semiconductor elements 10 convert a first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42 and 43 into, for example, a second power supply voltage (AC voltage), and output the second power supply voltage from the output terminal 44. The input terminals 41 to 43 and the output terminal 44 are all power supply terminals that handle power supply voltages. The input terminals 41 to 43 are first power supply terminals to which a first power supply voltage is input, and the output terminal 44 is a second power supply terminal that outputs a second power supply voltage.

[0022] Some of the semiconductor elements 10 (two in the example shown in FIG. 8) further include a diode function unit D1 (see FIG. 20) in addition to the switching function unit Q1. In the semiconductor module A1, one of the first semiconductor elements 10A (the first semiconductor element 10A arranged furthest in the y2 direction in FIG. 8) and one of the second semiconductor elements 10B (the second semiconductor element 10B arranged furthest in the y1 direction in FIG. 8) include the diode function unit D1 in addition to the switching function unit Q1. The function or role of the diode function unit D1 is not particularly limited, but may be, for example, a temperature detection diode. The diode D2 shown in FIG. 20 is, for example, a parasitic diode component of the switching function unit Q1.

[0023] 8 , the semiconductor element 10 having the diode functional unit D1 further includes a third principal surface electrode 13, a fourth principal surface electrode 14, and a fifth principal surface electrode 16 in addition to the first principal surface electrode 11, the second principal surface electrode 12, and the back surface electrode 15. The configurations of the third principal surface electrode 13, the fourth principal surface electrode 14, and the fifth principal surface electrode 16, which will be described below, are common to all semiconductor elements 10 having the diode functional unit D1. The third principal surface electrode 13, the fourth principal surface electrode 14, and the fifth principal surface electrode 16 are formed on the element principal surface 101. In the semiconductor element 10 having the diode functional unit D1, the third principal surface electrode 13 and the fourth principal surface electrode 14 are electrically connected to the diode functional unit D1. The fifth principal surface electrode 16 is, for example, a source sense electrode through which a source current in the switching functional unit Q1 flows.

[0024] As shown in FIG. 7 , each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. While FIG. 7 shows the first semiconductor element 10A arranged at the center in the y direction among the multiple first semiconductor elements 10A aligned in the y direction, the other first semiconductor elements 10A also have a first side 191, a second side 192, a third side 193, and a fourth side 194. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in a plan view, and the second side 192 is an edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in a plan view, and the fourth side 194 is an edge on the y1 direction side in a plan view. Because each first semiconductor element 10A has a rectangular shape in a plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 form approximately right angles in a plan view. As shown in Fig. 7, the four corners do not overlap with the conductive members 6 (first conductive members 61 and second conductive members 62 described below) in a plan view. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0025] The conductive substrate 2 is also called a lead frame. The conductive substrate 2 supports a plurality of semiconductor elements 10. The conductive substrate 2 is bonded onto a support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 has, for example, a rectangular shape in a plan view. The conductive substrate 2, together with the conductive member 6, constitutes a path for a main circuit current that is switched by the plurality of semiconductor elements 10.

[0026] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-shaped member made of metal. This metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B, together with the plurality of input terminals 41 to 43 and the plurality of output terminals 44, form a conductive path to the plurality of semiconductor elements 10. As shown in FIGS. 13 to 18, the first conductive portion 2A and the second conductive portion 2B are each bonded to the support substrate 3 via a first conductive bonding material 71. A plurality of first semiconductor elements 10A are each bonded to the first conductive portion 2A via a second conductive bonding material 72. A plurality of second semiconductor elements 10B are each bonded to the second conductive portion 2B via a second conductive bonding material 72. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x-direction as shown in FIGS. 3, 8, 13, and 14. In the examples shown in these figures, the first conductive portion 2A is positioned further in the x2 direction than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each, for example, rectangular in plan view. The first conductive portion 2A and the second conductive portion 2B overlap when viewed in the x direction. The first conductive portion 2A and the second conductive portion 2B each have, for example, an x-direction dimension of 15 mm to 25 mm (preferably about 20 mm), a y-direction dimension of 30 mm to 40 mm (preferably about 35 mm), and a z-direction dimension of 1.5 mm to 3.0 mm (preferably about 2.0 mm).

[0027] The conductive substrate 2 has a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 are spaced apart in the z direction, as shown in FIGS. 13, 14, and 16 to 18. The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The main surface 201 is formed by combining the upper surfaces of the first conductive portion 2A and the second conductive portion 2B. The back surface 202 is formed by combining the lower surfaces of the first conductive portion 2A and the second conductive portion 2B. The back surface 202 is bonded to the support substrate 3 so as to face the support substrate 3. As shown in FIGS. 5, 8, and 13, a plurality of recesses 201a are formed in the main surface 201. Each recess 201a is a portion recessed from the main surface 201 in the z direction. The recess depth of each recess 201a is, for example, greater than 0 μm and not greater than 100 μm. Each recess 201a is formed, for example, during molding, which will be described later. The multiple recesses 201a include those formed on the main surface 201 of the first conductive portion 2A and those formed on the main surface 201 of the second conductive portion 2B. The two recesses 201a formed on the main surface 201 of the first conductive portion 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recesses 201a formed on the main surface 201 of the second conductive portion 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0028] The conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base material 21, a main surface bonding layer 22, and a back surface bonding layer 23, which are stacked on top of each other. The base material 21 is a plate-shaped member made of metal. This metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is a surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 corresponds to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, Ag plated. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is a surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 corresponds to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is, for example, Ag plated, like the main surface bonding layer 22.

[0029] The support substrate 3 supports the conductive substrate 2. The support substrate 3 is formed of, for example, a DBC (Direct Bonded Copper) substrate. The support substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0030] The insulating layer 31 is made of, for example, ceramics with excellent thermal conductivity. An example of such ceramics is AlN (aluminum nitride). The insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The insulating layer 31 has, for example, a rectangular shape in a plan view.

[0031] The first metal layer 32 is formed on the upper surface (surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may include Al instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are spaced apart in the x direction. The first portion 32A is located on the x2 direction side of the second portion 32B. The first conductive portion 2A is joined to the first portion 32A and supports the first conductive portion 2A. The second portion 32B is joined to the second conductive portion 2B and supports the second conductive portion 2B. The first portion 32A and the second portion 32B are each, for example, rectangular in plan view.

[0032] The first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first portion 32A and the second portion 32B). The first bonding layer 321 is, for example, Ag plating. The first bonding layer 321 is provided to improve bonding with the first conductive bonding material 71 by solid-state diffusion.

[0033] The second metal layer 33 is formed on the lower surface (surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as the constituent material of the first metal layer 32. In the example shown in FIG. 10, the lower surface of the second metal layer 33 (bottom surface 302 described below) is exposed from the sealing resin 8, for example. The lower surface may not be exposed from the sealing resin 8, but may be covered by the sealing resin 8. In a plan view, the second metal layer 33 overlaps both the first portion 32A and the second portion 32B.

[0034] As shown in FIGS. 13 to 18, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces the z2 direction, and the bottom surface 302 faces the z1 direction. As shown in FIG. 10, the bottom surface 302 is exposed from the sealing resin 8. The support surface 301 is the upper surface of the first bonding layer 321, and is formed by combining the upper surfaces of the first portion 32A and the second portion 32B. The support surface 301 faces the conductive substrate 2, and the conductive substrate 2 is bonded to the support surface 301. The bottom surface 302 is the lower surface of the second metal layer 33. A heat dissipation member (e.g., a heat sink) (not shown) can be attached to the bottom surface 302. The dimension of the support substrate 3 in the z direction (the distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0035] The plurality of input terminals 41 to 43 and the plurality of output terminals 44 are each made of a plate-shaped metal plate. The metal plate is made of, for example, Cu or a Cu alloy. In the example shown in FIGS. 1 to 5, 8, and 10, the semiconductor module A1 has three input terminals 41 to 43 and two output terminals 44.

[0036] A power supply voltage is applied between the three input terminals 41 to 43. In this embodiment, the input terminal 41 is a positive terminal (P terminal), and the two input terminals 42 and 43 are each a negative terminal (N terminal). Alternatively, the input terminal 41 may be a negative terminal (N terminal), and the two input terminals 42 and 43 may each be a positive terminal (P terminal). In this case, the wiring inside the package may be changed appropriately in accordance with the change in terminal polarity. Each of the three input terminals 41 to 43 and the two output terminals 44 includes a portion covered by the sealing resin 8 and a portion exposed from the resin side surface of the sealing resin 8.

[0037] As shown in FIG. 14, the input terminal 41 is formed integrally with the first conductive portion 2A. Unlike this configuration, the input terminal 41 may be separated from the first conductive portion 2A and conductively joined to the first conductive portion 2A. As shown in FIG. 8 and other figures, the input terminal 41 is located on the x2 direction side with respect to the multiple first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The input terminal 41 is electrically connected to the first conductive portion 2A and is also electrically connected to the back electrode 15 (drain electrode) of each first semiconductor element 10A via the first conductive portion 2A. The input terminal 41 is an example of a "first input terminal."

[0038] The input terminal 41 has an input-side bonding surface 411 and an input-side side surface 412. The input-side bonding surface 411 faces the z2 direction and extends toward the x2 direction. The input-side side surface 412 is located on the periphery of the input-side bonding surface 411 when viewed in the z direction and faces a direction intersecting the input-side bonding surface 411. In this embodiment, the input-side side surface 412 includes a tip surface 413 and a pair of side surfaces 414. The tip surface 413 is located at the x2-direction end of the input terminal 41 and faces the x2 direction. The pair of side surfaces 414 are located at both ends of the input terminal 41 in the y direction and face the y1 and y2 directions. At least one of the tip surface 413 and the pair of side surfaces 414 of the input-side side surface 412 has an input-side processing mark. The input-side processing mark is formed by cutting the lead frame, which will be described later.

[0039] As shown in FIG. 8, the two input terminals 42, 43 are each spaced apart from the first conductive portion 2A. A second conductive member 62 is joined to each of the two input terminals 42, 43. As shown in FIG. 8 and other figures, each of the two input terminals 42, 43 is located on the x2 direction side with respect to the multiple first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). Each of the two input terminals 42, 43 is electrically connected to the second conductive member 62 and is electrically connected to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B via the second conductive member 62. The input terminal 42 is an example of a "second input terminal," and the input terminal 43 is an example of a "third input terminal."

[0040] The input terminals 42 and 43 have input-side bonding surfaces 421 and 431 and input-side side surfaces 422 and 432. The input-side bonding surfaces 421 and 431 face the z2 direction and extend toward the x2 direction. The input-side side surfaces 422 and 432 are located on the periphery of the input-side bonding surfaces 421 and 431 when viewed in the z direction and face a direction intersecting the input-side bonding surfaces 421 and 431. In this embodiment, the input-side side surface 422 includes a tip surface 423 and a pair of side surfaces 424. The tip surface 423 is located at the x2-direction end of the input terminal 42 and faces the x2 direction. The pair of side surfaces 424 are located at both ends of the input terminal 42 in the y direction and face the y1 and y2 directions. At least one of the tip surface 423 and the pair of side surfaces 424 of the input-side side surface 422 has input-side processing marks. The input-side processing marks are formed by cutting the lead frame, as described below. The input-side side surface 432 includes a tip surface 433 and a pair of side surfaces 434. The tip surface 433 is located at the x2-direction side end of the input terminal 43 and faces the x2 direction. The pair of side surfaces 434 are located at both ends of the input terminal 43 in the y direction and face the y1 and y2 directions. At least one of the tip surface 433 and the pair of side surfaces 434 of the input-side side surface 432 has an input-side processing mark. The input-side processing mark is formed by cutting the lead frame, which will be described later.

[0041] As shown in Figures 1 to 5, 8, and 10, the three input terminals 41 to 43 each protrude in the x2 direction from the sealing resin 8 in the semiconductor module A1. The three input terminals 41 to 43 are spaced apart from one another. The two input terminals 42 and 43 are located on opposite sides of the input terminal 41 in the y direction. The input terminal 42 is located on the y2-direction side of the input terminal 41, and the input terminal 43 is located on the y1-direction side of the input terminal 41. The three input terminals 41 to 43 overlap one another when viewed in the y direction.

[0042] As can be seen from FIGS. 8 and 14, the two output terminals 44 are each formed integrally with the second conductive portion 2B. Unlike this configuration, the output terminal 44 may be separated from the second conductive portion 2B and conductively joined to the second conductive portion 2B. As shown in FIG. 8 and other figures, the two output terminals 44 are each located on the x1 direction side with respect to the multiple second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2). Each output terminal 44 is electrically connected to the second conductive portion 2B and, via the second conductive portion 2B, to the back surface electrode 15 (drain electrode) of each second semiconductor element 10B. The two output terminals 44 are each an example of a "first output terminal" and a "second output terminal."

[0043] The output terminal 44 has an output-side bonding surface 441 and an output-side side surface 442. The output-side bonding surface 441 faces the z2 direction and extends toward the x1 direction. The output-side side surface 442 is located on the periphery of the output-side bonding surface 441 when viewed in the z direction and faces a direction intersecting the output-side bonding surface 441. In this embodiment, the output-side side surface 442 includes a tip surface 443 and a pair of side surfaces 444. The tip surface 443 is located at the end of the output terminal 44 in the x1 direction and faces the x1 direction. The pair of side surfaces 444 are located at both ends of the output terminal 44 in the y direction and face the y1 and y2 directions. At least one of the tip surface 443 and the pair of side surfaces 444 of the output-side side surface 442 has an output-side processing mark. The output-side processing mark is formed by cutting the lead frame, which will be described later. The number of output terminals 44 is not limited to two, and may be, for example, one, or three or more. For example, when there is one output terminal 44, it is desirable that it be connected to the center portion in the y direction of second conductive part 2B.

[0044] Each of the plurality of control terminals 45 is a pin-shaped terminal for controlling one of the semiconductor elements 10. The plurality of control terminals 45 includes a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D. The plurality of first control terminals 46A to 46E are used to control the respective first semiconductor elements 10A. The plurality of second control terminals 47A to 47D are used to control the respective second semiconductor elements 10B.

[0045] The multiple first control terminals 46A-46E are arranged at intervals in the y direction. As shown in Figures 8 and 14, each of the first control terminals 46A-46E is supported by the first conductive portion 2A via the control terminal support body 5 (a first support portion 5A described below). As shown in Figures 5 and 8, each of the first control terminals 46A-46E is located in the x direction between the multiple first semiconductor elements 10A and the three input terminals 41-43.

[0046] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal for the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0047] The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the multiple first semiconductor elements 10 A. The first control terminal 46B detects a voltage (voltage corresponding to a source current) applied to each second principal surface electrode 12 (source electrode) of the multiple first semiconductor elements 10 A.

[0048] The first control terminal 46C and the first control terminal 46D are terminals that are electrically connected to the diode functional portion D1. The first control terminal 46C is electrically connected to the third principal surface electrode 13 of the first semiconductor element 10A that has the diode functional portion D1, and the first control terminal 46D is electrically connected to the fourth principal surface electrode 14 of the first semiconductor element 10A that has the diode functional portion D1.

[0049] The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back surface electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0050] The second control terminals 47A to 47D are spaced apart in the y direction. As shown in FIGS. 5 and 18, each of the second control terminals 47A to 47D is supported by the second conductive portion 2B via the control terminal support body 5 (a second support portion 5B described below). As shown in FIGS. 5 and 8, each of the second control terminals 47A to 47D is located between the second semiconductor elements 10B and two output terminals 44 in the x direction.

[0051] Each of the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) includes a holder 451 and a metal pin 452.

[0052] Holder 451 is made of a conductive material. As shown in FIG. 15 , holder 451 is bonded to control terminal support 5 (first metal layer 52 described below) via conductive bonding material 459. Holder 451 includes a cylindrical portion, an upper flange, and a lower flange. The upper flange is connected to the upper part of the cylindrical portion, and the lower flange is connected to the lower part of the cylindrical portion. A metal pin 452 is inserted through at least the upper flange and the cylindrical portion of holder 451. The upper surface of the upper flange is exposed from sealing resin 8 (second protrusion 852 described below) and is covered with resin portion 87.

[0053] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the control terminal support body 5 (a first metal layer 52 described later) at least via the holder 451. As in the example shown in FIG. 15 , when the lower end (the end on the z1 direction side) of the metal pin 452 is in contact with the conductive bonding material 459 inside the insertion hole of the holder 451, the metal pin 452 is electrically connected to the control terminal support body 5 via the conductive bonding material 459.

[0054] The control terminal support body 5 supports a plurality of control terminals 45. The control terminal support body 5 is interposed between the main surface 201 (conductive substrate 2) and the plurality of control terminals 45.

[0055] The control terminal support member 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is disposed on the first conductive portion 2A of the conductive substrate 2 and supports a plurality of first control terminals 46A to 46E among the plurality of control terminals 45. As shown in FIG. 15 , the first support portion 5A is bonded to the first conductive portion 2A via a bonding material 59. The bonding material 59 may be conductive or insulating, and is, for example, solder. The second support portion 5B is disposed on the second conductive portion 2B of the conductive substrate 2 and supports a plurality of second control terminals 47A to 47D among the plurality of control terminals 45. The second support portion 5B is bonded to the second conductive portion 2B via the bonding material 59.

[0056] The control terminal support body 5 (each of the first support portion 5A and the second support portion 5B) is made of, for example, a DBC substrate. The control terminal support body 5 has an insulating layer 51, a first metal layer 52, and a second metal layer 53 stacked on top of each other.

[0057] The insulating layer 51 is made of, for example, ceramics and has, for example, a rectangular shape in plan view.

[0058] As shown in FIG. 15 and other figures, first metal layer 52 is formed on the upper surface of insulating layer 51. Each control terminal 45 is provided upright on first metal layer 52. First metal layer 52 is made of, for example, Cu or a Cu alloy. As shown in FIG. 8 and other figures, first metal layer 52 includes first portion 521, second portion 522, third portion 523, fourth portion 524, and fifth portion 525. First portion 521, second portion 522, third portion 523, fourth portion 524, and fifth portion 525 are spaced apart and insulated from one another.

[0059] A plurality of wires 731 are joined to the first portion 521, and the first portion 521 is electrically connected to the first principal surface electrode 11 (gate electrode) of each semiconductor element 10 via each wire 731. As shown in Fig. 8, a first control terminal 46A is joined to the first portion 521 of the first support portion 5A, and a second control terminal 47A is joined to the first portion 521 of the second support portion 5B.

[0060] A plurality of wires 732 are joined to the second portion 522, and the second portion 522 is electrically connected to the second principal surface electrode 12 (source electrode) of each semiconductor element 10 via each wire 732. As shown in Fig. 8, a first control terminal 46B is joined to the second portion 522 of the first support portion 5A, and a second control terminal 47B is joined to the second portion 522 of the second support portion 5B.

[0061] A wire 733 is joined to the third portion 523, and the third portion 523 is electrically connected to the third principal surface electrode 13 of the semiconductor element 10 having the diode functional portion D1 via the wire 733. As shown in Fig. 8, a first control terminal 46C is joined to the third portion 523 of the first support portion 5A, and a second control terminal 47C is joined to the third portion 523 of the second support portion 5B.

[0062] A wire 734 is joined to the fourth portion 524, and the fourth portion 524 is electrically connected to the fourth principal surface electrode 14 of the semiconductor element 10 having the diode functional portion D1 via the wire 734. As shown in Fig. 8, a first control terminal 46D is joined to the fourth portion 524 of the first support portion 5A, and a second control terminal 47D is joined to the fourth portion 524 of the second support portion 5B.

[0063] Wire 735 is joined to fifth portion 525 of first support portion 5A, and is electrically connected to first conductive portion 2A via wire 735. Fifth portion 525 of second support portion 5B is not electrically connected to other components. As shown in Fig. 8, first control terminal 46E is joined to fifth portion 525 of first support portion 5A.

[0064] 15 and other figures, the second metal layer 53 is formed on the lower surface of the insulating layer 51. The second metal layer 53 of the first support portion 5A is joined to the first conductive portion 2A via a bonding material 59, as shown in Fig. 15. The second metal layer 53 of the second support portion 5B is joined to the second conductive portion 2B via a bonding material 59.

[0065] The conductive member 6, together with the conductive substrate 2, constitutes a path for a main circuit current switched by the plurality of semiconductor elements 10. The conductive member 6 is spaced apart from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps the main surface 201 in a plan view. In this embodiment, the conductive member 6 is made of a metal plate material. The metal is, for example, Cu or a Cu alloy. Specifically, the conductive member 6 is a folded metal plate material. However, the conductive member 6 may also be made of a metal foil material. In this embodiment, the conductive member 6 includes a plurality of first conductive members 61 and second conductive members 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is a current that flows between the input terminal 41 and the output terminal 44. The second main circuit current is a current that flows between the output terminal 44 and the input terminals 42 and 43.

[0066] Each of the multiple first conductive members 61 is bonded to the second principal surface electrode 12 (source electrode) and the second conductive portion 2B of each first semiconductor element 10A, thereby electrically connecting the second principal surface electrode 12 and the second conductive portion 2B of each first semiconductor element 10A. Each first conductive member 61 is bonded to the second principal surface electrode 12 (see FIG. 8 ) of each first semiconductor element 10A, and each first conductive member 61 is bonded to the second conductive portion 2B via a conductive bonding material 69. The conductive bonding material 69 is, for example, solder, a metal paste material, or a sintered metal. As shown in FIG. 8 , each first conductive member 61 has a strip shape extending along the x direction in a plan view.

[0067] In this embodiment, as shown in FIG. 6 and other figures, an opening 61h is formed in each first conductive member 61 in a rectangular portion connecting each first semiconductor element 10A and the second conductive portion 2B. The opening 61h is preferably formed in the center of the rectangle in a plan view and is, for example, a through-hole penetrating in the z direction. The opening 61h is formed to facilitate the flow of resin material between the upper side (z2 direction side) and the lower side (z1 direction side) near each first conductive member 61 when injecting a fluid resin material to form the sealing resin. The planar shape of the opening 61h may be a perfect circle, or may be another shape such as an ellipse or a rectangle. The shape of the first conductive member 61 is not limited to this configuration; for example, the opening 61h may not be formed.

[0068] In this embodiment, three first conductive members 61 are provided corresponding to the number of first semiconductor elements 10A. As a modified example, one first conductive member 61 may be used that is common to the multiple first semiconductor elements 10A, regardless of the number of the multiple first semiconductor elements 10A.

[0069] The second conductive member 62 electrically connects the second main surface electrodes 12 of each second semiconductor element 10B to the input terminals 42, 43. The second conductive member 62 has a maximum dimension in the x direction of, for example, 25 mm to 40 mm (preferably, approximately 32 mm) and a maximum dimension in the y direction of, for example, 30 mm to 45 mm (preferably, approximately 38 mm). As shown in FIG. 6 , the second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624.

[0070] The first wiring portion 621 is connected to the input terminal 42. The first wiring portion 621 and the input terminal 42 are joined by a conductive bonding material 69. The first wiring portion 621 is a strip-shaped portion extending in the x-direction in a plan view.

[0071] The second wiring portion 622 is connected to the input terminal 43. The second wiring portion 622 and the input terminal 43 are joined by a conductive bonding material 69. The second wiring portion 622 is a strip-shaped portion extending in the x direction in a plan view. The first wiring portion 621 and the second wiring portion 622 are spaced apart in the y direction and arranged substantially parallel to each other. The second wiring portion 622 is positioned in the y1 direction relative to the first wiring portion 621.

[0072] The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622. The third wiring portion 623 is a strip-shaped portion extending in the y direction in a plan view. As can be seen from FIG. 6, the third wiring portion 623 overlaps multiple second semiconductor elements 10B in a plan view. The third wiring portion 623 is connected to each second semiconductor element 10B as shown in FIG. 17. The third wiring portion 623 has multiple recessed regions 623a. As shown in FIG. 17, each recessed region 623a protrudes in the z1 direction further than other portions of the third wiring portion 623. Each recessed region 623a of the third wiring portion 623 is bonded to each second semiconductor element 10B. Each recessed region 623a of the third wiring portion 623 is bonded to the second semiconductor element 10B (see FIG. 8) of each second semiconductor element 10B via a conductive bonding material 69.

[0073] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is also connected to the third wiring portion 623. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623. As can be seen from FIG. 6, the fourth wiring portion 624 overlaps with the multiple first semiconductor elements 10A in plan view. The fourth wiring portion 624 includes a first strip portion 625 and multiple second strip portions 626.

[0074] The first strip portion 625 is spaced apart from the third wiring portion 623 in the x direction and is a strip-shaped portion of the fourth wiring portion 624 in a plan view. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. The first strip portion 625 overlaps multiple first semiconductor elements 10A in a plan view. The first strip portion 625 has multiple convex regions 625a. As shown in FIG. 16, each convex region 625a protrudes in the z2 direction more than other portions of the first strip portion 625. As shown in FIG. 6, each convex region 625a overlaps a corresponding first semiconductor element 10A in a plan view. Since the first strip portion 625 has multiple convex regions 625a, regions to which each first conductive member 61 is bonded are provided on each first semiconductor element 10A, as shown in FIG. 16. This prevents the first strip portion 625 from coming into contact with each of the first conductive members 61.

[0075] Each of the multiple second strip-shaped portions 626 is connected to the first strip-shaped portion 625 and the third wiring portion 623. Each second strip-shaped portion 626 is strip-shaped extending in the x direction in a plan view. The multiple second strip-shaped portions 626 are spaced apart in the y direction and arranged substantially parallel to each other. In a plan view, each of the multiple second strip-shaped portions 626 has one end connected to a pair of first semiconductor elements 10A adjacent to each other in the y direction in the first strip-shaped portion 625, and the other end connected to a pair of second semiconductor elements 10B adjacent to each other in the y direction in the third wiring portion 623.

[0076] The first strip portion 625 has a first edge 627 and a second edge 628. As shown in FIG. 7, the first edge 627 is located further in the x1 direction than the first side 191 in a plan view, and extends in the y direction from at least the third side 193 to the fourth side 194. As a result, in a plan view, two corners 171, 172 on the x2 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. The two corners are the angle 171 between the first side 191 and the third side 193, and the angle 172 between the first side 191 and the fourth side 194. Therefore, in each first semiconductor element 10A, a portion of each of the two sides sandwiching the corners 171, 172 is visible in a plan view (more specifically, when viewed as shown in FIG. 7; the same applies below). 7, the second edge 628 is located further in the x2 direction than the second side 192 in a plan view, and extends in the y direction at least from the third side 193 to 194. As a result, in a plan view, two corners 173, 174 on the x1 direction side of each first semiconductor element 10A do not overlap the second conductive member 62. The two corners are the angle 173 between the second side 192 and the third side 193, and the angle 174 between the second side 192 and the fourth side 194. Therefore, in a plan view, for each first semiconductor element 10A, a portion of each of the two sides sandwiching the corners 173, 174 is visible.

[0077] For each of the corners 171, 172, 173, and 174, the two sides sandwiching each corner 171, 172, 173, and 174 may be visible with a length greater than 0 μm and less than 200 μm in plan view. Furthermore, the length of the visible portion of each of the two sides sandwiching each corner 171, 172, 173, and 174 is preferably greater than 5 μm and less than 150 μm in plan view. When the length of the visible portion of each of the two sides sandwiching each corner 171, 172, 173, and 174 is 2 μm or greater, the corners of the first semiconductor element 10A can be detected. When the length of the visible portion of each of the two sides is 5 μm or greater, the corners of the first semiconductor element 10A can be reliably detected. Note that it is not preferable for the length of the visible portion of each of the two sides to exceed 200 μm, because this unnecessarily reduces the bonding area between the first conductive member 61 and the first semiconductor element 10A. It is preferable that the upper limit of the length of the visible portion of the two sides is 150 μm or less, since this prevents the bonding area between the first conductive member 61 and the first semiconductor element 10A from becoming too small.

[0078] 6, the conductive member 6 (first conductive member 61 and second conductive member 62) has a first portion 601. The first portion 601 is a region that overlaps with the semiconductor element 10 (either the plurality of first semiconductor elements 10A or the plurality of second semiconductor elements 10B) in a planar view. In the second conductive member 62, a portion of the fourth wiring portion 624 (a region that overlaps with the plurality of first semiconductor elements 10A in a planar view) and a portion of the third wiring portion 623 (a region that overlaps with the plurality of second semiconductor elements 10B in a planar view) form the first portion 601.

[0079] As shown in FIGS. 6 and 8 , the principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A (the first semiconductor element 10A having the diode functional portion D1) are arranged side by side along the y direction at the end of the first semiconductor element 10A on the x2 direction side. In a plan view, the first conductive member 61 and the second conductive member 62 do not overlap any of the principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A or the corners 171 and 172 on the x2 direction side. Furthermore, in a plan view, the first conductive member 61 and the second conductive member 62 do not overlap at least one of the corners 173 and 174 on the x1 direction side of the first semiconductor element 10A (the side opposite to the side on which the principal surface electrodes are arranged). As a result, at least three of the four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible in a plan view. This allows automatic visual inspection to check whether the semiconductor element 10A is correctly mounted when the semiconductor element 10A, first conductive member 61, and second conductive member 62 are mounted on the conductive substrate 2. In a plan view, all four corners 171, 172, 173, and 174 of the semiconductor element 10A may be visible. Note that the above-described principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A are examples of "one-side principal surface electrodes."

[0080] 6, each second semiconductor element 10B is also rectangular in plan view, like the first semiconductor element 10A, and has four corners 181, 182, 183, and 184 corresponding to the four corners 171, 172, 173, and 174 of the first semiconductor element 10A. The relationship between the four corners 171, 172, 173, and 174 of each first semiconductor element 10A and the first conductive member 61 and the second conductive member 62 in plan view described above is also the same as the relationship between the four corners 181, 182, 183, and 184 of each second semiconductor element 10B and the second conductive member 62 in plan view.

[0081] As shown in FIG. 5 , the second conductive member 62 includes a first portion 62A and a second portion 62B. The first portion 62A overlaps the main surface 201 of the conductive substrate 2 (the main surface 201 of the first conductive portion 2A or the second conductive portion 2B) in a planar view, but does not overlap any of the multiple semiconductor elements 10 in a planar view. The second portion 62B overlaps the main surface 201 in a planar view, and also overlaps any of the multiple semiconductor elements 10 in a planar view. In FIG. 5 , the first portion 62A is hatched with diagonal lines slanting upward to the right, and the second portion 62B is hatched with diagonal lines slanting downward to the right. The first portion 62A has an opening 63. The opening 63 is a partially removed portion in a planar view, as shown in FIGS. 5 and 13 . In this embodiment, the opening 63 is located at a position that overlaps the main surface 201 of the first conductive portion 2A (the conductive substrate 2) in a planar view, but does not overlap any of the multiple semiconductor elements 10 in a planar view. The openings 63 are, for example, through holes that penetrate in the z direction. The openings 63 may be formed in the first wiring portion 621 or the second wiring portion 622. In a plan view, the openings 63 are provided near at least two of the four corners of the conductive substrate 2, and are provided, for example, closer to the x2 direction in each of the first wiring portion 621 and the second wiring portion 622. The planar shape of the openings 63 is not limited, and may be a hole as in this embodiment or a notch as in this embodiment. The openings 63 may be manufactured by, for example, electroforming. In this case, the second conductive member 62 has openings 63 formed from portions where metal has not been electrodeposited, rather than openings 63 formed from removed portions.

[0082] An opening 625h is formed in a rectangular portion of the second conductive member 62 that overlaps with each first semiconductor element 10A in a plan view. In this embodiment, the opening 625h is preferably formed to overlap the center of each first semiconductor element 10A in a plan view. The opening 625h is, for example, a through-hole formed in each convex region 625a of the first strip portion 625 (fourth wiring portion 624) (see FIG. 6). The opening 625h is used to optically check the state of bonding from above when bonding the first conductive member 61 and the first semiconductor element 10A.

[0083] In the second conductive member 62, an opening 623h is formed in a rectangular portion that overlaps with each second semiconductor element 10B in a plan view. In the present embodiment, the opening 623h is preferably formed to overlap the center of the second semiconductor element 10B in a plan view. The opening 623h is, for example, a through hole formed in each recessed region 623a of the third wiring portion 623. The opening 623h is used when positioning the second conductive member 62 with respect to the conductive substrate 2. The planar shapes of the two types of openings 623h, 625h may be a perfect circle, or may be other shapes such as an oval or a rectangle.

[0084] The shape of the second conductive member 62 is not limited to this configuration, and for example, the second conductive member 62 does not have to include the fourth wiring portion 624. However, in order to reduce the inductance value due to the current flowing through the second conductive member 62, it is preferable to provide the second conductive member 62 with the fourth wiring portion 624.

[0085] The first conductive bonding material 71 is interposed between the conductive substrate 2 and the support substrate 3 and electrically connects the conductive substrate 2 and the support substrate 3. There are two types of first conductive bonding material 71: one that electrically connects the first conductive portion 2A to the first portion 32A, and one that electrically connects the second conductive portion 2B to the second portion 32B. As shown in FIG. 15 , the first conductive bonding material 71 has a first base layer 711, a first layer 712, and a second layer 713 that are stacked on top of each other.

[0086] As shown in FIG. 15 , it is most preferable that the side surface of the first conductive bonding material 71 and the side surface of the first metal layer 32, which is the uppermost layer of the support substrate 3, are flush with each other. In plan view, it is preferable that the side surface of the first metal layer 32 is located slightly inward from the side surface of the first conductive bonding material 71. That is, in plan view, the side surface of the first metal layer 32 is bonded so as not to protrude beyond the side surface of the first conductive bonding material 71. If the side surface of the first metal layer 32 protrudes beyond the side surface of the first conductive bonding material 71 in plan view, this is not preferable because the creepage distance between the first metal layer 32 and the second metal layer 33 becomes small. Note that, in plan view, the side surface of the first metal layer 32 is located outward from the side surface of the base material 21 of the conductive substrate 2.

[0087] The first base layer 711 is made of metal, such as Al or an Al alloy. The first base layer 711 is a sheet material. The Young's modulus of Al (aluminum), which is the material that makes up the first base layer 711, is 70.3 GPa.

[0088] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is interposed between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The first layer 712 is, for example, Ag plating. The first layer 712 is bonded to the respective back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B by, for example, solid-state diffusion of metal. That is, the first layer 712 and the respective back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B are bonded by solid-state diffusion bonding. As a result, the first layer 712 and the respective back surface bonding layers 23 are bonded in direct contact with each other at the bonding interface. In the present disclosure, the phrase "A and B are bonded by solid-state diffusion bonding" means that, as a result of solid-state diffusion bonding, A and B are fixed to each other in direct contact with each other at the bonding interface, and it can be said that A and B constitute a solid-state diffusion bonding layer. When solid-state diffusion bonding is performed under ideal conditions, the bonded interface may not be clearly defined due to the diffusion of metal elements. On the other hand, if there are inclusions such as oxide films on the surfaces of A and B, or if there are voids between A and B, these inclusions or voids may exist at the bonded interface.

[0089] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is interposed between the first base layer 711 and the support substrate 3 (each of the first portion 32A and the second portion 32B). The second layer 713 is, for example, Ag plating. The second layer 713 is bonded to the first bonding layers 321 formed on the first portion 32A and the second portion 32B, respectively, by, for example, solid-state diffusion of metal. That is, the second layer 713 and the first bonding layer 321 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface. The Young's modulus of Ag (silver), which is the constituent material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0090] In the first conductive bonding material 71, the constituent material of the first base layer 711 and the constituent materials of the first layer 712 and the second layer 713 are as described above, and therefore the Young's modulus of the first base layer 711 is smaller than the Young's modulus of the first layer 712 and the second layer 713. The thickness (dimension in the z direction) of the first base layer 711 is larger than the thickness of each of the first layer 712 and the second layer 713.

[0091] In the first conductive bonding material 71, the end surface of the first base layer 711, which is made of Al or an Al alloy, is not Ag-plated, and the end surface of the first base layer 711 is exposed. However, the end surface of the first base layer 711 may be Ag-plated. From the viewpoint of reducing the manufacturing cost of the first conductive bonding material 71, it is preferable to manufacture the first conductive bonding material 71 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that the end surface of the first base layer 711 is not Ag-plated.

[0092] The second conductive bonding material 72 is interposed between the conductive substrate 2 and each semiconductor element 10, and electrically connects the conductive substrate 2 and each semiconductor element 10. The second conductive bonding material 72 is classified into one that electrically connects each first semiconductor element 10A to the first conductive portion 2A, and one that electrically connects each second semiconductor element 10B to the second conductive portion 2B. As shown in FIG. 15 , the second conductive bonding material 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 that are stacked on top of each other.

[0093] The second base layer 721 is made of a metal, such as Al or an Al alloy, and is a sheet material.

[0094] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is interposed between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, Ag plating. The third layer 722 is bonded to the back surface electrode 15 of each semiconductor element 10 by, for example, solid-state diffusion of metal. That is, the third layer 722 and the back surface electrode 15 are bonded by solid-state diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface.

[0095] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is interposed between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, Ag plating. The fourth layer 723 is bonded to each of the main surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B by, for example, solid-state diffusion of metal. That is, the fourth layer 723 and each of the main surface bonding layers 22 are bonded by solid-state diffusion bonding, and are bonded in direct contact with each other at the bonding interface.

[0096] In the second conductive bonding material 72, the constituent material of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are as described above, and therefore the Young's modulus of the second base layer 721 is smaller than the Young's modulus of the third layer 722 and the fourth layer 723. The thickness (dimension in the z direction) of the second base layer 721 is larger than the thickness of each of the third layer 722 and the fourth layer 723.

[0097] In the second conductive bonding material 72, the end surface of the second base layer 721, which is made of Al or an Al alloy, is not Ag-plated, and the end surface of the second base layer 721 is exposed. However, the end surface of the second base layer 721 may be Ag-plated. From the viewpoint of reducing the manufacturing cost of the second conductive bonding material 72, it is preferable to manufacture the second conductive bonding material 72 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that the end surface of the second base layer 721 is not Ag-plated.

[0098] Each of the wires 731 to 735 provides electrical continuity between two separate portions. Each of the wires 731 to 735 is, for example, a bonding wire. The material of each of the wires 731 to 735 includes, for example, any of Au (gold), Al, and Cu.

[0099] As shown in FIG. 8, the plurality of wires 731 are bonded to the first principal surface electrodes 11 (gate electrodes) of the respective semiconductor elements 10 and the first portions 521 (first metal layers 52) of the respective control terminal support bodies 5, thereby establishing electrical continuity therebetween. As shown in FIG. 8, the plurality of wires 731 include a plurality of first wires 731a and a plurality of second wires 731b. The plurality of first wires 731a are connected to the first principal surface electrodes 11 (gate electrodes) of the respective first semiconductor elements 10A and the first portions 521 (first metal layers 52) of the respective first support bodies 5A. As a result, the first control terminals 46A are established electrical continuity with the first principal surface electrodes 11 (gate electrodes) of the respective first semiconductor elements 10A via the respective first wires 731a. The plurality of second wires 731b are connected to the first principal surface electrodes 11 (gate electrodes) of the respective second semiconductor elements 10B and the first portions 521 (first metal layers 52) of the respective second support bodies 5B. As a result, the second control terminal 47A is electrically connected to the first principal surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b.

[0100] 8, the plurality of wires 732 are bonded to the second principal surface electrode 12 (source electrode) of each semiconductor element 10 and the second portion 522 (first metal layer 52) of each control terminal support body 5, thereby establishing electrical continuity between them. However, in each semiconductor element 10 having a diode functional portion D1, each wire 732 is bonded to the fifth principal surface electrode 16 (source sense electrode) instead of the second principal surface electrode 12 (source electrode).

[0101] As shown in FIG. 8, each of the multiple wires 733 is joined to the third main surface electrode 13 of each semiconductor element 10 having a diode functional portion D1 and the third portion 523 (first metal layer 52) of each control terminal support 5, thereby establishing electrical continuity between them.

[0102] As shown in FIG. 8, each of the multiple wires 734 is bonded to the fourth main surface electrode 14 of each semiconductor element 10 having a diode functional portion D1 and the fourth portion 524 (first metal layer 52) of each control terminal support 5, thereby establishing electrical continuity between them.

[0103] As shown in FIG. 8, the wire 735 is joined to the main surface 201 of the first conductive portion 2A (conductive substrate 2) and the fifth portion 525 (first metal layer 52) of the first support portion 5A (control terminal support portion 5), thereby providing electrical continuity between them.

[0104] The sealing resin 8 covers the semiconductor elements 10, the conductive substrate 2, the support substrate 3 (excluding the bottom surface 302), portions of the input terminals 41 to 43, portions of the output terminals 44, portions of the control terminals 45, the control terminal support 5, the conductive member 6, and the wires 731 to 735. The sealing resin 8 is made of, for example, a black epoxy resin. The sealing resin 8 is formed by, for example, molding, which will be described later. The sealing resin 8 has, for example, a dimension of about 35 mm to 60 mm in the x direction, a dimension of about 35 mm to 50 mm in the y direction, and a dimension of about 4 mm to 15 mm in the z direction. These dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and multiple resin side surfaces 831 to 834.

[0105] As shown in FIGS. 9, 11, and 12, the resin main surface 81 and the resin back surface 82 are spaced apart in the z direction. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. A plurality of control terminals 45 (a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in FIG. 10, the resin back surface 82 has a frame shape surrounding the bottom surface 302 (the lower surface of the second metal layer 33) of the support substrate 3 in a plan view. The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82. The plurality of resin side surfaces 831 to 834 are connected to both the resin main surface 81 and the resin back surface 82 and are sandwiched between them in the z direction. As shown in FIG. 4, the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. Resin side surface 831 faces the x1 direction, and resin side surface 832 faces the x2 direction. Two output terminals 44 protrude from resin side surface 831, and three input terminals 41 to 43 protrude from resin side surface 832. As shown in FIG. 4 and other figures, resin side surface 833 and resin side surface 834 are spaced apart in the y direction. Resin side surface 833 faces the y1 direction, and resin side surface 834 faces the y2 direction.

[0106] 4, a plurality of recesses 832a are formed on the resin side surface 832. Each recess 832a is a portion recessed in the x direction in a plan view. In a plan view, the plurality of recesses 832a include those formed between the input terminals 41 and 42 and those formed between the input terminals 41 and 43. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the input terminals 41 and 42 and the creepage distance along the resin side surface 832 between the input terminals 41 and 43.

[0107] As shown in FIGS. 13 and 14, the sealing resin 8 has a plurality of first protrusions 851, a plurality of second protrusions 852, and a resin cavity 86.

[0108] Each of the multiple first protrusions 851 protrudes in the z direction from the resin main surface 81. The multiple first protrusions 851 are arranged near the four corners of the sealing resin 8 in a plan view. A first protrusion end surface 851a is formed at the tip (end in the z2 direction) of each of the first protrusions 851. Each of the multiple first protrusions 851 has a hollow truncated cone shape with a bottom, for example. The multiple first protrusions 851 are used as spacers when the semiconductor module A1 is mounted on a control circuit board or the like of a device that uses power generated by the semiconductor module A1. Each of the multiple first protrusions 851 has a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each first protrusion 851 may be columnar, and is preferably cylindrical. The shape of recess 851b is preferably cylindrical, and inner wall surface 851c is preferably a single perfect circle in plan view. Each first protrusion 851 is an example of a "protrusion," and each first protrusion end surface 851a is an example of a "protrusion end surface."

[0109] The semiconductor module A1 may be mechanically fixed to a control circuit board or the like by a method such as screwing. In this case, a female screw thread may be formed on the inner wall surfaces 851c of the recesses 851b of the multiple first protrusions 851. Insert nuts may be embedded in the recesses 851b of the multiple first protrusions 851.

[0110] As shown in FIG. 14 and other figures, the multiple second protrusions 852 protrude in the z direction from the resin main surface 81. The multiple second protrusions 852 overlap the multiple control terminals 45 in a plan view. The metal pins 452 of the multiple control terminals 45 protrude from each second protrusion 852. A part of the holder 451 (the upper surface of the upper end flange) is exposed from the upper end surface of each second protrusion 852. Each second protrusion 852 has a truncated cone shape. A resin portion 87 is disposed on each second protrusion 852.

[0111] 13, the resin void 86 communicates in the z direction from the resin main surface 81 to a recess 201a formed in the main surface 201 of the conductive substrate 2. The resin void 86 is formed in a tapered shape such that the cross-sectional area decreases from the resin main surface 81 to the recess 201a in the z direction. A resin void edge 861 in the resin void 86 that contacts the main surface 201 and a recess edge 201b in the recess 201a that contacts the main surface 201 coincide with each other. The resin void 86 is formed during molding, which will be described later, and is a portion in which the sealing resin 8 is not formed during molding.

[0112] The resin portion 87 is provided on the second protrusion 852 of the sealing resin 8. In each control terminal 45, the resin portion 87 covers a part of the holder 451 (the upper surface of the upper end flange) exposed from the sealing resin 8 and a part of the metal pin 452. The resin portion 87 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a different material from the sealing resin 8.

[0113] The resin filling portion 88 is filled into the resin void portion 86 so as to fill the resin void portion 86. The resin filling portion 88 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a different material from the sealing resin 8.

[0114] Next, a method for manufacturing the semiconductor module A1 will be described with reference to FIGS. 21 to 29. FIG. 21 is a plan view showing one step of the method for manufacturing the semiconductor module A1. FIG. 22 is a cross-sectional schematic view showing one step of the method for manufacturing the semiconductor module A1. FIG. 23 is a plan view showing one step of the method for manufacturing the semiconductor module A1. FIG. 24 is a cut-away end view showing one step of the method for manufacturing the semiconductor module A1. FIG. 24 corresponds to the cross section shown in FIG. 13. FIGS. 25 and 28 are enlarged cross-sectional views of essential parts showing one step of the method for manufacturing the semiconductor module A1, and correspond to the enlarged view of a portion of the cross section shown in FIG. 13. FIGS. 26, 27, and 29 are enlarged cross-sectional views of essential parts showing one step of the method for manufacturing the semiconductor module A1, and correspond to the enlarged view of a portion of the cross section shown in FIG. 14.

[0115] First, a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44 are prepared. The configurations of the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. At the preparation stage, the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are prepared individually and are not bonded to each other. Furthermore, as shown in FIG. 21, the conductive substrate 2, the plurality of input terminals 41 to 43, and the plurality of output terminals 44 are connected to each other and are formed, for example, by the same lead frame. Furthermore, as shown in FIG. 21, no recess 201a is formed on the main surface 201 of the conductive substrate 2.

[0116] 22, the conductive substrate 2 is placed on the support substrate 3 with a first conductive bonding material 71 sandwiched therebetween, and then each semiconductor element 10 is placed on the conductive substrate 2 with a second conductive bonding material 72 sandwiched therebetween. Thereafter, while the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 are held between them (see the thick arrows in FIG. 22), heat is applied to bond each semiconductor element 10 to the conductive substrate 2 by solid-state diffusion, and also bond the conductive substrate 2 to the support substrate 3 by solid-state diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 and the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) and the back surface bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) and the main surface bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) and the back surface electrode 15 of each semiconductor element 10 are all bonded together by solid-phase diffusion. The conditions for solid-phase diffusion include a heating temperature during bonding that is between 200°C and 350°C, and a pressure (the clamping force) applied during bonding that is between 1 MPa and 100 MPa. While solid-phase diffusion is assumed to be performed in the atmosphere, it may also be performed in a vacuum. As a result, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is bonded to the conductive substrate 2 via the second conductive bonding material 72. The bonding between the conductive substrate 2 and the support substrate 3 and the bonding between the conductive substrate 2 and each semiconductor element 10 may be performed separately rather than all at once. However, performing the bonding all at once is preferable in terms of improving manufacturing efficiency.

[0117] When placing each semiconductor element 10 on the conductive substrate 2 with the second conductive bonding material 72 sandwiched therebetween, an individual second conductive bonding material 72 is placed corresponding to each semiconductor element 10, as shown in Figures 16 and 17. However, without being limited to this, one second conductive bonding material 72 may be placed in common corresponding to the three semiconductor elements 10 shown in Figure 16.

[0118] 23, the control terminal support body 5 is joined, the holders 451 of the plurality of control terminals 45 are joined, the plurality of wires 731 to 735 are wire-bonded, the plurality of first conductive members 61 are joined, and the second conductive members 62 are joined. Note that the order of these processes is not limited.

[0119] Next, the sealing resin 8 is formed. The sealing resin 8 is formed by, for example, molding. As shown in FIG. 24, a mold 91 used in molding is provided with a pressing pin 911 as a pressing member. The tip of the pressing pin 911 contacts the main surface 201 of the conductive substrate 2. At this time, the pressing force of the pressing pin 911 on the main surface 201 forms a recess 201a in the main surface 201. The degree of depression (depth) of the recess 201a varies depending on the magnitude of the pressing force, etc. Furthermore, the pressing pin 911 in contact with the main surface 201 of the first conductive part 2A is inserted into the opening 63 of the second conductive member 62. Then, a fluid resin material is injected into a cavity space 919 of the mold 91 sequentially via a resin flow path and a resin injection port (both not shown). The injected fluid resin material solidifies to form the sealing resin 8. As shown in FIGS. 25 and 26 , the formed sealing resin 8 has the first protrusion 851, the second protrusion 852, and the resin void 86. As shown in FIG. 25 , a resin void edge 861 that contacts the main surface 201 in the resin void 86 and a recess edge 201b that contacts the main surface 201 in the recess 201a coincide with each other. As shown in FIG. 26 , the upper surface of the holder 451 is exposed from the second protrusion 852 and is flush with the upper surface of the second protrusion 852. As can be seen from FIGS. 24 and 25 , the resin void 86 is formed by preventing the fluid resin material from being filled due to the presence of a presser pin 911. Note that the presser pin 911 may be a movable pin. In this case, the presser pin 911 is preferably provided in a hole formed in the mold 91 and elastically supported. A block-shaped presser member may be used instead of a pin-shaped presser member.

[0120] Next, the mold 91 is opened, and a molded body including the lead frame with the conductive substrate 2 and the sealing resin 8 is removed. After that, the sealing resin 8 is separated from the resin solidified in the resin flow path and the resin injection port. In this process, resin separation marks are formed at one of the following positions on the resin side surface 831 of the sealing resin 8 on the x1 direction side. The first position is at least one of two positions near both ends in the y direction on the resin side surface 831 shown in FIG. 1 or at the corners of both ends. When resin separation marks are formed at the corners of both ends, the resin separation marks are formed on the surfaces formed at the corners (the C-chamfered portions in plan view). The above-mentioned inclined surface is included in the resin side surface 831 on the x1 direction side of the sealing resin 8. The second position is between the two output terminals 44 on the resin side surface 831 shown in FIG. 1. These resin separation marks correspond to the positions of the resin injection ports of the mold 91 and are formed by separating the sealing resin 8 from the resin solidified at the resin injection port. To prevent uneven resin flow, it is preferable to inject the resin from the center position in the y direction. In this case, a resin separation mark is formed between the two output terminals 44.

[0121] Next, as shown in FIG. 27, each metal pin 452 of the multiple control terminals 45 is press-fitted into each holder 451. Specifically, each metal pin 452 having a cross-sectional dimension slightly larger than the inner diameter of the cylindrical portion (see FIG. 26) of each holder 451 is inserted while applying insertion pressure. As a result, each holder 451 and each metal pin 452 are mechanically fixed and electrically connected. Each holder 451 and each metal pin 452 may be electrically connected using, for example, solder. Thereafter, as shown in FIGS. 28 and 29, a resin portion 87 and a resin-filled portion 88 are formed. The resin portion 87 and the resin-filled portion 88 are formed by, for example, potting.

[0122] Next, the lead frame is appropriately cut to separate the multiple input terminals 41 to 43 and the output terminal 44. The input terminals 41 to 43 and the output terminal 44 shown in FIG. 21 can be cut using a mold or the like near the connection points between each terminal and the outer frame of the lead frame (portions indicated by dashed lines in FIG. 21). Here, the input terminals 41 to 43 have tip surfaces 413, 423, and 433 formed as input-side processing marks. The output terminal 44 has a tip surface 443 formed as output-side processing marks. If the lead frame has tie bars connecting adjacent terminals in the y direction, the tie bars may be cut using a mold or the like. In this case, processing marks are formed on the two side surfaces of each terminal facing the y direction. Through the above steps, the semiconductor module A1 shown in FIGS. 1 to 20 is manufactured.

[0123] The semiconductor module A1 is mounted on a control circuit board or the like. Here, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted and connected to a terminal around the pin hole. The input terminals 41, 42, and 43 have input-side bonding surfaces 411, 421, and 431 facing one side in the z direction (z2 direction), respectively. Each output terminal 44 has an output-side bonding surface 441 facing one side in the z direction (z2 direction). The input-side bonding surfaces 411, 421, and 431 and the output-side bonding surface 441 are connected, for example, using solder, to terminals of the circuit board on which the semiconductor module A1 is mounted.

[0124] The current path from the input terminal 41 to the output terminal 44 in the semiconductor module A1 of this embodiment will be described below. The first main circuit current flows through the input terminal 41, the first conductive portion 2A, each first semiconductor element 10A, the first conductive member 61, the second conductive portion 2B, and each output terminal 44. The first main circuit current flows along the x-direction between the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B via each first conductive member 61. The first main circuit current flows along the x-direction and a direction slightly tilted from the x-direction between the portion of the second conductive portion 2B where each first conductive member 61 is joined and each output terminal 44.

[0125] The current path from output terminal 44 to input terminal 42 and input terminal 43 will be described below. The second main circuit current flows through output terminal 44, second conductive portion 2B, each second semiconductor element 10B, second conductive member 62, input terminal 42, and input terminal 43. The path of the second main circuit current is possessed by second conductive member 62, and the second main circuit current flows through both third wiring portion 623 extending in the y direction and first wiring portion 621 and second wiring portion 622 connected to both ends of third wiring portion 623 and extending in the x2 direction. Furthermore, the second main circuit current flows through the first wiring portion 621 and the second wiring portion 622 via two second strip portions 626 arranged between the first wiring portion 621 and the second wiring portion 622 and extending in the x-direction, and the first strip portion 625 arranged between the first wiring portion 621 and the second wiring portion 622 and extending in the y-direction.

[0126] A second main circuit current flows between the input terminals 42 and 43 and the second main surface electrodes 12 of each second semiconductor element 10B via the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, the two second strip portions 626, and the first strip portion 625 included in each second conductive member 62. In the first wiring portion 621, the second wiring portion 622, and the two second strip portions 626, the second main circuit current flows along the x direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0127] The direction in which the first main circuit current flows in the first conductive member 61 and the direction in which the second main circuit current flows in the first wiring portion 621, the second wiring portion 622 and the two second strip portions 626 included in the second conductive member 62 are both the x direction.

[0128] The semiconductor module A1 has the following functions and effects.

[0129] The semiconductor module A1 includes a conductive substrate 2, a plurality of input terminals 41 to 43, an output terminal 44, and a conductive member 6. The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are bonded and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are bonded. The input terminal 41 is connected to the first conductive portion 2A and is electrically connected to the plurality of first semiconductor elements 10A via the first conductive portion 2A. The input terminals 42 and 43 are electrically connected to the plurality of second semiconductor elements 10B via a second conductive member 62 (conductive member 6). The output terminal 44 is connected to the second conductive portion 2B and is electrically connected to the plurality of second semiconductor elements 10B via the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 that electrically connects each first semiconductor element 10A to the second conductive portion 2B, and a second conductive member 62 that electrically connects each second semiconductor element 10B to each input terminal 42, 43. The input terminals 41 to 43 are arranged in the x2 direction with respect to the conductive substrate 2, and the output terminal 44 is arranged in the x1 direction with respect to the conductive substrate 2. The two input terminals 42, 43 are arranged on opposite sides of the input terminal 41 in the y direction. In a semiconductor module having a different configuration from the semiconductor module A1, if the input terminal 43 is not provided and the input terminals 41 and 42 are arranged side by side in the y direction, there is a possibility that variations will occur in the path of the current flowing from the input terminal 41 to the output terminal 44 via each first semiconductor element 10A, and that variations will also occur in the path of the current flowing from the output terminal 44 to each input terminal 42 via each second semiconductor element 10B. Therefore, the semiconductor module A1 is provided with two input terminals 42, 43, and by sandwiching the input terminal 41 between the two input terminals 42, 43, it is possible to reduce the variation in the path of the current flowing from the input terminal 41 to the output terminal 44 via each of the first semiconductor elements 10A, and also to reduce the variation in the path of the current flowing from the output terminal 44 to each of the input terminals 42, 43 via each of the second semiconductor elements 10B. This reduces the parasitic inductance component of the semiconductor module A1. In other words, the semiconductor module A1 has a package structure that is favorable for reducing the parasitic inductance component.

[0130] In the semiconductor module A1, the upper arm current path and the lower arm current path overlap in a plan view. The upper arm current path is a path of current flowing from the input terminal 41 to each output terminal 44 via the first conductive portion 2A, each first semiconductor element 10A, each first conductive member 61, and each second conductive portion 2B. In this embodiment, the upper arm current path extends from the x2 direction to the x1 direction, as can be seen from FIG. 5 . The lower arm current path is a path of current flowing from the output terminal 44 to each second semiconductor element 10B and each second conductive member 62 to the input terminal 42. In this embodiment, the lower arm current path extends from the x1 direction to the x2 direction, as can be seen from FIG. 5 . With this configuration, the magnetic fields generated by the currents flowing along the upper arm current path and the magnetic fields generated by the currents flowing along the lower arm current path cancel each other out, thereby reducing the parasitic inductance component. In particular, in the semiconductor module A1, the conductive members 6 (each of the plurality of first conductive members 61 and second conductive members 62) are made of a metal plate, which ensures an appropriate area where the upper arm current path and the lower arm current path overlap in a plan view. In other words, the semiconductor module A1 has a package structure that is preferable for reducing parasitic inductance components.

[0131] In the semiconductor module A1, the second conductive member 62 constituting the lower arm current path includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are connected to input terminals 42 and 43, respectively, which are arranged on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps with the plurality of first semiconductor elements 10A in a plan view. The second conductive member 62, which is configured to include the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624, is disposed at a distance from the main surface 201 (conductive substrate 2) in the z direction and overlaps a wide range of the main surface 201 in a plan view. This configuration appropriately reduces variations in the paths of the currents that flow from the output terminal 44 to the input terminals 42, 43 via the second semiconductor elements 10B, and is suitable for reducing the parasitic inductance component.

[0132] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. This configuration prevents the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be made smaller.

[0133] The fourth wiring portion 624 of the second conductive member 62 has a first strip-shaped portion 625 and multiple second strip-shaped portions 626. The first strip-shaped portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and overlaps with multiple first semiconductor elements 10A in a planar view. The multiple second strip-shaped portions 626 are each connected to the first strip-shaped portion 625 and the third wiring portion 623, and are strip-shaped extending in the x direction in a planar view. The multiple second strip-shaped portions 626 are spaced apart in the y direction and arranged substantially parallel to each other. In a planar view, one end of each of the multiple second strip-shaped portions 626 is connected between two first semiconductor elements 10A of the first strip-shaped portion 625 adjacent to each other in the y direction, and the other end is connected between two second semiconductor elements 10B of the third wiring portion 623 adjacent to each other in the y direction. This configuration allows the fourth wiring portion 624 (second conductive member 62) to have a larger size in plan view, which is preferable in terms of reducing the parasitic inductance component.

[0134] The first strip portion 625 has multiple convex regions 625a that protrude in the z2 direction further than other portions. Each of the convex regions 625a overlaps a corresponding one of the first semiconductor elements 10A in plan view. The configuration in which the first strip portion 625 has multiple convex regions 625a makes it possible to prevent the first strip portion 625 from making inappropriate contact with the first conductive member 61 bonded onto the first semiconductor element 10A.

[0135] The third wiring portion 623 has a plurality of recessed regions 623a that protrude in the z1 direction further than other portions. Each recessed region 623a is bonded to one of the plurality of second semiconductor elements 10B. This configuration makes it possible to ensure that the third wiring portion 623 (second conductive member 62) has a large size in a plan view while properly conducting the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B.

[0136] In addition to being equipped with the conductive member 6 (first conductive member 61 and second conductive member 62) configured as described above, the semiconductor module A1 is also equipped with a plurality of first control terminals 46A-46E and a plurality of second control terminals 47A-47D for controlling the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A-46E and the plurality of second control terminals 47A-47D are each arranged to extend along the z direction on the main surface 201 of the conductive substrate 2. The semiconductor module A1 configured in this way can be made smaller in size in a planar view, and is therefore suitable for achieving a smaller size in a planar view while reducing the parasitic inductance component.

[0137] The first control terminals 46A-46E are supported by the first conductive portion 2A and are arranged closer to the x2 direction than the first semiconductor elements 10A. The second control terminals 47A-47D are supported by the second conductive portion 2B and are arranged closer to the x1 direction than the second semiconductor elements 10B. The first control terminals 46A-46E and the second control terminals 47A-47D are arranged at intervals in the y direction. This allows the first control terminals 46A-46E and the second control terminals 47A-47D to be appropriately arranged in regions corresponding to the first semiconductor elements 10A constituting the upper arm circuit and the second semiconductor elements 10B constituting the lower arm circuit, respectively. A semiconductor module A1 having such a configuration is preferable for achieving miniaturization while reducing parasitic inductance components.

[0138] The first semiconductor element 10A and the second semiconductor element 10B each have a first principal surface electrode 11 (gate electrode) facing in the z2 direction. The first control terminal 46A is connected to the first principal surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. The second control terminal 47A is connected to the first principal surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b. This allows a drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function to be appropriately input to the first principal surface electrode 11 via the first control terminal 46A (second control terminal 47A) and the first wire 731a (second wire 731b).

[0139] When the semiconductor module A1 is mounted on a circuit board, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted and connected to a terminal around the pin hole. The input terminals 41, 42, and 43 each have an input-side bonding surface 411, 421, and 431 facing one side in the z direction (the z2 direction). Each output terminal 44 has an output-side bonding surface 441 facing one side in the z direction (the z2 direction). The input-side bonding surfaces 411, 421, and 431 and the output-side bonding surface 441 are connected, for example, using solder, to terminals of the circuit board on which the semiconductor module A1 is mounted. With the above-described configuration, the power circuit board to which the input terminals 41 to 43 and the output terminal 44 are connected and the control circuit board to which the metal pins 452 are connected can be arranged apart in the z direction. These features first improve the degree of freedom in arranging the signal terminals in the semiconductor module A1. Second, the degree of freedom regarding the routing and length of signal wiring in the semiconductor module A1 is improved. Third, when using the semiconductor module A1, the degree of freedom regarding the layout of the circuit board by the user is improved.

[0140] In the semiconductor module A1, each control terminal 45 protrudes from the resin main surface 81 and extends along the z direction. In a configuration different from the semiconductor module A1, each control terminal 45 may be arranged to extend along a plane (xy plane) perpendicular to the z direction. This configuration has a limit to how compact the semiconductor module A1 can be when viewed from above. Therefore, by arranging each control terminal 45 to extend along the z direction, as in the semiconductor module A1, it is possible to reduce the size of the semiconductor module A1 when viewed from above. In other words, the semiconductor module A1 has a package structure that is preferable for achieving a reduction in size when viewed from above.

[0141] In the semiconductor module A1 of this embodiment, a control terminal support body 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support body 5 has an insulating layer 51, and each control terminal 45 is supported on the conductive substrate 2 via the control terminal support body 5. With such a configuration including the control terminal support body 5, the control terminal 45 can be properly supported on the conductive substrate 2 while ensuring insulation between the control terminal 45 and the conductive substrate 2.

[0142] The control terminal support body 5 is a laminated structure having an insulating layer 51, a first metal layer 52, and a second metal layer 53 laminated on top of each other. The control terminal 45 is bonded to the first metal layer 52 formed on the upper surface of the control terminal support body 5 via a conductive bonding material 459. With this configuration, it is possible to use a ready-made laminated structure (such as a DBC substrate) as the control terminal support body 5 and to conductively bond the control terminal 45 to the control terminal support body 5 (first metal layer 52).

[0143] The semiconductor element 10 has an element principal surface 101 facing the z2 direction and an element rear surface 102 facing the z1 direction. A first principal surface electrode 11 (gate electrode) is arranged on the element principal surface 101. The first principal surface electrode 11 and the first metal layer 52 (first portion 521) of each semiconductor element 10 are connected by a conductive wire 731. This allows a drive signal for driving the semiconductor element 10, which has a switching function, to be input to the first principal surface electrode 11 as needed via the control terminal 45, the first metal layer 52, and the wire 731.

[0144] Each control terminal 45 includes a holder 451 and a metal pin 452. The holder 451 is made of a conductive material and includes a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z-direction and press-fitted into the holder 451. A portion of the holder 451 (the upper surface of the upper flange) is exposed from the sealing resin 8. With this configuration, when the sealing resin 8 is formed (molded), the holder 451 is covered with the sealing resin 8 except for a portion of it (the upper end surface), and the upper end surface of the holder 451 is exposed from the sealing resin 8. This makes it possible to insert the metal pin 452 into the holder 451 after the sealing resin 8 is formed. Therefore, with the control terminal 45 including the holder 451 and the metal pin 452, it is possible to avoid the mold 91 used in molding becoming complicated, which is suitable for efficient manufacturing of the semiconductor module A1.

[0145] The semiconductor module A1 of this embodiment includes a resin portion 87 bonded to the sealing resin 8. The resin portion 87 covers a part of the holder 451 (the upper surface of the upper flange) exposed from the sealing resin 8 and a part of the metal pin 452. This configuration can prevent foreign matter from entering the connection portion between the holder 451 and the metal pin 452. The semiconductor module A1 configured as described above is preferable in terms of durability and reliability.

[0146] The sealing resin 8 has a plurality of second protrusions 852 protruding from the resin main surface 81. The second protrusions 852 surround the control terminals 45 in a plan view. Each metal pin 452 of the control terminals 45 protrudes from each second protrusion 852. A resin portion 87 is disposed on each second protrusion 852. This configuration increases the creepage distance along the resin main surface 81 between adjacent control terminals 45. This is preferable for increasing the withstand voltage of adjacent control terminals 45.

[0147] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B spaced apart from each other in the x direction. The first conductive portion 2A is located further in the x2 direction than the second conductive portion 2B. The multiple semiconductor elements 10 include a first semiconductor element 10A bonded to the first conductive portion 2A and a second semiconductor element 10B bonded to the second conductive portion 2B. The multiple control terminals 45 include first control terminals 46A-46E and second control terminals 47A-47D. The first control terminals 46A-46E are supported by the first conductive portion 2A and are located between the first semiconductor element 10A and the input terminals 41, 42, etc. in the x direction. The second control terminals 47A-47D are located between the second semiconductor element 10B and the output terminal 44 in the x direction. According to this configuration, the plurality of control terminals 45 (first control terminals 46A-46E and second control terminals 47A-47D) are appropriately arranged in regions corresponding to the first semiconductor element 10A constituting the upper arm circuit and the second semiconductor element 10B constituting the lower arm circuit, respectively. This configuration is preferable in terms of miniaturizing the semiconductor module A1.

[0148] The sealing resin 8 has a plurality of first protrusions 851 protruding from the resin main surface 81. A first protrusion end surface 851a is formed at the tip of each of the first protrusions 851. The first protrusion end surfaces 851a of the plurality of first protrusions 851 are substantially parallel to the resin main surface 81 and are on the same plane (xy plane). With this configuration, in a device that uses power generated by the semiconductor module A1, a predetermined gap can be secured between the surface of a control circuit board on which the semiconductor module A1 is mounted and the resin main surface 81. As a result, even if various functional components are mounted on the surface of the control circuit board facing the semiconductor module A1, the functional components can be prevented from coming into undue contact with the sealing resin 8.

[0149] The semiconductor module A1 includes a conductive substrate 2 to which each semiconductor element 10 is bonded. With this configuration, heat generated by the passage of current through each semiconductor element 10 is transferred to the conductive substrate 2, and the heat transferred from each semiconductor element 10 is diffused by the conductive substrate 2. Therefore, the semiconductor module A1 has a package structure that is preferable for improving the heat dissipation performance of each semiconductor element 10.

[0150] In the semiconductor module A1, the conductive substrate 2 and the support substrate 3 are bonded to each other via a first conductive bonding material 71. The first conductive bonding material 71 includes a first layer 712 and a second layer 713. The first layer 712 is bonded to the conductive substrate 2 by solid-state diffusion of metal, and they are bonded in direct contact with each other at the bonding interface. The second layer 713 is bonded to the support substrate 3 by solid-state diffusion of metal, and they are bonded in direct contact with each other at the bonding interface. This configuration can increase the bonding strength between the conductive substrate 2 and the support substrate 3 compared to when the conductive substrate 2 and the support substrate 3 are bonded with a bonding material such as solder. Therefore, the semiconductor module A1 has a package structure that is favorable for preventing peeling between the conductive substrate 2 and the support substrate 3.

[0151] In the semiconductor module A1, each semiconductor element 10 and the conductive substrate 2 are bonded via a second conductive bonding material 72. The second conductive bonding material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is bonded to each semiconductor element 10 (rear electrode 15) by solid-state diffusion of metal, and the semiconductor elements 10 and the conductive substrate 2 are in direct contact with each other at the bonding interface. The fourth layer 723 is bonded to the conductive substrate 2 by solid-state diffusion of metal, and the semiconductor elements 10 and the conductive substrate 2 are in direct contact with each other at the bonding interface. This configuration can increase the bonding strength between each semiconductor element 10 and the conductive substrate 2 compared to when the semiconductor elements 10 and the conductive substrate 2 are bonded using a bonding material such as solder. Therefore, the semiconductor module A1 has a package structure that is preferable for preventing peeling between the semiconductor elements 10 and the conductive substrate 2.

[0152] In the semiconductor module A1 of this embodiment, the Young's modulus of the first base layer 711 in the first conductive bonding material 71 is smaller than the Young's modulus of each of the constituent materials of the first layer 712 and the second layer 713. With this configuration, when the first conductive bonding material 71 is bonded to the conductive substrate 2 and the support substrate 3 by solid-state diffusion, the relatively soft first base layer 711 relieves stress, thereby smoothing the bonded boundary. This allows the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3, to be more firmly bonded by solid-state diffusion.

[0153] Furthermore, in this embodiment, the thickness of the first base layer 711 is greater than the thickness of each of the first layer 712 and the second layer 713. This allows the pressure acting on the boundary between the first layer 712 and the conductive substrate 2 (rear surface bonding layer 23) and the boundary between the second layer 713 and the support substrate 3 (first bonding layer 321) to be more uniform during bonding by solid-state diffusion. This allows the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3, to be more firmly bonded electrically.

[0154] The constituent material of each of the first layer 712 and the second layer 713 contains silver. With this configuration, oxidation of the first layer 712 and the second layer 713 is suppressed during bonding by solid-phase diffusion using the first conductive bonding material 71, enabling good solid-phase diffusion bonding. Furthermore, because the back surface bonding layer 23 and the first bonding layer 321 bonded to the first layer 712 and the second layer 713 each contain silver, better solid-phase diffusion bonding is possible.

[0155] In this embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than the Young's modulus of each of the constituent materials of the third layer 722 and the fourth layer 723. With this configuration, when the second conductive bonding material 72 is bonded to the semiconductor element 10 (rear electrode 15) and the conductive substrate 2 by solid-state diffusion, the relatively soft second base layer 721 relieves stress and smooths the bonding boundary. As a result, the third layer 722 and the semiconductor element 10 (rear electrode 15), and the fourth layer 723 and the conductive substrate 2 are more firmly bonded by solid-state diffusion.

[0156] In this embodiment, the thickness of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723. This allows the pressure acting on the boundary between the third layer 722 and the semiconductor element 10 (rear surface electrode 15) and the boundary between the fourth layer 723 and the conductive substrate 2 (main surface bonding layer 22) to be more uniform during bonding by solid-phase diffusion. This allows the third layer 722 and the semiconductor element 10 (rear surface electrode 15), and the fourth layer 723 and the conductive substrate 2, to be more firmly bonded to each other.

[0157] The constituent material of each of the third layer 722 and the fourth layer 723 contains silver. With this configuration, oxidation of the third layer 722 and the fourth layer 723 is suppressed during bonding by solid-phase diffusion using the second conductive bonding material 72, enabling good solid-phase diffusion bonding. Furthermore, since the back surface electrode 15 and the main surface bonding layer 22 bonded to the third layer 722 and the fourth layer 723 each contain silver, better solid-phase diffusion bonding is possible.

[0158] The first conductive bonding material 71 has a configuration in which a first layer 712 and a second layer 713, which are Ag-plated layers, are laminated on the surfaces (both surfaces) of a first base layer 711 made of a sheet material containing Al. Similarly, the second conductive bonding material 72 has a configuration in which a third layer 722 and a fourth layer 723, which are Ag-plated layers, are laminated on the surfaces (both surfaces) of a second base layer 721 made of a sheet material containing Al. With this configuration, the first conductive bonding material 71 and the second conductive bonding material 72 can be easily prepared.

[0159] In the semiconductor module A1, an opening 63 is formed in the second conductive member 62. The opening 63 overlaps the main surface 201 (conductive substrate 2) in a plan view, but does not overlap each semiconductor element 10 in a plan view. With this configuration, a press pin 911 provided on the mold 91 can be inserted into the opening 63 during molding (a process for forming the sealing resin 8) in the manufacturing process of the semiconductor module A1. This allows the press pin 911 to press the conductive substrate 2 without interfering with the second conductive member 62, thereby suppressing warping of the support substrate 3 to which the conductive substrate 2 is bonded. This warping occurs, for example, such that both outer sides of the support substrate 3 in the y direction are positioned higher than the center side in the y direction. If warping occurs in the support substrate 3, there is a risk that the bonding strength between the conductive substrate 2 and the support substrate 3 will be reduced. Furthermore, during molding, resin leakage may cause part of the sealing resin 8 to be formed on the bottom surface 302, which may result in poor bonding of a heat dissipation member (e.g., a heat sink) that may be bonded to the bottom surface 302. Therefore, the semiconductor module A1 has a package structure that is preferable for improving the bonding strength between the conductive substrate 2 and the support substrate 3 by suppressing warping of the support substrate 3, and also for suppressing leakage of the sealing resin 8 to unintended positions.

[0160] The conductive substrate 2 includes a first conductive portion 2A to which multiple first semiconductor elements 10A are bonded and a second conductive portion 2B to which multiple second semiconductor elements 10B are bonded. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, and the first conductive portion 2A is positioned further in the x2 direction than the second conductive portion 2B. The second conductive member 62 is connected to the multiple second semiconductor elements 10B and the input terminals 42 and 43, and an opening 63 provided in the second conductive member 62 overlaps with the main surface 201 of the first conductive portion 2A in a planar view. With this configuration, even if the second conductive member 62 is made large in size in a planar view, the conductive substrate 2 can be held down by a press pin 911 provided in the mold 91 while avoiding interference with the second conductive member 62 when forming the sealing resin 8 (during molding). In addition, by increasing the size of the second conductive member 62 in a plan view, it is possible to suppress the parasitic resistance component of the second conductive member 62 (conductive member 6) that constitutes the path of the main circuit current.

[0161] The second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 located on opposite sides of the input terminal 41 in the y direction and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the second semiconductor elements 10B. The openings 63 are formed closer to the x2 direction in each of the first wiring portion 621 and the second wiring portion 622. As a result, the openings 63 are provided near two outer corners of the conductive substrate 2 (first conductive portion 2A) in the y direction in a plan view. Therefore, the openings 63 are provided near two outer corners of the support substrate 3 that supports the conductive substrate 2 (first conductive portion 2A) in the y direction in a plan view. With this configuration, the size of the second conductive member 62 in a plan view can be secured to be relatively large, and when the sealing resin 8 is formed (molded), the pressing pins 911 provided on the mold 91 can be inserted into the openings 63 to press down on the vicinity of the corners on both outer sides in the y direction of the conductive substrate 2 (first conductive portion 2A). As described above, warping of the support substrate 3 to which the conductive substrate 2 is bonded occurs so that both outer sides in the y direction of the support substrate 3 are positioned higher than the center side in the y direction, but with the above configuration, warping of the support substrate 3 during molding can be effectively suppressed.

[0162] In this embodiment, the conductive members 6 (first conductive member 61 and second conductive member 62) are made of metal plate material. This makes it possible to easily form the opening 63 in the second conductive member 62. Furthermore, the conductive members 6 (first conductive member 61 and second conductive member 62) made of metal plate material can easily be made into various shapes and sizes, and by ensuring a sufficient bonding area with other parts, the reliability of the bonding parts with other parts can be improved.

[0163] Recesses 201a are formed in portions of main surface 201 of conductive substrate 2 (first conductive portion 2A) that overlap with each opening 63 in a plan view. Each recess 201a is a trace of pressure applied to main surface 201 by press pins 911 during molding. In this embodiment, by devising the arrangement of second conductive member 62 and the openings 63 formed therein, it is possible to use press pins 911 to press conductive substrate 2 (first conductive portion 2A) in the appropriate position during molding while avoiding interference with functional elements such as semiconductor element 10.

[0164] The sealing resin 8 has a resin void 86 that extends from the resin main surface 81 to the recess 201a. The resin void 86 is tapered, and its cross-sectional area decreases from the resin main surface 81 toward the recess 201a. This resin void 86 is formed during molding (when the sealing resin 8 is formed). After molding, the surface of the recess 201a on the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. In this embodiment, the resin void 86 is filled with a resin filling portion 88 so as to fill the resin void 86. This configuration prevents foreign matter (including moisture) from entering the recess 201a exposed from the sealing resin 8. The semiconductor module A1 having the above configuration is preferable in terms of durability and reliability.

[0165] In this embodiment, each opening 63 formed in the second conduction member 62 (conductive member 6) is a through-hole penetrating in the z direction. With this configuration, in the second conduction member 62 (conductive member 6) that constitutes the path of the main circuit current, bias in the current path due to the formation of the openings 63 is suppressed.

[0166] The semiconductor module A1 includes conductive members 6. The conductive members 6 form a path for a main circuit current switched by each semiconductor element 10. The conductive members 6 include first conductive members 61 connected to each first semiconductor element 10A and second conductive members 62 connected to each second semiconductor element 10B. The conductive members 6 (each of the first conductive members 61 and the second conductive members 62) are made of a metal plate material. The main circuit current may be relatively large. In this case, suppressing the parasitic resistance component in the conductive members 6, which are the path for the main circuit current, is preferable for reducing the power consumption of the semiconductor module A1. Therefore, in the semiconductor module A1, as described above, the parasitic resistance component in the conductive members 6 is suppressed by forming the conductive members 6 from a metal plate material rather than a bonding wire. In other words, the semiconductor module A1 has a package structure that is preferable for suppressing the parasitic resistance component.

[0167] In the semiconductor module A1, each first semiconductor element 10A has a rectangular shape in a plan view, and the four corners of the first semiconductor element 10A do not overlap the second conductive member 62 in a plan view. This configuration allows for visual inspection of whether each first semiconductor element 10A is properly bonded before the step of forming the sealing resin 8 during the manufacturing process of the semiconductor module A1. That is, the semiconductor module A1 allows visual inspection of the bonded state of each first semiconductor element 10A during manufacturing (e.g., the state shown in FIG. 23 ), making it possible to determine whether each first semiconductor element 10A is properly bonded. For example, by measuring the distances between the four corners of the first semiconductor element 10A using laser distance measurement, it can be determined that the first semiconductor element 10A is properly bonded if the difference in the measured distances between the four corners is small. Therefore, since the semiconductor module A1 allows visual inspection during manufacturing, it has a package structure that is preferable for improving reliability. When performing the visual inspection, it is sufficient that at least three of the four corners of the first semiconductor element 10A can be confirmed in a planar view, so that the three corners do not overlap the second conductive member 62. Similarly, as shown in FIG. 5, the four corners of each second semiconductor element 10B do not overlap the second conductive member 62 in a planar view, so that a visual inspection can be performed on each second semiconductor element 10B to determine whether it is properly bonded before the step of forming the sealing resin 8 in the manufacturing process of the semiconductor module A1. The visual inspection may be an automatic visual inspection using imaging and image processing.

[0168] The second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 that are arranged on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623 and overlaps with the multiple first semiconductor elements 10A in a plan view. The second conductive member 62 including the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps a wide range of the main surface 201 in a plan view and is relatively large in size in a plan view. Increasing the size of the second conductive member 62 in a plan view in this manner is preferable in terms of suppressing the parasitic resistance component of the second conductive member 62 (conductive member 6) that forms the path of the main circuit current.

[0169] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in a plan view, and the second side 192 is an edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in a plan view, and the fourth side 194 is an edge on the y1 direction side in a plan view. Because each first semiconductor element 10A has a rectangular shape in a plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 form approximately right angles in a plan view. On the other hand, the fourth wiring portion 624 (first strip portion 625) of the second conductive member 62 has a first edge 627 and a second edge 628. The first edge 627 is an edge of the fourth wiring portion 624 located in the x2 direction and is located further in the x1 direction than the first side 191 in a plan view. The first edge 627 also extends in the y direction from at least the third side 193 to the fourth side 194. This prevents two corners 171, 172 of each first semiconductor element 10A on the x2 direction side from overlapping with the second conductive member 62 in a plan view. The second edge 628 is an edge of the fourth wiring portion 624 (first strip portion 625) located in the x1 direction and is located further in the x2 direction than the second side 192 in a plan view. The second edge 628 also extends in the y direction from at least the third side 193 to the fourth side 194. As a result, in a plan view, two corners 173, 174 of each first semiconductor element 10A on the x1 direction side do not overlap the second conductive member 62. With this configuration, by ensuring an area of ​​the fourth wiring portion 624 that overlaps with each first semiconductor element 10A in a plan view, the size of the second conductive member 62 in a plan view is increased, while the four corners of the first semiconductor element 10A in a plan view do not overlap the second conductive member 62. Therefore, the parasitic resistance component of the second conductive member 62 (conductive member 62) is effectively suppressed, and it is possible to perform a visual inspection of the bonding state of each first semiconductor element 10A during the manufacture of the semiconductor module A1.

[0170] The fourth wiring portion 624 (first strip portion 625) has multiple convex regions 625a that protrude in the z2 direction further than other portions. Each of the convex regions 625a overlaps a corresponding one of the first semiconductor elements 10A in plan view. By configuring the fourth wiring portion 624 to have multiple convex regions 625a, it is possible to prevent the fourth wiring portion 624 from coming into inappropriate contact with the first conductive member 61 bonded onto the first semiconductor element 10A.

[0171] The third wiring portion 623 has a plurality of recessed regions 623a that protrude in the z1 direction further than other portions. Each recessed region 623a is bonded to one of the plurality of second semiconductor elements 10B. This configuration makes it possible to ensure that the third wiring portion 623 (second conductive member 62) has a large size in a plan view while properly conducting the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B.

[0172] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. This configuration prevents the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be made smaller.

[0173] The semiconductor module A1 includes a conductive substrate 2, two input terminals 41 and 42 (or two input terminals 41 and 43), an output terminal 44, and a conductive member 6. The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B arranged in the x direction in a plan view. A plurality of first semiconductor elements 10A are electrically connected to the first conductive portion 2A. A plurality of second semiconductor elements 10B are electrically connected to the second conductive portion 2B. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are respectively arranged at intervals along the y direction. The two input terminals 41 and 42 (or the two input terminals 41 and 43) are located in the x2 direction with respect to the first conductive portion 2A. The input terminal 41 is a positive electrode and is connected to the first conductive portion 2A. The input terminal 42 (or the input terminal 43) is a negative electrode. The output terminal 44 is located in the x1 direction with respect to the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 connected between the plurality of first semiconductor elements 10A and the second conductive portion 2B, and a second conductive member 62 connected between the plurality of second semiconductor elements 10B and the input terminal 42 (or the input terminal 43). With this configuration, the path of the main circuit current switched by the plurality of semiconductor elements 10 (the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) is configured to extend along the x-direction in a plan view, and the axis of symmetry (see the auxiliary line L1 in FIG. 5 ) in the planar structure of the semiconductor module A1 is configured to extend along the y-direction in a plan view. In other words, the axis of symmetry and the path of the main circuit current are perpendicular to each other. This reduces the difference in the current paths to the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B in the main circuit current input through the two input terminals 41 and 42 (or the two input terminals 41 and 43) and output through the output terminal 44. That is, variations in parasitic inductance components and current variations in the semiconductor module A1 can be suppressed. Therefore, the semiconductor module A1 has a preferable package structure for equalizing the parasitic inductance components in the paths of the main circuit current and the amount of current to each semiconductor element 10.

[0174] The first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the x direction. The first semiconductor elements 10A and the second semiconductor elements 10B are aligned along the y direction. Therefore, the alignment direction of the semiconductor elements 10 is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. This prevents differences in the length of the current path of the first main circuit current among the three first semiconductor elements 10A when multiple switching elements are connected in parallel as in this embodiment. This reduces parasitic resistance components in the conductive member 6, which is the path of the main circuit current.

[0175] The region through which the first main circuit current flows and the region through which the second main circuit current flows are configured to overlap in a plan view. That is, the second conductive member 62, which connects the output terminal 44 to the negative terminals, the first input terminal 42 and the second input terminal 43, to allow the second main circuit current to flow, is disposed above the region through which the first main circuit current flows (the first conductive portion 2A, the first conductive member 61, and the second conductive portion 2B). The direction through which the first main circuit current flows is opposite to the direction through which the second main circuit current flows. Therefore, with this arrangement, the magnetic fields generated by the first main circuit current and the second main circuit current can cancel each other out, thereby reducing inductance.

[0176] The semiconductor module A1 of this embodiment includes two input terminals 42, 43. These input terminals 42, 43 are both negative polarities and sandwich the input terminal 41 in the y direction. A second conductive member 62 is connected to the two input terminals 42, 43. This configuration makes it possible to further reduce variation in the path of the current flowing from the output terminal 44 to the input terminals 42, 43 via each second semiconductor element 10B and the second conductive member 62.

[0177] In the semiconductor module A1, the second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 that are arranged on opposite sides of the input terminal 41 in the y direction and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623 and is connected to all of the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623. The second conductive member 62, which includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624, overlaps a wide area of ​​the main surface 201 in a plan view, thereby ensuring a large size in a plan view. This configuration appropriately reduces variations in the paths of currents flowing from the output terminal 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conductive member 62. Therefore, the semiconductor module A1 of this embodiment is preferable in terms of equalizing parasitic inductance components in the paths of the main circuit currents (second conductive member 62) and equalizing the amounts of currents to the second semiconductor elements 10B.

[0178] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps with multiple first semiconductor elements 10A in a planar view. The fourth wiring portion 624 (first strip portion 625) has multiple convex regions 625a that protrude in the z2 direction more than other portions. Each convex region 625a overlaps with a corresponding first semiconductor element 10A in a planar view. This configuration ensures that the size of the fourth wiring portion 624 (second conductive member 62) is large in a planar view, while preventing the fourth wiring portion 624 from coming into inappropriate contact with the first conductive member 61 bonded onto the first semiconductor element 10A.

[0179] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x direction. This configuration prevents the size in the y direction of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged from increasing, thereby enabling the semiconductor module A1 to be made smaller.

[0180] 30 to 32 show a semiconductor module according to Embodiment 2. In a semiconductor module A2 of this embodiment, the configuration of the sealing resin 8 is different from that of the semiconductor module A1 of the above embodiment.

[0181] In this embodiment, the sealing resin 8 does not include a second protrusion 852. As shown in FIG. 32, the resin main surface 81 of the sealing resin 8 is flush with the upper surface of the upper flange of the holder 451. As a result, a portion of each holder 451 (the upper surface of the upper flange) is exposed from the sealing resin 8. The resin portion 87 is disposed on the upper surface of the upper flange of each holder 451 and on the resin main surface 81 surrounding it. The resin portion 87 covers the portion of the holder 451 (the upper surface of the upper flange) exposed from the sealing resin 8 and a portion of the metal pin 452 in each control terminal 45.

[0182] The semiconductor module A2 of this embodiment also provides the same effects as the semiconductor module A1 of the above embodiment.

[0183] 33 to 35 show a semiconductor module according to Embodiment 3. In a semiconductor module A3 of this embodiment, the configuration of a resin part 87 is different from that of the semiconductor module A2 of the above embodiment.

[0184] In this embodiment, the sealing resin 8 does not include a second protrusion 852, and as shown in Fig. 35, the resin main surface 81 of the sealing resin 8 is flush with the upper surface of the upper flange of the holder 451. As a result, similar to the semiconductor module A2 shown in Fig. 32, a part of each holder 451 (the upper surface of the upper flange) is exposed from the sealing resin 8. Meanwhile, in this embodiment, the resin portion 87 is arranged on the upper surface of the upper flange of the holder 451 for each of the plurality of second control terminals 47A to 47D, and on the resin main surface 81 continuous thereto. Furthermore, the resin portion 87 is arranged on the upper surface of the upper flange of the holder 451 for each of the plurality of first control terminals 46A to 46E, and on the resin main surface 81 continuous thereto. In the semiconductor module A2 described above (see FIG. 32), a plurality of resin portions 87 are arranged corresponding to the holders 451 of the plurality of control terminals 45. However, in the present embodiment, one resin portion 87 is provided corresponding to the plurality of first control terminals 46A-46E, and another resin portion 87 is provided corresponding to the plurality of second control terminals 47A-47D. For the plurality of first control terminals 46A-46E, one resin portion 87 covers a portion of each holder 451 (upper surface of the upper end flange) exposed from the sealing resin 8 and a portion of each metal pin 452. For the plurality of second control terminals 47A-47D, the other resin portion 87 covers a portion of each holder 451 (upper surface of the upper end flange) exposed from the sealing resin 8 and a portion of each metal pin 452.

[0185] The semiconductor module A3 of this embodiment also provides the same effects as the semiconductor module A1 of the above embodiment.

[0186] 36 and 37 show a semiconductor module according to Embodiment 4. In a semiconductor module A4 of this embodiment, the configuration of the metal pins 452 in each of the plurality of control terminals 45 is different from that of the semiconductor module A1 of the above embodiment.

[0187] In the present embodiment, in each control terminal 45 (each of the first control terminals 46A to 46E and each of the second control terminals 47A to 47D), the metal pin 452 has a cushion portion 452a. The cushion portion 452a absorbs shock caused by vibration and is exposed from the sealing resin 8. In the example shown in FIGS. 36 and 37, the cushion portion 452a is provided at a position closer to the resin portion 87 in the longitudinal direction of the metal pin 452, and is configured as a portion that is bent in a substantially U-shape in a plane including the z direction.

[0188] The semiconductor module A4 of this embodiment also achieves the same effects as the semiconductor module A1 of the above embodiment. Furthermore, in the semiconductor module A4, each metal pin 452 (each control terminal 45) has a cushion portion 452a. With this configuration, even when the semiconductor module A4 is mounted in an electronic device (e.g., an automotive device) that may generate relatively large vibrations, the cushion portion 452a can absorb the shock caused by the vibrations, thereby preventing damage to the metal pins 452 (control terminals 45). The specific configuration of the cushion portion 452a is not limited to the example shown in the drawings. For example, the cushion portion 452a may be configured by providing an L-shaped bent portion in the middle of the metal pin 452.

[0189] 38 to 40 show a semiconductor module according to Embodiment 5. In a semiconductor module A5 of this embodiment, the configuration of the second conductive member 62 is different from that of the semiconductor module A1 of the above embodiment.

[0190] In this embodiment, the area occupied by the fourth wiring portion 624 of the second conductive member 62 differs from the above-described embodiment. Specifically, the dimension in the x direction of the first strip portion 625 is larger than that of the semiconductor module A1. As shown in FIGS. 39 and 40, the position of the second edge 628 of the first strip portion 625 is located closer to the x1 direction than the semiconductor module A1. As shown in FIG. 40, the second edge 628 is located further in the x1 direction than the second side 192 of the first semiconductor element 10A in a plan view. As a result, the two corners of each first semiconductor element 10A on the x1 direction side overlap the second conductive member 62 (first strip portion 625) in a plan view.

[0191] The semiconductor module A5 of this embodiment also achieves the same effects as the semiconductor module A1 of the above embodiment. Furthermore, in the semiconductor module A5, the size of the first strip portion 625 (second conductive member 62) of the fourth wiring portion 624 in a plan view can be made larger. This is preferable in terms of reducing the parasitic inductance component.

[0192] 41 and 42 show a semiconductor module according to Embodiment 6. A semiconductor module A6 of this embodiment differs from the semiconductor module A1 of the above-described embodiment mainly in the configuration of the second conductive member 62.

[0193] In the semiconductor module A6, unlike the above-described embodiments, the second conductive member 62 does not have an opening 63. When manufacturing the semiconductor module A6, the mold 91 used to form (mold) the sealing resin 8 does not have a pressing pin 911. As a result, as shown in FIG. 42 , no resin void 86 is formed in the sealing resin 8, and no recess 201a is formed in the main surface 201 of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B). Furthermore, since no resin void 86 is formed in the sealing resin 8, the semiconductor module A6 of this embodiment does not have the resin filling portion 88 used to fill the resin void 86 in the above-described embodiments.

[0194] The semiconductor module A6 of this embodiment also provides the same effects as the semiconductor module A1 of the above embodiment.

[0195] The semiconductor module according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor module according to the present disclosure can be freely modified in various ways.

[0196] The present disclosure includes the configurations described in the following appendices.

[0197] Appendix 1. a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing the opposite side to the main surface; a semiconductor element electrically connected to the main surface and having a switching function; a control terminal for controlling the semiconductor element; a sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side to the resin main surface, the sealing resin covering the conductive substrate, the semiconductor element, and a part of the control terminal; The control terminal protrudes from the resin main surface and extends along the thickness direction. Appendix 2. the sealing resin has a resin side surface that is connected to both the resin main surface and the resin back surface and is sandwiched between the resin main surface and the resin back surface in the thickness direction, a power supply terminal protruding from the resin side surface, electrically connected to the semiconductor element, and handling a power supply voltage; 2. The semiconductor module according to claim 1, wherein the power terminal includes a bonding surface facing one side in the thickness direction. Appendix 3. 3. The semiconductor module according to claim 2, wherein the power supply terminals include a first power supply terminal to which a first power supply voltage is input and a second power supply terminal to which a second power supply voltage is output. Appendix 4. 4. The semiconductor module according to claim 1, further comprising a control terminal support body having an insulating layer interposed between the main surface and the control terminal. Appendix 5. The semiconductor module described in Appendix 4, wherein the control terminal support includes the insulating layer, a first metal layer stacked on one side of the insulating layer in the thickness direction, and a second metal layer stacked on the other side of the insulating layer in the thickness direction and joined to the conductive substrate so as to face the main surface. Appendix 6. 6. The semiconductor module according to claim 5, wherein the control terminal is bonded to the first metal layer via a conductive bonding material. Appendix 7. Further comprising a conductive wire; the semiconductor element has a main surface facing the same side as the main surface, a back surface facing the opposite side to the main surface, and a gate electrode disposed on the main surface; 7. The semiconductor module of claim 6, wherein the conductive wire is connected to the gate electrode and the first metal layer. Appendix 8. The semiconductor module described in Appendix 6 or 7, wherein the control terminal includes a conductive cylindrical holder joined to the first metal layer, and a metal pin pressed into the holder and extending in the thickness direction. Appendix 9. 9. The semiconductor module according to claim 8, wherein a portion of the holder is exposed from the sealing resin on one side in the thickness direction. Appendix 10. Further, a resin portion bonded to the sealing resin is provided, 10. The semiconductor module according to claim 9, wherein the resin portion covers a portion of the holder exposed from the sealing resin and a portion of the metal pin. Appendix 11. the conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other and disposed on one side and the other side in a first direction that is perpendicular to the thickness direction, the first power supply terminal includes a first input terminal located on one side of the first semiconductor element in the first direction and connected to the first conductive portion, and a second input terminal located on one side of the first semiconductor element in the first direction and connected to the second semiconductor element, the second power supply terminal is an output terminal located on the other side in the first direction with respect to the second semiconductor element and connected to the second conductive portion, the control terminal includes a first control terminal that controls the first semiconductor element and a second control terminal that controls the second semiconductor element; the first control terminal is supported by the first conductive portion and is disposed between the first semiconductor element and the first input terminal and the second input terminal in the first direction; The semiconductor module according to claim 3, wherein the second control terminal is supported by the second conductive portion and is disposed between the second semiconductor element and the output terminal in the first direction. a plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to both the thickness direction and the first direction; a plurality of the first control terminals arranged at intervals in the second direction; a plurality of the second semiconductor elements arranged at intervals in the second direction; The semiconductor module described in Appendix 11, further comprising: a plurality of the second control terminals arranged at intervals in the second direction. Appendix 13. the sealing resin has a plurality of protruding portions protruding from the resin main surface and each having a protruding end face formed at a tip thereof; 13. The semiconductor module according to any one of claims 1 to 12, wherein the protruding end faces of the plurality of protruding portions are parallel to the resin main surface and on the same plane. Appendix 14. 14. The semiconductor module according to claim 1, wherein the control terminal has a cushion portion for absorbing shock caused by vibration. Appendix 15. 15. The semiconductor module according to claim 14, wherein the cushion portion is exposed from the sealing resin. Appendix 16. a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing the opposite side to the main surface; a semiconductor element electrically connected to the main surface and having a switching function; a control terminal for controlling the semiconductor element; a sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side to the resin main surface, the sealing resin covering the conductive substrate, the semiconductor element, and a part of the control terminal; The control terminal protrudes from the resin main surface and extends along the thickness direction. Appendix 17. 17. The semiconductor module of claim 16, further comprising a control terminal support interposed between the main surface and the control terminal and having an insulating layer. Appendix 18. The semiconductor module described in Appendix 17, wherein the control terminal support includes the insulating layer, a first metal layer stacked on one side of the insulating layer in the thickness direction, and a second metal layer stacked on the other side of the insulating layer in the thickness direction and joined to the conductive substrate so as to face the main surface. Appendix 19. 19. The semiconductor module of claim 18, wherein the control terminal is bonded to the first metal layer via a conductive bonding material. Appendix 20. the semiconductor element has a main surface facing the same side as the main surface, a back surface facing the opposite side to the main surface, and a gate electrode disposed on the main surface; 20. The semiconductor module of claim 19, wherein a conductive wire is connected to the gate electrode and the first metal layer. Appendix 21. 21. The semiconductor module of claim 19, wherein the control terminal includes a conductive cylindrical holder joined to the first metal layer, and a metal pin pressed into the holder and extending in the thickness direction. Appendix 22. 22. The semiconductor module according to claim 21, wherein a portion of the holder is exposed from the sealing resin on one side in the thickness direction. Appendix 23. Further, a resin portion bonded to the sealing resin is provided, 23. The semiconductor module according to claim 22, wherein the resin portion covers a portion of the holder exposed from the sealing resin and a portion of the metal pin. Appendix 24. the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other when viewed in the thickness direction and disposed on one side and the other side in a first direction perpendicular to the thickness direction, the semiconductor element includes a first semiconductor element electrically connected to the first conductive portion and a second semiconductor element electrically connected to the second conductive portion; a first input terminal located on one side in the first direction with respect to the first semiconductor element and connected to the first conductive portion; a second input terminal located on one side of the first semiconductor element in the first direction and connected to the second semiconductor element; an output terminal located on the other side in the first direction with respect to the second semiconductor element and connected to the second conductive portion, the control terminal includes a first control terminal that controls the first semiconductor element and a second control terminal that controls the second semiconductor element; the first control terminal is supported by the first conductive portion and is disposed between the first semiconductor element and the first input terminal and the second input terminal in the first direction; 24. A semiconductor module according to any one of claims 16 to 23, wherein the second control terminal is supported by the second conductive portion and is arranged between the second semiconductor element and the output terminal in the first direction. Appendix 25. a plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to both the thickness direction and the first direction; a plurality of the first control terminals arranged at intervals in the second direction; a plurality of the second semiconductor elements arranged at intervals in the second direction; The semiconductor module described in Appendix 24, further comprising: a plurality of the second control terminals arranged at intervals in the second direction. Appendix 26. the sealing resin has a plurality of protruding portions protruding from the resin main surface and each having a protruding end face formed at a tip thereof; 26. The semiconductor module according to claim 16, wherein the protruding end faces of the plurality of protruding portions are parallel to the resin main surface and on the same plane. Appendix 27. 27. The semiconductor module according to any one of claims 16 to 26, wherein the control terminal has a cushion portion for absorbing shock caused by vibration. Appendix 28. 28. The semiconductor module according to claim 27, wherein the cushion portion is exposed from the sealing resin. [Explanation of symbols]

[0198] A1, A2, A3, A4, A5, A6: Semiconductor modules 10: Semiconductor element 10A: First semiconductor element 10B: Second semiconductor element 101: Element main surface 102: Back surface of element 11: First principal surface electrode (gate electrode) 12: Second principal surface electrode (source electrode) 13: Third principal surface electrode 14: Fourth principal surface electrode 15: Back surface electrode (drain electrode) 16: 5th main surface electrode 171,172,173,174: Corner 181, 182, 183, 184: Corners 191: First side 192: Side 2 193: Side 3 194: Fourth side 2: Conductive substrate 2A: First conductive part 2B: Second conductive part 201: Main surface 201a: Recess 201b: recess edge 202: back surface 21: Base material 22: Main surface bonding layer 23: Back surface bonding layer 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: Part 1 32B: Part 2 321: First bonding layer 33: Second metal layer 41: First input terminal 411: Input side joint surface 412: Input side surface 413: Tip surface 414: Side 42: Second input terminal 421: Input side joint surface 422: Input side surface 423: Tip surface 424: Lateral surface 43: Third input terminal 431: Input side joint surface 432: Input side surface 433: Tip surface 434: Side 44: Output terminal 441: Output side joint surface 442: Output side surface 443: Tip surface 444: Lateral surface 45: Control terminal 451: Holder 452: Metal pin 452a: Cushion part 459: Conductive bonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C, 47D: Second control terminal 5: Control terminal support 51: Insulating layer 52: 1st metal layer 521: 1st part 522: Part 2 523: Part 3 524: Part 4 525: Part 5 53: Second metal layer 59: Bonding material 6: Conductive member 601: Part 1 61: First conductive member 61h: Opening 62: Second conductive member 62A: First part 62B: 2nd part 621: 1st wiring part 622: Second wiring section 623: Third wiring section 623a: Concave area 623h: Opening 624: Fourth wiring section 625: First strip section 625a: Convex area 625h: Opening 626: Second band portion 627: First edge 628: Second edge 63: Opening 69: Conductive bonding material 71: First conductive bonding material 711: 1st base layer 712: 1st layer 713: Second layer 72: Second conductive adhesive material 721: 2nd base layer 722: 3rd layer 723: 4th layer 731: Wire 731a: First wire 731b: Second wire 732, 733, 734, 735: Wire 8: Sealing resin 81: Resin main surface 82: Resin back surface 831, 832: Resin side surface 832a: Recess 833, 834: Resin side surface 851: First protrusion 851a: First protrusion end surface 851b: Recess 851c: Inner wall surface 852: Second protrusion 86: Resin cavity 861: Edge of resin gap 87: Resin part 88: Resin filling section 91: Mold 911: Retaining pin

Claims

1. A semiconductor module having a half-bridge type circuit, a support substrate including a first insulating layer, a first metal layer, and a second metal layer; a first conductive portion and a second conductive portion joined to the support substrate and made of a metal plate-like member; a first semiconductor element and a second semiconductor element which respectively constitute an upper arm circuit and a lower arm circuit in the half-bridge type circuit and have a switching function; a first wiring board disposed on the first conductive portion and conducting to the first semiconductor element, and a second wiring board disposed on the second conductive portion and conducting to the second semiconductor element, each of the first wiring board and the second wiring board having a second insulating layer and a third metal layer formed on an upper surface of the second insulating layer and including a plurality of wiring portions spaced apart and insulated from one another; a first input terminal disposed on one side of the first semiconductor element and the first conductive portion in a first direction perpendicular to a thickness direction; a second input terminal and a third input terminal that are arranged on one side in the first direction with respect to the first semiconductor element and the first conductive portion, and that are arranged on opposite sides of the first input terminal in a second direction that is orthogonal to the thickness direction and the first direction; at least one output terminal arranged on the other side in the first direction with respect to the second semiconductor element and the second conductive portion; a conductive member constituting a part of a first main circuit current path which is a path for a first main circuit current flowing between the first input terminal and the output terminal, and a part of a second main circuit current path which is a path for a second main circuit current flowing between the output terminal and the second input terminal and between the output terminal and the third input terminal; a sealing resin having a resin main surface and a resin back surface facing the opposite side to the resin main surface, and covering a part of the support substrate, the first conductive portion, the second conductive portion, the first semiconductor element, the second semiconductor element, a part of the first input terminal, a part of the second input terminal, a part of the third input terminal, a part of the output terminal, the first wiring board, the second wiring board, and the conductive member; a semiconductor module, wherein the plurality of wiring portions in the first wiring substrate and the plurality of wiring portions in the second wiring substrate are provided with connection portions that are exposed from the main resin surface of the sealing resin and that are electrically connected to a control system circuit board.

2. the first main circuit current path is formed between the first input terminal and the output terminal via the first semiconductor element, the second main circuit current path is configured between the output terminal and the second input terminal and between the output terminal and the second input terminal and the third input terminal via the second semiconductor element; 2. The semiconductor module according to claim 1, wherein the first main circuit current path and the second main circuit current path are respectively arranged symmetrically with respect to a center line that passes through a center of the first input terminal and extends in the first direction, as viewed in the thickness direction.

3. 3. The semiconductor module according to claim 2, wherein the conductive members are arranged symmetrically with respect to a center line that passes through a center of the first input terminal and extends in the first direction, as viewed in the thickness direction.

4. The semiconductor module according to claim 3 , wherein the region through which the first main circuit current flows and the region through which the second main circuit current flows are configured to overlap in a plan view.

5. the first semiconductor element has a first element main surface, a first element back surface facing the opposite side to the first element main surface, and a first gate electrode disposed on the first element main surface; the second semiconductor element has a second element main surface, a second element back surface facing the opposite side to the second element main surface, and a second gate electrode disposed on the second element main surface; a conductive wire is connected to the third metal layer of the first wiring substrate and the first gate electrode of the first semiconductor element; 2. The semiconductor module according to claim 1, wherein a conductive wire is connected to the third metal layer of the second wiring substrate and the second gate electrode of the second semiconductor element.

6. 6. The semiconductor module according to claim 1, wherein the first wiring board and the second wiring board are made of DBC substrates.

7. The semiconductor module according to claim 1 , comprising: a plurality of the first semiconductor elements arranged at intervals in the second direction; and a plurality of the second semiconductor elements arranged at intervals in the second direction.

Images