Photoelectric conversion device and apparatus

Abstract

The present invention provides a photoelectric conversion apparatus that reduces deterioration of a gate insulating film and is advantageous in reducing failures or manufacturing defects.SOLUTION: A first wiring structure, a second wiring structure, and a second semiconductor substrate that generates a signal to be applied to a gate electrode of the transistor and supplies the signal to the transistor are stacked in this order, the first semiconductor substrate includes a protection element and a plurality of the pixels arranged in a row direction and a column direction, the signal is supplied from the second semiconductor substrate to a gate electrode of the transistor, the first wiring structure includes a first wiring that extends in at least one of the row direction and the column direction so as to overlap two or more pixels in a plan view and through which the signal passes, and the first wiring and the protective element are connected to each other.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to photoelectric conversion devices and equipment. [Background technology]

[0002] In recent years, CMOS image sensors suitable for high-speed readout have been widely used in photoelectric conversion devices such as digital still cameras and digital video cameras. For example, Patent Document 1 discloses a photoelectric conversion device in which a first substrate including a first semiconductor substrate and a first wiring structure is stacked with a second substrate including a second wiring structure and a second semiconductor substrate. Patent Document 1 also discloses that a circuit disposed on the first substrate and a circuit disposed on the second substrate are connected via a metal junction. Patent Document 1 also discloses that a protective element is disposed on at least one of the first substrate and the second substrate, and the protective element is electrically connected to the metal junction, thereby protecting the circuit connected to the metal junction from a large current generated during the process of joining the first substrate and the second substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-125491 Summary of the Invention [Problem to be solved by the invention]

[0004] During the process of forming the first component, the gate insulating film of the transistor included in the first substrate may deteriorate, preventing the supply of potential from the second substrate to the transistor, which may result in a malfunction of the photoelectric conversion device or a manufacturing defect; however, this is not considered in Patent Document 1.

[0005] According to the present invention, it is possible to reduce the deterioration of the gate insulating film and reduce the occurrence of breakdowns or manufacturing defects in photoelectric conversion devices. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising: a first semiconductor substrate having pixels including a photoelectric conversion element and a transistor; a first wiring structure; a second wiring structure; and a second semiconductor substrate that generates a signal to be applied to a gate electrode of the transistor and supplies the signal to the transistor, stacked in this order; the first semiconductor substrate has a protection element and a plurality of the pixels arranged in row and column directions; the signal is supplied from the second semiconductor substrate to the gate electrode of the transistor; the first wiring structure extends in at least one of the row and column directions so as to overlap with two or more pixels in a planar view; and has a first wiring through which the signal passes; and the first wiring is connected to the protection element.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising: a first semiconductor substrate including pixels each including a photoelectric conversion element and a transistor, and stacked on a second semiconductor substrate, the first semiconductor substrate having a protection element and a plurality of the pixels arranged in a row direction and a column direction; and a first wiring structure having a first wiring extending in at least one of the row direction and the column direction so as to overlap with two or more pixels in a planar view, and through which a signal supplied to a gate electrode of the transistor passes, wherein the first wiring and the protection element are connected, and the first wiring and the gate electrode of the transistor are connected.

[0008] According to another disclosure of the present specification, there is provided a method for manufacturing a photoelectric conversion device, comprising: a step of preparing a first substrate having a first semiconductor substrate and a first wiring structure stacked in this order; a step of preparing a second substrate having a second wiring structure and a second semiconductor substrate stacked in this order; and a step of bonding the first substrate and the second substrate together so that the first wiring structure and the second wiring structure face each other, wherein in the step of preparing the first substrate, the method comprises: a step of preparing a first semiconductor substrate having a protection element and a plurality of pixels arranged in row and column directions, each pixel including a photoelectric conversion element and a transistor; and a step of forming first wiring included in the first wiring structure, the first wiring extending in at least one of the row and column directions so that the protection element and the first wiring, and the gate electrode of the transistor and the first wiring are connected to each other. [Effects of the Invention]

[0009] An object of the present invention is to provide a photoelectric conversion device that reduces deterioration of the gate insulating film and is advantageous in reducing breakdowns or manufacturing defects. [Brief explanation of the drawings]

[0010] [Figure 1] Schematic diagram illustrating a photoelectric conversion device according to the first embodiment. Chip drawing. [Figure 2] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 3] FIG. 1 is a plan view schematically illustrating pixels of a photoelectric conversion device according to a first embodiment; [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a photoelectric conversion device according to a first embodiment; [Figure 5] FIG. 10 is a schematic top view illustrating another example of the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 10 is a schematic top view illustrating another example of the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 1 is a top view illustrating a pad and a pixel region of a photoelectric conversion device according to a first embodiment. [Figure 8]1 is a cross-sectional view illustrating a photoelectric conversion device according to a first embodiment; [Figure 9] Circuit diagram of a protection element of a photoelectric conversion device according to a first embodiment [Figure 10] Schematic cross-sectional view illustrating a photoelectric conversion device according to a second embodiment. [Figure 11] 10 is a cross-sectional view illustrating a photoelectric conversion device according to a third embodiment. [Figure 12] FIG. 10 is a process flow diagram illustrating a photoelectric conversion device according to a third embodiment. [Figure 13] FIG. 10 is a schematic diagram illustrating a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Each embodiment will be described below with reference to the drawings. Note that the following embodiments do not limit the scope of the claimed invention. Although the embodiments describe multiple features, not all of these features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar components are given the same reference numerals, and redundant description will be omitted. Furthermore, each embodiment described below will focus on an imaging sensor (imaging device) as an example of a photoelectric conversion device. However, each embodiment is not limited to imaging sensors and can be applied to other examples of photoelectric conversion devices. For example, these include distance measurement devices (devices for measuring distance using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light, etc.), etc.

[0012] In this specification, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) are used as necessary. The use of these terms is for the purpose of facilitating understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0013] In this specification, "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. Furthermore, "planar view" refers to a view from a direction perpendicular to the main surface of the substrate. Furthermore, "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. Furthermore, "cross section" refers to a view from a direction parallel to the main surface of the substrate.

[0014] In this specification, we may refer to connections between elements in a circuit. In this case, even if there is another element between the elements of interest, the elements of interest will be treated as being connected unless otherwise specified. For example, suppose that element A is connected to one node of a capacitive element C with multiple nodes, and element B is connected to the other node. Even in this case, elements A and B will be treated as being connected unless otherwise specified.

[0015] In this specification, the phrase "electrically connecting component A and component B" does not necessarily mean that component A and component B are directly connected. For example, even if another component C is connected between component A and component B, it is acceptable as long as they are electrically connected.

[0016] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0017] In the following description, it is assumed that the charges accumulated by the photoelectric conversion unit in a pixel are electrons. Also, it is assumed that all transistors provided in a pixel are N-channel MOS transistors (hereinafter abbreviated as NMOS transistors). However, the charges accumulated by the photoelectric conversion unit may be holes, in which case the transistors of the pixel may be P-channel MOS transistors (hereinafter abbreviated as PMOS transistors). In other words, the conductivity type of transistors etc. can be changed as appropriate depending on the polarity of the charges handled as signals.

[0018] (First embodiment) A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 9. FIG.

[0019] Fig. 1 is a schematic diagram of a photoelectric conversion device according to this embodiment. Fig. 1 shows the photoelectric conversion device as a stacked-type backside illuminated imaging device. All or a part of the stacked-type backside illuminated imaging device is a semiconductor device IC that is a stack of a first substrate 1 and a second substrate 2. A stack of a first substrate 1 and a second substrate 2 as a part of the stacked-type backside illuminated imaging device includes a stack of three or more substrates, such as a stack of a third substrate having a semiconductor element on the stack of the first substrate 1 and the second substrate 2.

[0020] The photoelectric conversion device according to this embodiment is a laminate of a first substrate 1 and a second substrate 2. The first substrate 1 includes a plurality of pixels 10 arranged in a matrix across a plurality of rows and a plurality of columns. The second substrate 2 is provided with a row scanning circuit 20 for driving the pixels 10, a column scanning circuit 21, a signal processing circuit 22 for processing signals from the pixels 10, and the like.

[0021] The first substrate 1 includes a semiconductor layer 11 (first semiconductor substrate) provided with a plurality of semiconductor elements that constitute a plurality of pixels 10, and a wiring structure 12 (first wiring structure) including M wiring layers that are electrically connected to the plurality of pixels 10. The second substrate 2 includes a semiconductor layer 23 (second semiconductor substrate) provided with a plurality of semiconductor elements that constitute a plurality of electric circuits such as a row scanning circuit 20, a column scanning circuit 21, and a signal processing circuit 22, and a wiring structure 24 (second wiring structure) including N wiring layers that constitute the plurality of electric circuits. The wiring structure 12 is disposed between the semiconductor layer 11 and the semiconductor layer 23, and the wiring structure 24 is disposed between the wiring structure 12 and the semiconductor layer 23.

[0022] FIG. 2 is a circuit diagram illustrating the photoelectric conversion device according to this embodiment.

[0023] As shown in Fig. 2, the first substrate 1 includes a semiconductor layer 11 including pixels 10 and transistors described below, and a wiring structure 12 including wiring connected to each transistor of the pixels 10. Also, as shown in Fig. 2, the second substrate 2 includes a semiconductor layer 23 including a row scanning circuit 20 and the like, and a wiring structure 24 including wiring connecting the semiconductor layer 23 to the first substrate 1. The pixel 10 includes a photodiode which is a photoelectric conversion element PD, and typically includes a transfer transistor TX, a selection transistor SEL, a reset transistor RES, an amplification transistor AMP, and the like. The pixel 10 may also include a capacitance-adding transistor FDINC and a gate capacitance GATEC that can add capacitance to the floating diffusion (FD).

[0024] Pixels 10 are arranged on the semiconductor layer 11. Each pixel 10 includes four photoelectric conversion elements PD1A to PD2B and four transfer transistors TX1A to TX2B, and the four photoelectric conversion elements PD1A to PD2B are connected to one amplification transistor AMP. However, in the pixel 10, one photoelectric conversion element PD may be connected to one amplification transistor AMP. Also, one amplification transistor AMP is connected to each of two selection transistors SEL1 and SEL2, but one amplification transistor AMP may be connected to one selection transistor SEL. Also, multiple amplification transistors AMP, each with their gate electrodes connected to a common node, may be connected to one selection transistor SEL.

[0025] A power supply voltage SVDD is supplied to the reset transistor RES and the amplification transistor AMP. A plurality of vertical output lines may be arranged for one pixel column. For example, the selection transistor SEL1 may be connected to one of the plurality of vertical output lines, and the selection transistor SEL2 may be connected to a vertical output line different from the vertical output line to which the selection transistor SEL1 is connected. The amplification transistor AMP can be said to be electrically connected to the vertical output line via the selection transistors SEL1 and SEL2.

[0026] Signals PTX1A to PTX2B are supplied to the gate electrodes of the transfer transistors TX1A to TX2B from the row scanning circuit 20 in the semiconductor layer 23 via wiring in the wiring structure 24 and wiring in the wiring structure 12. While FIG. 2 shows a single signal line for supplying the signals PTX1A to PTX2B, the signals PTX1A to PTX2B may be supplied to each of the transfer transistors TX1A to TX2B via separate signal lines. A signal PRES is supplied to the gate electrode of the reset transistor RES from the row scanning circuit 20 in the semiconductor layer 23 via wiring in the wiring structure 24 and wiring in the wiring structure 12. A signal PFDINC is supplied to the gate electrode of the capacitance-addition transistor FDINC from the row scanning circuit 20 in the semiconductor layer 23 via wiring in the wiring structure 24 and wiring in the wiring structure 12. Signals PSEL1 and PSEL2 are supplied to the gate electrodes of the select transistors SEL1 and SEL2 from the row scanning circuit 20 in the semiconductor layer 23 via wiring in the wiring structure 24 and wiring in the wiring structure 12. 2, the signal lines to which the signals PSEL1 and PSEL2 are supplied are shown together, but this is not limiting. For example, the signal line to which the signal PSEL1 is supplied may be connected to the select transistor SEL1, and a signal line to which the signal PSEL2 is supplied, which is different from the signal line to which the signal PSEL1 is supplied, may be connected to the select transistor SEL2.

[0027] The row scanning circuit 20 is supplied with a potential DVDD and a potential DGND.

[0028] Hereinafter, the signal level of each signal will be described, with a relatively high voltage signal being represented as Hi (short for High) and a relatively low voltage signal being represented as Lo (short for Low). Furthermore, when describing matters common to signals PTX1A to PTX2B, these signals may be collectively referred to as signal PTX. Furthermore, when describing matters common to signals PSEL1 and PSEL2, these signals may be collectively referred to as signal PSEL.

[0029] The signal PRES may have two values, Hi and Lo, or may have three or more values. In Fig. 2, the potential of the signal PRES is adjusted by a signal output from the row scanning circuit 20 and at least one selected from the potentials DVDDH, VRESH, SGND, VPRESL, and VPRESL2. The signal potential of the signal PTX is controlled by the signal output from the row scanning circuit 20, the potential VTXH, and the potential VTXL, and controls the on / off of the transfer transistor. The signal potential of the signal PSEL is controlled by the signal output from the row scanning circuit 20, the potential DVDDH, and the potential VSELL, and controls the on / off of the selection transistor.

[0030] As shown in FIG. 2, in this embodiment, the diodes constituting the protection elements 18A and 18B are disposed in the semiconductor layer 11 included in the first substrate 1. The protection element 18A is connected to the gate electrode of the transfer transistor and to the wiring through which the signals PTX1A to PTX2B pass. One node of the diode constituting the protection element 18A is connected to the wiring through which the signal PTX passes, and the other node is connected to the potential SVDD. In this embodiment, the cathode of the protection element 18A is connected to the power supply line through which the potential SVDD is supplied, and the anode is connected to the wiring through which the signal PTX passes. A reverse bias voltage is applied to the protection element 18A.

[0031] Furthermore, the protection element 18B is connected to the gate electrodes of the select transistors SEL1 and SEL2, and is connected to the wiring through which the signals PSEL1 and PSEL2 pass. One node of the diode constituting the protection element 18B is connected to the wiring through which the signal PSEL passes, and the other node is connected to the potential SVDD. In this embodiment, the cathode of the protection element 18B is connected to the power supply line through which the potential SVDD is supplied, and the anode is connected to the wiring through which the signal PSEL passes. A reverse bias voltage is applied to the protection element 18B.

[0032] As will be described in more detail later, by disposing the protective elements 18A and 18B in the semiconductor layer 11 and connecting them to the wiring connected to the gate electrodes of the transistors included in the pixel 10, it is possible to reduce failures or manufacturing defects in the photoelectric conversion device.

[0033] In FIG. 2, two protection elements, protection element 18A and protection element 18B, are connected to wiring in one pixel 10. However, this is not limiting, and one protection element may be provided and connected to wiring connected to the gate electrode of a transistor included in the pixel 10. For example, a configuration may be adopted in which only protection element 18A is provided connected to wiring connected to the gate electrode of a transfer transistor, and protection element 18B is not provided. Furthermore, a protection element may be connected to each of the wiring through which the signal PRES and the signal PFDINC pass. The relationship between the number of protection elements and the connection to the wiring can be changed as appropriate depending on the reliability required of the photoelectric conversion device, the degree of freedom in layout, and the like.

[0034] 3 is a plan view schematically illustrating pixels of a photoelectric conversion device according to this embodiment. Four photoelectric conversion elements PD1A to PD2B share one floating diffusion region. In addition, the photoelectric conversion element of a given pixel and the photoelectric conversion element of an adjacent pixel in the column direction are arranged in the same active region. A well contact WCNT is arranged between the photoelectric conversion element of a given pixel and the photoelectric conversion element of an adjacent pixel.

[0035] The gate electrodes of the transfer transistors TX1A-2B are arranged along the amplifier transistor AMP and therefore have bent portions, which form corners. When the gate electrodes have bent corners like this, an electric field tends to concentrate at the corners during the process of forming the wiring included in the wiring structure 12, which may make leakage more likely to occur in the gate insulating film. In such cases, connecting a protective element can make it possible to prevent leakage in the gate insulating film.

[0036] 4(a) and 4(b) are schematic top views illustrating the photoelectric conversion device according to this embodiment.

[0037] FIG. 4(a) shows a pixel region in a plan view seen from the light incident surface of the semiconductor layer 11, a chip edge that is an edge of the semiconductor layer 11, a pad section 16 where pads electrically connected to the semiconductor layer 23 are arranged, and a bypass capacitor region arranged between the pixel region and the pad section. The pad section 16 receives signals from outside the photoelectric conversion device or transmits signals to the outside. The pixel region may include effective pixels, optical black (OB) pixels, test pixels, etc., as described below. The bypass capacitor region is arranged with a bypass capacitor to prevent fluctuations in the power supply voltage. In a plan view, the pad section 16 is arranged between the pixel region and the chip edge. FIG. 4(a) also shows an antenna diode region where multiple antenna diodes are arranged as protection elements between the pixel region and the pad section 16. FIG. 4(a) also shows that buffer circuits are arranged on the left and right sides of the pixel region and in the center of the pixel region to supply signals from the semiconductor layer 23 to each transistor shown in FIG. 2.

[0038] As shown in Fig. 4(b), an antenna diode serving as a protection element is connected to a wiring (first wiring) connected to a gate electrode of a transistor in the pixel 10 and connected to a protection element. The wiring in Fig. 4(b) is, for example, a wiring through which a signal PTX passes or a wiring through which a signal PSEL passes. Details of the wiring 31, wiring 32, etc. shown in Fig. 4(b) will be described later with reference to Fig. 8.

[0039] In Fig. 4(b), in a plan view, the wiring connected to the protection element is arranged so as to overlap two or more pixels in the row direction. Specifically, it extends from one end of the pixel area to the other end in the row direction. The arrangement of the wiring and the protection element is not limited to this.

[0040] 5, the pad section 16, the antenna diode region, the bypass capacitor region, the pixel region, the bypass capacitor region, the antenna diode region, and the pad section 16 may be arranged in this order in the column direction. In addition, in a plan view, the wiring connected to the protection element may be arranged so as to overlap two or more pixels in the column direction.

[0041] Furthermore, as shown in FIG. 6, an antenna diode region and the like may be arranged in the same manner as in FIG. 4, and wiring connected to a protection element may be arranged so as to overlap two or more pixels in the row and column directions.

[0042] FIG. 7 is a schematic plan view of the semiconductor layer 11 for explaining the pad portion and pixel region of the photoelectric conversion device according to this embodiment.

[0043] The semiconductor layer 11 includes pixels 10 arranged in a matrix, each of which includes an effective pixel area 100 for capturing an image and an OB area 101 for detecting a reference value for the black level. The OB area 101 is disposed around the effective pixel area 100 and includes a light-shielding layer 13 for blocking light from entering the photoelectric conversion elements. The pixels 10 are formed in a well area 14. A bypass capacitor may be disposed in the area of ​​the well area 14 outside the pixels 10 to prevent fluctuations in the power supply voltage. The area of ​​the semiconductor layer 11 other than the well area 14 forms a substrate area 15. A pad area 16 for inputting and outputting electrical signals is provided at an end of the semiconductor layer 11. An isolation area 17 is disposed around the pad area 16. The isolation area 17 is an element isolation area formed by filling a trench formed in the semiconductor layer 11 with an insulating film such as a silicon oxide film or a silicon nitride film.

[0044] 8 shows a cross-sectional view taken along line XX' in FIG. 7. The first substrate 1 and the second substrate 2 are laminated by being bonded together at their lamination surfaces 3. The wiring structure 12 of the first substrate 1 and the wiring structure 24 of the second substrate 2 are located between the semiconductor layer 11 of the first substrate 1 and the semiconductor layer 23 of the second substrate 2. The first substrate 1 includes a color filter and a microlens.

[0045] The wiring structure 12 has M wiring layers 121 (first wiring layer), 122 (second wiring layer), and 123. The wiring layers 121, 122, and 123 may be Cu wiring layers. In FIG. 8, the wiring layer 123 includes a wiring 31 (second wiring). The wiring 31 is embedded in a recess formed in an interlayer insulating film and has a damascene structure.

[0046] The wiring structure 24 has N wiring layers 241, 242, and 243. The wiring layers 241, 242, and 243 may be Cu wiring layers. In FIG. 8, the wiring layer 243 includes a wiring 32 (third wiring). The wiring 32 is embedded in a recess formed in an interlayer insulating film and has a damascene structure.

[0047] The wiring 31 and the wiring 32 are joined to form a metal junction 30, and the wirings 31 and 32 are joined to each other. The interlayer insulating film having the recess in which the wiring 31 is buried and the interlayer insulating film having the recess in which the wiring 32 is buried are joined (contacted).

[0048] Here, contact plug 124 formed in the interlayer insulating film of wiring layer 123 provides electrical conduction between wiring 31 and the wiring included in wiring layer 122. Contact plug 244 formed in the interlayer insulating film of wiring layer 243 provides electrical conduction between wiring 32 and the wiring included in wiring layer 242. Contact plugs 124 and 244 are disposed at metal junction 30, and provide electrical connection with the wiring of the upper and lower wiring layers.

[0049] The pad section 16 has a trench that penetrates the first substrate 1 and the wiring layer 243. The pad section 16 has wiring of the wiring layer 242 formed on the second substrate 2, and has a wire-bonded structure in which a bonding wire and a bonding pad, both made of a metal such as gold, are connected to the wiring. The wiring of the wiring layer 242 can be Al wiring. Note that it is not necessary for all the wiring of the wiring layer 242 to be made of Al; for example, the wiring (pad) of the pad section 16 may be made of Al, and the other wiring of the wiring layer 242 may be made of Cu.

[0050] Although wire bonding is shown as an example here, a through via (TSV, an abbreviation for Through Silicon Via) in which a trench is filled with metal may also be used. Furthermore, the pad portion 16 may be formed by forming a trench deep enough not to penetrate the first substrate 1 and providing electrical continuity via a bonding wire or a bonding pad. For example, the trench may stop midway through the semiconductor layer 11, or the trench may be formed up to the wiring of a wiring layer included in the wiring structure 12 and providing electrical continuity via a bonding wire or a bonding pad. In such a case, contact plugs may be disposed between multiple wiring layers, and electrical continuity between the wiring layers may be achieved with the wiring layers and the semiconductor layer 23 included in the second substrate 2.

[0051] The wiring layer 121 has wiring 125 (first wiring) arranged thereon, extending in the row direction of the pixels (the direction extending along the rows of the pixels). The wiring 125 may extend in the column direction (the direction extending along the columns of the pixels), or may extend in the row direction, or may have both a portion extending in the row direction and a portion extending in the column direction. The wiring 125 is connected to a plurality of gate electrodes 126. The gate electrodes 126 may be gate electrodes provided in a transfer transistor, a selection transistor, a reset transistor, a capacitance element, or the like. The wiring 125 is also electrically connected to the second substrate 2 via a metal junction 30. As a result, signals for driving the pixels generated on the second substrate 2 and fixed voltages are supplied to the wiring 125.

[0052] In this embodiment, the second substrate 2 and the wiring 125 are electrically connected via the metal joint 30, but this is not limited to this, and conductivity may also be achieved by connecting the wiring layer of the first substrate 1 and the wiring layer of the second substrate 2 with a through-hole via (TSV) in which metal is filled in a trench.

[0053] A protective element 18 is also connected to the wiring 125. The protective element 18 is arranged between the chip edge 4 and the pixel 10. The protective element 18 may also be arranged between the pad portion 16 and the pixel 10. If a bypass capacitor is arranged in the well region 14 outside the pixel 10, the protective element 18 may also be arranged between the pad portion 16 and the bypass capacitor.

[0054] 9(a) and 9(b) show an example of the circuit configuration of the protection element 18. FIG.

[0055] 9(a), the wiring 125 is connected to the anode of the diode 403, and the power supply line 401 is connected to the cathode. When the wiring 125 operates at a voltage equal to or lower than that of the power supply line 401, the diode 403 is always in a reverse bias state.

[0056] 9(b), the wiring 125 is connected to the cathode of the diode 403, and the ground line 402 is connected to the cathode. When the wiring 125 operates at a voltage equal to or higher than the voltage of the ground line 402, the diode 403 is always in a reverse bias state. As a result, the effect on the operation of the imaging device caused by providing the protection element 18 on the wiring 125 can be almost negligible.

[0057] In this embodiment, the protective element 18 is connected to the wiring 125 to which a plurality of gate electrodes 126 are connected. This allows charges generated in the wiring 125 when forming the wiring 125 and when forming the wiring layers 122 and 123 above the wiring 125 (for example, during plasma etching) to flow to the substrate via the wiring 125 and the protective element 18. As a result, deterioration of the gate insulating film due to charge-up at the gate electrode can be suppressed, and breakdowns or manufacturing defects in the photoelectric conversion device can be reduced.

[0058] (Second embodiment) 10 is a schematic cross-sectional view of a photoelectric conversion device according to this embodiment. The cross-section in FIG. 10 is taken at the same position as the cross-section taken along line XX′ in FIG.

[0059] This embodiment differs from the first embodiment in that there is no metal joint 30, and electrical conductivity between the first substrate 1 and the second substrate 2 is ensured via a through via 40. Other than this point and the points described below, the configuration is substantially the same as that of the first embodiment, and therefore, description thereof may be omitted.

[0060] In this embodiment, the wiring 125 and the protective element 18 are connected to the through via 40. This allows charges generated in the wiring 125 when forming the through via 40 (for example, during plasma etching) to flow to the semiconductor layer 11 via the wiring 125 and the protective element 18. As a result, it is possible to suppress deterioration of the gate insulating film due to charge-up at the gate electrode, and reduce the failure rate of the photoelectric conversion device.

[0061] (Third embodiment) 11 is a schematic cross-sectional view of a photoelectric conversion device according to this embodiment. The cross-section in FIG. 11 is taken at the same position as the cross-section taken along line XX′ in FIG.

[0062] 11 differs from the first embodiment in that the wiring 125 is formed in the wiring layer 122, not in the wiring layer 121 that is closest to the semiconductor layer 11. Other than this point and points that will be described below, the configuration is substantially the same as in the first embodiment, and therefore, description thereof may be omitted.

[0063] The wiring 125 is connected to a plurality of gate electrodes 126 via the wiring layer 122 and the underlying wiring layer 121. The protection element 18 is also connected to the wiring 125 via the wiring layer 122 and the underlying wiring layer 121.

[0064] 12(a) to 12(e) show a method for manufacturing a photoelectric conversion device according to this embodiment.

[0065] First, as shown in FIG. 12(a), a semiconductor layer 11 is prepared, and wells, photodiodes, and the like are formed by known methods. The surface of the semiconductor layer 11 is thermally oxidized to form a gate oxide film made of SiO2, and then a polysilicon film is deposited on the gate insulating film. A gate electrode 126 is formed on this polysilicon film by photolithography, etching, and photoresist film removal processes. Then, an interlayer insulating film for a wiring layer 121 included in the wiring structure 12 is deposited.

[0066] Next, as shown in FIG. 12(b), wiring for the wiring layer 121 is formed. After forming trenches on the interlayer insulating film by performing a photolithography process and a plasma etching process, a metal film is deposited on the interlayer insulating film. A planarization process is then performed to form the wiring for the wiring layer 121. After that, an interlayer insulating film for the wiring layer 122 is deposited.

[0067] Next, as shown in FIG. 12(c), wiring for the wiring layer 122 is formed. After forming trenches on the interlayer insulating film by performing a photolithography process and a plasma etching process, a metal film is deposited on the interlayer insulating film. A planarization process is then performed to form the wiring for the wiring layer 122. At this time, the wiring 125 is connected to the protection element 18. After that, an interlayer insulating film for the wiring layer 122 is deposited.

[0068] 12(b)-(c), each process is explained using an example in which Cu is used for wiring. For example, when Al is used, an Al film is deposited first, followed by a photolithography process, a plasma etching process, and a photoresist film removal process, followed by the deposition of an interlayer insulating film and planarization.

[0069] Next, as shown in Fig. 12(d), wiring of the wiring layer 123 is formed. After forming trenches on the interlayer insulating film by performing a photolithography process and a plasma etching process, a metal film is deposited on the interlayer insulating film. A planarization process is then performed to form the wiring of the wiring layer 123.

[0070] Next, as shown in 12(e), the first substrate 1 and the second substrate 2 are bonded together, thereby bonding the wiring 31 and the wiring 32 together, and electrical connection between the first substrate 1 and the second substrate becomes possible.

[0071] Then, after planarizing the semiconductor layer 11 (CMP, an abbreviation for Chemical Mechanical Polishing), a color filter layer, microlenses, and pad portions 16 are formed by a known method, completing the photoelectric conversion device as shown in Fig. 11. Note that the color filter layer and microlenses may be omitted depending on the properties required for the photoelectric conversion device.

[0072] In this embodiment, a protective element 18 is connected to the wiring 125 to which multiple gate electrodes 126 are connected. This allows charges generated in the wiring 125 when forming the wiring 125 and when forming the layer 123 above the wiring 125 (for example, during plasma etching) to flow to the substrate via the wiring 125 and the protective element 18. As a result, deterioration of the gate insulating film due to charge-up at the gate electrode is suppressed, and breakdowns or manufacturing defects in the photoelectric conversion device can be reduced. Furthermore, since it is no longer necessary to arrange the wiring 125 in the lowest wiring layer 121, the degree of freedom in arranging the wiring layer increases, improving the layout efficiency of the wiring layer.

[0073] (Fourth embodiment) The fourth embodiment is applicable to the first to third embodiments. FIG. 13(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to each of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0074] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0075] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0076] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0077] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0078] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using an imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0079] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0080] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0081] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 13(b) and 13(c).

[0082] FIG. 13(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 800. The photoelectric conversion device 800 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 800, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 800, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 800. For example, multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The photoelectric conversion units receive light beams that have passed through different positions of the pupil of the optical system, and the photoelectric conversion device 800 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. The distance information includes information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of this distance information to determine the possibility of a collision. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be implemented by dedicated hardware or a software module. Furthermore, it may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be realized by a combination of these.

[0083] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0084] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 13(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends an instruction to the photoelectric conversion system 8 or the photoelectric conversion device 800. This configuration can further improve the accuracy of distance measurement.

[0085] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generating unit that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generating unit can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, a propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0086] (Modified embodiment) The present disclosure is not limited to the above-described embodiment, and various modifications are possible.

[0087] For example, an example in which part of the configuration of any one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present disclosure.

[0088] Furthermore, the equipment shown in the above fourth embodiment is an example of a photoelectric conversion system to which the photoelectric conversion device can be applied, and the equipment and photoelectric conversion system to which the photoelectric conversion device of the present disclosure can be applied are not limited to the configuration shown in Figure 13.

[0089] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present disclosure, and the technical scope of the present disclosure should not be construed as being limited by these embodiments. In other words, the present disclosure can be carried out in various forms without departing from its technical concept or main features.

[0090] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0091] The matters described in this disclosure have the following configuration.

[0092] (Configuration 1) a first semiconductor substrate having pixels including photoelectric conversion elements and transistors, a first wiring structure, a second wiring structure, and a second semiconductor substrate that generates signals to be applied to gate electrodes of the transistors and supplies the signals to the transistors, stacked in this order; the first semiconductor substrate has a protection element and a plurality of the pixels arranged in row and column directions; the signal is supplied from the second semiconductor substrate to a gate electrode of the transistor; the first wiring structure extends in at least one of the row direction and the column direction so as to overlap with two or more pixels in a plan view, and includes a first wiring through which the signal passes; A photoelectric conversion device, wherein the first wiring and the protection element are connected.

[0093] (Configuration 2) a first semiconductor substrate including pixels each including a photoelectric conversion element and a transistor, the first semiconductor substrate being stacked on a second semiconductor substrate, the first semiconductor substrate having a protection element and a plurality of the pixels arranged in row and column directions; a first wiring structure extending in at least one of the row direction and the column direction so as to overlap with two or more pixels in a plan view, the first wiring structure having a first wiring through which a signal supplied to a gate electrode of the transistor passes; the first wiring and the protection element are connected, The photoelectric conversion device is characterized in that the first wiring and the gate electrode of the transistor are connected.

[0094] (Configuration 3) the first wiring structure includes a second wiring arranged in a layer different from the first wiring, the second wiring structure includes a third wiring; The photoelectric conversion device described in configuration 1, characterized in that the second semiconductor substrate and the transistor are electrically connected via a metal junction where the second wiring and the third wiring are joined.

[0095] (Configuration 4) the first wiring structure includes a plurality of wiring layers including a first wiring layer and a second wiring layer in this order from the first semiconductor substrate side; 4. The photoelectric conversion device according to any one of configurations 1 to 3, wherein the first wiring is disposed in at least one of the first wiring layer and the second wiring layer.

[0096] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that, in a planar view seen from a direction parallel to the main surface of the first semiconductor substrate, the protection element is arranged between an end of the first semiconductor substrate and the photoelectric conversion element.

[0097] (Configuration 6) a pad portion electrically connected to the second semiconductor substrate; 6. The photoelectric conversion device according to any one of configurations 1 to 5, wherein the protection element is disposed between the pad portion and the photoelectric conversion element in the plan view.

[0098] (Configuration 7) a pad portion electrically connected to the second semiconductor substrate; 6. The photoelectric conversion device according to claim 5, wherein, in the plan view, the protection element is disposed between a pad portion and a bypass capacitor region.

[0099] (Configuration 8) 8. The photoelectric conversion device according to any one of configurations 1 to 7, wherein the protection element is connected in a state where a reverse bias voltage is applied between the first wiring and a power supply voltage.

[0100] (Configuration 9) the pixel includes a transfer transistor and a reset transistor; 9. The photoelectric conversion device according to any one of configurations 1 to 8, wherein the protection element is connected to the gate electrode of the transfer transistor and is not connected to the gate electrode of the reset transistor.

[0101] (Configuration 10) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 9, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

[0102] (Configuration 11) preparing a first substrate on which a first semiconductor substrate and a first wiring structure are stacked in this order; preparing a second substrate in which a second wiring structure and a second semiconductor substrate are stacked in this order; and bonding the first substrate and the second substrate together so that the first wiring structure and the second wiring structure face each other; In the step of preparing the first substrate, preparing a first semiconductor substrate having a protection element and a plurality of pixels arranged in row and column directions, each pixel including a photoelectric conversion element and a transistor; and forming a first wiring included in the first wiring structure, the first wiring extending in at least one of the row direction and the column direction so as to connect the protection element to the first wiring, and the gate electrode of the transistor to the first wiring, respectively.

[0103] (Configuration 12) A method for manufacturing a photoelectric conversion device according to configuration 11, characterized in that in the step of forming the first wiring, the first wiring is formed so as to simultaneously connect the protection element and the first wiring, and the gate electrode of the transistor and the first wiring.

[0104] (Configuration 13) 13. The method for manufacturing a photoelectric conversion device according to claim 12, further comprising, after the step of forming the first wiring, a plasma etching step for forming wiring connected to the first wiring. [Explanation of symbols]

[0105] 1 First board 2 Second board 10 pixels 18 Protection elements 125 Wiring (1st wiring) 126 gate electrode

Claims

1. a first semiconductor substrate having pixels including photoelectric conversion elements and transistors, a first wiring structure, a second wiring structure, and a second semiconductor substrate that generates signals to be applied to gate electrodes of the transistors and supplies the signals to the transistors, stacked in this order; the first semiconductor substrate has a protection element and a plurality of the pixels arranged in row and column directions, the signal is supplied from the second semiconductor substrate to a gate electrode of the transistor; the first wiring structure includes a first wiring extending in at least one of the row direction and the column direction so as to overlap with two or more pixels in a plan view, and through which the signal passes; The photoelectric conversion device is characterized in that the first wiring and the protection element are connected to each other.

2. a first semiconductor substrate including pixels each including a photoelectric conversion element and a transistor, the first semiconductor substrate being stacked on a second semiconductor substrate, the first semiconductor substrate having a protection element and a plurality of the pixels arranged in row and column directions; a first wiring structure extending in at least one of the row direction and the column direction so as to overlap with two or more pixels in a plan view, the first wiring including a first wiring through which a signal supplied to a gate electrode of the transistor passes; the first wiring and the protection element are connected, a first wiring connected to a gate electrode of the transistor;

3. the first wiring structure includes a second wiring arranged in a layer different from the first wiring, the second wiring structure includes a third wiring; 2. The photoelectric conversion device according to claim 1, wherein the second semiconductor substrate and the transistor are electrically connected via a metal junction where the second wiring and the third wiring are joined.

4. the first wiring structure includes a plurality of wiring layers including a first wiring layer and a second wiring layer in this order from the first semiconductor substrate side; 4. The photoelectric conversion device according to claim 3, wherein the first wiring is arranged in at least one of the first wiring layer and the second wiring layer.

5. The photoelectric conversion device according to claim 1, characterized in that, in a planar view seen from a direction parallel to the main surface of the first semiconductor substrate, the protection element is arranged between an end of the first semiconductor substrate and the photoelectric conversion element.

6. a pad portion electrically connected to the second semiconductor substrate; 6. The photoelectric conversion device according to claim 5, wherein the protection element is disposed between the pad portion and the photoelectric conversion element in the plan view.

7. a pad portion electrically connected to the second semiconductor substrate; 6. The photoelectric conversion device according to claim 5, wherein, in the plan view, the protection element is disposed between a pad portion and a bypass capacitor region.

8. 2. The photoelectric conversion device according to claim 1, wherein the protection element is connected in a state where a reverse bias voltage is applied between the first wiring and a power supply voltage.

9. the pixel includes a transfer transistor and a reset transistor; 2. The photoelectric conversion device according to claim 1, wherein the protection element is connected to the gate electrode of the transfer transistor and is not connected to the gate electrode of the reset transistor.

10. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 9, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

11. preparing a first substrate on which a first semiconductor substrate and a first wiring structure are stacked in this order; preparing a second substrate in which a second wiring structure and a second semiconductor substrate are stacked in this order; and bonding the first substrate and the second substrate together so that the first wiring structure and the second wiring structure face each other. In the step of preparing the first substrate, preparing a first semiconductor substrate having a protection element and a plurality of pixels arranged in row and column directions, each pixel including a photoelectric conversion element and a transistor; and forming a first wiring included in the first wiring structure, the first wiring extending in at least one of the row direction and the column direction so as to connect the protection element to the first wiring, and the gate electrode of the transistor to the first wiring, respectively.

12. 12. The method for manufacturing a photoelectric conversion device according to claim 11, wherein in the step of forming the first wiring, the first wiring is formed so as to simultaneously connect the protection element and the first wiring, and the gate electrode of the transistor and the first wiring.

13. 13. The method for manufacturing a photoelectric conversion device according to claim 12, further comprising, after the step of forming the first wiring, a plasma etching step for forming wiring connected to the first wiring.

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