Semiconductor memory device and method of manufacturing the same

Abstract

To easily form contacts respectively connected to a plurality of conductive layers having a difference in height.SOLUTION: A stacked body having a staircase portion in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one and each of the plurality of conductive layers processed into a staircase shape is used as a terrace portion; A pillar penetrating the stacked body, and a contact penetrating a terrace portion of one conductive layer of the plurality of conductive layers and a conductive layer below the one conductive layer in the staircase portion, in which each of the plurality of conductive layers has a layer thickness thinner than a layer thickness of each of the plurality of conductive layers in a region where the pillar is disposed in the terrace portion, and both surfaces in a stacking direction including the terrace portion are covered with a first metal containing layer, in each of the lower conductive layers through which the contact penetrates, an end surface facing the contact is also covered with the first metal containing layer, and one conductive layer through which the contact penetrates is electrically connected to the contact in the terrace portion.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as 3D nonvolatile memories, memory cells are arranged three-dimensionally in a stack of multiple conductive layers and multiple insulating layers stacked one by one. These conductive layers are processed into a stepped shape in some areas of the stack, and contacts are connected to each conductive layer. The challenge is how to form contacts that are connected to multiple conductive layers that belong to different layers of the stack and have different heights. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0173120 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can easily form contacts that are connected to a plurality of conductive layers having different heights. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a stacked body having a staircase portion in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one layer at a time, and each of the plurality of conductive layers is processed into a staircase shape and serves as a terrace portion; a pillar penetrating the stacked body at a position away from the staircase portion in a first direction intersecting the stacking direction of the stacked body; and a contact penetrating the terrace portion of one of the plurality of conductive layers and a conductive layer below the one conductive layer in the staircase portion, wherein each of the plurality of conductive layers has a layer thickness in the terrace portion that is thinner than the layer thickness of each of the plurality of conductive layers in the region where the pillar is arranged, and both sides in the stacking direction, including the terrace portion, are covered by a first metal-containing layer, and each of the lower conductive layers through which the contact penetrates has an end face facing the contact covered by the first metal-containing layer, and the one conductive layer through which the contact penetrates is electrically connected to the contact in the terrace portion. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9]1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 14] 10A to 10C are cross-sectional views illustrating a part of a procedure of a method for forming a contact according to a modified example of the embodiment. [Figure 15] 10A to 10C are cross-sectional views further illustrating a part of the procedure of the contact forming method according to the modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0010] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0012] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical continuity is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL. Although FIG. 1 shows a case where only one layer of electrode film EL is used, this is not limiting. A plurality of electrode films EL may be stacked via an insulating layer (not shown).

[0013] 1(a) and 1(b), a memory region MR is arranged in the center of the word lines WL in the X direction, and staircase regions SR are arranged at both ends of the word lines WL in the X direction. The memory region MR and staircase region SR are divided into multiple regions by multiple plate-like contacts LI that extend in the X direction and penetrate the word lines WL.

[0014] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0015] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0016] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0017] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0018] The isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0019] In the terrace portion of each stage formed by a plurality of word lines WL and select gate lines SGD, SGS, contacts CC are disposed which penetrate the word lines WL and select gate lines SGD, SGS and connect to the word lines WL and select gate lines SGD, SGS of each layer at their respective terrace portions. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each section of the select gate line SGD separated by the separation layer SHE per layer. However, multiple contacts CC may be connected to one word line WL in one layer, or multiple contacts CC may be connected to each section of one layer of the select gate line SGD separated by the separation layer SHE.

[0020] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0021] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0022] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0023] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0024] However, the connection between the contacts CC and the memory cells is not limited to the above, and the contacts CC may be provided in the staircase regions SR on both sides of the stacked body LM in the X direction, and the memory cells may be driven from both sides in the X direction in one block region BLK.

[0025] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0026] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0027] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0028] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0029] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0030] Fig. 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS. Fig. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL. Fig. 2(d) is an enlarged cross-sectional view of a contact CC at the height of the word line WL.

[0031] Figure 2(e) is a cross-sectional view along the X direction in the staircase region SR of the semiconductor memory device 1. In Figure 2(e), the structure below the insulating layer 60 and above an insulating layer 53, which will be described later, is omitted.

[0032] In this specification, the direction in which the terrace surface of the word line WL of each step in the staircase region SR faces is defined as the upward direction in the semiconductor memory device 1.

[0033] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0034] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0035] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA through the insulating layer 50 on the outside of the laminated body LM.

[0036] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0037] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0038] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0039] Also, as an example, the thickness of each of the word lines WL and select gate lines SGD, SGS can be, for example, 15 nm or more and 30 nm or less, etc. Furthermore, the thickness of the insulating layer OL may be the same as the thickness of these word lines WL and select gate lines SGD, SGS.

[0040] As shown in FIGS. 2(b) to 2(d), a metal-containing layer 27 and a metal-containing layer 57 are disposed in this order on both sides of the word lines WL and the select gate lines SGD, SGS in the stacking direction.

[0041] When the word lines WL are tungsten layers or the like, the metal-containing layer 27 is, for example, at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer, and functions as a barrier metal layer that suppresses the diffusion of tungsten atoms into structures near the word lines WL. When the word lines WL are molybdenum layers or the like, the metal-containing layer 27 is, for example, a molybdenum nitride layer or the like, and functions as a precursor when forming the word lines WL. The metal-containing layer 57 is, for example, a metal oxide layer or the like, more specifically, an aluminum oxide (Al2O3) layer, a hafnium oxide (HfOx) layer, a zirconium oxide (ZrOx) layer, or the like. Alternatively, the metal-containing layer 57 may be formed by stacking at least two of these types of layers.

[0042] Furthermore, as an example, when the thickness of each of the word lines WL and the select gate lines SGD, SGS is, for example, 15 nm to 30 nm, the thickness of each of the metal-containing layers 27, 57 can be, for example, 1 nm to 5 nm.

[0043] 2(a), the upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described later, each constitute a part of the insulating layer 50 in FIG.

[0044] As described above, the multilayer body LM is divided in the Y direction by the plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0045] In this way, the plate-shaped contact LI extends continuously within the stack LM from one end to the other end in the X direction of the stack LM. The plate-shaped contact LI also penetrates the stack LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0046] The plate-shaped contact LI has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0047] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0048] The insulating layer 54 covers the side walls of the plate-shaped contacts LI facing each other in the Y direction. The conductive layer 24 is filled further inside the insulating layer 54 covering the side walls of the plate-shaped contacts LI, and is electrically connected to the source lines SL including the intermediate source line BSL.

[0049] However, instead of the plate-shaped contacts LI, plate-shaped members filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction.

[0050] Between the plate contacts LI adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, which penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0051] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0052] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0053] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0054] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0055] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0056] 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0057] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL via the memory layer ME. However, a portion of the channel layer CN contacts the intermediate source line BSL on the side, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0058] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0059] 2(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0060] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0061] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0062] 2(b), select gates STD are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGS0 and SGS1 below the word lines WL.

[0063] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0064] As shown in Fig. 2(e), the staircase region SR has a staircase portion SP in which multiple word lines WL and select gate lines SGD, SGS are processed in a staircase shape. The staircase portion SP shown in Fig. 2(e) is a part of the staircase region SR divided into multiple block regions BLK, where contacts CC are arranged and which has the function of drawing out the word lines WL, etc.

[0065] The stepped portion SP is covered with an insulating layer 51. The insulating layer 51 reaches, for example, the height position of the uppermost layer of the laminated body LM, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 also forms part of the insulating layer 50 in FIG.

[0066] In the staircase region SR, the source lines SL include an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0067] Therefore, in the staircase region SR, the plate-shaped contact LI penetrates the insulating layer 51, the stacked body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0068] In the stepped portion SP, the word lines WL and select gate lines SGD, SGS are processed in a stepped shape, and each has a terrace portion TR that does not have an upper layer portion that overlaps in the stacking direction of the laminated body LM. The layer thickness of these terrace portions TR is thinner than the layer thickness of the other portions of these word lines WL and select gate lines SGD, SGS, that is, the layer thickness of the portions that overlap each other in the stacking direction of the laminated body LM. More specifically, the layer thickness of these terrace portions TR is, for example, half or less of the layer thickness of the other portions.

[0069] As an example, when the thickness of each of the word lines WL and select gate lines SGD, SGS is, for example, 15 nm or more and 30 nm or less, the thickness of each of these terrace portions TR can be set to, for example, 5 nm or more and 20 nm or less.

[0070] Furthermore, a plurality of contacts CC are arranged in the stepped portion SP, which are connected to the individual word lines WL and the like that are processed in a stepped shape. These contacts CC are connected to upper layer wiring MX arranged in the insulating layer 53 via plugs V0 arranged in the insulating layer 52. This upper layer wiring MX is electrically connected to the peripheral circuit CBA (see FIG. 1) described above.

[0071] This allows the word lines WL of each layer and the select gate lines SGD, SGS above and below the word lines WL to be electrically drawn out from one end or the other end of the stacked body LM in the X direction. In other words, with the above configuration, a predetermined voltage can be applied to the memory cells MC from the peripheral circuit CBA via the upper layer wiring MX, contacts CC, word lines WL, etc., to operate the memory cells MC as storage elements.

[0072] In the example of FIG. 2(e), a staircase portion SP is shown in which a word line WL and an insulating layer OL are paired, and the word line WL rises and falls in the X direction by one layer at a time. However, within one block region BLK, the staircase portion SP may be configured so that the word line WL also rises and falls in the Y direction. In this case, the staircase portion SP includes multiple rows of staircase structures lined up in the Y direction and each extending in the X direction. This type of staircase structure is also called a multi-row staircase.

[0073] In a multi-column staircase, in one column extending in the X direction, the word lines WL rise and fall in the X direction by multiple layers at a time. That is, in a two-column staircase having two staircase-structure columns, in one column, the word lines WL rise and fall in the X direction by two layers at a time, and in a three-column staircase, the word lines WL rise and fall in the X direction by three layers at a time.

[0074] In other words, the multiple word lines WL included in the laminate LM form terrace portions TR of one of multiple rows of stairs, and by connecting contacts CC to these terrace portions TR, it is possible to electrically extract the multiple word lines WL included in the laminate LM.

[0075] Each contact CC of the staircase portion SP reaches the source line SL at a position where it overlaps with the terrace portion TR of each of the word lines WL and select gate lines SGD, SGS that constitute each step of the staircase portion SP in the stacking direction, penetrating the insulating layer 51, the word lines WL and select gate lines SGD, SGS that constitute the terrace portion TR, and the layered body LM below them. Note that in the example of Figure 2(e), the multiple contacts CC reach the upper source line DSLb of the source lines SL, but these contacts CC may also reach the lower source line DSLa.

[0076] Each contact CC is electrically connected to the uppermost word line WL or select gate lines SGD, SGS constituting the terrace portion TR in the portion of the laminate LM through which the contact CC penetrates. An insulating layer 55 and the like are disposed between the contact CC and the word line WL and select gate lines SGD, SGS in a layer below the word line WL or select gate line SGD, SGS to which the contact CC is connected, and the lower end of the contact CC reaching the upper source line DSLb is covered with an insulating layer 58. This electrically insulates the contact CC from the lower word line WL and select gate lines SGD, SGS, and the source line SL.

[0077] 2(d) shows a detailed configuration of such a contact CC and the word line WL etc. to be connected. In FIG. 2(d), a contact CC to be connected to an arbitrary word line WL will be described.

[0078] 2(d), a flange FLc is disposed on the sidewall of the contact CC at the height of the word line WL to be connected and constituting the terrace portion TR, protruding toward the word line WL. Also, a plurality of flanges FLd are disposed on the sidewall of the contact CC at the height of the word lines WL and other layers below the word line WL to be connected, protruding toward those word lines WL.

[0079] The flange portion FLc is formed integrally with the main body portion of the contact CC extending through the laminate LM, and like the main body portion of the contact CC, includes a conductive layer 25. The conductive layer 25 is preferably formed of the same material as the word lines WL, etc., such as a tungsten layer or a molybdenum layer. However, the conductive layer 25 and the word lines WL, etc. may be formed of different metal materials, such as when the conductive layer 25 is a tungsten layer and the word lines WL, etc. are molybdenum layers. The thickness of the flange portion FLc is substantially equal to the total thickness of the word lines WL in the terrace portions TR of the word lines WL to be connected and the metal-containing layers 27, 57 on both sides of the word lines WL.

[0080] On the other hand, each of the plurality of flange portions FLd includes an insulating layer 55 such as a silicon oxide layer. The thickness of these flange portions FLd is substantially equal to the total thickness of the word lines WL and the like located at height positions corresponding to these flange portions FLd and the metal-containing layers 27, 57 on both sides thereof.

[0081] Here, the layer thicknesses of the flange portion FLc and the word line WL and metal-containing layer 27, 57 in the terrace portion TR, and the layer thicknesses of the flange portion FLd and the corresponding word line WL and metal-containing layer 27, 57 being substantially equal means that these layer thicknesses are not only completely equal, but also approximately equal to the extent that differences that may arise due to manufacturing errors in the manufacturing process described below can be tolerated.

[0082] Furthermore, among these flange portions FLd, at least the flange portion FLd adjacent to the flange portion FLc in the stacking direction has a longer protruding distance from the side wall of the main body portion of the contact CC than the flange portion FLc. Alternatively, all of the plurality of flange portions FLd may have a longer protruding distance than the flange portion FLc.

[0083] As an example, if the thickness of each of the word lines WL and the select gate lines SGD, SGS is, for example, 15 nm or more and 30 nm or less, the protrusion distance of each of the multiple flange portions FLd can be, for example, 15 nm or more and 150 nm or less, and the protrusion distance of the flange portion FLc can be less than the protrusion distance of these flange portions FLd.

[0084] In this way, at least the flange portion FLd adjacent to the flange portion FLc in the stacking direction has a longer protrusion distance than the flange portion FLc, so that the opposing surfaces of the word line WL to be connected by the contact CC and the word line WL adjacent to this word line WL in the stacking direction with the insulating layer OL interposed therebetween are covered with the insulating metal-containing layer 57, thereby suppressing leakage current between these word lines WL. Furthermore, the flange portion FLc of the contact CC that is not covered with the metal-containing layer 57 or the like does not overlap in the height direction with the word line WL adjacent to it in the stacking direction and faces the insulating layer 55 with the insulating layer OL interposed therebetween, which also suppresses leakage current between the word lines WL.

[0085] The body portion of each contact CC has, for example, a tapered shape in which the diameter and cross-sectional area decrease from the upper end to the lower end, or, for example, a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper end and the lower end.

[0086] The metal-containing layer 27 and the metal-containing layer 57 also cover, in this order, the end faces of the word lines WL and the like below the connection target of the contacts CC, the end faces facing the flange portions FLd of the contacts CC. In this way, the insulating layer 55 and the metal-containing layer 57, which is a metal oxide layer or the like, are interposed between the main body of the contacts CC and the word lines WL and the like below. This keeps the contacts CC electrically insulated from the word lines WL and the like below.

[0087] On the other hand, in the word line WL to which the contact CC is connected, at least the end face of the contact CC facing the flange portion FLc is not covered with the metal-containing layer 57. In this way, the metal-containing layer 57, such as a metal oxide layer, is not interposed between the main body of the contact CC and the word line WL to which it is connected. As a result, the contact CC is electrically connected to the word line WL to which it is connected.

[0088] In addition, the metal-containing layer 27, which is a conductor, may cover the end face facing the flange portion FLc of the word line WL to be connected, as shown in Figure 2(d), or may not cover the end face facing the flange portion FLc of the word line WL to be connected, regardless of the example of Figure 2(d).

[0089] The contacts CC to be connected to any word line WL have been described above, but the contacts CC to be connected to the select gate lines SGD and SGS also have the same configuration as above.

[0090] That is, such a contact CC has a flange portion FLc, which is a conductive layer 25 or the like formed integrally with the main body of the contact CC, at the height of the select gate line SGD or select gate line SGS to be connected, and a plurality of flange portions FLd, which are formed with an insulating layer 55, at the height of the word lines WL or the like below. Like the terrace portions TR of these select gate lines SGD, SGS, the flange portions FLc are formed thinner than the flange portions FLd, and have a smaller protrusion distance than the flange portions FLd.

[0091] Furthermore, at least the metal-containing layer 57 is not interposed between the select gate line SGD or select gate line SGS to be connected and the end face of the flange portion FLc facing it. On the other hand, between the word lines WL etc. in the lower layer and the end face of the flange portion FLd facing them, the metal-containing layers 27, 57 are interposed in this order from the word line WL etc. side.

[0092] 2(b) and 2(c), the metal-containing layers 27 and 57 covering the word lines WL and the like around the pillars PL also have a layer structure similar to that of the word lines WL and the like that are not connected to the contacts CC. That is, the end faces of these word lines WL and the like that face the pillars PL are also covered with the metal-containing layer 27 and the metal-containing layer 57 in this order. As a result, the metal-containing layer 57 functions as a metal block layer for the memory cells MC formed in the pillars PL.

[0093] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 3 to 13. Figures 3 to 13 are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0094] 3 shows the laminate LMsa, which is the lower layer of the laminate LM before the word lines WL are formed, and how various components are formed in the laminate LMsa. Fig. 3 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0095] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a support substrate SS.

[0096] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface side of the support substrate SS.

[0097] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. As described above, the intermediate insulating layer SCO is, for example, a silicon oxide layer or the like.

[0098] Furthermore, a stacked body LMsa is formed on the upper source line DSLb, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become word lines WL or select gate lines SGS.

[0099] 3(b), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. Such processing can be performed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layers NL and OL of the laminate LMsa.

[0100] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are retracted to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the above-mentioned stepped shape is formed.

[0101] Instead of the above-described method of processing the insulating layers NL and OL from the top layer to the bottom layer of the laminated body LMsa into a staircase shape in order, a plurality of layers may be processed into a staircase shape at once.

[0102] In this case, strip-shaped mask patterns are formed in the area that will become the staircase portion SP, spaced apart from each other in the X direction and extending in the Y direction. Slimming of these multiple mask patterns and etching of the insulating layers NL and OL are repeated multiple times to process the insulating layers NL and OL on the upper side of the laminate LMsa into a staircase shape. This forms multiple staircase shapes with the multiple mask patterns as their apexes. Furthermore, after protecting the staircase shape close to the area that will later become the memory region MR, the staircase shape on the side away from the area that will later become the memory region MR is dug down until the bottom step reaches the lowest insulating layer NL or OL. This allows staircase shapes for multiple layers to be formed at once.

[0103] In addition, when forming the above-mentioned multiple-row staircase, a method of sequentially processing the top layer to the bottom layer of the laminate LMsa into a staircase shape, or a method of forming them all at once can be used. When forming the multiple-row staircase, first, the sacrificial layer NL is processed so that it rises and falls layer by layer in the Y direction, creating multiple rows of steps in the Y direction. Then, for example, by using one of the above-mentioned methods, these multiple rows are processed into a staircase shape to obtain the multiple-row staircase.

[0104] As shown in Figure 3(c), the terrace portions of the multiple sacrificial layers NL processed into a stepped shape are processed by, for example, reactive ion etching (RIE) or the like to reduce the thickness of the sacrificial layers NL in each terrace portion. At this time, it is preferable to perform the processing so that the layer thickness of the terrace portions becomes half or less of the original layer thickness of the sacrificial layers NL. Note that in the portions other than the terrace portions, these sacrificial layers NL are overlapped with each other in the stacking direction, so the original layer thickness is maintained.

[0105] 3(d), an insulating layer 51 is formed to cover the step portion and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the laminated body LMsa.

[0106] Furthermore, a plurality of memory holes MHa are formed in the stacked body LMsa, extending in the stacking direction. The memory holes MHa are portions that will later become the lower structure of the pillars PL. The plurality of memory holes MHa are arranged in an area that will later become the memory region MR, and reach the lower source line DSLa through the stacked body LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN.

[0107] 3(e), these memory holes MHa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer. As a result, in the region that will later become the memory region MR, pillars PLc in which the sacrificial layer 26 is filled in multiple memory holes MHa are formed.

[0108] The order of the processes shown in Fig. 3 can be interchanged. For example, the formation of the staircase shape in the stacked body LMsa shown in Fig. 3(b) and (c) may be performed after the formation of the pillar PLc shown in Fig. 3(d) and (e).

[0109] 4 to 7 show how a laminate LMsb, which is the upper layer of the laminate LM before the word lines WL are formed, is formed, and how various components are formed in the laminate LMsb. Similar to the above-described FIG. 3, FIGS. 4, 5, and 7 are cross-sectional views along the X direction of the regions that will later become the memory region MR and the staircase region SR.

[0110] As shown in Fig. 4(a), a laminate LMsb is formed by covering the laminate LMsa including the stepped portion with multiple insulating layers NL and multiple insulating layers OL stacked one by one. The sacrificial layers NL of the laminate LMsb will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0111] As shown in FIG. 4(b), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the process shown in FIG. 3(b) above. Alternatively, the stepped shape of the laminate LMsb may be formed by a method of simultaneously processing the stepped shapes of multiple layers. Furthermore, in this case, these stepped shapes may be formed into multiple rows of steps.

[0112] At this time, the top step of the staircase portion already formed in the laminate LMsa and the bottom step of the staircase portion formed in the laminate LMsb are brought close together, and these are formed so that they are continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb.

[0113] As shown in Fig. 4(c), the terrace portions of the plurality of sacrificial layers NL processed into a stepped shape in the laminate LMsb are treated by, for example, RIE in the same manner as the treatment for the laminate LMsa in Fig. 3(c) described above, to reduce the thickness of the sacrificial layers NL in each terrace portion. In this case, too, it is preferable to perform the treatment so that the thickness of the terrace portions becomes half or less of the original thickness of the sacrificial layers NL.

[0114] 5(a), an insulating layer 51 is formed that covers the upper surface of the insulating layer 51 that covers the staircase shape of the laminate LMsa and the newly formed staircase portion of the laminate LMsb, and reaches the height of the upper surface of the laminate LMsb. The insulating layer 51 is also formed in the outer regions of the laminates LMsa and LMsb.

[0115] As shown in Figure 5(b), at positions overlapping with each terrace portion of the insulating layer NL processed into a stepped shape of the laminated bodies LMsa and LMsb in the stacking direction, a plurality of contact holes CL are formed, which extend through the insulating layer 51, the insulating layer NL constituting the terrace portion, and the laminated bodies LMsa and LMsb below it, and reach, for example, the upper source line DSLb.

[0116] Furthermore, the upper source lines DSLb, such as polysilicon layers, exposed from the contact holes CL are subjected to a thermal oxidation treatment, whereby the exposed surfaces of the upper source lines DSLb at the lower ends of the contact holes CL are oxidized, and an insulating layer 58, such as a silicon oxide layer, is formed to cover the lower ends of the contact holes CL.

[0117] As shown in FIG. 5(c), the insulating layers NL exposed in the contact holes CL are recessed from the sidewalls of the contact holes CL by wet etching, CDE (Chemical Dry Etching), or the like.

[0118] As a result, flange portions FLt, FLb are formed on the sidewalls of the contact hole CL, protruding toward the insulating layers NL. The flange portions FLt are formed at the height of the insulating layers NL that form each terrace portion among the insulating layers NL through which the contact hole CL passes, and the flange portions FLb are formed at the height of the other insulating layers NL.

[0119] Thereafter, the flange portion FLt is filled with a sacrificial layer 28 such as an amorphous silicon layer, and the flange portion FLb is filled with an insulating layer 55 such as a silicon oxide layer. This process is shown in Figure 6. Figure 6 is an enlarged cross-sectional view of a contact hole CL that penetrates a terrace portion of any insulating layer NL, and shows a cross section corresponding to Figure 2(d) described above.

[0120] As shown in FIG. 6(a), flange portions FLt and FLb are formed on the sidewalls of the contact holes CL by wet etching or the like on the contact holes CL.

[0121] At this time, the flange portion FLt is formed by the wet etching solution or the etchant of the CDE eroding the terrace portion, which is thinner than the original insulating layer NL, outward from the contact hole CL. Therefore, the recession distance of the terrace portion, i.e., the protrusion distance of the flange portion FLt, is smaller than the recession distance of the insulating layer NL below the insulating layer NL that constitutes the terrace portion, i.e., the protrusion distance of the flange portion FLb.

[0122] In this way, a sacrificial layer 28 is formed on the side wall of the contact hole CL in which the flange portions FLt and FLb are formed. The sacrificial layer 28 may be an amorphous silicon layer or the like, or may be a metal layer such as a tungsten layer, or may be silicon nitride or the like.

[0123] At this time, the sacrificial layer 28 is formed to a thickness that will almost completely fill the voids in the flange portion FLt, but will not completely fill the voids in the flange portion FLb. As a result, a thin sacrificial layer 28 is formed on the sidewalls of the contact hole CL, the top and bottom surfaces of the flange portion FLb, and the end surface facing the insulating layer NL, and the inside of the flange portion FLt is almost completely filled with the sacrificial layer 28.

[0124] 6(b), the sacrificial layer 28 formed on the sidewall of the contact hole CL is removed by wet etching, CDE, or the like. At this time, the thin sacrificial layer 28 formed inside the flange portion FLb is also removed. On the other hand, because the inside of the flange portion FLt is almost completely filled with the sacrificial layer 28 and the aspect ratio of the flange portion FLt is smaller than the aspect ratio of the flange portion FLb, the sacrificial layer 28 filled inside the flange portion FLt can be left almost as it is without being removed.

[0125] After removing the sacrificial layer 28 from the flange portion FLb, the end face of the insulating layer NL exposed from the flange portion FLb may be further recessed by wet etching, CDE, or the like. In this case, the flange portion FLt is filled with the sacrificial layer 28, so the end face of the sacrificial layer NL facing the flange portion FLt is not recessed. This allows the protrusion distance of the flange portion FLb to be even greater than the protrusion distance of the flange portion FLt.

[0126] Thereafter, an insulating layer 55 such as a silicon oxide layer is formed again on the sidewall of the contact hole CL. At this time, the thickness of the insulating layer 55 is adjusted so that the inside of the flange portion FLb is almost completely filled. On the other hand, since the sacrificial layer 28 has already been formed inside the flange portion FLt, the insulating layer 55 is not formed therein.

[0127] 6(c), the insulating layer 55 formed on the sidewall of the contact hole CL is removed by wet etching, CDE, etc. At this time, the insulating layer 55 filled in the flange portion FLb is left as it is.

[0128] As a result of the above, a flange portion FLt filled with the sacrificial layer 28 and the above-mentioned flange portion FLd filled with the insulating layer 55 are formed on the side wall of the contact hole CL.

[0129] 7(a), the entire inside of the contact hole CL is filled with a sacrificial layer 28 such as an amorphous silicon layer to form a contact CCc. In this case, the sacrificial layer 28 may be a metal layer such as a tungsten layer in addition to an amorphous silicon layer or the like.

[0130] Furthermore, a plurality of memory holes MHb are formed in the stacked body LMsb, extending in the stacking direction. The memory holes MHb are portions that will later become the upper structures of the pillars PL. The plurality of memory holes MHb are arranged in an area that will later become the memory region MR, penetrate the stacked body LMsb, and each reach the upper end of the pillar PLc formed in the stacked body LMsa.

[0131] 7(b), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb, thereby opening a memory hole MHa at the bottom of each of the memory holes MHb, and forming a plurality of memory holes MH that penetrate the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0132] In addition, if the sacrificial layer 26 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in the processing of Figure 7(a) described above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed all at once from these pillars PLc as well.

[0133] 4 to 7, the order of the processes can be interchanged. For example, the formation of the memory hole MH shown in FIGS. 7(a) and 7(b) may be performed before the formation of the staircase shape in the stacked body LMsb shown in FIGS. 4(b) and 4(c), or before the formation of the contact CCc shown in FIGS. 5(b) to 6(c).

[0134] 8 and 9 show how a pillar PL is formed by forming a multilayer structure in the memory hole MH. Figures 8 and 9 are cross-sectional views along the Y direction of a region that will later become the memory region MR.

[0135] As shown in FIG. 8(a), a plurality of memory holes MH are formed in a region that will later become the memory region MR.

[0136] 8(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH, whereby the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0137] The multilayer insulating layer MEb is an insulating layer with a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0138] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminated body LMsb.

[0139] As shown in Figure 8(c), the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the top surface of the stack LMsb, and a recess DN is formed at the top end of the memory hole MH from which the insulating layer CRb and the semiconductor layer CNb have been removed.

[0140] As a result, the memory layer ME, the channel layer CN, and the core layer CR are formed in the memory hole MH in this order from the outer periphery.

[0141] 9(a), a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0142] 9(b), the semiconductor layer CPb on the top surface of the stacked body LMsb is removed by chemical mechanical polishing (CMP) or the like, and a cap layer CP is formed at the top end of the memory hole MH. In addition, an insulating layer OL, which is the top layer of the stacked body LMsb that has been thinned by CMP or the like, is added.

[0143] This forms a pillar PL in which the cap layer CP is buried in the uppermost insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a part of the side surface of the channel layer CN is not exposed from the memory layer ME.

[0144] Next, the formation of the source lines SL and word lines WL will be shown with reference to Figures 10 and 11. Figures 10 and 11 are cross-sectional views along the Y direction of a region that will later become the memory region MR, similar to Figures 8 and 9 described above.

[0145] 10(a), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 54s are formed on the side walls of the slit ST that face each other in the Y direction.

[0146] The slits ST have a tapered or bowed cross section in the Y direction, and extend in the X direction within the stacks LMsa and LMsb. Therefore, in the staircase region SR (not shown), the lower ends of the slits ST reach the intermediate insulating layer SCO.

[0147] As shown in FIG. 10(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0148] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs.

[0149] At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well. In addition, in the staircase region SR (not shown), there is no intermediate sacrificial layer SCN between the lower source line DSLa and the upper source line DSLb, and therefore no gap layer GPs is formed.

[0150] 10(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b) and 2(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0151] 10(d), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0152] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0153] At this time, in the staircase region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb, and no intermediate source line BSL is formed either.

[0154] As shown in FIG. 11(a), the insulating layer 54s on the sidewall of the slit ST is temporarily removed.

[0155] 11(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0156] The stacked bodies LMga and LMgb, which include multiple gap layers GP, have a fragile structure. In the region that will later become the memory region MR, multiple pillars PL support the fragile stacked bodies LMga and LMgb. This prevents the remaining insulating layer OL from bending and the stacked bodies LMga and LMgb from being distorted or broken.

[0157] 11(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0158] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0159] When forming the word lines WL, as described above, the metal-containing layer 27 and the metal-containing layer 57 are formed in this order in the gap layers GP, and then a conductive material such as tungsten is filled in to form the word lines WL. The detailed procedure for forming the word lines WL is shown in FIGS. 12 and 13.

[0160] 12 and 13 are enlarged cross-sectional views of a contact hole CL penetrating a terrace portion of an arbitrary insulating layer NL, and show a cross section corresponding to the above-mentioned FIG.

[0161] As shown in FIG. 12(a), the insulating layer NL is removed from the laminated bodies LMsa and LMsb by the process of FIG. 11(b) described above, and a plurality of gap layers GP are formed.

[0162] Furthermore, in the contact CCc, the process shown in Figures 6(a) to 7(a) described above fills the main body portion of the contact hole CL and the inside of the flange portion FLt with a sacrificial layer 28, and an insulating layer 55 is formed inside the flange portion FLb.

[0163] However, as described above, if the inside of the flange portion FLt of the contact CCc is filled with a sacrificial layer such as a silicon nitride layer instead of the sacrificial layer 28 which is an amorphous silicon layer or the like, the sacrificial layer inside the flange portion FLt is also removed by the process shown in Figure 11(b) above, and the gap layer GP located at the height position of the flange portion FLt and the flange portion FLt become connected.

[0164] Furthermore, by the process of FIG. 11(b) described above, the insulating layer NL is removed from the laminated bodies LMsa and LMsb, and a plurality of gap layers GP are formed.

[0165] As shown in FIG. 12(b), a metal-containing layer 57 and a metal-containing layer 27 are formed in this order on both sides of the insulating layer OL exposed in the gap layer GP in the stacking direction and on the end faces of the flange portions FLt and FLd.

[0166] As shown in FIG. 12(c), a conductive material is filled into the gap layer GP in which the metal-containing layers 57 and 27 are formed, to form the word lines WL and the like.

[0167] 13(a), the sacrificial layer 28 filled in the contact hole CL and the flange portion FLt is removed, thereby exposing the metal-containing layer 57 at the end surface of the flange portion FLt on the word line WL side.

[0168] 13(b), the metal-containing layer 57 exposed at the end surface of the flange portion FLt is removed. As a result, the metal-containing layer 27 is exposed at the end surface of the flange portion FLt. However, at this time, the metal-containing layer 27 may be removed after the metal-containing layer 57. In this case, the end surface of the word line WL is exposed at the end surface of the flange portion FLt.

[0169] 6(a) to 7(a), if a sacrificial layer such as a silicon nitride layer is filled inside the flange portion FLt and then removed by the process of FIG. 11(b), the metal-containing layers 57, 27 will be formed on the sidewall of the main body portion of the contact CCc at the height of the flange portion FLt, not on the end face of the flange portion FLt. Therefore, the process of FIG. 13(b) will remove the metal-containing layer 57 and the like from the sidewall of the contact CCc.

[0170] 13(c), the contact hole CL and the flange portion FLt are filled with a conductive layer 25. This forms a contact CC having a flange portion FLc filled with the conductive layer 25 and a flange portion FLd filled with the insulating layer 55 on its sidewall.

[0171] At this time, the conductive layer 25 of the flange portion FLc and the word line WL constituting the terrace portion TR are in contact with each other directly or via the conductive metal-containing layer 27. Therefore, the contact CC is electrically connected to the word line WL constituting the terrace portion TR.

[0172] Meanwhile, an insulating layer 55 and an insulating metal-containing layer 57 are interposed between the flange portion FLd and the metal-containing layer 27 and the word lines WL and the like below the word lines WL that make up the terrace portion TR, thereby preventing the contacts CC from becoming electrically connected to the word lines WL and the like below the word lines WL that make up the terrace portion TR.

[0173] For the sake of clarity, FIG. 14 shows an example in which the metal-containing layers 67 and 27 are both removed in the process of FIG. 13(b) to form a contact CCx without the metal-containing layer 27 interposed between the flange portion FLx and the word line WL.

[0174] 14(a) to 14(c) correspond to the above-mentioned FIGS. 13(a) to 13(c), respectively. In the process of FIG. 14(b), the metal-containing layers 57 and 27 are both removed, thereby forming a contact CCx in which the conductive layer 25 filling the flange portion FLx is directly connected to the end face of the word line WL at the height of the flange portion FLx.

[0175] 15 shows an example in which the metal-containing layer 27 is left in the process of FIG. 13(b) when a sacrificial layer such as a silicon nitride layer is filled in the flange portion FLt in the process of FIG. 6(a) to FIG. 7(a) described above, and an example in which the metal-containing layer 27 is removed in the process of FIG. 13(b).

[0176] As shown in Figure 15(a), which corresponds to Figure 12(a), by the process of Figure 11(b) described above, multiple gap layers GP are formed in the laminates LMga and LMgb, and sacrificial layers such as silicon nitride layers are removed from the flange portions FLt of the contacts CCc.

[0177] As shown in Figure 15(b), which corresponds to Figure 12(c), when the metal-containing layers 57, 27 and the word line WL are formed in this order in the gap layer GP, at the height position of the flange portion FLt, the metal-containing layers 57, 27 are also formed on the side walls of the contact CCc exposed in the flange portion FLt.

[0178] As shown in FIG. 15(c1) corresponding to FIG. 13(b), the sacrificial layer 28 filling the contact CCc is removed, and the metal-containing layer 57 exposed in the contact hole CL is removed.

[0179] As shown in FIG. 15(d1) corresponding to FIG. 13(c), a conductive layer 25 is filled in the contact hole CL to form a contact CCy having flanges FLy and FLd on the sidewalls.

[0180] On the other hand, as shown in FIG. 15(c2) corresponding to FIG. 14(b), the sacrificial layer 28 filling the contact CCc is removed, and the metal-containing layers 57, 27 exposed in the contact hole CL are also removed.

[0181] As shown in FIG. 15(d2) corresponding to FIG. 14(c), a conductive layer 25 is filled in the contact hole CL to form a contact CCz having flanges FLz and FLd on the side walls.

[0182] As described above, in the processes of Figures 6(a) to 7(a) described above, by filling the flange portion FLt with a sacrificial layer such as a silicon nitride layer, the metal-containing layer 57 covering the word lines WL connected to the contacts CCy and CCz can be extended even further to the vicinity of the main body portion of the contact CC.

[0183] Thereafter, an insulating layer 54 is formed on the sidewall of the slit ST, and the insulating layer 54 is filled with the conductive layer 24 to form the plate-like contact LI. However, the slit ST may be filled with the insulating layer 54 or the like without forming the conductive layer 24, to form a plate-like member.

[0184] In addition, a trench is formed through one or more conductive layers including the topmost conductive layer of the laminated body LMb, and an insulating layer 56 is filled in the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0185] An insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the stacked body LM and the staircase region SR, and a plug V0 is formed through the insulating layer 52 to be connected to the contact CC. A plug CH is formed through the insulating layer 52 to be connected to the pillar PL. An insulating layer 53 is then formed on the insulating layer 52, and upper layer wiring MX and bit lines BL, etc., connected to the plugs V0 and CH are formed. Electrode pads, etc., for electrical conduction with the peripheral circuit CBA are formed on the upper surface of the insulating layer 53.

[0186] It should be noted that the plugs V0, CH, upper layer wiring MX, bit line BL, etc. may be formed all at once by using, for example, a dual damascene method.

[0187] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0188] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0189] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0190] (Overview) A semiconductor memory device such as a three-dimensional nonvolatile memory is configured such that multiple word lines, etc. are stacked, some of which are formed in a stepped shape, and contacts are connected to these stepped portions, thereby enabling voltage application to the multiple word lines, etc. These contacts are obtained, for example, by collectively forming multiple contact holes that penetrate an insulating layer covering the stepped portions and reach the terrace portions of the multiple word lines, etc.

[0191] However, due to the large difference in elevation between the word lines belonging to different layers of the stack, some of the contact holes that should reach the word lines in the upper layers may penetrate the target word lines. In this case, if the contact holes reach the word lines in the lower layers, there is a risk that these word lines will become conductive through the contacts that will be formed later.

[0192] Therefore, a method is sometimes adopted to prevent contact penetration by thickening the terrace portions of multiple word lines, etc. In this case, a silicon nitride layer or the like made of the same material as the sacrificial layer is stacked on the terrace portions of the sacrificial layer before it is replaced with the word lines to thicken the layer.

[0193] Furthermore, some attempts have been made to form contact holes through the thickened sacrificial layer and the underlying stack, and connect the thickened word lines to the contacts after replacement with word lines.

[0194] In this case, after forming the contact holes, the sacrificial layer exposed in the contact holes is recessed by wet etching or the like, and then these recessed portions are filled with an insulating layer. At this time, the voids in the recessed portions of the thickened sacrificial layer are larger than the voids in the other sacrificial layers, so they remain without being filled with the insulating layer. When forming contacts by embedding a conductive material in the contact holes, by filling the voids in the thickened sacrificial layer with the conductive layer, it is possible to obtain contacts that are connected only to the thickened word lines after replacement with word lines.

[0195] However, the above-mentioned method of thickening the terrace portion of the word line has various problems. For example, a process is required to separate the thick portion of the terrace portion from the upper step surface so that the thickened terrace portion does not come into contact with the end face of the word line that constitutes the step portion above the terrace portion. If this separation process is insufficient, the word lines above and below the terrace portion will become conductive, causing a short circuit. On the other hand, if this separation process is performed excessively, the sacrificial layer that constitutes the terrace portion will be disconnected.

[0196] According to the semiconductor memory device 1 of the embodiment, each of the word lines WL has a layer thickness in the terrace portion TR that is thinner than the layer thickness of each of the word lines WL in the region where the pillars PL are arranged, and a predetermined word line WL through which a contact CC penetrates is electrically connected to the contact CC in the terrace portion TR. By configuring the connection portion between the contact CC and the word line WL in this manner, it is possible to easily form contacts CC that are connected to each of the word lines WL having different heights.

[0197] According to the semiconductor memory device 1 of the embodiment, each of the word lines WL below the word line WL to which the contact CC is connected is covered with the metal-containing layer 57 even at the end face facing the contact CC, and the metal-containing layer 57 is not arranged on the end face facing the contact CC of the word line WL connected to the contact CC at the terrace portion TR.

[0198] This allows electrical conduction between the word line WL to be connected and the contact CC at the terrace portion TR of the word line WL, and also prevents conduction between the word line WL and the contact CC in a layer below that.

[0199] According to the semiconductor memory device 1 of the embodiment, the end of the metal-containing layer 57 on the contact CC side, which covers both sides of the word line WL to which the contact CC is connected, is located closer to the contact CC than the end of the metal-containing layer 57 on the contact CC side, which covers both sides of each of the underlying word lines WL.

[0200] As a result, the opposing surfaces of adjacent word lines WL in the stacking direction are all covered with the metal-containing layer 57, and the flange portion FLc of the contact CC faces the insulating layer 55 of the flange portion FLd in the lower layer, thereby suppressing leakage current between adjacent word lines WL in the stacking direction.

[0201] According to the embodiment of the semiconductor memory device 1, the contact CC has a conductive flange portion FLc that protrudes from the side wall of the contact CC toward the word line WL to be connected, and a plurality of insulating flange portions FLd that protrude from the side wall of the contact CC toward each of the word lines WL of the layer and contact the metal-containing layer 57 that covers the end faces of the word lines WL of the lower layer.

[0202] This allows electrical conduction between the word line WL to be connected and the contact CC at the terrace portion TR of the word line WL, and also prevents conduction between the word line WL and the contact CC in a layer below that.

[0203] In the semiconductor memory device 1 of the embodiment, the protrusion distance of the flange portion FLc is shorter than the protrusion distance of each of the plurality of flange portions FLd, so that the opposing surfaces of the word lines WL adjacent to each other in the stacking direction are all covered with the metal-containing layer 57, and the flange portion FLc of the contact CC faces the insulating layer 55 of the flange portion FLd in the lower layer, thereby suppressing leakage current between the word lines WL adjacent to each other in the stacking direction.

[0204] According to the semiconductor memory device 1 of the embodiment, the flange portion FLc is in contact with the end face of the word line WL to be connected that faces the contact CC, or is in contact with the metal-containing layer 27 that covers the end face of the word line WL to be connected that faces the contact CC. As a result, in either of the above cases, the word line WL to be connected and the contact CC can be electrically connected through the terrace portion TR of the word line WL.

[0205] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, the difference in layer thickness between the insulating layer NL that will be the word line WL to be connected and the lower insulating layer NL is utilized to set the lower insulating layer NL back from the side wall of the contact hole CL by a greater amount than the insulating layer NL that will be the word line WL to be connected.

[0206] This results in the above configuration in which the opposing surfaces of adjacent word lines WL in the stacking direction are all covered with the metal-containing layer 57, and the flange portion FLc of the contact CC faces the insulating layer 55 of the flange portion FLd of the lower layer.

[0207] The manufacturing method of the semiconductor memory device 1 of the embodiment includes forming the sacrificial layer 28 covering the sidewall of the contact hole CL with a thickness that fills the flange portion FLt with the sacrificial layer 28 and does not fill the plurality of flange portions FLb with the sacrificial layer 28. This allows the insulating layer 55 to be filled only in the flange portion FLb in a later process of forming the insulating layer 55.

[0208] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, after filling the flange portion FLt with the sacrificial layer 28, the insulating layer NL is further recessed from the ends of the plurality of flange portions FLb, thereby making the protrusion distance of the plurality of flange portions FLb greater than the protrusion distance of the flange portion FLt, and later obtaining a configuration capable of suppressing leakage current between the word lines WL adjacent in the stacking direction.

[0209] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, the sacrificial layer 28 is removed, and the metal-containing layer 57 exposed at the end surface of the flange portion FLt is removed, thereby establishing electrical continuity between the word line WL to be connected and the contact CC at the terrace portion TR of the word line WL.

[0210] (Other variations) In the above-described embodiment, in the method of drawing out a plurality of word lines WL etc. on one side, contacts are arranged alternately in the Y direction for every two block regions BLK in the staircase region SR on one side in the X direction. However, in the method of drawing out word lines WL etc. on one side, it is sufficient to arrange contacts on one side in the X direction within the same block region BLK, and the arrangement order is not limited to the above.

[0211] In the above embodiment, the staircase regions SR are provided on both sides of the stack LM in the X direction, but the arrangement of the staircase regions SR is not limited to this. As an example, the staircase region may be provided in the center of the stack LM in the X direction, with a memory region provided on the X direction side. In this case, the staircase region can be arranged in the center of the stack LM by digging out the center of the stack LM in a mortar-shaped manner.

[0212] In the above embodiment, the laminate LM has a two-tier structure, but the laminate may have a one-tier structure or may have three or more tiers.

[0213] In the above-described embodiment, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0214] In the above embodiment, the peripheral circuit CBA is arranged above the laminated body LM, but the peripheral circuit may be arranged below the laminated body or on the same layer as the laminated body.

[0215] When the peripheral circuit is disposed below the stack, the source line and the stack can be formed on an insulating layer of a semiconductor substrate having the peripheral circuit covered with the insulating layer, for example. When the peripheral circuit is disposed on the same layer as the stack, the stack can be formed at a different position from the peripheral circuit on the semiconductor substrate on which the peripheral circuit is formed.

[0216] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0217] 1...semiconductor memory device, 27, 57...metal-containing layer, 28...sacrificial layer, 51, 55...insulating layer, CC...contact, CL...contact hole, FLb, FLc, FLd, FLt...flange portion, LI...plate-shaped contact, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, PL...pillar, SGD, SGS...select gate line, SP...staircase portion, SR...staircase region, WL...word line.

Claims

1. a laminate having a staircase portion in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and each of the plurality of conductive layers processed into a staircase shape serves as a terrace portion; a pillar penetrating the stack at a position away from the staircase portion in a first direction intersecting a stacking direction of the stack; the step portion includes a contact penetrating the terrace portion of one of the plurality of conductive layers and a conductive layer below the one conductive layer, Each of the plurality of conductive layers is the terrace portion has a thickness that is thinner than each of the plurality of conductive layers in a region where the pillar is disposed, both surfaces in the stacking direction including the terrace portions are covered with a first metal-containing layer, Each of the underlying conductive layers through which the contacts pass includes: an end surface facing the contact is also covered with the first metal-containing layer; The one conductive layer through which the contact passes is The terrace portion is electrically connected to the contact. Semiconductor memory device.

2. The first metal-containing layer comprises: a metal oxide layer, The conductive layer is not disposed on an end surface facing the contact.

2. The semiconductor memory device according to claim 1.

3. The contact a conductive first collar portion protruding from a sidewall of the contact toward the one conductive layer; a plurality of insulating second flange portions protruding from the sidewalls of the contact toward each of the underlying conductive layers and in contact with the first metal-containing layer covering the end faces of the underlying conductive layers; 2. The semiconductor memory device according to claim 1.

4. a protruding distance of the first flange portion is shorter than a protruding distance of each of the second flange portions; 4. The semiconductor memory device according to claim 3.

5. The first flange portion includes: The contact has the same material as the body portion of the contact and is integral with the body portion.

4. The semiconductor memory device according to claim 3.

6. forming a laminate in which a plurality of first sacrificial layers and a plurality of first insulating layers are alternately laminated one by one; forming a staircase portion in the stacked body by processing the plurality of first sacrificial layers into a staircase shape, with each of the plurality of first sacrificial layers serving as a terrace portion; thinning the terrace portions of each of the plurality of first sacrificial layers; forming a pillar penetrating the stack at a position away from the staircase portion in a first direction intersecting the stacking direction of the stack; forming a contact hole in the stepped portion, the contact hole penetrating through the terrace portion of one of the plurality of first sacrificial layers and a first sacrificial layer below the one first sacrificial layer; the one first sacrificial layer and the lower first sacrificial layer exposed on the side wall of the contact hole are recessed from the side wall to form a first flange portion protruding toward the one first sacrificial layer on the side wall of the contact hole at a height position of the one first sacrificial layer, and a plurality of second flange portions protruding toward the lower first sacrificial layer on the side wall of the contact hole at respective height positions of the lower first sacrificial layers; Filling each of the plurality of second flange portions with a second insulating layer; replacing each of the plurality of first sacrificial layers with a conductive material to form one first conductive layer from the one first sacrificial layer and a lower first conductive layer from the lower first sacrificial layer; a second conductive layer is filled into the contact hole and the first flange portion to form a contact connected to the one first conductive layer in the terrace portion of the first conductive layer; A method for manufacturing a semiconductor memory device.

7. The recession of the one first sacrificial layer and the underlying first sacrificial layer comprises: utilizing a difference in thickness between the one first sacrificial layer and the lower first sacrificial layer to recess the lower first sacrificial layer from a sidewall of the contact hole to a greater extent than the one first sacrificial layer; 7. The method for manufacturing a semiconductor memory device according to claim 6.

8. The filling of the second insulating layer into the plurality of second flange portions includes: and filling each of the plurality of second flange portions with a second insulating layer after filling the first flange portion with a second sacrificial layer.

7. The method for manufacturing a semiconductor memory device according to claim 6.

9. Filling the first flange with the second sacrificial layer includes: forming the second sacrificial layer covering the sidewall of the contact hole to a layer thickness such that the first flange portion is filled with the second sacrificial layer and the plurality of second flange portions are not filled with the second sacrificial layer; 9. The method for manufacturing a semiconductor memory device according to claim 8.

10. The filling of the second insulating layer into the plurality of second flange portions includes: After filling the first flange portions with the second sacrificial layer, further recessing the underlying first sacrificial layer from the ends of the plurality of second flange portions; and filling the second insulating layer into each of the second flange portions after the lower first sacrificial layer is further recessed.

9. The method for manufacturing a semiconductor memory device according to claim 8.

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