Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of forming a device having suitable performance, and to provide a method of manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device includes a substrate having a first upper surface, and an element isolation region provided in the substrate and having a second upper surface higher than the first upper surface. The device further includes at least one transistor including a gate insulating film provided on the first upper surface of the substrate and a gate electrode provided on the gate insulating film. The device further includes a resistor including a conductive layer provided on the second upper surface of the element isolation region. The apparatus further includes a capacitor including a first dielectric layer disposed on the first upper surface of the substrate, a first electrode layer disposed on the first dielectric layer, a second dielectric layer disposed on the first electrode layer, and a second electrode layer disposed on the second dielectric layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When forming devices such as transistors, resistors, and capacitors on a substrate, it can be difficult to form devices with suitable performance. For example, if the conductive layer for the resistor is too thick, it is difficult to increase the resistance value. It is also difficult to increase the capacitance of the capacitor without increasing the area of ​​the capacitor in a plan view. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. US2022 / 0069097 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a device with favorable performance and a manufacturing method thereof are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a substrate having a first top surface and an isolation region disposed within the substrate and having a second top surface higher than the first top surface. The device further includes at least one transistor including a gate insulating film disposed on the first top surface of the substrate and a gate electrode disposed on the gate insulating film. The device further includes a resistor including a conductive layer disposed on the second top surface of the isolation region. The device further includes a capacitor including a first dielectric layer disposed on the first top surface of the substrate, a first electrode layer disposed on the first dielectric layer, a second dielectric layer disposed on the first electrode layer, and a second electrode layer disposed on the second dielectric layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 3 is a cross-sectional view (1 / 3) showing the details of the structure of the semiconductor device of the first embodiment. FIG. [Figure 3] 2 is a cross-sectional view (2 / 3) showing the details of the structure of the semiconductor device according to the first embodiment. FIG. [Figure 4] 3 is a cross-sectional view (3 / 3) showing the details of the structure of the semiconductor device according to the first embodiment. FIG. [Figure 5] 1A to 1C are plan views showing three examples of the structure of the semiconductor device according to the first embodiment. [Figure 6] FIG. 3 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 7] 1A and 1B are cross-sectional views (1 / 19) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 10 is a cross-sectional view (2 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3 is a cross-sectional view (3 / 19) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 4 is a cross-sectional view (4 / 19) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11]5 is a cross-sectional view (5 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 6 is a cross-sectional view (6 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 7 is a cross-sectional view (7 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 8 is a cross-sectional view (8 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 9 is a cross-sectional view (9 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 10 is a cross-sectional view (10 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 11 is a cross-sectional view (11 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 12 is a cross-sectional view (12 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 13A to 19C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 14 is a cross-sectional view (14 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] 15A and 15B are cross-sectional views (15 / 19) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 16A to 19C are cross-sectional views (16 / 19) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 23] 17A to 19C are cross-sectional views (17 / 19) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 24] 18A to 19C are cross-sectional views (18 / 19) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 25] 19 is a cross-sectional view (19 / 19) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 26] 10 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 27] 10 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 28] 10 is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 29] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third modified example of the first embodiment. [Figure 31] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modified example of the first embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 33] FIG. 10 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 34] 10 is a cross-sectional view (1 / 2) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 35] 10 is a cross-sectional view (2 / 2) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 36] FIG. 10 is a block diagram showing the configuration of a memory system according to a third embodiment. [Figure 37] FIG. 10 is a circuit diagram showing a configuration of a memory cell array 91 according to a third embodiment. [Figure 38] FIG. 10 is a circuit diagram showing a configuration of a voltage generating circuit 95 according to a third embodiment. [Figure 39] FIG. 10 is a circuit diagram showing the configuration of a resistor R2 according to a third embodiment. [Figure 40] FIG. 10 is a circuit diagram showing the configuration of a charge pump CP according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 40, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0009] The semiconductor device of this embodiment includes a transistor HV(N) shown in Fig. 1(a), a transistor HV(P) shown in Fig. 1(b), a transistor LV(N) shown in Fig. 1(c), a transistor LV(P) shown in Fig. 1(d), a resistor (resistive element) R shown in Fig. 1(e), and a capacitor (capacitive element) C shown in Fig. 1(f). The transistors HV(N) and HV(P) are examples of first transistors, and the transistors LV(N) and LV(P) are examples of second transistors.

[0010] The transistor HV(N) is an N-type high-voltage transistor. The transistor HV(P) is a P-type high-voltage transistor. The transistor LV(N) is an N-type low-voltage transistor. The transistor LV(P) is a P-type low-voltage transistor. As shown in FIGS. 1(a) to 1(f), the transistors HV(N), HV(P), LV(N), LV(P), the resistor R, and the capacitor C of this embodiment are formed using the same material. These materials will be described in detail below.

[0011] 1(a) to 1(f), the semiconductor device of this embodiment includes a substrate 1, a plurality of element isolation regions 2, an insulating film 3, an insulating film 4, a semiconductor layer 5, an insulating film 6, an insulating film 7, an electrode material base layer 8, an electrode material layer 9, a sidewall insulating film 11, a liner insulating film 12, an interlayer insulating film 13, a plurality of silicide regions 14, and a plurality of contact plugs 15. The insulating film 3 is an example of the first and third insulating films, the insulating film 7 is an example of the second, fourth, and fifth insulating films, and the insulating film 6 is an example of the sixth insulating film. The electrode material base layer 8 is an example of the first conductive layer, and the electrode material layer 9 is an example of the second conductive layer.

[0012] [Board 1] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Figures 1(a) to 1(f) show six different portions of the same substrate 1. Figures 1(a) to 1(f) also show the X and Y directions, which are parallel to the upper surface of the substrate 1 and perpendicular to each other, and the Z direction, which is perpendicular to the upper surface of the substrate 1. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. Note that the -Z direction may or may not coincide with the direction of gravity.

[0013] The substrate 1 of this embodiment has an upper surface with a generally uniform height (Z coordinate). However, the upper surface of the substrate 1 shown in FIGS. 1(a) and 1(b) is lower than the upper surface of the substrate 1 shown in FIGS. 1(c) to 1(f). The upper surfaces of the substrate 1 shown in FIGS. 1(a) and 1(b) are examples of the first and third upper surfaces, and the upper surfaces of the substrate 1 shown in FIGS. 1(c) to 1(f) are examples of the first and fourth upper surfaces. Furthermore, in FIGS. 1(a) to 1(f), the upper surface of the substrate 1 below the element isolation region 2 is lower than the upper surface of the other portions of the substrate 1.

[0014] [Element isolation region 2] Each element isolation region 2 is formed in a substrate 1. The transistor HV(N) shown in FIG. 1(a) is formed on the substrate 1 between two element isolation regions 2. This also applies to the transistors HV(P), LV(N), and LV(P) shown in FIGS. 1(b) to 1(d). The resistor R shown in FIG. 1(e) is formed on one element isolation region 2. The capacitor C shown in FIG. 1(f) is formed on the substrate 1 between two element isolation regions 2.

[0015] In this embodiment, these element isolation regions 2 are formed of the same insulating film (for example, an SiO2 film (silicon oxide film)). Specifically, these element isolation regions 2 are formed by forming trenches in the substrate 1 and filling the trenches with the insulating film. The insulating film is called, for example, an STI (Shallow Trench Isolation) insulating film. Further details of the element isolation regions 2, such as the timing for forming the element isolation regions 2, will be described later.

[0016] The element isolation region 2 shown in Figure 1(e) has an upper surface that is higher than the upper surface of the substrate 1 shown in Figures 1(a) and 1(b) and the upper surface of the substrate 1 shown in Figures 1(c) to 1(f). Hereinafter, this upper surface of the element isolation region 2 shown in Figure 1(e) will also be referred to as the uppermost surface. The uppermost surface of the element isolation region 2 shown in Figure 1(e) is an example of the second upper surface.

[0017] [Insulating film 3, 4] Insulating films 3 and 4 are formed on substrate 1. However, insulating film 4 is thicker than insulating film 3. Insulating films 3 and 4 are, for example, SiO2 films. The upper surface of substrate 1 under insulating film 4 is lower than the upper surface of substrate 1 under insulating film 3.

[0018] 1(a), an insulating film 4, an insulating film 7, an electrode material base layer 8, and an electrode material layer 9 are formed in this order on a substrate 1. In FIG. 1(a), the insulating films 4 and 7 between the upper surface of the substrate 1 and the lower surface of the electrode material base layer 8 function as a gate insulating film of the transistor HV(N), and the electrode material base layer 8 and the electrode material layer 9 function as a gate electrode of the transistor HV(N). This is also true for the transistor HV(P) shown in FIG. 1(b).

[0019] 1(c), an insulating film 3, an insulating film 7, an electrode material base layer 8, and an electrode material layer 9 are formed in this order on a substrate 1. In FIG. 1(c), the insulating films 3 and 7 between the upper surface of the substrate 1 and the lower surface of the electrode material base layer 8 function as a gate insulating film of the transistor LV(N), and the electrode material base layer 8 and the electrode material layer 9 function as a gate electrode of the transistor LV(N). This is also true for the transistor LV(P) shown in FIG. 1(d).

[0020] The gate insulating film of the transistor HV(N) includes insulating films 4 and 7, and the gate insulating film of the transistor LV(N) includes insulating films 3 and 7. In this embodiment, the thickness of the insulating film 4 is greater than the thickness of the insulating film 3, and therefore the thickness of the gate insulating film of the transistor HV(N) is greater than the thickness of the gate insulating film of the transistor LV(N). This also applies to the gate insulating film of the transistor HV(P) and the gate insulating film of the transistor LV(P).

[0021] 1(f), an insulating film 3, a semiconductor layer 5, an insulating film 6, an insulating film 7, an electrode material base layer 8, and an electrode material layer 9 are sequentially formed on a substrate 1. In FIG. 1(f), the substrate 1 functions as the lower electrode layer of a capacitor C, the semiconductor layer 5 functions as the intermediate electrode layer of the capacitor C, and the electrode material base layer 8 and the electrode material layer 9 function as the upper electrode layer of the capacitor C. Furthermore, the insulating film 3 between the upper surface of the substrate 1 and the lower surface of the semiconductor layer 5 functions as the lower dielectric layer of the capacitor C, and the insulating films 6 and 7 between the upper surface of the semiconductor layer 5 and the lower surface of the electrode material base layer 8 function as the upper dielectric layer of the capacitor C. The capacitor C of this embodiment includes a lower capacitor between the lower electrode layer and the intermediate electrode layer, and an upper capacitor between the intermediate electrode layer and the upper electrode layer. The lower dielectric layer, the intermediate electrode layer, the upper dielectric layer, and the upper electrode layer are examples of a first dielectric layer, a first electrode layer, a second dielectric layer, and a second electrode layer, respectively. Moreover, the lower capacitor is an example of a first capacitor, and the upper capacitor is an example of a second capacitor.

[0022] Further details of the semiconductor layer 5, the insulating film 6, the insulating film 7, the electrode material underlayer 8, and the electrode material layer 9 will be described later.

[0023] [Semiconductor layer 5] The semiconductor layer 5 is formed on the insulating film 3 in FIG. 1(f). The semiconductor layer 5 is, for example, a polysilicon layer. In this embodiment, the height of the upper surface of the semiconductor layer 5 is the same as the height of the upper surface of the element isolation region 2 on the right side in FIG. 1(f). Furthermore, the height of the upper surface of the element isolation region 2 on the right side in FIG. 1(f) is the same as the height of the uppermost surface of the element isolation region 2 shown in FIG. 1(e).

[0024] [Insulating film 6] The insulating film 6 is formed on the semiconductor layer 5 in Fig. 1(f). The insulating film 6 is further formed on the element isolation region 2 on the right side in Fig. 1(f). The insulating film 6 is, for example, a SiO2 film.

[0025] [Insulating film 7] The insulating film 7 is formed on the insulating film 4 in FIGS. 1(a) and 1(b), and on the insulating film 3 in FIGS. 1(c) and 1(d). The insulating film 7 is further formed on the top surface of the element isolation region 2 in FIG. 1(e), and on the insulating film 6 in FIG. 1(f). The insulating film 7 is, for example, a high-k insulating film such as a metal oxide film. Examples of high-k insulating films include hafnium (Hf) oxide film, zirconium (Zr) oxide film, hafnium oxysilicide film, zirconium oxysilicide film, hafnium oxysilicide film, zirconium oxysilicide film, hafnium oxysilicide film, and zirconium oxysilicide film. The high-k insulating film may contain additive elements such as aluminum (Al) and lanthanum (La).

[0026] 1(a) to 1(f), the insulating film 7 is formed on the lower surface and side surfaces of the electrode material base layer 8, and the electrode material base layer 8 is formed on the lower surface and side surfaces of the electrode material layer 9. In each of FIGS. 1(a) and 1(b), the insulating film 7, electrode material base layer 8, and electrode material layer 9 having such a structure are formed, for example, by sequentially filling a recess formed by the insulating film 4 and the sidewall insulating film 11 with the insulating film 7, electrode material base layer 8, and electrode material layer 9. In each of FIGS. 1(c) and 1(d), the insulating film 7, electrode material base layer 8, and electrode material layer 9 having such a structure are formed, for example, by sequentially filling a recess formed by the insulating film 3 and the sidewall insulating film 11 with the insulating film 7, electrode material base layer 8, and electrode material layer 9. 1(e), the insulating film 7, electrode material base layer 8, and electrode material layer 9 having such a structure are formed, for example, by sequentially filling a recess formed by the element isolation region 2 and the sidewall insulating film 11 with the insulating film 7, electrode material base layer 8, and electrode material layer 9. In FIG. 1(f), the insulating film 7, electrode material base layer 8, and electrode material layer 9 having such a structure are formed, for example, by sequentially filling a recess formed by the insulating film 6 and the sidewall insulating film 11 with the insulating film 7, electrode material base layer 8, and electrode material layer 9.

[0027] [Electrode material base layer 8] 1(a) to 1(f), the electrode material base layer 8 is formed on the upper surface and side surfaces of the insulating film 7. The electrode material base layer 8 is, for example, a laminated film including a plurality of metal layers. In this case, examples of the metal layers included in the electrode material base layer 8 include a TiN (titanium nitride) film, a TiNO (titanium oxynitride) film, a TiC (titanium carbide) film, a TiAlC (titanium aluminum carbide) film, and a TiSiNOC (titanium silicide oxynitride carbide) film.

[0028] In this embodiment, the height of the upper surface of the semiconductor layer 5 is the same as the height of the uppermost surface of the element isolation region 2 shown in Fig. 1(e). Therefore, the height of the lower surface of the electrode material base layer 8 is higher than the height of the uppermost surface of the element isolation region 2 shown in Fig. 1(e). In other words, the height of the upper surface of the intermediate electrode layer of the capacitor C is the same as the height of the uppermost surface of this element isolation region 2, and the height of the lower surface of the upper electrode layer of the capacitor C is higher than the height of the uppermost surface of this element isolation region 2.

[0029] [Electrode material layer 9] 1(a) to 1(f), the electrode material layer 9 is formed on the upper surface and side surfaces of the electrode material base layer 8. The electrode material layer 9 is a metal layer such as a W (tungsten) layer, an Al (aluminum) layer, or a TiAlC (titanium aluminum carbide) layer.

[0030] The resistor R shown in Fig. 1(e) includes a conductive layer formed on the uppermost surface of the element isolation region 2 via an insulating film 7. The conductive layer includes an electrode material base layer 8 and an electrode material layer 9, and functions as the resistor R having a predetermined resistance value.

[0031] When manufacturing the semiconductor device of this embodiment, the upper surface of the electrode material layer 9 is planarized by CMP (Chemical Mechanical Polishing) together with the electrode material base layer 8 and the insulating film 7. Therefore, the electrode material layer 9 shown in Figures 1(a) to 1(f) has an upper surface with a substantially uniform height.

[0032] [Sidewall insulating film 11 and liner insulating film 12] The sidewall insulating film 11 and the liner insulating film 12 are formed in this order on each side surface of the insulating film 7 in each of FIGS. 1(a) to 1(f). The sidewall insulating film 11 and the liner insulating film 12 are further formed in this order on the side surface of the semiconductor layer 5 in FIG. 1(f). The liner insulating film 12 is further formed on the substrate 1, the element isolation region 2, and the upper surface of the semiconductor layer 5. The sidewall insulating film 11 is, for example, a laminated film including a plurality of insulating films. The liner insulating film 12 is, for example, a laminated film including a plurality of insulating films.

[0033] [Interlayer insulating film 13] The interlayer insulating film 13 is formed on the substrate 1 so as to cover the element isolation region 2, the insulating film 3, the insulating film 4, the semiconductor layer 5, the insulating film 6, the insulating film 7, the electrode material base layer 8, the electrode material layer 9, the sidewall insulating film 11, and the liner insulating film 12. The interlayer insulating film 13 is, for example, a SiO2 film.

[0034] [Silicide region 14] Each silicide region 14 is formed in the substrate 1 or the semiconductor layer 5. Each silicide region 14 is, for example, a NiSi (nickel silicide) region, a NiPtSi (nickel platinum silicide) region, or a CoSi (cobalt silicide) region. Each silicide region 14 may contain an additive element such as Ge (germanium) or F (fluorine).

[0035] In Fig. 1(a), two silicide regions 14 are formed in the substrate 1 so as to sandwich the gate electrode (electrode material base layer 8 and electrode material layer 9). This is also true for Figs. 1(b) to 1(d). In Fig. 1(f), two silicide regions 14 are formed in the substrate 1 and the semiconductor layer 5.

[0036] [Contact Plug 15] Each contact plug 15 is formed in the interlayer insulating film 13. Specifically, each contact plug 15 is formed on a silicide region 14 provided in the substrate 1, on a silicide region 14 provided in the semiconductor layer 5, or on the electrode material layer 9. Each contact plug 15 is, for example, a metal plug.

[0037] In Fig. 1(a), three contact plugs 15 are formed on one silicide region 14, the other silicide region 14, and the electrode material layer 9. These contact plugs 15 are used to control the source region, drain region, and gate electrode (electrode material base layer 8 and electrode material layer 9) of the transistor HV(N). This also applies to Figs. 1(b) to 1(d).

[0038] In Figure 1(e), two or more contact plugs 15 are actually formed on the electrode material layer 9. Figure 1(e) shows one of these contact plugs 15. Further details of these contact plugs 15 for the resistor R will be described later.

[0039] 1(f), three contact plugs 15 are formed on one silicide region 14, the other silicide region 14, and the electrode material layer 9. These contact plugs 15 are used to control the lower electrode layer (substrate 1), the intermediate electrode layer (semiconductor layer 5), and the upper electrode layer (electrode material base layer 8 and electrode material layer 9) of the capacitor C.

[0040] The semiconductor device of this embodiment will be described in further detail below with continued reference to FIGS. 1(a) to 1(f).

[0041] 1(a) to 1(d), the channel lengths of the transistors HV(N) and HV(P) are approximately the same as the channel lengths of the transistors LV(N) and LV(P). However, the channel lengths of the transistors HV(N) and HV(P) may be longer than the channel lengths of the transistors LV(N) and LV(P).

[0042] 1(a) to 1(d), the gate length directions of the transistors HV(N), HV(P), LV(N), and LV(P) are parallel to the X direction. However, the gate length directions of the transistors HV(N), HV(P), LV(N), and LV(P) do not have to be parallel to the X direction, and may be parallel to, for example, the Y direction. Similarly, the cross section shown in FIG. 1(e) and the cross section shown in FIG. 1(f) may be other than an XZ cross section, and may be, for example, a YZ cross section.

[0043] The capacitor C of this embodiment includes a lower capacitor formed between the lower electrode layer (substrate 1) and the intermediate electrode layer (semiconductor layer 5), and an upper capacitor formed between the intermediate electrode layer (semiconductor layer 5) and the upper electrode layer (electrode material base layer 8 and electrode material layer 9). According to this embodiment, by configuring the capacitor C with the lower capacitor and upper capacitor stacked in the Z direction, it is possible to increase the capacitance of the capacitor C without increasing the area of ​​the capacitor C in a plan view.

[0044] Furthermore, the resistor R of this embodiment includes a conductive layer (electrode material base layer 8 and electrode material layer 9) formed on the upper surface of the element isolation region 2, and this upper surface of the element isolation region 2 is formed at a high position. The value of the resistance R increases as the cross-sectional area of ​​the vertical cross section (XZ cross section) of the conductive layer decreases, and this cross-sectional area decreases as the thickness of the conductive layer decreases. Therefore, according to this embodiment, by increasing the height of the upper surface of the element isolation region 2, it is possible to reduce the thickness of the conductive layer, thereby increasing the value of the resistance R. The width of the conductive layer of the resistor R in the X direction may be smaller or larger than the width of the gate electrodes (electrode material base layer 8 and electrode material layer 9) of the transistors LV(N) and LV(P) in the X direction.

[0045] Furthermore, the electrode material base layer 8 and electrode material layer 9 of this embodiment are used as the gate electrodes of the transistors HV(N), HV(P), LV(N), and LV(P), as the conductive layer of the resistor R, and as the upper electrode layer of the capacitor C. According to this embodiment, the gate electrodes of the transistors HV(N), HV(P), LV(N), and LV(P), the conductive layer of the resistor R, and the upper electrode layer of the capacitor C can be easily formed using the common material of the electrode material base layer 8 and the electrode material layer 9. In this embodiment, the other components of the transistors HV(N), HV(P), LV(N), and LV(P), the resistor R, and the capacitor C are also formed using the common material, as described above.

[0046] The semiconductor device of this embodiment includes not only low-voltage transistors (transistors LV(N) and LV(P)) but also high-voltage transistors (transistors HV(N) and HV(P)). According to this embodiment, by using high-voltage transistors, it becomes possible to form, for example, circuits that require high breakdown voltage. Note that the semiconductor device of this embodiment may include only one, two, or three of the four types of transistors HV(N), HV(P), LV(N), and LV(P).

[0047] The semiconductor device of this embodiment is, for example, a semiconductor memory. In this case, the transistors HV(N), HV(P), LV(N), and LV(P), the resistor R, and the capacitor C are used, for example, in a circuit that controls a memory cell array in the semiconductor memory. An example of such a circuit is a voltage generating circuit, which will be described later. Examples of such semiconductor devices will be described in detail in the second and third embodiments, which will be described later.

[0048] The semiconductor device of this embodiment may be a device other than a semiconductor memory. In this case, the transistors HV(N), HV(P), LV(N), and LV(P), the resistor R, and the capacitor C are used, for example, in a digital-analog mixed circuit. According to this embodiment, by applying the structure of this embodiment to a digital-analog mixed circuit, it is possible to preferably form, for example, a digital-analog circuit that requires high breakdown voltage.

[0049] The capacitor C of this embodiment is formed in a form that uses the substrate 1 as a lower electrode layer. That is, the capacitor C of this embodiment is formed not at a position away from the upper surface of the substrate 1 but at a position in contact with the upper surface of the substrate 1, and the substrate 1 becomes a part of the capacitor C of this embodiment. This enables, for example, the capacitor C to appropriately handle high voltages. A charge pump is a circuit that generates high voltages and often handles high voltages, so the capacitor C of this embodiment is suitable for charge pumps. Generally, a charge pump is formed using not only low-voltage transistors but also high-voltage transistors, and therefore the structure of this embodiment is also suitable for charge pumps from the viewpoint of high breakdown voltage.

[0050] In FIG. 1(f), the capacitor C is formed so as to be in contact with the side and top surfaces of the element isolation region 2, but it may be formed so as to be in contact with only the side or top surface of the element isolation region 2, or may be formed so as not to be in contact with the element isolation region 2.

[0051] 1(e), the lower surface of the insulating film 7 below the resistor R is in contact only with the upper surface of the element isolation region 2, but it may also be in contact with the upper surface of the element isolation region 2 and the upper surface of the substrate 1. In other words, the insulating film 7 below the resistor R may be formed so as to protrude onto the upper surface of the substrate 1. Similarly, the electrode material base layer 8 and the electrode material layer 9 within the resistor R may be formed so as to protrude onto the upper surface of the substrate 1.

[0052] 1(a) to 1(d), the transistors HV(N), HV(P), LV(N), and LV(P) are planar field effect transistors (FETs), but may be other types of transistors. For example, the transistors HV(N), HV(P), LV(N), and LV(P) may be fin FETs or trench FETs.

[0053] As described above, according to this embodiment, when devices such as transistors HV(N), HV(P), LV(N), LV(P), resistors R, and capacitors C are formed on the substrate 1, it is possible to form devices with suitable performance.

[0054] 2 to 4 are cross-sectional views showing the details of the structure of the semiconductor device of the first embodiment.

[0055] Fig. 2(a) shows an enlarged view of the transistor HV(N) shown in Fig. 1(a). The semiconductor device of this embodiment includes source / drain regions 16 formed in the substrate 1 so as to sandwich the gate electrode (electrode material base layer 8 and electrode material layer 9) of the transistor HV(N). Fig. 2(a) also shows silicide regions 14 formed in the source / drain regions 16.

[0056] In FIG. 2(a), the electrode material base layer 8 includes four metal layers 8a, 8b, 8d, and 8e formed in this order on the upper surface and side surfaces of the insulating film 7. The metal layer 8a is, for example, a TiN film (titanium nitride film). The metal layer 8b is, for example, a TaN film (tantalum nitride film). The metal layer 8d is, for example, a TiAl film (titanium aluminum film). The metal layer 8e is, for example, a TiN film. In this embodiment, the metal layers 8a and 8b are provided to optimize the work function of the electrode material base layer 8, the metal layer 8d is provided as an electrode layer, and the metal layer 8e is provided as a barrier metal layer.

[0057] 2(a), the sidewall insulating film 11 includes an insulating film 11a formed on the side surface of the insulating film 7, an insulating film 11b formed on the side surface of the insulating film 11a and on the upper surface of the insulating film 4, and an insulating film 11c formed on the side surface and upper surface of the insulating film 11b. The insulating film 11a is, for example, a SiO2 film. The insulating film 11b is, for example, a SiN film (silicon nitride film). The insulating film 11c is, for example, a SiO2 film.

[0058] 2(a), the liner insulating film 12 includes an insulating film 12a formed on the side surfaces of the insulating film 11c and the upper surfaces of the substrate 1 and the element isolation region 2, and an insulating film 12b formed on the side surfaces and upper surface of the insulating film 12a. The insulating film 12a is, for example, a SiO2 film. The insulating film 12b is, for example, a SiN film. The contact plugs 15 on each silicide region 14 are formed to penetrate the liner insulating film 12.

[0059] 2(b) shows an enlarged view of the transistor HV(P) shown in FIG. 1(b). The semiconductor device of this embodiment includes source / drain regions 16 formed in the substrate 1 so as to sandwich the gate electrode (electrode material base layer 8 and electrode material layer 9) of the transistor HV(P). FIG. 2(b) further shows silicide regions 14 formed in the source / drain regions 16.

[0060] 2(b), the electrode material base layer 8 includes metal layers 8a, 8b, 8d, and 8e, as well as a metal layer 8c formed between the metal layer 8b and the metal layer 8d. The metal layer 8c is, for example, a TiN film. In this embodiment, the metal layer 8c is provided to optimize the work function of the electrode material base layer 8.

[0061] In FIG. 2(b), the sidewall insulating film 11 and the liner insulating film 12 are formed in the same manner as in FIG. 2(a).

[0062] Fig. 3(a) shows an enlarged view of the transistor LV(N) shown in Fig. 1(c). The semiconductor device of this embodiment includes source / drain regions 16 formed in the substrate 1 so as to sandwich the gate electrode (electrode material base layer 8 and electrode material layer 9) of the transistor LV(N). Fig. 3(a) also shows silicide regions 14 formed in the source / drain regions 16.

[0063] 3(a), the electrode material base layer 8, the sidewall insulating film 11, and the liner insulating film 12 are formed in the same manner as in FIG. 2(a). However, the insulating film 11b is formed on the side surface of the insulating film 11a and on the upper surface of the insulating film 3.

[0064] Fig. 3(b) shows an enlarged view of the transistor LV(P) shown in Fig. 1(d). The semiconductor device of this embodiment includes source / drain regions 16 formed in the substrate 1 so as to sandwich the gate electrode (electrode material base layer 8 and electrode material layer 9) of the transistor LV(P). Fig. 3(b) further shows silicide regions 14 formed in the source / drain regions 16.

[0065] 3(b), the electrode material base layer 8, the sidewall insulating film 11, and the liner insulating film 12 are formed in the same manner as in FIG. 2(b). However, the insulating film 11b is formed on the side surface of the insulating film 11a and on the upper surface of the insulating film 3.

[0066] FIG. 4(a) shows an enlarged view of the resistor R shown in FIG. 1(e).

[0067] 4(a), the electrode material base layer 8, sidewall insulating film 11, and liner insulating film 12 are formed in the same manner as in FIG. 2(a). However, insulating film 11b is formed on the side surface of insulating film 11a and the upper surface of element isolation region 2, and insulating film 12a is formed on the side surface of insulating film 11c and element isolation region 2, and the upper surface of element isolation region 2 and substrate 1. Note that electrode material base layer 8 shown in FIG. 4(a) may further include a metal layer 8c.

[0068] FIG. 4(b) shows an enlarged view of the capacitor C shown in FIG. 1(f).

[0069] 4(b), the electrode material base layer 8, sidewall insulating film 11, and liner insulating film 12 are formed in the same manner as in FIG. 2(a). However, insulating film 11b is formed on the side surface of insulating film 11a and on the upper surfaces of insulating films 3 and 6, and insulating film 12a is formed on the side surface of insulating film 11c and on the upper surfaces of semiconductor layer 5, element isolation region 2, and substrate 1. Note that the electrode material base layer 8 shown in FIG. 4(b) may further include a metal layer 8c.

[0070] FIG. 5 is a plan view showing three examples of the structure of the semiconductor device according to the first embodiment.

[0071] Fig. 5(a) shows a first example of the semiconductor device of this embodiment. Fig. 5(a) shows the planar shape of the electrode material layer 9 in the resistor R, and does not show the electrode material base layer 8 formed on the side surface of the electrode material layer 9. In Fig. 5(a), the electrode material layer 9 extends in the Y direction above the element isolation region 2.

[0072] 5(a) further shows four contact plugs 15 formed on the electrode material layer 9. These contact plugs 15 include two contact plugs 15 (hereinafter referred to as "first contact plugs 15") arranged near the end of the electrode material layer 9 in the +Y direction, and two contact plugs 15 (hereinafter referred to as "second contact plugs 15") arranged near the end of the electrode material layer 9 in the -Y direction. In FIG. 5(a), the electrode material layer 9 (and the electrode material base layer 8) between the first contact plugs 15 and the second contact plugs 15 functions as a resistor R.

[0073] 5(b) shows a second example of the semiconductor device of this embodiment. In FIG. 5(b), multiple resistors R (electrode material layers 9) are arranged on one element isolation region 2. These resistors R are adjacent to each other in the X direction. The structure of each resistor R shown in FIG. 5(b) is the same as the structure of the resistor R shown in FIG. 5(a).

[0074] 5(b), the semiconductor device of this embodiment may include a large number of resistors R on one element isolation region 2. In this case, among these resistors R, some of the electrode material layers 9 near the ends in the ±X directions may not be used as resistors R. This is because the electrode material layers 9 near the ends in the ±X directions often do not have a stable shape.

[0075] 5(c) shows a third example of the semiconductor device of this embodiment. In FIG. 5(c), one resistor R (electrode material layer 9) extends in a serpentine manner over one element isolation region 2. Specifically, the electrode material layer 9 includes three portions P1 extending in the Y direction and two portions P2 connecting these portions P1 to each other. This makes it possible to increase the length of the electrode material layer 9 between the first contact plug 15 and the second contact plug 15, thereby increasing the resistance R. Note that the number of portions P1 may be N, and the number of portions P2 may be N-1 (N is an integer greater than or equal to 2).

[0076] FIG. 6 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0077] Figures 6(a) to 6(f) correspond to Figures 1(a) to 1(f), respectively. The structures shown in Figures 6(a) to 6(f) are similar to the structures shown in Figures 1(a) to 1(f), respectively. However, the height of the upper surface of the element isolation region 2 shown in Figure 6(e) is the same as the height of the upper surface of the substrate 1 shown in Figure 6(e). Furthermore, the capacitor C shown in Figure 6(f) does not include the semiconductor layer 5 and the insulating film 6, and therefore includes only one capacitor between the lower electrode layer (substrate 1) and the upper electrode layer (electrode material base layer 8 and electrode material layer 9).

[0078] In this comparative example, the capacitor C is composed of only one capacitor between the lower electrode layer and the upper electrode layer. Therefore, in this comparative example, it is difficult to increase the capacitance of the capacitor C without increasing the area of ​​the capacitor C in a planar view. On the other hand, in this embodiment, the capacitor C is composed of a lower capacitor and an upper capacitor stacked in the Z direction. Therefore, according to this embodiment, it is possible to increase the capacitance of the capacitor C without increasing the area of ​​the capacitor C in a planar view.

[0079] Furthermore, the resistor R of this comparative example includes an electrode material base layer 8 and an electrode material layer 9 formed on the upper surface of the element isolation region 2, and this upper surface of the element isolation region 2 is formed at a low position. Therefore, in this comparative example, the thickness of the conductive layer in the resistor R is increased, and the value of the resistor R is reduced. On the other hand, the resistor R of this embodiment includes an electrode material base layer 8 and an electrode material layer 9 formed on the upper surface of the element isolation region 2, and this upper surface of the element isolation region 2 is formed at a high position. Therefore, according to this embodiment, it is possible to reduce the thickness of the conductive layer in the resistor R, and to increase the value of the resistor R.

[0080] 7 to 25 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0081] Figures 7(a) to 7(f), 8(a) to 8(f), ..., and 25(a) to 25(f) correspond to Figures 1(a) to 1(f), respectively. Below, we will explain the steps for manufacturing the semiconductor device shown in Figures 1(a) to 1(f).

[0082] First, a portion of the substrate 1 is processed from the upper surface thereof by lithography and etching (FIGS. 7(a) to 7(f)). As a result, the upper surface of the substrate 1 shown in FIGS. 1(a) and 1(b) is lower than the upper surface of the substrate 1 shown in FIGS. 1(c) to 1(f). Next, an insulating film 4 is formed on the upper surface of the substrate 1 shown in FIGS. 1(a) and 1(b), and an insulating film 3 is formed on the upper surface of the substrate 1 shown in FIGS. 1(c) to 1(f) (FIGS. 7(a) to 7(f)). In this embodiment, the thickness of the insulating film 4 is set to be thicker than the thickness of the insulating film 3.

[0083] Next, a semiconductor layer 5 is formed on the insulating films 3 and 4, and a cap layer 21 is formed on the semiconductor layer 5 (FIGS. 7(a) to 7(f)). The semiconductor layer 5 is, for example, a polysilicon layer containing B (boron) atoms, P (phosphorus) atoms, or As (arsenic) atoms as impurity atoms. The semiconductor layer 5 containing B atoms is formed, for example, by forming a semiconductor layer that does not contain B atoms and then implanting B atoms into the semiconductor layer. The semiconductor layer 5 containing P atoms is formed, for example, by forming a semiconductor layer that contains P atoms from the beginning. The same applies to the semiconductor layer 5 containing As atoms. On the other hand, the semiconductor layer 5 containing P atoms or As atoms may be formed by the same method as the semiconductor layer 5 containing B atoms. The cap layer 21 is, for example, a SiN film.

[0084] Next, a trench T is formed in the cap layer 21, semiconductor layer 5, insulating film 4, insulating film 3, and substrate 1 by lithography and RIE (Reactive Ion Etching), an insulating film (e.g., an SiO2 film) is formed in the trench T, and the surface of the insulating film is planarized by CMP (FIGS. 8(a) to 8(f)). As a result, a plurality of element isolation regions 2 are formed in the trench T, i.e., in the substrate 1, insulating film 3, insulating film 4, semiconductor layer 5, and cap layer 21.

[0085] Next, a portion of these element isolation regions 2 is processed from the upper surfaces of the element isolation regions 2 by etch-back (FIGS. 8(a) to 8(f)). As a result, the upper surfaces of these element isolation regions 2 are lowered. Next, the cap layer 21 is removed (FIGS. 8(a) to 8(f)). Note that the etch-back in this embodiment is performed until the height of the upper surfaces of these element isolation regions 2 becomes approximately the same as the height of the upper surface of the semiconductor layer 5.

[0086] Next, an insulating film 6 is formed on the semiconductor layer 5 and these element isolation regions 2 (FIGS. 9(a) to 9(f)). The insulating film 6 is an example of the first portion of the second dielectric layer.

[0087] Next, a resist layer 22 is formed on the insulating film 6, the resist layer 22 is patterned, and the insulating film 6 is processed by etching using the resist layer 22 (FIGS. 10(a) to 10(f)). As a result, the insulating film 6 is removed from the regions shown in FIGS. 10(a) to 10(e), exposing the semiconductor layer 5. Furthermore, the insulating film 6 shown in FIG. 10(f) is processed into a predetermined shape.

[0088] Next, a semiconductor layer 23 is formed on the semiconductor layer 5 and the insulating film 6 (FIGS. 11(a) to 11(f)). The semiconductor layer 23 is, for example, a polysilicon layer (undoped polysilicon layer) that contains almost no impurity atoms such as B atoms, P atoms, or As atoms. The semiconductor layer 23 is an example of the first layer.

[0089] Next, a cap layer 24 is formed on the semiconductor layer 23, a resist layer 25 is formed on the cap layer 24, and the resist layer 25 is patterned (FIGS. 12(a) to 12(f)). As a result, multiple patterns of the resist layer 25 are formed within the region shown in FIGS. 12(a) to 12(f). These patterns are used to form multiple recesses for embedding the insulating film 7, electrode material base layer 8, and electrode material layer 9, as will be described later. The cap layer 24 is, for example, a SiN film. The cap layer 24 is also an example of the first layer.

[0090] Next, the cap layer 24, the semiconductor layer 23, and the semiconductor layer 5 are processed by RIE using the resist layer 25, and then the resist layer 25 is removed (FIGS. 13(a) to 13(f)). As a result, the pattern of the resist layer 25 is transferred to the cap layer 24, the semiconductor layer 23, and the semiconductor layer 5 in the regions shown in FIGS. 13(a) to 13(e), and to the cap layer 24 and the semiconductor layer 23 in the region shown in FIG. 13(f). Furthermore, the shape of the insulating film 6 is transferred to the semiconductor layer 5 in the region shown in FIG. 13(f).

[0091] Next, a sidewall insulating film 11 is formed on the entire surface of the substrate 1, and the sidewall insulating film 11 is processed by etch-back (FIGS. 14(a) to 14(f)). In this etch-back, the sidewall insulating film 11 remains on the side surfaces of the cap layer 24, the semiconductor layer 23, and the semiconductor layer 5, and is removed from other regions. As a result, parts of the upper surfaces of the substrate 1, the element isolation region 2, the semiconductor layer 5, and the cap layer 25 are exposed. In addition, in this etch-back, the element isolation region 2 exposed from the sidewall insulating film 11 is processed, and the upper surface of the processed part of the element isolation region 2 is lowered. In this embodiment, the upper surface of the processed part of the element isolation region 2 is lowered to the upper surface of the substrate 1.

[0092] Next, a plurality of silicide regions 14 are formed in the substrate 1 and the semiconductor layer 5 (FIGS. 14(a) to 14(f)). These silicide regions 14 are formed in the portions of the substrate 1 and the semiconductor layer 5 that are exposed by the etch-back. Note that, in the steps shown in FIGS. 14(a) to 14(f), the step of forming the silicide regions 14 may be omitted.

[0093] Next, a liner insulating film 12 is formed on the entire surface of the substrate 1 (FIGS. 15(a) to 15(f)). As a result, the liner insulating film 12 is formed on the surfaces of the substrate 1, the element isolation region 2, the semiconductor layer 5, the sidewall insulating film 11, the cap layer 24, and the like.

[0094] Next, an insulating film 13a, which is part of the interlayer insulating film 13, is formed on the entire surface of the substrate 1 (FIGS. 16(a) to 16(f)). As a result, the liner insulating film 12 and the like are covered with the insulating film 13a. The insulating film 13a is, for example, an SiO2 film.

[0095] Next, the surface of the insulating film 13a is planarized (FIGS. 17(a) to 17(f)). As a result, the insulating film 13a and the liner insulating film 12 are removed from the upper surface of the cap layer 24, and the upper surface of the cap layer 24 is exposed. The surface of the insulating film 13a is planarized by, for example, CMP. In this way, insulating films such as the sidewall insulating film 11, the liner insulating film 12, and the insulating film 13a are formed on the side surfaces of the cap layer 24, the semiconductor layer 23, the semiconductor layer 5, etc.

[0096] Next, the cap layer 24 is removed (FIGS. 18(a) to 18(f)). As a result, a plurality of recesses H shown in FIGS. 18(a) to 18(f) are formed. Each recess H is formed on the semiconductor layer 23 in the insulating films including the sidewall insulating film 11, the liner insulating film 12, and the insulating film 13a, and the upper surface of the semiconductor layer 23 is exposed in the recess H.

[0097] Next, the semiconductor layers 23 and 5 are removed from within these recesses H (FIGS. 19(a) to 19(f)). As a result, the side surfaces of the sidewall insulating film 11 and the upper surfaces of the insulating films 4, 3, element isolation regions 2, or insulating films 6 are exposed in each recess H shown in FIGS. 19(a) to 19(f). Note that the semiconductor layer 5 shown in FIG. 19(f) is not removed because it is covered with the insulating film 6.

[0098] Next, an insulating film 7 and metal layers 8a, 8b, and 8c of an electrode material base layer 8 are formed in this order on the entire surface of the substrate 1 (FIGS. 20(a) to 20(f)). As a result, the insulating film 7 and metal layers 8a, 8b, and 8c are formed in each recess H, covering the side and bottom surfaces of each recess H. The insulating film 7 is an example of the second portion of the second dielectric layer. The side surfaces of each recess H are formed by a sidewall insulating film 11, and the bottom surface of each recess H is formed by the insulating film 4, the insulating film 3, the element isolation region 2, or the insulating film 6.

[0099] Next, a resist layer 26 is formed on the metal layer 8c and patterned (FIGS. 21(a) to 21(f)). As a result, the regions shown in FIGS. 21(b) and 21(d) are covered with the resist layer 26. Next, the metal layer 8c is removed from the regions shown in FIGS. 21(a), 21(c), 21(e), and 21(f) (FIGS. 21(a) to 21(f)). As a result, as described with reference to FIGS. 2(a) to 4(b), it is possible to remove the metal layer 8c from the regions shown in FIGS. 21(a), 21(c), 21(e), and 21(f) while leaving the metal layer 8c in the regions shown in FIGS. 21(b) and 21(d). Note that the metal layer 8c may not be removed from the region shown in FIG. 21(e) or the region shown in FIG. 21(f). After the steps shown in FIGS. 21(a) to 21(f), the resist layer 26 is removed.

[0100] Next, metal layers 8d and 8e of the electrode material base layer 8 are formed in order on the entire surface of the substrate 1 (FIGS. 22(a) to 22(f)). As a result, the metal layers 8d and 8e are formed in each recess H, covering the side and bottom surfaces of each recess H. The metal layer 8d in the region shown in FIGS. 22(b) and 22(d) is formed on the side and top surface of the metal layer 8c, and the metal layer 8d in the region shown in FIGS. 22(a), 22(c), 22(e), and 22(f) is formed on the side and top surface of the metal layer 8b.

[0101] Next, an electrode material layer 9 is formed over the entire surface of the substrate 1 (FIGS. 23(a) to 23(f)). As a result, the electrode material layer 9 is formed in each of the recesses H. The electrode material layer 9 of this embodiment is formed so that each of the recesses H is filled with the electrode material layer 9.

[0102] Next, the surface of the electrode material layer 9 is planarized by CMP (FIGS. 24(a) to 24(f)). As a result, the electrode material layer 9, the electrode material base layer 8, and the insulating film 7 outside the recesses H are removed, and the upper surfaces of the insulating film 13a, the liner insulating film 12, and the sidewall insulating film 11 are exposed. In this embodiment, since the surface of the electrode material layer 9 is planarized by CMP, the height of the upper surface of the electrode material layer 9 shown in FIGS. 24(a) to 24(f) is approximately uniform. For example, the height of the upper surface of the electrode material layer 9 shown in FIG. 24(a) is approximately the same as the height of the upper surface of the electrode material layer 9 shown in each of FIGS. 24(b) to 24(f).

[0103] Next, an insulating film 13b, which is another part of the interlayer insulating film 13, is formed on the entire surface of the substrate 1 (FIGS. 25(a) to 25(f)). As a result, the electrode material layer 9, the insulating film 13a, etc. are covered with the insulating film 13b. The insulating film 13b is, for example, a SiO2 film.

[0104] Next, a plurality of contact holes HC are formed in the interlayer insulating film 13 (FIGS. 25(a) to 25(f)). Each contact hole HC is formed so as to reach the silicide region 14 or the upper surface of the electrode material layer 9. Thereafter, a contact plug 15 is formed in each contact hole HC (see FIGS. 1(a) to 1(f)). Note that if the step of forming the silicide region 14 is omitted from the steps shown in FIGS. 14(a) to 14(f), the silicide region 14 may be formed in the substrate 1 and the semiconductor layer 5 from the contact hole HC in the steps shown in FIGS. 25(a) to 25(f).

[0105] In this way, the semiconductor device of this embodiment is manufactured. Specifically, transistors HV(N), HV(P), LV(N), LV(P), resistor R, and capacitor C are formed in the region shown in Figures 25(a) to 25(f).

[0106] Continuing with reference to FIGS. 7(a) to 25(f), the method for manufacturing the semiconductor device of this embodiment will be described in further detail below.

[0107] The element isolation region 2 of this embodiment is formed after the insulating film 3, the insulating film 4, the semiconductor layer 5, and the cap layer 21 are formed on the substrate 1 (FIGS. 8(a) to 8(f)). As a result, the height of the upper surface of the element isolation region 2 is higher than the height of the upper surface of the substrate 1. This makes it possible to thin the conductive layers (electrode material base layer 8 and electrode material layer 9) in the resistor R, and therefore makes it possible to increase the value of the resistor R.

[0108] In this embodiment, the gate electrodes of the transistors HV(N), HV(P), LV(N), and LV(P), the conductive layer of the resistor R, and the upper electrode layer of the capacitor C are formed by embedding an electrode material base layer 8 and an electrode material layer 9 in the recess H (see, for example, FIGS. 23(a) to 23(f)). This allows these gate electrodes, conductive layers, and upper electrode layers to be formed from suitable materials such as metal layers.

[0109] At this time, the recesses H for the electrode material base layer 8 and the electrode material layer 9 are formed while leaving the semiconductor layer 5 for the capacitor C (see, for example, FIGS. 19(a) to 19(f)). This makes it possible to form the capacitor C including a lower capacitor and an upper capacitor, and the capacitance of the capacitor C can be increased.

[0110] Next, various modifications of this embodiment will be described.

[0111] (1) First Modification 26 to 28 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment.

[0112] Figures 26(a) to 26(f) correspond to Figures 17(a) to 17(f), respectively. In this modification, after the steps shown in Figures 17(a) to 17(f) are performed, a resist layer 27 is formed on the entire surface of the substrate 1, and the resist layer 27 is patterned (Figures 26(a) to 26(f)). As a result, the region shown in Figure 26(a) is covered with the resist layer 27.

[0113] Next, the cap layer 24 is removed (FIGS. 27(a) to 27(f)). As a result, the cap layer 24 remains in the region shown in FIG. 27(a), while a plurality of recesses H shown in FIGS. 27(b) to 27(f) can be formed. Each recess H is formed on the semiconductor layer 23 in the insulating film including the sidewall insulating film 11, the liner insulating film 12, and the insulating film 13a, and the upper surface of the semiconductor layer 23 is exposed in the recess H.

[0114] Next, the processes shown in FIGS. 19(a) to 19(f), 20(a) to 20(f), ..., and 25(a) to 25(f) are performed. As a result, a plurality of contact holes HC are formed in the interlayer insulating film 13 (FIGS. 28(a) to 28(f)). Each contact hole HC is formed to reach the silicide region 14 or the upper surface of the electrode material layer 9. However, the contact hole HC shown in the center of FIG. 28(a) is formed to penetrate the cap layer 24 and reach the semiconductor layer 23. Thereafter, a contact plug 15 is formed in each contact hole HC (see FIGS. 1(a) to 1(f)).

[0115] In addition, if the process of forming the silicide region 14 is omitted in the processes shown in Figures 14(a) to 14(f), the silicide region 14 may be formed in the substrate 1, the semiconductor layer 5, and the semiconductor layer 23 from the contact hole HC in the processes shown in Figures 28(a) to 28(f).

[0116] In this way, the semiconductor device of this embodiment is manufactured. Specifically, transistors HV(N), HV(P), LV(N), LV(P), resistor R, and capacitor C are formed in the region shown in Figures 28(a) to 28(f).

[0117] According to this modification, the gate electrode of the transistor HV(N) can be formed from the semiconductor layers 5 and 23. Similarly, in this modification, the gate electrode of the transistor HV(P), the gate electrode of the transistor LV(N), the gate electrode of the transistor LV(P), or the conductive layer of the resistor R may be formed from the semiconductor layers 5 and 23.

[0118] (2) Second Modification FIG. 29 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment.

[0119] 29(a) and 29(b) show two resistors R formed on the same substrate 1. The resistor R shown in FIG. 29(a) includes a conductive layer formed of a metal layer (electrode material base layer 8 and electrode material layer 9), similar to the conductive layer of the resistor R shown in FIG. 1(e), FIG. 4(a), or FIG. 25(e). On the other hand, the resistor R shown in FIG. 29(b) includes a conductive layer formed of a semiconductor layer (semiconductor layers 5 and 23), similar to the gate electrode of the transistor HV(N) shown in FIG. 28(a).

[0120] According to this modification, it is possible to form two types of resistors R made of different materials on the same substrate 1. The resistor R shown in FIG. 29(b) can be formed, for example, by diverting the process of forming the gate electrode of the transistor HV(N) of the first modification to the process of forming the conductive layer of the resistor R.

[0121] When resistor R is applied to a circuit that requires small resistance variations, it is desirable to form resistor R from a metal material. On the other hand, when resistor R is applied to a circuit that requires small circuit area, even if large resistance variations are acceptable, it is desirable to form resistor R from a semiconductor material. When the semiconductor device of this modification includes the former circuit and the latter circuit, the structure of FIG. 29(a) may be applied to resistor R of the former, and the structure of FIG. 29(b) may be applied to resistor R of the latter.

[0122] (3) Third Modification FIG. 30 is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the first embodiment.

[0123] 30, like FIG. 4(b), shows a capacitor C and two element isolation regions 2 formed near the capacitor C. FIG. 30 also shows two element isolation regions 2 formed away from the capacitor C. Hereinafter, with regard to these two element isolation regions 2, the left element isolation region 2 will be referred to as the "left element isolation region 2" and the right element isolation region 2 will be referred to as the "right element isolation region 2."

[0124] In FIG. 30, the upper surface of the left isolation region 2 is located at a higher position, and the upper surface of the right isolation region 2 is located at a lower position. In this manner, the isolation regions 2 of this modification may have upper surfaces with different heights. The height of the upper surface of the left isolation region 2 is, for example, the same as the height of the uppermost surface of the isolation region 2 shown in FIG. 1(e). On the other hand, the height of the upper surface of the right isolation region 2 is higher than the height of the upper surface of the substrate 1 in FIG. 30, but it may also be the same as the height of the upper surface of the substrate 1.

[0125] Such a difference in height between the upper surfaces of the isolation regions 2 can occur, for example, when manufacturing a semiconductor device using the steps shown in Figures 7(a) to 25(f). For example, in the steps shown in Figures 14(a) to 14(f), the upper surfaces of some of the isolation regions 2 formed on the substrate 1 may be etched, while the upper surfaces of other parts of the isolation regions 2 formed on the substrate 1 may not be etched. As a result, the left isolation region 2 and the right isolation region 2 shown in Figure 30 may be formed on the same substrate 1.

[0126] 30 has the same height as the upper surface of the substrate 1 shown in Figures 1(c) to 1(f). In Figure 30, the difference in height between the upper surface of the substrate 1 and the upper surface of the right element isolation region 2 may be smaller than the difference in height between the upper surface of the right element isolation region 2 and the upper surface of the semiconductor layer 5.

[0127] In FIG. 30, the isolation region 2 adjacent to the right side of the capacitor C is in contact with the capacitor C. In FIG. 30, the difference in height between the upper surface of the semiconductor layer 5 and the upper surface of this isolation region 2 is smaller than the difference in height between the upper surface of this isolation region 2 and the upper surface of the substrate 1. In the example shown in FIG. 30, the difference in height between the upper surface of the semiconductor layer 5 and the upper surface of this isolation region 2 is almost zero. The upper surface of this isolation region 2 is an example of a fifth upper surface.

[0128] (4) Fourth Modification FIG. 31 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the first embodiment.

[0129] 31(a) and 31(b) are a plan view and a cross-sectional view showing the structure of the capacitor C of this modification. Fig. 31(b) corresponds to Fig. 1(f), but omits the sidewall insulating film 11, the liner insulating film 12, the interlayer insulating film 13, the silicide region 14, and the contact plug 15.

[0130] 31(a) shows, in a top view, a contour line L1 of the intermediate electrode layer (semiconductor layer 5), a contour line L2 of the upper dielectric layer (insulating films 6, 7), and a contour line L3 of the upper electrode layer (electrode material base layer 8 and electrode material layer 9). In this modification, these contour lines L1 to L3 are all rectangular. In this modification, the contour line L2 of the upper dielectric layer has a portion L2a located inside the contour line L1 of the intermediate electrode layer and a portion L2b located outside the contour line L1 of the intermediate electrode layer, and surrounds the contour line L3 of the upper electrode layer.

[0131] 31(a) and 31(b) further show a region AA that is a part of the substrate 1. In a top view, the region AA is surrounded in a ring shape by an insulating film (e.g., an SiO2 film) that forms a plurality of element isolation regions 2 shown in FIG. 31(b). The insulating film 3, semiconductor layer 5, insulating film 6, insulating film 7, electrode material base layer 8, and electrode material layer 9 included in the capacitor C of this modification are formed on the region AA. The region AA is called, for example, an active area.

[0132] The semiconductor device of this modification may have the structure shown in Fig. 31(c) instead of the structure shown in Fig. 31(b). In Fig. 31(c), the insulating film 6 is removed from the upper surface of a part of the element isolation region 2 located to the left of the capacitor C and from the upper surface of the element isolation region 2 located to the right of the capacitor C. As a result, the height of these upper surfaces is reduced by the effect of etching.

[0133] As described above, according to this embodiment, when devices such as transistors HV(N), HV(P), LV(N), and LV(P), resistors R, and capacitors C are formed on the substrate 1, it is possible to form devices with suitable performance. For example, by forming resistor R on an isolation region 2 having an upper surface higher than the upper surface of the substrate 1, it is possible to increase the value of resistor R. Furthermore, by forming capacitor C including a lower capacitor and an upper capacitor, it is possible to increase the capacitance of capacitor C.

[0134] (Second embodiment) FIG. 32 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0135] The semiconductor device of this embodiment includes, for example, a three-dimensional semiconductor memory. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer including an array chip 31 and a circuit wafer including a circuit chip 32. The semiconductor device of this embodiment corresponds to an example of the semiconductor device of the first embodiment.

[0136] The array chip 31 includes a memory cell array 41 including a plurality of memory cells, an insulating film 42 on the memory cell array 41, and an interlayer insulating film 43 below the memory cell array 41. The insulating film 42 is, for example, a SiO2 film. The interlayer insulating film 43 is, for example, a stacked film including a SiO2 film and another insulating film.

[0137] The circuit chip 32 is provided below the array chip 31. The symbol S indicates the bonding surface between the array chip 31 and the circuit chip 32. The circuit chip 32 includes an interlayer insulating film 44 below the interlayer insulating film 43, and a substrate 45 below the interlayer insulating film 44. The interlayer insulating film 44 is, for example, a laminated film including an SiO2 film and other insulating films. The substrate 45 is, for example, a semiconductor substrate such as a Si substrate. The substrate 45 of this embodiment corresponds to an example of the substrate 1 of the first embodiment, and the interlayer insulating film 44 of this embodiment corresponds to an example of the interlayer insulating film 13 of the first embodiment.

[0138] 32 shows the X direction and Y direction which are parallel to the surface of the substrate 45 and perpendicular to each other, and the Z direction which is perpendicular to the surface of the substrate 45. The X direction, Y direction, and Z direction intersect with each other.

[0139] The array chip 31 includes a plurality of word lines WL as a plurality of electrode layers in a memory cell array 41. FIG. 32 shows a staircase structure 51 in the memory cell array 41 and a plurality of beam portions 52 provided in the staircase structure 51. Each word line WL is electrically connected to a word wiring layer 54 via a contact plug 53. Each columnar portion CL passing through the plurality of word lines WL is electrically connected to a bit line BL via a via plug 55 and is also electrically connected to a source line SL. The bit line BL is provided below the plurality of word lines WL, and the source line SL is provided above the plurality of word lines WL.

[0140] The circuit chip 32 includes a plurality of transistors 61. Each transistor 61 includes a gate insulating film 61a and a gate electrode 61b provided in this order on the substrate 45, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 45. The circuit chip 32 also includes a plurality of contact plugs 62 provided on the gate electrodes 61b, source diffusion layers, or drain diffusion layers of the plurality of transistors 61. The circuit chip 32 also includes a wiring layer 63, a wiring layer 64, and a wiring layer 65. The wiring layer 63 includes a plurality of wires and is provided on the plurality of contact plugs 62. The wiring layer 64 includes a plurality of wires and is provided on the wiring layer 63. The wiring layer 65 includes a plurality of wires and is provided on the wiring layer 64.

[0141] The circuit chip 32 further includes a plurality of via plugs 66 provided on the wiring layer 65, and a plurality of metal pads 67 provided on the plurality of via plugs 66. The metal pads 67 are, for example, a metal layer including a Cu (copper) layer. The circuit chip 32 functions as a circuit that controls the operation of the array chip 31. This circuit is composed of transistors 61 and the like, and is electrically connected to the metal pads 67.

[0142] The plurality of transistors 61 of this embodiment include the transistors HV(N), HV(P), LV(N), and LV(P) of the first embodiment, and the transistors HV(N), HV(P), LV(N), and LV(P) configure the above circuit. The above circuit further includes the resistor R and capacitor C of the first embodiment. The contact plug 62 of this embodiment corresponds to an example of the contact plug 15 of the first embodiment.

[0143] The array chip 31 includes a plurality of metal pads 71 ​​provided on the plurality of metal pads 67, and a plurality of via plugs 72 provided on the plurality of metal pads 71. The metal pads 71 ​​are, for example, a metal layer including a Cu layer. The array chip 31 also includes a wiring layer 73 and a wiring layer 74. The wiring layer 73 includes a plurality of wires and is provided on the plurality of via plugs 72. The wiring layer 74 includes a plurality of wires and is provided on the wiring layer 73. The bit lines BL are included in the wiring layer 74. The above circuits are electrically connected to the memory cell array 41 via the metal pads 71, 67, etc., and control the operation of the memory cell array 41 via the metal pads 71, 67, etc.

[0144] The array chip 31 further includes a plurality of via plugs 75 provided on the wiring layer 74, and metal pads 76 provided on the plurality of via plugs 75 and on the insulating film 42. The array chip 31 also includes a passivation insulating film 77 provided on the metal pads 76 and on the insulating film 42. The metal pads 76 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of this embodiment. The passivation insulating film 77 is, for example, a laminated film including an SiO2 film and an SiN film, and has an opening P that exposes the top surface of the metal pad 76. The metal pads 76 can be electrically connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through the opening P.

[0145] FIG. 33 is an enlarged cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0146] FIG. 33 shows the memory cell array 41 shown in FIG. 32. The memory cell array 41 includes a stacked film 81 including multiple electrode layers 81a and multiple insulating films 81b alternately stacked in the Z direction. The multiple electrode layers 81a function as the above-mentioned word lines WL, for example. Each electrode layer 81a is, for example, a metal layer including a W layer. Each insulating film 81b is, for example, a SiO2 film.

[0147] FIG. 33 further illustrates one of the plurality of columnar portions CL illustrated in FIG. 32. Each columnar portion CL includes a memory insulating film 82, a channel semiconductor layer 83, and a core insulating film 84, which are provided in this order on the side surface of a stacked film 81. The memory insulating film 82 includes a block insulating film 82a, a charge storage layer 82b, and a tunnel insulating film 82c, which are provided in this order on the side surface of the stacked film 81. The block insulating film 82a is, for example, a SiO2 film. The charge storage layer 82b is, for example, an insulating film such as a SiN film. The charge storage layer 82b may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 82c is, for example, a SiO2 film. The channel semiconductor layer 83 is, for example, a polysilicon layer. The channel semiconductor layer 83 functions as a channel of the memory cell. The core insulating film 84 is, for example, a SiO2 film.

[0148] 34 and 35 are cross-sectional views showing a method for manufacturing the semiconductor device of the second embodiment.

[0149] Figure 34 shows an array wafer W1 including a plurality of array chips 31 and a circuit wafer W2 including a plurality of circuit chips 32. The orientation of the array wafer W1 in Figure 34 is opposite to the orientation of the array chips 31 in Figure 32. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 34 shows the array wafer W1 before its orientation is reversed for bonding, and Figure 32 shows the array chips 31 after their orientation is reversed for bonding, bonding, and dicing.

[0150] 34, symbol S1 indicates the upper surface of the array wafer W1, and symbol S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 46 provided under an insulating film 42. The substrate 46 is, for example, a semiconductor substrate such as a Si substrate.

[0151] In this embodiment, first, as shown in FIG. 34, the memory cell array 41, insulating film 42, interlayer insulating film 43, metal pad 71, etc. are formed on the substrate 46 of the array wafer W1, and the interlayer insulating film 44, transistor 61, metal pad 67, etc. are formed on the substrate 45 of the circuit wafer W2. Next, as shown in FIG. 35, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the surface S1 and the surface S2 face each other. This bonds the interlayer insulating film 43 and the interlayer insulating film 44. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 71 and the metal pad 67. In this way, the substrate 46 and the substrate 45 are bonded together with the interlayer insulating films 43 and 44 interposed therebetween.

[0152] Thereafter, the substrate 46 is removed by CMP, the substrate 45 is thinned by CMP, and the array wafer W1 and the circuit wafer W2 are then cut into a plurality of chips (dicing). In this manner, the semiconductor device shown in Fig. 32 is manufactured. Note that the metal pads 76 and the passivation insulating film 77 are formed on the insulating film 42 after the substrate 46 is removed and the substrate 45 is thinned.

[0153] 32 shows the boundary surface between the interlayer insulating film 43 and the interlayer insulating film 44 and the boundary surface between the metal pad 71 and the metal pad 67, but these boundaries may not be visible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of the metal pad 71 or the side surface of the metal pad 67, or the positional deviation between the side surface of the metal pad 71 and the side surface of the metal pad 67.

[0154] According to this embodiment, by applying the semiconductor device of the first embodiment to a three-dimensional semiconductor memory, it becomes possible to form a device having suitable performance for the three-dimensional semiconductor memory.

[0155] (Third embodiment) FIG. 36 is a block diagram showing the configuration of a memory system according to the third embodiment.

[0156] The memory system of this embodiment includes a NAND memory 101 and a memory controller 102. The NAND memory 101 includes a memory cell array 91, a command register 92, an address register 93, a sequencer 94, a voltage generation circuit 95, a row decoder module 96, a sense amplifier module 97, and a temperature sensor 98. The NAND memory 101 of this embodiment corresponds to an example of the semiconductor device of the second embodiment. The memory cell array 91 of this embodiment corresponds to an example of the memory cell array 41 of the second embodiment.

[0157] The operation of the NAND memory 101 is controlled by the memory controller 102. The memory controller 102 operates in response to a request from a host device (not shown). For example, the memory controller 102 controls reading of data from the NAND memory 101 in response to a read request from the host device. The memory controller 102 also controls writing of data to the NAND memory 101 in response to a write request from the host device. The memory controller 102 also controls erasure of data from the NAND memory 101 in response to an erase request from the host device.

[0158] The memory cell array 91 includes a plurality of blocks BLK. Each block BLK is a collection of a plurality of memory cells capable of storing data non-volatilely. The blocks BLK are used, for example, as a unit for erasing data. Meanwhile, pages, which will be described later, are used, for example, as a unit for writing and reading data. FIG. 36 shows n+1 blocks BLK_0 to BLK_n (n is an integer equal to or greater than 1) as examples of the blocks BLK. The memory cell array 91 further includes a plurality of bit lines and a plurality of word lines. Each memory cell is associated with one bit line and one word line.

[0159] The command register 92 holds the command CMD that the NAND memory 101 receives from the memory controller 102. The command CMD includes, for example, an instruction to make the sequencer 94 execute a read operation, a write operation, an erase operation, or the like.

[0160] The address register 93 holds address information ADD that the NAND memory 101 receives from the memory controller 102. The address information ADD includes, for example, a block address BA and a column address CA. The block address BA and the column address CA are used to select a block BLK and a bit line, respectively.

[0161] The sequencer 94 controls the overall operation of the NAND memory 101. For example, the sequencer 94 controls the operations of the voltage generation circuit 95, the row decoder module 96, and the sense amplifier module 97 based on the command CMD held in the command register 92. As a result, a read operation, a write operation, an erase operation, etc. are executed based on the command CMD.

[0162] The voltage generation circuit 95 generates voltages used in read, write, erase, and other operations under the control of the sequencer 94. For example, the voltage generation circuit 95 applies the generated voltage to a signal line corresponding to a selected word line. The voltage generation circuit 95 also generates a power supply voltage for the temperature sensor 98 and applies the power supply voltage to the temperature sensor 98.

[0163] The row decoder module 96 selects a block BLK based on the block address BA held in the address register 93, and transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0164] During a write operation, the sense amplifier module 97 transfers write data received from the memory controller 102 to the memory cell array 91. During a read operation, the sense amplifier module 97 determines the value stored in each memory cell based on the voltage of the bit line, and transfers the result of this determination to the memory controller 102 as read data DAT.

[0165] The temperature sensor 98 detects the temperature of the NAND memory 101. The temperature sensor 98 generates temperature information based on the detected temperature and transmits the temperature information to the sequencer 94. The temperature information is used by the sequencer 94 to correct the voltage generated by the voltage generation circuit 95 during, for example, a write operation, a read operation, or an erase operation.

[0166] FIG. 37 is a circuit diagram showing the configuration of a memory cell array 91 of the third embodiment.

[0167] FIG. 37 shows one of the multiple blocks BLK included in the memory cell array 91. As shown in FIG. 37, each block BLK in this embodiment includes multiple string units SU0 to SU3. Each of the string units SU0 to SU3 includes m+1 NAND strings NS (m is an integer equal to or greater than 1) between m+1 bit lines BL0 to BLm and one source line SRC. Hereinafter, each of the string units SU0 to SU3 will also be referred to as a "string unit SU," and each of the bit lines BL0 to BLm will also be referred to as a "bit line BL."

[0168] In the string unit SU0, the NAND string NS between the bit line BL0 and the source line SRC includes memory cell transistors (memory cells) MT0 to MT7 on the word lines WL0 to WL7. This NAND string NS further includes a select transistor STS on the source-side select line SGS0 and a select transistor STD on the drain-side select line SGD0. In this embodiment, the other NAND strings NS in the memory cell array 91 have a similar structure. Hereinafter, each of the word lines WL0 to WL7 will also be referred to as a "word line WL," each of the memory cell transistors MT0 to MT7 will also be referred to as a "memory cell transistor MT," and each of the select transistors STS and STD will also be referred to as a "select transistor ST."

[0169] Each block BLK in this embodiment includes multiple cell units CU. Each cell unit CU includes multiple memory cell transistors MT arranged on one word line WL in one string unit SU. Therefore, each cell unit CU in FIG. 37 includes m+1 memory cell transistors MT. Each cell unit CU corresponds to one page. In each cell unit CU, each word line WL is electrically connected in common to the gates of the m+1 memory cell transistors MT.

[0170] FIG. 38 is a circuit diagram showing the configuration of a voltage generating circuit 95 according to the third embodiment.

[0171] 38, the voltage generating circuit 95 includes a plurality of charge pumps CP1 to CP4, a plurality of resistors R1 and R2, an operational amplifier AMP1, a state control circuit STCNTL, and a plurality of logic gates (AND gates) AND1 to AND4. FIG. 38 further shows a node NOUT and a node N1 in the voltage generating circuit 95.

[0172] When a voltage V is input to the voltage generation circuit 95, the voltage generation circuit 95 generates a voltage V higher than the voltage V and outputs the voltage V from a node NOUT. The voltage V is supplied to the voltage generation circuit 95 from a voltage source in the NAND memory 101, for example. The voltage V is used in, for example, a read operation, a write operation, an erase operation, and the like.

[0173] 38 is output from the sequencer 94 and input to the voltage generating circuit 95. The signal BIN is a control signal used by the sequencer 94 to control the operation of the voltage generating circuit 95, and is, for example, a digital signal. As will be described later, the waveform of the voltage VOUT changes depending on the information held by the signal BIN. Therefore, the sequencer 94 can change the waveform of the voltage VOUT by controlling the information held by the signal BIN.

[0174] Next, still referring to FIG. 38, the components in the voltage generating circuit 95 will be described in detail.

[0175] Charge pump CP1 has an input terminal to which voltage VIN is input, an input terminal to which signal PCLK1 is input, and an output terminal electrically connectable to node NOUT. This is similar for charge pumps CP2 to CP4. However, charge pumps CP2 to CP4 each have an input terminal to which signals PCLK2 to PCLK4 are input instead of signal PCLK1. Hereinafter, each of charge pumps CP1 to CP4 will also be referred to as a "charge pump CP," and each of signals PCLK1 to PCLK4 will also be referred to as a "signal PCLK."

[0176] Each charge pump CP performs a boost operation while the signal PCLK input to that charge pump CP is the clock signal CLK and the boost operations of all charge pumps CP are not collectively prohibited by the sequencer 94. For example, when the voltage VOUT is higher than the threshold for collectively prohibiting the boost operation, the sequencer 94 collectively prohibits the boost operations of all charge pumps CP. When the signal PCLK input to a certain charge pump CP is the clock signal CLK and that charge pump CP is designated by the state control circuit STCNTL as a pump capable of boost operation, the state of that charge pump CP is called "active." An active charge pump CP performs a boost operation while the boost operations of all charge pumps CP are not collectively prohibited by the sequencer 94.

[0177] On the other hand, each charge pump CP stops its boosting operation when the signal PCLK input to that charge pump CP is not the clock signal CLK or when the boosting operations of all charge pumps CP are collectively prohibited by the sequencer 94. When the signal PCLK input to a certain charge pump CP is not the clock signal CLK or when that charge pump CP is designated by the state control circuit STCNTL as a pump that is not capable of boosting, the state of that charge pump CP is called "inactive." An inactive charge pump CP stops its boosting operation even when the boosting operations of all charge pumps CP are not collectively prohibited by the sequencer 94. An example of when the signal PCLK input to a charge pump CP is not the clock signal CLK is when the value of the signal PCLK is maintained at L (low), as will be described later.

[0178] Resistor R1 is arranged between node NOUT and node N1. Resistor R2 is arranged between node N1 and the ground node. Therefore, resistors R1 and R2 are arranged in series between node NOUT and the ground node. Resistor R2 in this embodiment is a variable resistor. The value of resistor R2 can be changed by signal BIN. The relationship between voltages VOUT and VMON is VOUT={(R1+R2) / R2}VMON.

[0179] The operational amplifier AMP1 has a non-inverting input terminal to which a reference voltage VREF is input, an inverting input terminal to which a voltage VMON is input, and an output terminal from which a signal FLG1 is output. The signal FLG1 is generated based on the comparison result between the reference voltage VREF and the voltage VMON. For example, when the voltage VMON is less than the reference voltage VREF, the value of the signal FLG1 becomes H (high) level. On the other hand, when the voltage VMON is equal to or greater than the reference voltage VREF, the value of the signal FLG1 becomes L (low) level.

[0180] The state control circuit STCNTL has an input terminal to which a signal FLG1 is input from the operational amplifier AMP1, an input terminal to which a clock signal CLK is input, and an output terminal that outputs signals EN1 to EN4 to the logic gates AND1 to AND4, respectively. Using the clock signal CLK, the state control circuit STCNTL calculates a period NH during which the value of the signal FLG1 is maintained at H level and a period NL during which the value of the signal FLG1 is maintained at L level. The state control circuit STCNTL further generates signals EN1 to EN4 based on the period NH and the period NL. The signals EN1 to EN4 specify whether the charge pumps CP1 to CP4 are active or inactive, respectively. Hereinafter, each of the signals EN1 to EN4 will also be referred to as a "signal EN."

[0181] When the value of the signal EN is at H level, the signal EN specifies that the charge pump CP is activated. On the other hand, when the value of the signal EN is at L level, the signal EN specifies that the charge pump CP is deactivated. The state control circuit STCNTL controls the number Nu of signals EN1 to EN4 that have a value of H level based on the period NH and the period NL. The state of the state control circuit STCNTL transitions among four states S1 to S4 according to the number Nu. The states S1 to S4 are states where the number Nu is 1 to 4, respectively.

[0182] The logic gate AND1 has an input terminal to which the signal EN1 is input, an input terminal to which the clock signal CLK is input, and an output terminal that outputs the signal PCLK1 to the charge pump CP1. The signal PCLK1 indicates the result of an AND operation between the signal EN1 and the clock signal CLK. For example, when the value of the signal EN1 is H level, the signal PCLK1 becomes the clock signal CLK. On the other hand, when the value of the signal EN1 is L level, the value of the signal PCLK1 is maintained at L level. This is also true for the logic gates AND2 to AND4. However, the logic gates AND2 to AND4 each have an input terminal to which the signals EN2 to EN4 are input instead of the signal EN1, and an output terminal that outputs the signals PCLK2 to PCLK4 instead of the signal PCLK1. Hereinafter, each of the logic gates AND1 to AND4 will also be referred to as a "logic gate AND."

[0183] FIG. 39 is a circuit diagram showing the configuration of the resistor R2 in the third embodiment.

[0184] The resistor R2 includes a control circuit 99, N resistors such as resistors R2a to R2e, and N transistors such as transistors TRa to TRe (N is an integer equal to or greater than 2). These circuit elements allow the resistor R2 to function as a variable resistor.

[0185] The resistors R2a to R2e are connected in parallel with the resistor R1. The transistors TRa to TRe are connected in series with the resistors R2a to R2e, respectively. The control circuit 99 outputs control signals for controlling the transistors TRa to TRe based on the signal BIN. The control signals for the transistors TRa to TRe are supplied to the gates of the transistors TRa to TRe, respectively. The above also applies to resistors other than the resistors R2a to R2e and transistors other than the transistors TRa to TRe.

[0186] The control circuit 99 controls the ON / OFF of the N transistors using the control signals described above based on the signal BIN. As a result, the value of resistor R2 is determined by the value of the resistor connected in series with the transistor that is turned on. This makes it possible to change the value of resistor R2 using the signal BIN.

[0187] The signal BIN is, for example, an N-bit digital signal, and the value of each bit, "L level" or "H level," corresponds to the "off" or "on" of the corresponding transistor. For example, when the values ​​of all bits are H level, all N transistors are turned on. Figure 39 shows the BIN signal included in the BIN signal. <0> ~BIN <4> The transistors TRa to TRe are turned on and off by the BIN <0> ~BIN <4> is controlled by

[0188] FIG. 40 is a circuit diagram showing the configuration of the charge pump CP of the third embodiment.

[0189] The charge pump CP shown in FIG. 40 includes n+1 transistors T1 to Tn+1 (n is an integer greater than or equal to 1) arranged in series between an input terminal for a voltage VIN and an output terminal for a voltage VOUT. The charge pump CP shown in FIG. 40 further includes n capacitors C1 to Cn. One electrode of capacitor Ck is electrically connected to a node between transistor Tk and transistor Tk+1, and the other electrode of capacitor Ck is electrically connected to the input terminal for signal PCLK or signal / PCLK (k is an integer satisfying the condition 1≦k≦n). When the value of k is odd, capacitor Ck is electrically connected to the input terminal for signal / PCLK, and when the value of k is even, capacitor Ck is electrically connected to the input terminal for signal PCLK.

[0190] Each of the capacitors C1 to Cn in this embodiment is the capacitor C in the first embodiment. Furthermore, each of the transistors T1 to Tn+1 in this embodiment may be any of the transistors HV(N), HV(P), LV(N), and LV(P) in the first embodiment.

[0191] The transistors T1 to Tn+1 of this embodiment may have a triple-well structure. For example, a P-type semiconductor substrate may have an N-type well, a P-type well may be provided within this N-type well, and the transistors T1 to Tn+1 may be provided within this P-type well.

[0192] According to this embodiment, by applying the semiconductor device of the first embodiment to the NAND memory 101, it is possible to form a device having suitable performance for the NAND memory 101. For example, it is possible to form a capacitor C having suitable performance for the charge pump CP. This makes it possible to form the charge pump CP, which handles high voltages, using a capacitor C that can appropriately handle high voltages.

[0193] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0194] 1: substrate, 2: element isolation region, 3: insulating film, 4: insulating film, 5: semiconductor layer, 6: insulating film, 7: insulating film, 8: electrode material base layer, 8a: metal layer, 8b: metal layer, 8c: metal layer, 8d: metal layer, 8e: metal layer, 9: electrode material layer, 11: sidewall insulating film, 11a: insulating film, 11b: insulating film, 11c: insulating film, 12: liner insulating film, 12a: insulating film, 12b: insulating film, 13: interlayer insulating film, 13a: insulating film, 13b: insulating film, 14: silicide region; 15: contact plug; 16: source / drain region; 21: cap layer, 22: resist layer, 23: semiconductor layer, 24: cap layer, 25: resist layer, 26: resist layer, 27: resist layer, 31: array chip, 32: circuit chip, 41: memory cell array, 42: insulating film, 43: interlayer insulating film, 44: Interlayer insulating film, 45: Substrate, 46: Substrate, 51: staircase structure portion, 52: beam portion, 53: contact plug, 54: word wiring layer, 55: via plug, 61: transistor; 61a: gate insulating film; 61b: gate electrode; 62: contact plug, 63: wiring layer, 64: wiring layer, 65: wiring layer, 66: via plug, 67: metal pad, 71: metal pad, 72: via plug, 73: wiring layer, 74: wiring layer, 75: via plug, 76: metal pad, 77: passivation insulating film, 81: laminated film, 81a: electrode layer, 81b: insulating film, 82: memory insulating film, 82a: block insulating film, 82b: charge storage layer, 82c: tunnel insulating film, 83: channel semiconductor layer, 84: core insulating film, 91: memory cell array, 92: command register, 93: address register, 94: sequencer, 95: voltage generation circuit, 96: row decoder module, 97: Sense amplifier module, 98: Temperature sensor, 99: Control circuit, 101: NAND memory, 102: memory controller

Claims

1. a substrate having a first top surface; an isolation region provided in the substrate and having a second upper surface higher than the first upper surface; at least one transistor including a gate insulating film provided on the first upper surface of the substrate and a gate electrode provided on the gate insulating film; a resistor including a conductive layer provided on the second upper surface of the element isolation region; a capacitor including a first dielectric layer provided on the first top surface of the substrate, a first electrode layer provided on the first dielectric layer, a second dielectric layer provided on the first electrode layer, and a second electrode layer provided on the second dielectric layer; A semiconductor device comprising:

2. the gate insulating film includes one or more insulating films, 2. The semiconductor device according to claim 1, wherein at least one of said one or more insulating films is provided on a bottom surface and a side surface of said gate electrode.

3. the first upper surface of the substrate includes a third upper surface and a fourth upper surface higher than the third upper surface; The at least one transistor a first transistor including the gate insulating film provided on the third upper surface; a second transistor including the gate insulating film provided on the fourth upper surface, a thickness of the gate insulating film in the first transistor is greater than a thickness of the gate insulating film in the second transistor; 2. The semiconductor device according to claim 1, wherein said second upper surface of said element isolation region is higher than said third upper surface and higher than said fourth upper surface.

4. the gate insulating film contains a metal element, the second dielectric layer contains the metal element; The semiconductor device according to claim 1 .

5. the conductive layer is provided on the second upper surface of the element isolation region via one or more insulating films; The semiconductor device according to claim 1 , wherein at least one of said one or more insulating films is provided on a bottom surface and a side surface of said conductive layer.

6. an isolation region disposed in the substrate, the isolation region having a fifth upper surface higher than the first upper surface, the fifth upper surface being adjacent to the capacitor; 2 . The semiconductor device according to claim 1 , wherein a difference in height between the upper surface of said first electrode layer and said fifth upper surface is smaller than a difference in height between said fifth upper surface and said first upper surface.

7. the second dielectric layer includes one or more insulating films; The semiconductor device according to claim 1 , wherein at least one of said one or more insulating films is provided on a lower surface and a side surface of said second electrode layer.

8. The semiconductor device according to claim 1 , wherein the first electrode layer includes a semiconductor layer, and the second electrode layer includes a metal layer.

9. 2. The semiconductor device according to claim 1, wherein the height of the upper surface of said first electrode layer is the same as the height of said second upper surface of said element isolation region.

10. 2. The semiconductor device according to claim 1, wherein a lower surface of said second electrode layer is higher than a second upper surface of said element isolation region.

11. 2. The semiconductor device according to claim 1, wherein said capacitor is provided in a charge pump.

12. the gate insulating film in the at least one transistor includes a first insulating film and a second insulating film provided on the first insulating film; the first dielectric layer in the capacitor includes a third insulating film formed of the same material as the first insulating film; the second dielectric layer in the capacitor includes a fourth insulating film formed of the same material as the second insulating film; The semiconductor device according to claim 1 .

13. 13. The semiconductor device according to claim 12, wherein the conductive layer in the resistor is provided on the second upper surface of the element isolation region via a fifth insulating film made of the same material as the second insulating film.

14. 13. The semiconductor device according to claim 12, wherein said second dielectric layer in said capacitor further includes a sixth insulating film provided below said fourth insulating film.

15. the gate electrode in the at least one transistor includes a first conductive layer and a second conductive layer disposed on the first conductive layer; the conductive layers in the resistor include the first conductive layer and the second conductive layer; the second electrode layer in the capacitor includes the first conductive layer and the second conductive layer; The semiconductor device according to claim 1 .

16. A substrate; a first dielectric layer disposed on the substrate; a first electrode layer disposed on the first dielectric layer and forming a first capacitor between the first electrode layer and the substrate; a second dielectric layer provided on the first electrode layer; a second electrode layer provided on the second dielectric layer and forming a second capacitor between the first electrode layer and the second electrode layer; the second dielectric layer includes one or more insulating films; At least one of the one or more insulating films is provided on a lower surface and a side surface of the second electrode layer.

17. 17. The semiconductor device according to claim 16, wherein, in a top view, the contour of the second dielectric layer has a portion located within the contour of the second electrode layer and a portion located outside the contour of the second electrode layer, and surrounds the contour of the third electrode layer.

18. forming a first dielectric layer on a substrate; forming a first electrode layer on the first dielectric layer to form a first capacitor between the substrate and the first electrode layer; forming a second dielectric layer on the first electrode layer; forming a first layer on the second dielectric layer; forming an insulating film on a side surface of the first layer; removing the first layer after forming the insulating film; forming a second electrode layer on the second dielectric layer within the insulating film after removing the first layer, to form a second capacitor between the first electrode layer and the second electrode layer; A method for manufacturing a semiconductor device, comprising:

19. a first portion of the second dielectric layer is formed on the first electrode layer before forming the first layer; after removing the first layer, a second portion of the second dielectric layer is formed on the first portion within the insulating film; the second electrode layer is formed on the second portion within the insulating film; The method for manufacturing a semiconductor device according to claim 18.

20. after forming the first electrode layer, further comprising forming an isolation region within the first electrode layer, the first dielectric layer, and the substrate; 20. The method for manufacturing a semiconductor device according to claim 18, wherein the second dielectric layer is formed after the element isolation region is formed.

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