Semiconductor module

Abstract

To reduce wiring inductance in a semiconductor module.SOLUTION: The semiconductor module includes a laminated substrate 310 in which a plurality of wiring layers 500 to 540 are laminated, and a plurality of semiconductor devices 200 mounted on a first surface of the laminated substrate. The plurality of wiring layers include the second level wiring layer 510 including the high-potential P wiring 350 to which a high potential is applied, the first level wiring layer 500 including the low-potential N wiring 352 to which a low potential is applied, and the fifth level wiring layer 540 including the U-connection wiring 580 that connects the plurality of semiconductor devices mounted on the first surface of the laminated substrate to each other via the U-phase potential conductor 570, and the P wiring 350 and the N wiring 352 at least partially overlap each other in the lamination direction.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] Patent Document 1 states, "Mirroring the first and second patterns for the patterns connecting the power conversion circuit and the control circuit places greater constraints on the arrangement of the patterns than mirroring both patterns within the power conversion circuit or the control circuit. Therefore, by using a surface-mounted component SMD with a mirrored pin arrangement on a substrate 30 having both patterns, as in this embodiment, the aforementioned effect of making it easier to mirror both patterns is significantly demonstrated" (paragraph 99). [Prior art document] [Patent documents] Patent Document 1: JP 2020-188656 A Summary of the Invention [Problem to be solved by the invention]

[0003] To reduce wiring inductance in a semiconductor module. [Means for solving the problem]

[0004] In a first aspect of the present invention, a semiconductor module is provided, comprising a laminated substrate having a plurality of wiring layers stacked thereon, and a plurality of semiconductor devices mounted on a first surface of the laminated substrate, wherein the plurality of wiring layers include a first wiring layer having high-potential wiring to which a high potential is applied, a second wiring layer having low-potential wiring to which a low potential is applied, and a third wiring layer having connection wiring that connects the plurality of semiconductor devices mounted on the first surface of the laminated substrate to each other, and the high-potential wiring and the low-potential wiring overlap each other at least partially in the stacking direction.

[0005] The semiconductor module may further include at least one temperature sensor disposed on the second surface side of the laminated substrate, the temperature sensor detecting the temperature of at least one of the plurality of semiconductor devices.

[0006] The semiconductor module may further include a plurality of temperature sensors arranged on the second surface side of the laminated substrate, the temperature sensors detecting the temperatures of the plurality of semiconductor devices, respectively.

[0007] In any of the semiconductor modules described above, the at least one temperature sensor may be arranged so as to overlap at least one of the plurality of semiconductor devices in the stacking direction.

[0008] In any of the semiconductor modules described above, the laminated substrate may include a conductor having one end connected to a main electrode plate of at least one of the plurality of semiconductor devices and extending to the third wiring layer.

[0009] In the semiconductor module, the conductor may be formed in a non-penetrating manner in the laminated substrate.

[0010] In any of the above semiconductor modules, the temperature sensor corresponding to at least one of the plurality of semiconductor devices may be mounted at a position overlapping a conductor connected to that semiconductor device in the stacking direction.

[0011] In any of the semiconductor modules described above, the laminated substrate may have a non-penetrating temperature detection conductor between the at least one temperature sensor and at least one of the plurality of semiconductor devices in the stacking direction.

[0012] In the semiconductor module, the temperature detection conductor may extend in the stacking direction from a wiring layer connected to at least one of the plurality of semiconductor devices, among the plurality of wiring layers, toward the second surface of the laminated substrate.

[0013] Any of the above semiconductor modules may further include at least one control device arranged on the second surface of the laminated substrate to control at least one semiconductor device, and the control device may control the at least one semiconductor device in accordance with a temperature of the at least one semiconductor device detected by a temperature sensor.

[0014] In the above semiconductor module, the control device may obtain the lifetime of at least one semiconductor device estimated from the temperature detected by the temperature sensor, and control the at least one semiconductor device in accordance with the lifetime of the at least one semiconductor device.

[0015] In any of the semiconductor modules described above, a plurality of control devices may be arranged on the second surface of the laminated substrate, and each control a plurality of semiconductor devices.

[0016] In any of the above semiconductor modules, each of the multiple semiconductor devices may have a first main electrode plate, a second main electrode plate, and a control electrode plate on one side, and may have a switching element where the first main electrode is connected to the first main electrode plate, the second main electrode is connected to the second main electrode plate, and the control electrode is connected to the control electrode plate, and the connection wiring of the third wiring layer may connect the first main electrode plate of a first semiconductor device among the multiple semiconductor devices and the second main electrode plate of a second semiconductor device among the multiple semiconductor devices to each other.

[0017] In the above-mentioned semiconductor module, the first semiconductor device may be mounted on the first surface of the laminated substrate so that the first main electrode plate is closer to the second semiconductor device than the second main electrode plate, and the second semiconductor device may be mounted on the first surface of the laminated substrate so that the second main electrode plate is closer to the first semiconductor device than the first main electrode plate.

[0018] In any of the above semiconductor modules, the high-potential wiring and the low-potential wiring may at least partially overlap with the connection wiring in the stacking direction.

[0019] In any of the semiconductor modules described above, the plurality of wiring layers may further include a fourth wiring layer having output wiring that connects the plurality of semiconductor devices to output terminals formed on the second surface of the laminated substrate.

[0020] In the semiconductor module, the high-potential wiring and the low-potential wiring may at least partially overlap with the output wiring in the stacking direction.

[0021] Any of the above semiconductor modules may include at least one snubber capacitor arranged on the second surface of the laminated substrate between a positive terminal connected to the high potential wiring and a negative terminal connected to the low potential wiring.

[0022] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a perspective view of a switching element 10 according to the present embodiment. [Figure 2] FIG. 1 is a perspective view of a semiconductor device 200 according to an embodiment of the present invention. [Figure 3] FIG. 2 is a perspective view of a semiconductor module 300 according to the present embodiment. [Figure 4] 2 is a schematic diagram showing the internal structure of a semiconductor module 300 according to the present embodiment. FIG. [Figure 5] 1 shows the connections of the wiring within the semiconductor module 300 according to this embodiment. [Figure 6] 1 shows a schematic cross-sectional view of a semiconductor module 300 according to this embodiment. [Figure 7] 1 shows a schematic top view of the second surface of the laminated substrate 310 of the semiconductor module 300. FIG. [Figure 8] 1 shows a schematic diagram of a first wiring layer 500 of a laminated substrate 310 of a semiconductor module 300. FIG. [Figure 9]1 shows a schematic diagram of a second wiring layer 510 of a laminated substrate 310 of a semiconductor module 300. FIG. [Figure 10] 1 shows a schematic diagram of a third wiring layer 520 of a laminated substrate 310 of a semiconductor module 300. FIG. [Figure 11] 1 shows a schematic diagram of a fourth wiring layer 530 of the laminated substrate 310 of the semiconductor module 300. FIG. [Figure 12] 1 shows a schematic diagram of a fifth wiring layer 540 of a laminated substrate 310 of a semiconductor module 300. FIG. [Figure 13] 10 shows another example of the connection of the wiring within the semiconductor module 300 according to this embodiment. [Figure 14] 1 shows an example of the configuration of a control device 320 of a semiconductor module 300. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] FIG. 1 is a perspective view of a switching element 10 according to this embodiment. The switching element 10 is a semiconductor switching element such as a MOSFET (metal-oxide semiconductor field-effect transistor). The switching element 10 may be a power MOSFET with a vertical structure. The switching element 10 may be a SiC semiconductor element such as a SiC-MOSFET that is capable of faster switching, or may be one that uses a wide-gap semiconductor such as GaN, diamond, a gallium nitride-based material, a gallium oxide-based material, AlN, AlGaN, or ZnO. Alternatively, the switching element 10 may be a semiconductor switch element such as an IGBT (insulated gate bipolar transistor), or may be a SiC-IGBT. The switching element 10 may also be a HEMT (high electron mobility transistor).

[0026] The switching element 10 may be a semiconductor chip, having a first main electrode 100 and a control electrode 110 on one surface (the upper surface in the figure) and a second main electrode 120 on the opposite surface. In the example shown in the figure, the switching element 10 further has a sense electrode 130 on the upper surface in the figure. If the switching element 10 is a MOSFET, the switching element 10 has a source and a drain as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sense source as the sense electrode 130. If the switching element 10 is an IGBT, the switching element 10 has an emitter and a collector as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sense emitter as the sense electrode 130. For convenience of explanation, this embodiment will be described assuming that the switching element 10 is a MOSFET.

[0027] 2 is a perspective view of a semiconductor device 200 according to this embodiment. A semiconductor module using a switching element such as the switching element 10 shown in FIG. 1 generally has a structure in which one surface of the switching element (e.g., the surface on the side of the second main electrode 120) is bonded to a wiring pattern on a substrate, and the electrodes on the other surface (e.g., the first main electrode 100, the control electrode 110, and the sense electrode 130) are electrically connected to other wiring patterns by wire bonding. Such a semiconductor module is realized as an integrated module by resin-sealing the substrate on which the switching element is mounted, the bonding wires, and the metal plates connected to the positive terminal, negative terminal, and output terminal.

[0028] In contrast, the semiconductor device 200 has a structure in which each electrode plate electrically connected to each electrode of the switching element 10 is exposed on one surface of the plate-shaped semiconductor device 200. In this embodiment, the semiconductor device 200 includes a mounting substrate 210, a first main electrode plate 220, a second main electrode plate 230, a control electrode plate 240, a sub-electrode plate 250, and a sealing portion 260.

[0029] The mounting substrate 210 mounts the switching element 10 on its mounting surface (the upper surface in the figure). The first main electrode plate 220 is provided on one surface (mounting surface) of the mounting substrate 210 and is electrically connected to the first main electrode 100 of the switching element 10. The second main electrode plate 230 is provided on one surface (mounting surface) of the mounting substrate 210 and is electrically connected to the second main electrode 120 of the switching element 10. The control electrode plate 240 is provided on one surface (mounting surface) of the mounting substrate 210 and is electrically connected to the control electrode 110 of the switching element 10. The sub-electrode plate 250 is electrically connected to the first main electrode 100 of the switching element 10. Here, the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 are exposed on the surface of the semiconductor device 200 opposite the mounting substrate 210 side (the switching element 10 mounting surface side of the mounting substrate 210). The sealing portion 260 covers the mounting surface of the mounting substrate 210 on which the switching element 10 is mounted, while leaving the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 exposed.

[0030] Instead of modularizing a switching element such as switching element 10 as described above, the semiconductor device 200 of this embodiment can be used to bond each electrode plate on one side of the semiconductor device 200 to a wiring pattern on a substrate, thereby electrically connecting all of the necessary electrodes in the switching element 10 to the wiring on the substrate without wire bonding.

[0031] The semiconductor device 200 may further have an electrode plate electrically connected to the sense electrode 130 on the same surface as the first main electrode plate 220, etc. The first main electrode plate 220 and the sub-electrode plate 250 are both electrically connected to the first main electrode 100 of the switching element 10, but the first main electrode plate 220 has a large area and is used to pass a large current, while the sub-electrode plate 250 is used to control the switching element 10 in a pair with the control electrode plate 240. In another embodiment, the semiconductor device 200 may not include the sub-electrode plate 250, in which case the first main electrode plate 220 is also used to control the switching element 10.

[0032] Fig. 3 is a perspective view of a semiconductor module 300 according to this embodiment. Fig. 4 is a schematic diagram showing the internal structure of the semiconductor module 300 according to this embodiment. The semiconductor module 300 according to this embodiment is an inverter device. The semiconductor module 300 includes a plurality of semiconductor devices 200, a laminated substrate 310, a temperature sensor 315, at least one control device 320, at least one snubber capacitor 325, and a heat sink 330.

[0033] The semiconductor devices 200 are respectively assigned to an upper arm and a lower arm of each of one or more phases. In the examples of FIGS. 3 and 4, the semiconductor module 300 is a three-phase inverter, and two semiconductor devices 200 are assigned to the upper arm and two semiconductor devices 200 are assigned to the lower arm of each phase. Therefore, the semiconductor module 300 includes 12 semiconductor devices 200 (=3 phases×(2 upper arms+2 lower arms)). Note that the semiconductor module 300 may include any number of semiconductor devices 200 depending on the application.

[0034] The laminated substrate 310 may be a printed wiring board, and a plurality of semiconductor devices 200 are mounted on a first surface of the laminated substrate 310. The first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 of each semiconductor device 200 are connected to the respective electrodes on the first surface of the laminated substrate 310. The laminated substrate 310 is formed by stacking a plurality of wiring layers. The laminated substrate 310 has P wiring 350, N wiring 352, U wiring 354, V wiring 356, and W wiring 358 in the plurality of wiring layers. Note that in FIG. 4, the P wiring 350, N wiring 352, U wiring 354, V wiring 356, and W wiring 358 are separately and schematically illustrated on the underside of the laminated substrate 310 to make the structure of the wiring layers easier to see.

[0035] The P wiring 350, the N wiring 352, the U wiring 354, the V wiring 356, and the W wiring 358 may be conductive patterns formed on different wiring layers within the laminated substrate 310. The laminated substrate 310 may be formed by laminating and bonding, using a resin or the like, multiple substrates on which conductive patterns corresponding to the P wiring 350, the N wiring 352, the U wiring 354, the V wiring 356, and the W wiring 358, respectively, are formed. In this embodiment, the P wiring 350 may be a high-potential wiring to which a high potential is applied, and the N wiring 352 may be a low-potential wiring to which a low potential is applied. The U wiring 354, the V wiring 356, and the W wiring 358 may each be output wiring that connects multiple semiconductor devices 200 to output terminals formed on the second surface of the laminated substrate 310.

[0036] The laminated substrate 310 has, on a second surface opposite the first surface, terminals connected to the first main electrode plates 220 of the multiple semiconductor devices 200 via wiring within the laminated substrate 310 and terminals connected to the second main electrode plate 230 via wiring within the laminated substrate 310. In this example embodiment, the laminated substrate 310 has a P terminal (positive terminal), an N terminal (negative terminal), a U terminal (U-phase output terminal), a V terminal (V-phase output terminal), and a W terminal (W-phase output terminal) on the second surface. The P terminal and N terminal may be arranged along one side of the second surface of the laminated substrate 310, and the U terminal, V terminal, and W terminal may be arranged along the other side of the second surface of the laminated substrate 310. Connection between each terminal provided on the second surface of the laminated substrate 310 and one or more semiconductor devices 200 via wiring such as the P wiring 350 will be described later with reference to FIG. 5.

[0037] At least one temperature sensor 315 may be disposed on the second surface side of the laminated substrate 310 and may detect the temperature of at least one of the plurality of semiconductor devices 200. The one or more temperature sensors 315 may be, for example, a thermistor or a thermocouple. The plurality of temperature sensors 315 may detect the temperatures of the plurality of semiconductor devices 200, respectively. One of the plurality of temperature sensors 315 may detect the temperature of the plurality of semiconductor devices 200.

[0038] At least one temperature sensor 315 may be arranged so as to overlap at least one of the multiple semiconductor devices 200 in the stacking direction. For example, each temperature sensor 315 may be arranged on the second surface of the laminated substrate 310 at a position where the distance from the semiconductor device 200 to be detected is minimum. The temperature sensor 315 corresponding to at least one of the multiple semiconductor devices 200 may be mounted at a position where the temperature sensor 315 overlaps a conductor connected to the semiconductor device 200 to be detected in the stacking direction. The multiple temperature sensors 315 may be fixed on the second surface of the laminated substrate 310 in the same arrangement as the semiconductor devices 200 are mounted on the first surface of the laminated substrate 310. In this embodiment, the multiple temperature sensors 315 may be fixed in two rows on the second surface of the laminated substrate 310 (two rows x six sensors = 12 sensors). Note that at least a portion of each temperature sensor 315 may be embedded in the second surface side of the laminated substrate 310.

[0039] At least one control device 320 is arranged on the second surface of the laminated substrate 310. A plurality of control devices 320 may be arranged on the second surface of the laminated substrate 310, and each control device 320 may control a plurality of semiconductor devices 200. Each of the plurality of control devices 320 is electrically connected to the control electrode plate 240 and the sub-electrode plate 250 of each of the plurality of semiconductor devices 200 via wiring within the laminated substrate 310. Each control device 320 controls the semiconductor device 200 by controlling the voltage of the control electrode plate 240 relative to the sub-electrode plate 250 of the semiconductor device 200. Each control device 320 may be connected to one semiconductor device 200 and control that single semiconductor device 200, or may be connected to two or more semiconductor devices 200 and control that two or more semiconductor devices 200. Note that one or more control devices 320 may control one or more semiconductor devices 200 in response to a control signal from an external control device. The at least one control device 320 may control the at least one semiconductor device 200 in accordance with the temperature of the at least one semiconductor device 200 detected by the temperature sensor 315. The control device 320 may obtain a lifetime of the at least one semiconductor device 200 estimated from the temperature detected by the temperature sensor 315, and control the at least one semiconductor device 200 in accordance with the lifetime of the at least one semiconductor device 200.

[0040] At least one snubber capacitor 325 is disposed on the second surface of the laminate substrate 310 between a positive terminal connected to the high-potential wiring and a negative terminal connected to the low-potential wiring. At least one snubber capacitor 325a and at least one snubber capacitor 325b may be connected in series and provided for each phase. In this embodiment, multiple snubber capacitors 325a and multiple snubber capacitors 325b are provided. The multiple snubber capacitors 325a and multiple snubber capacitors 325b are connected in series and in parallel to the P wiring 350 and the N wiring 352. This prevents transient high voltages from occurring during switching of the corresponding semiconductor device 200 and prevents a short circuit between the high potential and the low potential even if one of the capacitors fails due to a short circuit. The multiple snubber capacitors 325a and multiple snubber capacitors 325b may be mounted on the second surface of the laminate substrate 310 or may be provided on an inner layer of the laminate substrate 310.

[0041] The heat sink 330 is fixed so as to be in contact with the surfaces of the semiconductor devices 200 opposite to the stacked substrate 310. The heat sink 330 may be, for example, a heat spreader, a heat sink, or a heat exchanger for liquid cooling.

[0042] FIG. 5 shows the connections of the wiring within the semiconductor module 300 according to this embodiment. In this diagram, the semiconductor device 200 (UU1) and the semiconductor device 200 (UU2) are assigned to the U-phase upper arm, and the semiconductor device 200 (UD1) and the semiconductor device 200 (UD2) are assigned to the U-phase lower arm. The second main electrode 230 of each semiconductor device 200 in the U-phase upper arm is connected to the P-terminal via a P wiring 350. The first main electrode 220 of each semiconductor device 200 in the U-phase upper arm is connected to the U-terminal via a U wiring 354. The second main electrode 230 of each semiconductor device 200 in the U-phase lower arm is connected to the U-terminal and the first main electrode 220 of each semiconductor device 200 in the U-phase upper arm via a U wiring 354. The first main electrode 220 of each semiconductor device 200 in the U-phase lower arm is connected to the N-terminal via an N wiring 352. With this connection, each semiconductor device 200 in the U-phase upper arm and each semiconductor device 200 in the U-phase lower arm are connected in series in this order between the P terminal and the N terminal, and the node between the first main electrode plate 220 (e.g., source) of each semiconductor device 200 in the U-phase upper arm and the second main electrode plate 230 (e.g., drain) of each semiconductor device 200 in the U-phase lower arm is connected to the U terminal.

[0043] The semiconductor devices 200 (VU1) and 200 (VU2) are assigned to the V-phase upper arm, and the semiconductor devices 200 (VD1) and 200 (VD2) are assigned to the V-phase lower arm. Each semiconductor device 200 in the V-phase upper arm and the V-phase lower arm is connected in the same way as each semiconductor device 200 in the U-phase upper arm and the U-phase lower arm, except that it is connected to the V-terminal instead of the U-terminal.

[0044] Semiconductor devices 200 (WU1) and 200 (WU2) are assigned to the W-phase upper arm, and semiconductor devices 200 (WD1) and 200 (WD2) are assigned to the W-phase lower arm. Each semiconductor device 200 in the W-phase upper arm and the W-phase lower arm is connected in the same way as each semiconductor device 200 in the U-phase upper arm and the U-phase lower arm, except that it is connected to the W terminal instead of the U terminal.

[0045] As shown in the figure, the semiconductor devices 200 assigned to the upper arm of each phase out of the plurality of semiconductor devices 200 may be arranged in a row (the upper row in the figure) on the first surface of the laminated substrate 310. The semiconductor devices 200 assigned to the lower arm of each phase out of the plurality of semiconductor devices 200 may be arranged in a row (the lower row in the figure) alongside the row of the semiconductor devices 200 assigned to the upper arm of each phase on the first surface of the laminated substrate 310. With this arrangement, the second main electrode plates 230 of the semiconductor devices 200 in the upper arm and the first main electrode plates 220 of the semiconductor devices 200 in the lower arm are aligned in a row, so that the P wiring 350 and the N wiring 352 can be extended in the arrangement direction of the semiconductor devices 200 in the upper arm and the arrangement direction of the semiconductor devices 200 in the lower arm, respectively, and connected to each semiconductor device 200. Accordingly, the U wiring 354, V wiring 356, and W wiring 358 can also extend in the arrangement direction of the semiconductor devices 200 and be connected to the first main electrode plate 220 of each semiconductor device 200 in the corresponding upper arm and the second main electrode plate 230 of each semiconductor device 200 in the corresponding lower arm.

[0046] As shown in the figure, on the first surface of the laminated substrate 310, each semiconductor device 200 assigned to the upper arm of each phase may be arranged in an orientation such that the first main electrode plate 220 is located on the side of the semiconductor device 200 assigned to the opposing lower arm among the multiple semiconductor devices 200 (the first main electrode plate 220 is oriented toward the bottom in the figure). On the first surface of the laminated substrate 310, each semiconductor device 200 assigned to the lower arm of each phase may be arranged in an orientation such that the first main electrode plate 220 is located on the side of the semiconductor device 200 assigned to the opposing upper arm among the multiple semiconductor devices 200 (the first main electrode plate 220 is oriented toward the top in the figure). In such an arrangement, the control electrode plate 240 and the sub-electrode plate 250 of each semiconductor device 200 are located at the end of the semiconductor device 200 opposite the semiconductor device 200 of the opposing arm. This allows the semiconductor devices 200 of the upper and lower arms to face each other, and makes it possible to arrange control wiring outside the area where the P wiring 350, N wiring 352, U wiring 354, V wiring 356, and W wiring 358 through which large currents flow are arranged.

[0047] FIG. 6 is a schematic cross-sectional view of a semiconductor module 300 according to this embodiment. FIG. 6 shows a schematic cross-section of the semiconductor module 300 taken along the direction in which the semiconductor devices 200 of the upper and lower arms face each other and along the stacking direction of the laminated substrate 310. The laminated substrate 310 includes, from the second surface side to the first surface side in the stacking direction, a first-level wiring layer 500, a second-level wiring layer 510, a third-level wiring layer 520, a fourth-level wiring layer 530, a fifth-level wiring layer 540, and multiple conductors. Each of the multiple conductors in the laminated substrate 310 may be a via, a copper inlay, a copper pin, or the like, used to connect components in the stacking direction.

[0048] One exposed surface of the first-stage wiring layer 500 becomes the second surface of the laminated substrate 310, and the other surface is in direct contact with the second-stage wiring layer 510. The first-stage wiring layer 500 has N wiring 352. The N wiring 352 is connected to the first main electrode plate 220 and N terminal of each semiconductor device 200 in the lower arm via an N-potential conductor 550. As a result, the first main electrode plate 220 and N terminal of each semiconductor device 200 are electrically connected by the N-potential conductor 550 and the N wiring 352. A plurality of N-potential conductors 550 may be arranged, and may be conductors that penetrate the laminated substrate 310 (penetrating conductors) or conductors that do not penetrate the laminated substrate 310 (non-penetrating conductors). The first-stage wiring layer 500 is an example of the second wiring layer in this application.

[0049] One surface of the second-stage wiring layer 510 is in direct contact with the third-stage wiring layer 520. The second-stage wiring layer 510 has P wiring 350. The P wiring 350 is connected to the second main electrode plate 230 and P terminal of each semiconductor device 200 in the upper arm via a P potential conductor 560. As a result, the second main electrode plate 230 and N terminal of each semiconductor device 200 are electrically connected by the N potential conductor 550 and N wiring 352. A plurality of P potential conductors 560 may be arranged, and may be conductors that penetrate the laminated substrate 310 (penetrating conductors) or conductors that do not penetrate the laminated substrate 310 (non-penetrating conductors). The second-stage wiring layer 510 is an example of the first wiring layer in this application.

[0050] In the adjacent first-stage wiring layer 500 and second-stage wiring layer 510, the high-potential wiring (P wiring 350) and the low-potential wiring (N wiring 352) at least partially overlap each other in the stacking direction. The P wiring 350 may extend from the connected P-potential conductor 560 toward the N-potential conductor 550, and the N wiring 352 may extend from the N-potential conductor 550 toward the P-potential conductor 560. As a result, the P wiring 350 and the N wiring 352 overlap each other between the P-potential conductor 560 and the N-potential conductor 550 in the stacking direction. According to this embodiment, by arranging the high-potential wiring and the low-potential wiring to which a DC voltage is applied so that they overlap in the stacking direction of the wiring layers, magnetic fluxes due to the flowing currents cancel each other out, thereby reducing wiring inductance. Even if the current flowing in the semiconductor module 300 increases as the capacity of the power converter increases, surge voltages due to wiring inductance can be reduced.

[0051] One surface of the third-stage wiring layer 520 is in direct contact with the fourth-stage wiring layer 530. The third-stage wiring layer 520 has a U wiring 354. The U wiring 354 is connected to the first main electrode plate 220 of each semiconductor device 200 in the U-phase upper arm, the second main electrode plate 230 of each semiconductor device 200 in the U-phase lower arm, and the U-terminal via a U-phase potential conductor 570. As a result, the first main electrode plate 220 of each semiconductor device 200 in the U-phase upper arm, the second main electrode plate 230 of each semiconductor device 200 in the U-phase lower arm, and the U-terminal are electrically connected by the U-phase potential conductor 570 and the U wiring 354. A plurality of U-phase potential conductors 570 may be arranged, and may be formed in a non-penetrating manner within the laminated substrate 310.

[0052] One surface of the fourth-stage wiring layer 530 is in direct contact with the fifth-stage wiring layer 540. The fourth-stage wiring layer 530 may have a W wiring 358 (not shown), which will be described in detail with reference to FIG.

[0053] One surface of the fifth-stage wiring layer 540 is exposed and serves as the first surface of the laminated substrate 310. The fifth-stage wiring layer 540 has a U-connection wiring 580. The U-connection wiring 580 connects the multiple semiconductor devices 200 mounted on the first surface of the laminated substrate 310 to one another via a U-phase potential conductor 570. One end of the U-phase potential conductor 570 is connected to a main electrode plate of at least one of the multiple semiconductor devices 200, and may extend to the fifth-stage wiring layer 540. The U-connection wiring 580 may connect a first main electrode plate 220 of a first semiconductor device 200 of the multiple semiconductor devices 200 to a second main electrode plate 230 of a second semiconductor device 200 of the multiple semiconductor devices 200 to one another via the U-phase potential conductor 570. In this embodiment, the U-connection wiring 580 connects the semiconductor devices 200 of the U-phase upper arm and the semiconductor devices 200 of the U-phase lower arm in series to one another. The U-connection wiring 580 connects the first main electrode plate 220 of each semiconductor device 200 in the U-phase upper arm and the second main electrode plate 230 of each semiconductor device 200 in the U-phase lower arm to each other via a U-phase potential conductor 570. The fifth wiring layer 540 is an example of the third wiring layer defined in the present application.

[0054] The high-potential wiring (P wiring 350) and the low-potential wiring (N wiring 352) may at least partially overlap with the output wiring in the stacking direction. The P wiring 350 and the N wiring 352 may overlap with at least one of the U wiring 354, the V wiring 356, and the W wiring 358 in the stacking direction. According to this embodiment, by arranging the high-potential wiring and the low-potential wiring to which a DC voltage is applied so as to overlap with the output wiring in the stacking direction, magnetic fluxes cancel each other out, thereby further reducing wiring inductance.

[0055] The laminated substrate 310 may have a non-penetrating temperature detection conductor 585. The temperature detection conductor 585 may be a via, a copper inlay, a copper pin, or the like extending in the stacking direction of the laminated substrate 310. The temperature detection conductor 585 may be formed between the at least one temperature sensor 315 and at least one of the multiple semiconductor devices 200 in the stacking direction. The temperature detection conductor 585 may include a conductor such as a metal inside. The temperature detection conductor 585 may be formed in the laminated substrate 310 between the temperature sensor 315 and the semiconductor device 200 to be detected by the temperature sensor 315 in the stacking direction. The temperature detection conductor 585 may extend from a wiring layer, among the multiple wiring layers, connected to at least one of the multiple semiconductor devices 200 toward the second surface of the laminated substrate 310 in the stacking direction. The temperature detection conductor 585 may be formed to extend from the wiring layer to directly below the semiconductor device 200 to be detected. One or more temperature detection conductors 585 may be formed for each semiconductor device 200 to be detected. In this embodiment, the temperature detection conductor 585 may be formed without penetrating, extending from the U wiring 354 of the third-layer wiring layer 520 into the first-layer wiring layer 500. Since the temperature detection conductor 585 does not penetrate, it is not exposed to the outside of the laminated substrate 310. The temperature detection conductor 585 may be formed so as not to be connected to any wiring (such as the P wiring 350 and N wiring 352) in the laminated substrate 310 other than the wiring to which it is connected (the U wiring 354). Note that the temperature detection conductor 585 does not have to be connected to any wiring in the laminated substrate 310. The temperature detection conductor 585 may be filled with a metal or the like. The temperature detection conductor 585 can efficiently transmit the temperature of the semiconductor device 200 on the first surface side to the temperature sensor 315 on the second surface side.

[0056] The control device 320 is electrically connected to the control electrode plate 240 and the sub-electrode plate 250 of the semiconductor device 200 via a control conductor 590 in the laminated substrate 310. Next, each wiring layer of the laminated substrate 310 according to this embodiment will be described.

[0057] FIG. 7 is a schematic top view of the second surface of the laminated substrate 310 of the semiconductor module 300 shown in FIG. 6 . The control device 320, the temperature sensor 315, and the like of the semiconductor module 300 are omitted in FIG. 7 . Note that FIGS. 7 to 12 show a configuration for arranging 12 semiconductor devices 200 in the upper arm (four semiconductor devices 200 for each phase of the upper arm) and 12 semiconductor devices 200 in the lower arm (four semiconductor devices 200 for each phase of the lower arm). However, this is not limiting. For example, the laminated substrate 310 can be similarly configured to arrange six semiconductor devices 200 in the upper arm and six semiconductor devices 200 in the lower arm, as in the semiconductor module 300 shown in FIGS. 3 to 5 . The laminated substrate 310 of this embodiment can mount multiple semiconductor devices 200 in the order of U phase, W phase, and V phase from the P terminal or N terminal side to the output terminal side.

[0058] On the second surface, the laminated substrate 310 has a P-potential conductor 560a connected to the P-terminal, a P-potential conductor 560b connected to the semiconductor device 200, an N-potential conductor 550a connected to the N-terminal, an N-potential conductor 550b connected to the semiconductor device 200, a U-phase potential conductor 570a connected to the U-terminal, a V-phase potential conductor 610a connected to the V-terminal, and a W-phase potential conductor 620a connected to the W-terminal. On the second surface, the laminated substrate 310 has the P-terminal formed on the P-potential conductor 560a, the N-terminal formed on the N-potential conductor 550a, the U-terminal formed on the U-phase potential conductor 570a, the V-terminal formed on the V-phase potential conductor 610a, and the W-terminal formed on the W-phase potential conductor 620a. Note that in this figure, and the same applies to the following figures, each conductor is represented by a circle.

[0059] One or more P-potential conductors 560b may be formed at positions corresponding to each semiconductor device 200 in the upper arm. The multiple P-potential conductors 560b are arranged side by side on the second surface from the P-terminal toward the U-terminal, V-terminal, and W-terminal. One or more N-potential conductors 550b may be formed at positions corresponding to each semiconductor device 200 in the lower arm. The multiple N-potential conductors 550b are arranged side by side on the second surface from the N-terminal toward the U-terminal, V-terminal, and W-terminal. The row of the N-potential conductors 550b may be parallel to the row of the P-potential conductors 560b.

[0060] The laminated substrate 310 has first surface wiring 625 and second surface wiring 630 on its second surface. The first surface wiring 625 electrically connects the plurality of P-potential conductors 560 to one another and may further connect the plurality of P-potential conductors 560 to the snubber capacitor 325a. The first surface wiring 625 is formed extending from the P-terminal (P-potential conductor 560a) to the plurality of P-potential conductors 560b and the snubber capacitor 325a. The second surface wiring 630 electrically connects the plurality of N-potential conductors 550 to one another and may further connect the plurality of N-potential conductors 550 to the snubber capacitor 325b. The second surface wiring 630 is formed extending from the N-terminal (N-potential conductor 550a) to the plurality of N-potential conductors 550b and the snubber capacitor 325b.

[0061] Fig. 8 is a schematic diagram of the first-level wiring layer 500 of the laminated substrate 310 of the semiconductor module 300 shown in Fig. 6. Fig. 8 shows a plane of the first-level wiring layer 500 that is perpendicular to the stacking direction of the wiring layers inside the laminated substrate 310. Fig. 8 omits the configuration related to the control device 320 and the temperature sensor 315 of the semiconductor module 300. The first-level wiring layer 500 has N wiring 352.

[0062] The N wiring 352 in the first-stage wiring layer 500 electrically connects the multiple N-potential conductors 550 to one another and connects the N-terminal to each semiconductor device 200 in the lower arm. The N wiring 352 is connected to the N-terminal via the N-potential conductor 550a and to each semiconductor device 200 in the lower arm via the N-potential conductor 550b. The N wiring 352 is formed to extend from the N-potential conductor 550a to the multiple N-potential conductors 550b. The N wiring 352 is further formed to extend from the row of the N-potential conductors 550b in the direction of the row of the P-potential conductors 560b, and is formed in a region between the row of the multiple N-potential conductors 550b and the row of the multiple P-potential conductors 560b so as not to come into contact with the P-potential conductor 560. The N wiring 352 may be formed to extend from the N-potential conductor 550b to a position beyond the midpoint between the row of the N-potential conductors 550b and the row of the P-potential conductors 560b. In addition, in the first wiring layer 500, all of the P potential conductors 560 may be connected to each other by wiring that is separated from the N wiring 352.

[0063] Fig. 9 is a schematic diagram of the second-level wiring layer 510 of the laminated substrate 310 of the semiconductor module 300 shown in Fig. 6. Fig. 9 shows a surface of the second-level wiring layer 510 that is perpendicular to the stacking direction inside the laminated substrate 310. Fig. 9 omits the configuration related to the control device 320 and the temperature sensor 315 of the semiconductor module 300. The second-level wiring layer 510 has a P wiring 350.

[0064] The P wiring 350 in the second-stage wiring layer 510 electrically connects the multiple P-potential conductors 560 to one another and connects the P terminal to each semiconductor device 200 in the upper arm. The P wiring 350 is connected to the P terminal via the P-potential conductor 560a and to each semiconductor device 200 in the upper arm via the P-potential conductor 560b. The P wiring 350 is formed to extend from the P-potential conductor 560a to the multiple P-potential conductors 560b. The P wiring 350 is further formed to extend from the row of the P-potential conductors 560b in the direction of the row of the N-potential conductors 550b, and is formed in a region between the row of the multiple N-potential conductors 550b and the row of the multiple P-potential conductors 560b so as not to come into contact with the N-potential conductor 550. The P wiring 350 may be formed to extend from the P-potential conductor 560b to a position beyond the midpoint between the row of the P-potential conductors 560b and the row of the N-potential conductors 550b. The P wiring 350 is formed up to a position close to the N-potential conductors 550b, so that it overlaps with the N wiring 352 in the stacking direction in a region between the row of the N-potential conductors 550b and the row of the P-potential conductors 560b. The N-potential conductors 550b may be connected to the P wiring 350 by a wiring spaced apart from the P wiring 350.

[0065] Fig. 10 is a schematic diagram of the third-level wiring layer 520 of the laminated substrate 310 of the semiconductor module 300 shown in Fig. 6. Fig. 10 shows a surface of the third-level wiring layer 520 that is perpendicular to the stacking direction inside the laminated substrate 310. Fig. 10 omits the configuration related to the control device 320 and the temperature sensor 315 of the semiconductor module 300. The third-level wiring layer 520 has U wiring 354 and is an example of the fourth wiring layer of the present application.

[0066] The U wiring 354 in the third-stage wiring layer 520 electrically connects the multiple U-phase potential conductors 570 to one another and connects the U-terminal to each U-phase semiconductor device 200. The U wiring 354 is connected to the U-terminal via a U-phase potential conductor 570a, to the semiconductor devices 200 in the U-phase upper arm via a U-phase potential conductor 570b, and to the semiconductor devices 200 in the U-phase lower arm via a U-phase potential conductor 570c. In the third-stage wiring layer 520, the U wiring 354 is separated (insulated) from the P-potential conductors 560 and the N-potential conductors 550, etc. The U wiring 354 overlaps with the N wiring 352 and the P wiring 350 in the stacking direction in a region between the row of the N-potential conductors 550b and the row of the P-potential conductors 560b.

[0067] Fig. 11 is a schematic diagram of the fourth-level wiring layer 530 of the laminated substrate 310 of the semiconductor module 300 shown in Fig. 6. Fig. 11 shows a surface of the fourth-level wiring layer 530 that is perpendicular to the stacking direction inside the laminated substrate 310. Fig. 11 omits the configuration related to the control device 320 and the temperature sensor 315 of the semiconductor module 300. The fourth-level wiring layer 530 has W wiring 358 and is an example of the fourth wiring layer of the present application.

[0068] The W wiring 358 in the fourth wiring layer 530 electrically connects the multiple W-phase potential conductors 620 to one another and connects the W terminal to each W-phase semiconductor device 200. The W wiring 358 is connected to the W terminal via a W-phase potential conductor 620a, to the semiconductor devices 200 in the W-phase upper arm via a W-phase potential conductor 620b, and to the semiconductor devices 200 in the W-phase lower arm via a W-phase potential conductor 620c. The W wiring 358 overlaps with the N wiring 352 and the P wiring 350 in the stacking direction in a region between the row of N-potential conductors 550b and the row of P-potential conductors 560b.

[0069] 12 is a schematic diagram of the fifth-level wiring layer 540 of the laminated substrate 310 of the semiconductor module 300 shown in FIG. 12 shows a surface of the fifth-level wiring layer 540 perpendicular to the stacking direction inside the laminated substrate 310. FIG. 12 omits the configuration related to the control device 320 and the temperature sensor 315 of the semiconductor module 300. The fifth-level wiring layer 540 has a V wiring 356, a U-connecting wiring 580, and a W-connecting wiring 660. The fifth-level wiring layer 540 has output wiring and connection wiring, and is an example of the third wiring layer or fourth wiring layer of the present application.

[0070] The V wiring 356 in the fifth wiring layer 540 electrically connects the multiple V-phase potential conductors 610 to one another and connects the V terminal to each V-phase semiconductor device 200. The V wiring 356 is connected to the V terminal via a V-phase potential conductor 610a, to the semiconductor devices 200 in the V-phase upper arm via a V-phase potential conductor 610b, and to the semiconductor devices 200 in the V-phase lower arm via a V-phase potential conductor 610c. The V wiring 356 overlaps with the N wiring 352 and the P wiring 350 in the stacking direction in a region between the row of N-potential conductors 550b and the row of P-potential conductors 560b.

[0071] The U-connection wiring 580 in the fifth wiring layer 540 electrically connects the plurality of U-phase potential conductors 570b and 570c to each other and connects the semiconductor devices 200 in the U-phase upper arm and the semiconductor devices 200 in the U-phase lower arm in series. The U-connection wiring 580 may be connected to the first main electrode plate 220 of each semiconductor device 200 in the U-phase upper arm via the U-phase potential conductor 570b and to the second main electrode plate 230 of each semiconductor device 200 in the U-phase lower arm via the U-phase potential conductor 570c. The U-connection wiring 580 may at least partially overlap with the P wiring 350 and the N wiring 352 in the stacking direction. The U-connection wiring 580 may overlap with the N wiring 352 and the P wiring 350 in the stacking direction in a region between the row of the N-potential conductors 550b and the row of the P-potential conductors 560b.

[0072] The W-connection wiring 660 in the fourth wiring layer 530 electrically connects the plurality of W-phase potential conductors 620b and 620c to each other and connects the semiconductor devices 200 in the W-phase upper arm and the semiconductor devices 200 in the W-phase lower arm in series. The W-connection wiring 660 may be connected to the first main electrode plate 220 of each semiconductor device 200 in the W-phase upper arm via the W-phase potential conductor 620b and to the second main electrode plate 230 of each semiconductor device 200 in the W-phase lower arm via the W-phase potential conductor 620c. The W-connection wiring 660 is disposed between the U-connection wiring 580 and the V wiring 356. The W-connection wiring 660 may at least partially overlap with the P wiring 350 and the N wiring 352 in the stacking direction. The W-connection wiring 660 may overlap with the N wiring 352 and the P wiring 350 in the stacking direction in a region between the row of the N-potential conductors 550b and the row of the P-potential conductors 560b.

[0073] According to this embodiment, by overlapping the N wiring 352 and the P wiring 350 with each other in the stacking direction and further overlapping with the output wiring, magnetic fluxes due to currents flowing through the wiring are canceled out, thereby reducing wiring inductance. Furthermore, by providing one high-voltage potential wiring in each wiring layer of the laminated substrate 310, insulation performance can be ensured. Furthermore, by using, for example, semi-buried vias (IVH: Inner Via Hole or BVH: Buried Via Hole) for connection to the output terminal, packaging density can be improved, and the temperature sensor 315 can be placed directly above the semiconductor device 200.

[0074] In the laminated substrate 310 of this embodiment, the N wiring 352 and the P wiring 350 do not have to be formed in adjacent wiring layers; for example, a wiring layer having at least one of the U wiring 354, the V wiring 356, and the W wiring 358 may be arranged between the wiring layer in which the N wiring 352 is arranged and the wiring layer in which the P wiring 350 is arranged.

[0075] FIG. 13 shows another example of the connection of each wiring within the semiconductor module 300 according to this embodiment. The wiring shown in FIG. 13 may be similar to the wiring shown in FIG. 5, except for the arrangement of the electrode plates of the semiconductor devices 200. In this figure, the semiconductor devices 200 of the upper arm may be mounted on the first surface of the laminated substrate 310 such that the first main electrode plate 220 is closer to the semiconductor devices 200 of the lower arm than the second main electrode plate 230, and the semiconductor devices 200 of the lower arm may be mounted on the first surface of the laminated substrate 310 such that the second main electrode plate 230 is closer to the semiconductor devices 200 of the upper arm than the first main electrode plate 220. In this figure, the second main electrode plate 230 of each semiconductor device 200 of the upper arm is connected to the P terminal via a P wiring 350. The first main electrode plate 220 of the semiconductor device 200 of the upper arm is connected to the U terminal, the V terminal, and the W terminal via a U wiring 354, a V wiring 356, and a W wiring 358, respectively. The second main electrode plate 230 of each semiconductor device 200 in the upper arm is disposed between the control electrode plate 240 and the first main electrode plate 220. The first main electrode plate 220 of each semiconductor device 200 in the lower arm is connected to the N terminal via an N wiring 352. The second main electrode plate 230 of the semiconductor device 200 in the lower arm is connected to the U terminal, V terminal, and W terminal via a U wiring 354, a V wiring 356, and a W wiring 358, respectively. The first main electrode plate 220 of each semiconductor device 200 in the lower arm is disposed between the control electrode plate 240 and the second main electrode plate 230.

[0076] By using such wiring, the connection wiring that connects the semiconductor devices 200 on the upper arm and the semiconductor devices 200 on the lower arm in series can be easily formed with a smaller width.

[0077] In the above embodiment, an example was shown in which the semiconductor module 300 is a three-phase inverter having three output terminals, but this is not limited to this, and the semiconductor module 300 of this embodiment may have only one output terminal for the P terminal and the N terminal.

[0078] 14 shows an example configuration of a control device 320 of a semiconductor module 300. Fig. 14 shows the control device 320 together with a semiconductor device 200 to be controlled and a temperature sensor 315 that detects the temperature of the semiconductor device 200 to be controlled. The control device 320 in this figure may be an example of one of the multiple control devices 320 of the semiconductor module 300 shown in Fig. 3 or 6.

[0079] The control device 320 has an acquisition unit 800, a prediction unit 810, and a control unit 820. The acquisition unit 800 is connected to the temperature sensor 315 and the prediction unit 810. The acquisition unit 800 acquires the detected temperature of the semiconductor device 200 detected by the temperature sensor 315. The acquisition unit 800 may receive information such as a current value indicating the detected temperature from the temperature sensor 315, and calculate the detected temperature from the received information.

[0080] The prediction unit 810 is connected to the control unit 820. The prediction unit 810 may predict the lifetime of the corresponding semiconductor device 200 based on the detected temperature acquired by the acquisition unit 800. The prediction unit 810 may predict the lifetime (for example, the remaining usage period of the semiconductor device 200, or whether the lifetime is short, etc.) according to changes in the detected temperature. The prediction unit 810 may predict the lifetime using a rainflow method. The prediction unit 810 may calculate the amount of change in the detected temperature for each predetermined period (for example, for each acquisition cycle of the detected temperature by the acquisition unit 800), and if the sum of the absolute values ​​of the change amounts exceeds a predetermined threshold, predict that the lifetime will be shorter than a predetermined lifetime threshold. The prediction unit 810 may use the sum of the absolute values ​​of the change amounts in the detected temperature to predict the lifetime, such as the remaining usage period, of the semiconductor device 200 using a pre-stored function indicating the relationship between the sum of the absolute values ​​of the change amounts in the detected temperature and the lifetime. The predetermined threshold value or function used by the prediction unit 810 may be obtained in advance through an experiment or simulation using a semiconductor device having the same structure as the semiconductor device 200 .

[0081] The control unit 820 is connected to the semiconductor device 200 to be controlled. The control unit 820 controls the semiconductor device 200. In controlling the semiconductor device 200, the control unit 820 may change the gate output voltage or gate resistance for the semiconductor device 200 in accordance with the lifetime predicted by the prediction unit 810.

[0082] According to this embodiment, by controlling each semiconductor device 200 according to the lifespan predicted from the detected temperature, the lifespans of the multiple semiconductor devices 200 in the semiconductor module 300 can be made uniform, and heat concentration can be suppressed.

[0083] An external control device may execute at least some of the operations of the acquisition unit 800, the prediction unit 810, and the control unit 820. In this case, the external control device may acquire the temperature detected by the temperature sensor 315, predict the lifespan of the semiconductor device 200 based on the detected temperature, and transmit a control signal based on the lifespan to the control device 320. The control device 320 may control the semiconductor device 200 based on the control signal from the external control device.

[0084] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0085] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0086] 10 switching element, 100 first main electrode, 110 control electrode, 120 second main electrode, 130 sense electrode, 200 semiconductor device, 210 mounting substrate, 220 first main electrode plate, 230 second main electrode plate, 240 control electrode plate, 250 sub-electrode plate, 260 sealing portion, 300 semiconductor module, 310 laminated substrate, 315 temperature sensor, 320 control device, 330 heat sink, 325 snubber capacitor, 350 P wiring, 352 N wiring, 354 U wiring, 356 V wiring, 358 W wiring, 500 first wiring layer, 510 second wiring layer, 520 third wiring layer, 530 fourth wiring layer, 540 fifth wiring layer, 550 N potential conductor, 560 P potential conductor, 570 U phase potential conductor, 590 Control conductor, 610 V-phase potential conductor, 620 W-phase potential conductor, 625 first surface wiring, 630 second surface wiring, 660 W connection wiring, 800 acquisition unit, 810 prediction unit, 820 control unit

Claims

1. a laminated substrate on which a plurality of wiring layers are laminated; a plurality of semiconductor devices mounted on a first surface of the laminated substrate; The plurality of wiring layers include: a first wiring layer having high-potential wiring to which a high potential is applied; a second wiring layer having low potential wiring to which a low potential is applied; a third wiring layer having connection wiring that connects the plurality of semiconductor devices mounted on the first surface of the laminated substrate to each other; The high-potential wiring and the low-potential wiring at least partially overlap each other in the stacking direction. Semiconductor module.

2. at least one temperature sensor disposed on the second surface side of the laminated substrate for detecting a temperature of at least one of the plurality of semiconductor devices; The semiconductor module according to claim 1 .

3. a plurality of temperature sensors disposed on the second surface side of the laminated substrate, the temperature sensors detecting the temperatures of the plurality of semiconductor devices, respectively; The semiconductor module according to claim 2 .

4. The at least one temperature sensor is disposed so as to overlap at least one of the plurality of semiconductor devices in the stacking direction. The semiconductor module according to claim 2 .

5. The laminated substrate includes a conductor having one end connected to a main electrode plate of at least one of the plurality of semiconductor devices and extending to the third wiring layer. The semiconductor module according to claim 2 .

6. The conductor is formed in the laminate substrate without penetrating the laminate substrate. The semiconductor module according to claim 5 .

7. The temperature sensor corresponding to at least one semiconductor device of the plurality of semiconductor devices is mounted at a position overlapping the conductor connected to the semiconductor device in the stacking direction. The semiconductor module according to claim 5 .

8. The laminated substrate has a non-penetrating temperature detection conductor between the at least one temperature sensor and at least one of the plurality of semiconductor devices in the stacking direction. The semiconductor module according to claim 2 .

9. The temperature detection conductor extends in the stacking direction from a wiring layer connected to at least one of the plurality of semiconductor devices among the plurality of wiring layers toward a second surface of the laminated substrate. The semiconductor module according to claim 8 .

10. at least one control device disposed on a second surface of the laminate substrate to control the at least one semiconductor device; The control device controls the at least one semiconductor device in response to a temperature related to the at least one semiconductor device detected by the temperature sensor. The semiconductor module according to claim 2 .

11. The control device obtains a lifetime of the at least one semiconductor device estimated from the temperature detected by the temperature sensor, and controls the at least one semiconductor device in accordance with the lifetime of the at least one semiconductor device. The semiconductor module according to claim 10.

12. The control device is arranged on the second surface of the laminated substrate and controls each of the semiconductor devices. The semiconductor module according to claim 10.

13. Each of the plurality of semiconductor devices has a first main electrode plate, a second main electrode plate, and a control electrode plate provided on one surface thereof, and has a switching element having a first main electrode connected to the first main electrode plate, a second main electrode connected to the second main electrode plate, and a control electrode connected to the control electrode plate; The connection wiring of the third wiring layer connects a first main electrode plate of a first semiconductor device of the plurality of semiconductor devices to a second main electrode plate of a second semiconductor device of the plurality of semiconductor devices. The semiconductor module according to claim 1 .

14. The first semiconductor device is mounted on the first surface of the laminated substrate such that the first main electrode plate is closer to the second semiconductor device than the second main electrode plate, and the second semiconductor device is mounted on the first surface of the laminated substrate such that the second main electrode plate is closer to the first semiconductor device than the first main electrode plate. The semiconductor module according to claim 13 .

15. The high-potential wiring and the low-potential wiring at least partially overlap with the connection wiring in the stacking direction. The semiconductor module according to claim 1 .

16. The plurality of wiring layers further includes a fourth wiring layer having output wiring that connects the plurality of semiconductor devices to output terminals formed on the second surface of the laminated substrate. The semiconductor module according to claim 1 .

17. The high-potential wiring and the low-potential wiring at least partially overlap with the output wiring in the stacking direction. The semiconductor module according to claim 16.

18. At least one snubber capacitor is disposed on the second surface of the laminated substrate between a positive terminal connected to the high potential wiring and a negative terminal connected to the low potential wiring. The semiconductor module according to claim 1 .

Images