Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor element having an impurity implantation region with a high current blocking effect.SOLUTION: The semiconductor element includes a semiconductor layer (substrate 10) which is an n-type or non-doped gallium oxide-based semiconductor, and an impurity implantation region 11 which is provided in a partial region of the semiconductor layer and contains impurities. The impurities are any one or more of Ni, Co, Ti, V, Cr, Mn, and Cu. The distribution of the impurity implantation region in the thickness direction includes, in order from the surface side of the semiconductor layer, a first monotonically decreasing region in which the concentration of the impurity monotonically decreases, a plateau region in which the concentration of the impurity is constant, and a second monotonically decreasing region in which the concentration of the impurity monotonically decreases.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Gallium oxide (Gallium Oxide) has attracted attention as a semiconductor material for next-generation power devices due to its wide band gap and high breakdown field strength. Gallium oxide functions as an n-type semiconductor with electron conductivity when undoped or doped with tetravalent cations such as Si, Sn, or Ge. However, in order to fabricate power devices with high voltage and current resistance, it is generally necessary to form a p-type conductive layer with hole transport properties.

[0003] In gallium oxide, the formation of shallow acceptor levels that realize p-type conductivity has not been achieved. However, it is known that deep acceptor levels, more than 1 eV below the energy position of the top of the valence band, can be formed by ion implantation of Mg or N. When n-type gallium oxide is doped with impurities that form deep acceptor levels to a concentration higher than the donor concentration, the free electrons of the n-type gallium oxide are trapped in the deep acceptor levels, causing it to lose electronic conductivity and exhibit insulating properties (counterdoping).

[0004] Furthermore, because electrons are localized in the deep acceptor level, the Fermi level of gallium oxide is lower than the center of the band gap, so although it does not exhibit p-type conduction, it effectively functions as a p-type layer. For example, by partially doping n-type gallium oxide with acceptors, a pn junction with an energy barrier of 3 eV or more is formed in the boundary region.

[0005] Non-Patent Document 1 describes implanting Ni ions into gallium oxide, and describes that crystal defects caused by ion implantation can be reduced by heating during the ion implantation.

[0006] Non-Patent Document 2 describes a Schottky barrier diode (SBD) having a guard ring structure or a field plate structure, and states that these structures can be realized by forming an impurity-implanted region by ion-implanting N into gallium oxide. Also, Non-Patent Document 3 describes that a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) can be realized by forming an impurity-implanted region by ion-implanting N into gallium oxide.

[0007] Patent Document 1 describes the formation of an impurity-implanted region by ion-implanting Mg or Al into gallium oxide, and describes how this makes it possible to realize an SBD or vertical MOSFET with a guard ring structure or a field plate structure. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] International Publication No. 2024 / 005152 [Non-patent literature]

[0009] [Non-Patent Document 1] J. Vac. Sci. Technol. A 41, 023101 (2023) [Non-patent document 2] IEEE ELECTRON DEVICE LETTERS, VOL. 40, NO. 9, SEPTEMBER 2019 [Non-patent document 3] IEEE ELECTRON DEVICE LETTERS, VOL. 41, NO. 2, FEBRUARY 2020 Summary of the Invention [Problem to be solved by the invention]

[0010] However, the methods of Patent Document 1 and Non-Patent Documents 1 to 3 could not sufficiently improve the current blocking effect of the impurity-implanted region.

[0011] The present invention has been made in view of the above-mentioned problems, and aims to provide a semiconductor element having an impurity-implanted region with a high current blocking effect, and a method for manufacturing the same. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor layer that is an n-type or non-doped gallium oxide-based semiconductor; an impurity-implanted region containing impurities, the impurity-implanted region being provided in a partial region of the semiconductor layer; The impurities are at least one of Ni, Co, Ti, V, Cr, Mn, and Cu; The semiconductor element has a thickness-wise distribution of the impurity-implanted region that includes, in order from the surface side of the semiconductor layer, a first monotonically decreasing region in which the concentration of the impurity monotonically decreases, a plateau region in which the concentration of the impurity is constant, and a second monotonically decreasing region in which the concentration of the impurity monotonically decreases.

[0013] Another aspect of the present invention is an ion implantation step of ion-implanting impurities into the vicinity of the surface of a semiconductor layer that is an n-type or non-doped gallium oxide-based semiconductor to form an impurity-implanted region; a heat treatment step of performing heat treatment in an inert gas atmosphere after the ion implantation step, The impurities are at least one of Ni, Co, Ti, V, Cr, Mn, and Cu. [Effects of the Invention]

[0014] In the above embodiment, the impurity-implanted region contains one or more of Ni, Co, Ti, V, Cr, Mn, and Cu, and these impurities function as counter dopants, thereby enhancing the current blocking effect of the impurity-implanted region.

[0015] As described above, according to the above aspect, it is possible to provide a semiconductor element having an impurity-implanted region with a high current blocking effect, and a method for manufacturing the same. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor element according to Embodiment 1, taken along a plane perpendicular to the main surface of a substrate. [Figure 2] Graph showing simulation results for the depth dependence of N concentration. [Figure 3] 10 is a graph showing the simulation results of the depth dependence of Ni concentration. [Figure 4] 10 is a graph showing current-voltage characteristics of a semiconductor element of a comparative example. [Figure 5] 1 is a graph showing current-voltage characteristics of a semiconductor element according to an example. [Figure 6] Graph showing the depth dependence of Ni concentration. [Figure 7] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a second embodiment, taken along a plane perpendicular to the main surface of the substrate. [Figure 8] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a third embodiment, taken along a plane perpendicular to the main surface of the substrate. [Figure 9] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor element according to a fourth embodiment, taken along a plane perpendicular to the main surface of the substrate. DETAILED DESCRIPTION OF THE INVENTION

[0017] The semiconductor element includes a semiconductor layer made of an n-type or undoped gallium oxide-based semiconductor, and an impurity-implanted region provided in a portion of the semiconductor layer and containing impurities. The impurities are one or more of Ni, Co, Ti, V, Cr, Mn, and Cu. The thickness distribution of the impurity-implanted region includes, from the surface side of the semiconductor layer, a first monotonically decreasing region in which the impurity concentration monotonically decreases, a plateau region in which the impurity concentration is constant, and a second monotonically decreasing region in which the impurity concentration monotonically decreases.

[0018] In the semiconductor element, the impurity may include Ni.

[0019] In the semiconductor element, the impurity concentration of the impurity implanted region may have a peak in the thickness direction. The impurity concentration at the peak may be 1×10 18 ~1×10 20 / cm 3 The impurity concentration at the peak may be 2 to 100 times the donor concentration of the semiconductor layer.

[0020] In semiconductor devices, the average impurity concentration in the thickness direction is 1×10 16 ~1×10 19 / cm 3 may be.

[0021] In the semiconductor element, the impurity-implanted region may have a guard ring structure, or the semiconductor element may be an FET and the impurity-implanted region may be a channel layer.

[0022] The method for manufacturing a semiconductor device includes an ion implantation step of ion-implanting impurities into the surface vicinity of a semiconductor layer that is an n-type or non-doped gallium oxide-based semiconductor to form an impurity-implanted region, and a heat treatment step of performing heat treatment in an inert gas atmosphere after the ion implantation step. The impurities are one or more of Ni, Co, Ti, V, Cr, Mn, and Cu.

[0023] In the method for manufacturing a semiconductor device, the impurity may include Ni.

[0024] In the method for manufacturing a semiconductor element, the heat treatment step may be performed at a temperature of 500° C. or higher and lower than 1100° C. This can enhance the current blocking effect of the impurity-implanted region while suppressing Ni diffusion to a range that does not pose a problem in device applications.

[0025] In the semiconductor device, the ion implantation process is carried out so that the concentration of impurities in the impurity implantation region is 1×10 19 / cm 3 Ion implantation may be performed so that the above results are obtained.

[0026] (Embodiment 1) 1. Structure of semiconductor elements 1 is a cross-sectional view perpendicular to the main surface of a substrate showing the configuration of a semiconductor device according to embodiment 1. The semiconductor device according to embodiment 1 is a Schottky barrier diode, and includes a substrate 10, an impurity-implanted region 11, an anode electrode 12, and a cathode electrode 13.

[0027] The substrate 10 is a substrate made of n-type Ga2O3. The Ga2O3 is β-type. While a crystal structure other than β-type is also acceptable, α-type or β-type is preferred in terms of ease of fabrication. The main surface of the substrate 10 is, for example, the (001) plane. The main surface may also be the (100) plane, the (010) plane, the (-201) plane, or the like.

[0028] The n-type impurity is Sn, and the Sn concentration in the substrate 10 is 3×10 18 / cm 3 The n-type impurity may be other than Sn, such as Si or Ge. Sn and Si are preferred. The n-type impurity concentration of the substrate 10 is 1×10 16 ~1×10 20 / cm 3 The thickness of the substrate 10 may be in the range of 50 to 600 μm, for example.

[0029] The impurity-implanted region 11 is a current blocking region provided on the surface of the substrate 10. The impurity-implanted region 11 is a region formed by ion-implanting Ni into the substrate 10, as described below. Therefore, the impurity-implanted region 11 is β-type Ga2O3 like the substrate 10, and contains not only Sn but also Ni as impurities. Ni is an impurity that forms a deep acceptor level. Ni functions as a counter dopant, reducing the electron concentration in the impurity-implanted region 11 and decreasing its conductivity.

[0030] In the first embodiment, the impurity-implanted region 11 is provided directly on the substrate 10. Alternatively, a semiconductor layer made of n-type or non-doped Ga2O3 may be provided on the substrate 10, and the impurity-implanted region 11 may be provided in the semiconductor layer.

[0031] The impurity-implanted region 11 is provided in a range from the surface of the substrate 10 to a predetermined depth. The thickness of the impurity-implanted region 11 is, for example, 50 to 1000 nm. Here, the range of the impurity-implanted region 11 is specified as a range in which the Ni concentration is higher than the donor concentration of the substrate 10.

[0032] The distribution of the Ni concentration in the impurity implanted region 11 in the thickness direction includes, in order from the surface side of the substrate 10, a first monotonically decreasing region, a plateau region, and a second monotonically decreasing region.

[0033] The first monotonically decreasing region and the second monotonically decreasing region are regions in which the Ni concentration monotonically decreases. The maximum value of the Ni concentration in the first monotonically decreasing region is, for example, 1×10 19 ~1×10 20 / cm 3 The minimum Ni concentration is 1×10 18 ~1×10 19 / cm 3 The width of the first monotonically decreasing region is, for example, 50 to 150 nm. The maximum value of the Ni concentration in the second monotonically decreasing region is, for example, 1×10 18 ~1×10 19 / cm 3 The minimum Ni concentration is 1×10 16 ~1×10 18 / cm 3 is.

[0034] The plateau region is a region where the Ni concentration is constant. Here, "constant Ni concentration" does not mean that the Ni concentration is completely constant; some fluctuation is allowed, and it is sufficient if the change in Ni concentration is sufficiently small compared to the first monotonic decrease region and the second monotonic decrease region. For example, in the plateau region, the difference between the maximum and minimum Ni concentrations is 0.5 × 10 18 / cm 3The width of the plateau region is, for example, 20 to 150 nm. The average Ni concentration in the plateau region may be 1.0 to 1.3 times the donor concentration of the semiconductor layer. The average Ni concentration in the plateau region may be, for example, 1×10 18 ~1×10 19 / cm 3 is.

[0035] As described above, the distribution of the Ni concentration in the thickness direction of the impurity-implanted region 11 has a first monotonically decreasing region, a plateau region, and a second monotonically decreasing region, which are successively arranged in this order. This allows for stable device manufacturing with high yields by minimizing variations in device performance while suppressing Ni diffusion to a range that does not interfere with device design.

[0036] The distribution of the Ni concentration in the thickness direction of the impurity-implanted region 11 may have a peak, for example, when the Ni concentration increases slightly in a plateau region or when a region where the Ni concentration increases exists between the plateau region and the second monotonically decreasing region.

[0037] The peak value of the Ni concentration in the impurity-implanted region 11 may be 2 to 100 times the donor concentration in the substrate 10. Here, the Ni concentration and donor concentration are averages in the thickness direction. Within this range, Ni acting as a counter dopant can be increased, and the electron concentration in the impurity-implanted region 11 can be sufficiently reduced. For example, the electron concentration in the impurity-implanted region 11 can be reduced to 1×10 14 / cm 3 The average Ni concentration in the thickness direction of the impurity-implanted region 11 is preferably 2 to 100 times the donor concentration of the substrate 10.

[0038] The peak value of the Ni concentration in the impurity implanted region 11 is, for example, 1×10 18 ~1×10 20 / cm 3 More preferably, 1×10 18 ~1×10 19 / cm 3The lower limit of the Ni concentration in the impurity implanted region 11 is, for example, 1×10 16 ~1×10 19 / cm 3 , which is naturally lower than the Ni concentration at the peak. The average Ni concentration in the thickness direction is, for example, 1 × 10 16 ~1×10 19 / cm 3 is.

[0039] Instead of Ni, any of Co, Ti, V, Cr, Mn, and Cu may be contained. Also, two or more of these elements and Ni may be ion-implanted. In particular, it is preferable to contain Ni.

[0040] The anode electrode 12 is an electrode provided on the impurity-implanted region 11. The anode electrode 12 is made of Ni. Materials other than Ni may be used as long as they can form a Schottky contact with the substrate 10, such as Cu, Pt, or Au. The anode electrode 12 may be multilayered, in which case the layer in contact with the substrate 10 must be made of a material that can form a Schottky contact.

[0041] The cathode electrode 13 is an electrode provided on the back surface of the substrate 10. The cathode electrode 13 is made of Ti. Materials other than Ti may be used as long as they can make ohmic contact with the substrate 10. The cathode electrode 13 may be multi-layered, in which case the layer in contact with the substrate 10 should be made of a material that can make ohmic contact.

[0042] As described above, according to the semiconductor device of the first embodiment, Ni in the impurity-implanted region 11 functions as a counter dopant, which can enhance the current blocking effect of the impurity-implanted region 11. As a result, the reverse leakage current can be reduced.

[0043] 2. Manufacturing method of semiconductor element Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0044] First, a substrate 10 made of n-type Ga2O3 is prepared, and Ni ions are implanted near the surface of the substrate 10 to form an impurity-implanted region 11. The implantation energy and dose are set so that the Ni concentration in the desired area of ​​the impurity-implanted region 11 is at least twice the donor concentration of the substrate 10. Ion implantation may be performed multiple times by changing the implantation energy and dose. For example, the dose is set to 1×10 12 ~1×10 16 / cm 2 The implantation energy is 5 to 600 keV. More preferably, the ion implantation is performed so that the Ni concentration in the impurity implanted region 11 is 2 to 100 times the donor concentration in the substrate 10.

[0045] The ion implantation may be performed while heating the substrate 10. This makes it possible to suppress crystal defects caused by the ion implantation. For example, the substrate 10 may be heated to 200 to 1050°C. The temperature is preferably 200 to 800°C, and more preferably 200 to 600°C.

[0046] Next, the substrate 10 is heat-treated. The heat treatment is carried out in an inert gas atmosphere, such as nitrogen or argon. A nitrogen atmosphere is particularly preferable.

[0047] The heat treatment temperature is set to 500°C or higher and lower than 1100°C. This range allows for sufficient repair of crystal defects caused by ion implantation. At temperatures above 1100°C, Ni diffuses widely, causing a large discrepancy between the design dimensions and the actual dimensions, making application to devices difficult. A more preferred temperature is 800 to 1050°C, and even more preferred is 850 to 1000°C.

[0048] The heat treatment time is, for example, 1 minute to 1 hour. Within this range, crystal defects in the impurity implanted region 11 can be sufficiently repaired. The heat treatment time is more preferably 5 to 40 minutes.

[0049] Any suitable heat treatment method may be used, but rapid thermal annealing (RTA) is preferred.

[0050] The heat treatment repairs the crystal defects in the impurity-implanted region 11. In addition, the ion-implanted Ni substitutes for the Ga site of Ga2O3, thereby electrically activating it. The activation of Ni forms a deep acceptor level, and Ni functions as a counter dopant. As a result, the conductivity of the impurity-implanted region 11 can be reduced, and the current blocking effect can be enhanced. For example, if the electron concentration of the impurity-implanted region 11 is reduced to 1×10 14 / cm 3 It can be as follows:

[0051] Furthermore, Ni diffuses, slightly expanding the impurity-implanted region 11. For example, the thickness of the impurity-implanted region 11 increases by about 5 to 50 nm. This activation of Ni can enhance the current blocking effect of the impurity-implanted region 11. Furthermore, this level of Ni diffusion is within a range that does not pose a problem in terms of device application.

[0052] Furthermore, the heat treatment causes the distribution of the Ni concentration in the thickness direction to have a peak. The Ni concentration at this peak is, for example, 2 to 100 times the donor concentration of the substrate 10. Also, for example, 18 ~1×10 20 / cm 3 The average Ni concentration in the thickness direction is, for example, 1 × 10 16 ~1×10 19 / cm 3 is.

[0053] Next, an anode electrode 12 is formed on the impurity-implanted region 11, and a cathode electrode 13 is formed on the back surface of the substrate 10. These electrodes are formed by sputtering, vapor deposition, or the like.

[0054] As described above, according to the method for manufacturing a semiconductor device in the first embodiment, it is possible to form the impurity-implanted region 11 having a high current blocking effect.

[0055] 3. Experimental Results Next, various experimental results regarding the semiconductor device according to the first embodiment will be described.

[0056] Experiment 1 The semiconductor device according to the first embodiment was fabricated as follows (hereinafter referred to as an example). 18 / cm 3 A substrate 10 made of doped n-type β-gallium oxide and having a (001) plane as its main surface was prepared.

[0057] Next, Ni ions were implanted near the surface of the substrate 10 to form an impurity-implanted region 11. The ion implantation was carried out so that the Ni concentration in the film was 5×10 19 / cm 3 The implantation was performed multiple times while changing the implantation energy and the dose so as to obtain a box profile of 3.7×10 at 150 keV. 14 / cm 2 , 9.0 × 10 at 50 keV 13 / cm 2 , 3.0 × 10 at 10 keV 13 / cm 2 A total of three stages of ion implantation were performed.

[0058] Next, a heat treatment was performed using an RTA device to repair crystal defects in the impurity-implanted region 11 and to electrically activate Ni. The heat treatment was performed in a nitrogen atmosphere for 30 minutes. The heat treatment temperatures were set to three levels: 900°C, 1000°C, and 1100°C. Samples that were not subjected to heat treatment were also prepared.

[0059] Next, the substrate 10 was ultrasonically cleaned with acetone, IPA, and ultrapure water. Next, a cathode electrode 13 made of Ti and having a thickness of 300 nm was formed on the back surface of the substrate 10 by DC magnetron sputtering.

[0060] Next, a 100 nm thick anode electrode 12 made of Ni was formed on the surface of the impurity-implanted region 11 by resistance heating deposition, and the anode electrode 12 was patterned by wet etching. The wet etching solution was a mixed acid solution of phosphoric acid, acetic acid, and nitric acid, and the mask was a positive resist. The planar pattern of the anode electrode 12 was a pattern consisting of multiple circular patterns spaced apart, with a total of 15 patterns, three of each of five diameters: 0.1 mm, 0.2 mm, 0.3 mm, 0.5 mm, and 1.0 mm. This was done for device performance evaluation.

[0061] Next, a heat treatment was carried out using an RTA device to adjust the bonding and characteristics of the electrodes. The heat treatment was carried out in a nitrogen atmosphere for 1 minute at 400° C. In this way, the semiconductor device of Example 1 was produced.

[0062] As a comparative example, a semiconductor device was fabricated in which N was ion-implanted instead of Ni. In the comparative example, the N concentration in the film was 5×10 in the range of 100 nm deep from the surface of the substrate 10, as in the example. 19 / cm 3 box profile of 4.0×10 at 45 keV. 14 / cm 2 , 1.0 × 10 at 20 keV 14 / cm 2 , 3.5 × 10 at 10 keV 13 / cm 2 A three-stage ion implantation was performed. Other than that, a semiconductor device was fabricated in the same manner as in the example.

[0063] 2 shows the simulation results of the distribution of N concentration in the depth direction in the comparative example, and FIG. 3 shows the simulation results of the distribution of Ni concentration in the depth direction in the example. In FIGS. 2 and 3, the depth is the depth from the surface of the impurity implanted region 11. As shown in FIGS. 2 and 3, the Ni concentration or N concentration increases by approximately 5×10 over a 100 nm range from the surface of the substrate 10 due to ion implantation. 19 / cm 3 It can be seen that:

[0064] The current-voltage characteristics were measured for the semiconductor devices of the example and comparative examples. The cathode electrode 13 was grounded, and one of the 15 anode electrodes 12 was selected. A reverse anode voltage was applied and swept from 0 V to -100 V in -0.1 V increments, and the current value between the anode and cathode at each voltage was measured. The selected anode electrode 12 was also changed to obtain current-voltage characteristics at a total of 15 points.

[0065] Figure 4 shows the current-voltage characteristics of the comparative example, and Figure 5 shows the current-voltage characteristics of the example. Figures 4(a) and 5(a) show the results without heat treatment, Figures 4(b) and 5(b) show the results with a heat treatment temperature of 900°C, Figures 4(c) and 5(c) show the results with a heat treatment temperature of 1000°C, and Figures 4(d) and 5(d) show the results with a heat treatment temperature of 1100°C.

[0066] In an SBD using gallium oxide, when a reverse voltage is applied, the current flowing between the cathode and anode is thought to be dominated by leakage current tunneling through the Schottky barrier formed at the interface between the anode electrode 12 and the n-type semiconductor. As the applied reverse voltage increases, the Schottky barrier becomes thinner and the number of tunneling electrons increases. In other words, the leakage current increases. Furthermore, when a certain voltage or higher is applied, dielectric breakdown of the Schottky barrier occurs.

[0067] As shown in Figures 4 and 5, the reverse current was smaller without heat treatment than with heat treatment at 900°C or higher. Generally, when ions are implanted into crystalline materials, the collisions of ions accelerated to high energy break the bonds between the atoms that make up the crystal, reducing the crystalline order. This reduces the electrical conductivity. Heat treatment at a certain temperature or higher is required to repair the crystal damage caused by this ion implantation. Therefore, it is thought that the reason the reverse current increased with heat treatment at 900°C or higher is due to the repair of the damage caused by ion implantation.

[0068] Previous literature has reported that N ions implanted into β-GaO form acceptor (deep acceptor) levels at deep energy positions within the band gap of β-GaO, thereby functioning as a counterdopant that reduces the conductivity of n-type β-GaO. It has also been reported that activation annealing at 1150°C is required to bring about the counterdopant effect of the implanted N.

[0069] Figure 4 shows that when N ions were implanted, the reverse current increased as the heat treatment temperature increased to 1000°C and 1100°C. This is presumably because the annealing temperature was below 1150°C, so the counter-doping effect of N did not occur, and the improvement in the conductivity of β-gallium oxide due to recovery from damage caused by ion implantation was dominant.

[0070] On the other hand, as shown in Figure 5, when Ni ions were implanted, the reverse current increased at a heat treatment temperature of 900°C compared to when no heat treatment was performed, but decreased at a heat treatment temperature of 1000°C compared to when it was performed at 900°C. Furthermore, when the heat treatment temperature was increased to 1100°C, a significant decrease in the reverse current was confirmed. These results indicate that Ni implanted into β-gallium oxide forms a deep acceptor level, just like N, and functions as a counter dopant that increases the resistance.

[0071] Furthermore, it is believed that the counterdopant effect appears at a lower heat treatment temperature than in the case of N. As a result, it is believed that N implanted into β-gallium oxide forms deep acceptor levels by substituting O, and Ni forms deep acceptor levels by substituting Ga, and it is speculated that the formation of bonds by Ni substituting Ga occurs at a lower energy than the formation of bonds by N substituting O.

[0072] Experiment 2 For the semiconductor device of the example, the distribution of Ni concentration in the depth direction of the impurity-implanted region 11 and the substrate 10 was measured by secondary ion mass spectrometry (SIMS). Fig. 6 is a graph showing the relationship between the depth from the surface of the impurity-implanted region 11 toward the substrate 10 and the Ni concentration.

[0073] As shown in Figure 6, it was found that the Ni concentration profile changed between the case where heat treatment was not performed and the case where heat treatment was performed. In other words, it was found that Ni had undergone thermal diffusion. Generally, thermal diffusion of implanted impurities is undesirable in device applications because it leads to deviation from the device design dimensions.

[0074] When the heat treatment temperature was 900°C or 1000°C, the diffusion distance was 100 nm or less, and the effect on actual device characteristics was small and within the acceptable range. It was also found that Ni diffusion caused a peak in the Ni concentration. When the heat treatment temperature was 900°C, the peak was observed around 0.13 μm, and when it was 1000°C, the peak was observed around 0.15 μm.

[0075] On the other hand, when the heat treatment temperature was 1100°C, Ni diffused to a deep range, more than 500 nm. As shown in Figure 5, the increase in the resistance of β-gallium oxide due to the counterdoping effect was maximized by heat treatment at 1100°C, but it was found that the dominant factor was the long diffusion length of Ni. Therefore, it was found that heat treatment at 1100°C is not desirable for device applications.

[0076] Furthermore, when the heat treatment temperatures were 900°C and 1000°C, the impurity concentration in the impurity-implanted region was found to have the following three regions in this order: a first monotonically decreasing region in which the impurity concentration monotonically decreases from the surface layer toward the thickness direction; a plateau region where the impurity concentration is constant; and a second monotonically decreasing region in which the impurity concentration monotonically decreases. The plateau region refers to the region in which the impurity concentration in the plateau region is 1.0 to 1.3 times the donor concentration in the semiconductor layer. Simply implanting Ni ions would cause the Ni concentration in this region to decrease rapidly, resulting in large variations in device characteristics and making it difficult to manufacture devices stably with high yields. However, the presence of this plateau region is believed to suppress Ni diffusion within a range that does not interfere with device design, reduce variations in device performance, and enable stable device manufacturing with high yields.

[0077] As a result of the above, it was found that a heat treatment temperature of less than 1100°C is preferable for application to devices.

[0078] (Embodiment 2) 7 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 2, taken perpendicular to the main surface of the substrate. The semiconductor device according to embodiment 2 is an SBD having a guard ring and a field plate. As shown in FIG. 7, the semiconductor device according to embodiment 2 includes a substrate 20, an n-type layer 25, an impurity-implanted region 21, an anode electrode 22, a cathode electrode 23, and an insulating film 24. The substrate 20 and the cathode electrode 23 are similar to the substrate 10 and the cathode electrode 23 according to embodiment 1, and therefore will not be described here.

[0079] The n-type layer 25 is a layer made of n-type GaO provided on the substrate 20. The n-type impurity is, for example, Si, and the Si concentration is 3×10 17 / cm 3 The following is the result.

[0080] The impurity-implanted region 21 is a current blocking region provided on the surface of the n-type layer 25, and is a region formed by ion-implanting Ni into the n-type layer 25. The impurity-implanted region 21 is formed in a ring-shaped pattern on the outer periphery of the anode electrode 22 in plan view. Other than that, it is the same as the impurity-implanted region 11 of the first embodiment.

[0081] Generally, when a reverse voltage is applied, electric field concentration causes breakdown at the edge of the anode electrode 22. Forming a field plate using the insulating film 24 is an effective method for terminating the electrode edge, alleviating the electric field at the edge of the anode electrode 22 and improving the breakdown voltage of the SBD. The impurity-implanted region 21 is a region in which a deep acceptor level is formed, and similar to the field plate, it functions as a guard ring that alleviates the electric field strength at the edge of the anode electrode 22.

[0082] The impurity implanted region 21 is formed to a predetermined depth from the surface of the n-type layer 25. The depth is, for example, 200 to 500 nm.

[0083] The insulating film 24 is provided from a part of the surface of the impurity implanted region 21 to the surface of the n-type layer 25 .

[0084] Anode electrode 22 is continuously formed on the surface of n-type layer 25, the surface of impurity-implanted region 21, and the surface of insulating film 24. Other than that, it is the same as anode electrode 12 of embodiment 1. Anode electrode 22 functions as an anode electrode by contacting the surface of n-type layer 25 surrounded by impurity-implanted region 21, and also functions as a field plate because it is located on the surface of n-type layer 25 via insulating film 24.

[0085] As described above, according to the semiconductor device of the second embodiment, a guard ring can be formed by the impurity implanted region 21, and the breakdown voltage can be improved.

[0086] (Embodiment 3) 8 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 3, taken perpendicular to the main surface of the substrate. The semiconductor device according to embodiment 3 is configured by adding a junction barrier structure to the SBD according to embodiment 2. As shown in FIG. 8, the semiconductor device according to embodiment 3 is configured such that an impurity-implanted region 31 is further provided within the region surrounded by impurity-implanted region 21.

[0087] The impurity-implanted regions 31 have a pattern in which the n-type layers 25 and the impurity-implanted regions 31 are alternately and periodically arranged in a plan view. The planar pattern of the impurity-implanted regions 31 is, for example, a striped pattern. The impurity-implanted regions 31 are similar to the impurity-implanted regions 21 except for the planar pattern.

[0088] The anode electrode 22 is provided continuously on the surface of the n-type layer 25 (the region sandwiched between the impurity-implanted regions 31), the surface of the impurity-implanted regions 31, and the surface of the insulating film .

[0089] As described above, the semiconductor device of the third embodiment is provided with a junction barrier structure formed by the impurity-implanted region 31. When a reverse voltage is applied to the SBD of the first and second embodiments, which does not have a junction barrier structure, electrons in the n-type gallium oxide near the anode electrode 22 are depleted, leaving behind ionized donors with a positive charge.

[0090] It is known that the leakage current of SBDs using wide-gap semiconductors is largely due to electrons tunneling through the Schottky barrier due to the electric field acceleration between the anode electrode 22 to which a negative charge is applied and the positive charges due to ionized donors in the depletion layer region.

[0091] Furthermore, the impurity implanted region 31 in the third embodiment is negatively charged due to a deep acceptor level that traps electrons.

[0092] Therefore, when a reverse voltage is applied to an SBD having a junction barrier structure as in the third embodiment, the electric field lines from the depletion layer are directed toward and dispersed not only the anode electrode 22 but also the periodically embedded impurity-implanted regions 31. In other words, when a reverse characteristic voltage is applied to the SBD in the third embodiment, the electric field between the depletion layer and the anode electrode 22 interface is relaxed, thereby reducing the leakage current.

[0093] (Embodiment 4) 9 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 4, taken perpendicular to the main surface of the substrate. The semiconductor device according to embodiment 4 is a vertical MOSFET. As shown in FIG. 9, the semiconductor device according to embodiment 4 includes a substrate 40, an n-type layer 47, an impurity-implanted region 41, an n-type impurity-implanted region 42, a gate insulating film 43, a gate electrode 44, a source electrode 45, and a drain electrode 46. The substrate 40 is similar to the substrate 10 according to embodiment 1, and the n-type layer 47 is similar to the n-type layer 25 according to embodiment 2, and therefore further description will be omitted.

[0094] 2, the impurity-implanted region 41 is a current blocking region provided on the surface of the n-type layer 47, and is separated into two regions sandwiching the n-type layer 47. Other than that, it is the same as the impurity-implanted region 11 of the first embodiment.

[0095] The n-type impurity implanted region 42 is an n-type region formed by implanting Si ions into a region inside the impurity implanted region 41 in a plan view. The n-type impurity implanted region 42 is formed to a predetermined depth from the surface of the substrate 40, and this depth is shallower than the depth of the impurity implanted region 41. The depth of the n-type impurity implanted region 42 is, for example, 50 to 200 nm. The Si concentration is, for example, 1×10 19 ~1×10 22 / cm 3 is.

[0096] The gate insulating film 43 is provided continuously between the surfaces of one of the two n-type impurity-implanted regions 42 and the other. The gate insulating film 43 may be made of Al2O3, Si3N4, SiO2, ZrO2, HfO2, BeO, AlN, or a mixed crystal thereof. Alternatively, the gate insulating film 43 may be made of a laminate of a plurality of these materials. Alternatively, amorphous Si, amorphous SiC, polycrystalline GaN, or the like may also be used.

[0097] The gate electrode 44 is an electrode provided in a region extending from the surface of one of the two impurity-implanted regions 41 to the surface of the other, with the gate insulating film 43 interposed therebetween. The gate insulating film 43 is in contact with the gate electrode 44. Examples of materials for the gate electrode 44 include Ni, Pt, Au, Ag, Cu, Co, Ir, Ru, Pd, Cr, Mo, W, Ni / Au, Ni / Pt, Pt / Au, W / Au, Pt / Ti / Au, Pt / Au / Ni, Ti / Au / Ni, and ITO.

[0098] The source electrode 45 is an electrode provided from the surface of the n-type impurity-implanted region 42 to the surface of the impurity-implanted region 41. The material of the source electrode 45 is Ti, Ti / Au, Ti / Al / Au, Ti / Al / Ti / Au, Ti / Al / Ni / Au, Ti / Au / Ni, Sn, or the like.

[0099] The drain electrode 46 is an electrode provided on the back surface of the substrate 40. The material of the drain electrode 46 is the same as that of the source electrode 45.

[0100] As described above, the semiconductor device of the fourth embodiment has a structure in which the p-type well layer in a conventional vertical MOSFET is replaced with the impurity-implanted region 41. The impurity-implanted region 41 has high resistance due to the counter-doping effect described above. In addition, a pn junction is formed between the n-type layer 47 and the n-type impurity-implanted region 42.

[0101] Here, even if a voltage is applied between the source electrode 45 and the drain electrode 46 while the gate voltage applied to the gate electrode 44 is less than the threshold voltage, no current flows between the n-type impurity implantation region 42 and the n-type layer 47 sandwiching the impurity implantation region 41. That is, the impurity implantation region 41 functions as a current blocking layer.

[0102] Also, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 44, electrons accumulate at the interface between the impurity implantation region 41 and the gate insulating film 43, and an n-type inversion layer having electron conductivity is formed. As a result, conduction is established between the n-type impurity implantation region 42 and the n-type layer 47 under the gate insulating film 43, and current flows between the source and drain electrodes. That is, the impurity implantation region 41 also functions as a channel layer, and the vertical MOSFET can be operated in a switching manner.

[0103] (Modifications of the Embodiment) Embodiments 1 to 4 were semiconductor devices using gallium oxide, but the present invention is not limited to gallium oxide and is applicable to any gallium oxide-based semiconductor. The gallium oxide-based semiconductor is a semiconductor in which a part of Ga in gallium oxide is substituted with Al or In, and is represented by (Ga x Al y In z )2O3, where 0 < x ≤ 1, 0 ≤ y < 1, 0 ≤ z < 1, and x + y + z = 1.

[0104] Embodiments 1 to 3 are SBDs, and Embodiment 4 is a MOSFET. However, the present invention can be applied not only to SBDs and MOSFETs but also to FETs such as MISFETs, JFETs, and HFETs, IGBTs, bipolar transistors, SITs, diodes, and the like. Further, since a pn junction can be formed between the impurity implantation region in the present invention and an n-type region, it can be used in place of the p-type region in a conventional semiconductor device.

[0105] The present invention is not limited to the above embodiments, and can be applied to various embodiments without departing from the gist thereof.

Explanation of Reference Numerals

[0106] 10, 20, 30, 40: Substrate 11, 21, 31, 41: Impurity implantation region 12, 22: Anode electrode 13, 23: Cathode electrode 25, 47: n-type layer 42: n-type impurity implanted region 43: Gate insulating film 44: Gate electrode 45: Source electrode 46: Drain electrode

Claims

1. a semiconductor layer that is an n-type or non-doped gallium oxide-based semiconductor; an impurity-implanted region containing impurities, the impurity-implanted region being provided in a partial region of the semiconductor layer; The impurities are at least one of Ni, Co, Ti, V, Cr, Mn, and Cu; a semiconductor element, wherein the distribution of the impurity implantation region in the thickness direction includes, in order from the surface side of the semiconductor layer, a first monotonically decreasing region in which the concentration of the impurity monotonically decreases, a plateau region in which the concentration of the impurity is constant, and a second monotonically decreasing region in which the concentration of the impurity monotonically decreases.

2. The semiconductor device according to claim 1 , wherein the impurity comprises Ni.

3. The semiconductor device according to claim 1 , wherein the concentration of the impurity in the impurity-implanted region has a peak in the thickness direction.

4. The width of the plateau region is 0.02 μm or more and 0.15 μm or less. The semiconductor element according to claim 1 or 2.

5. 3. The semiconductor device according to claim 1, wherein the concentration of the impurity in the plateau region is 1.0 to 1.3 times the donor concentration of the semiconductor layer.

6. The concentration of the impurity at the peak is 1×10 １８ ~1 x 10 ２０ / cm ３ 4. The semiconductor device according to claim 3, wherein:

7. The average concentration of the impurities in the thickness direction is 1×10 １６ ~1 x 10 １９ / cm ３ 4. The semiconductor device according to claim 1, wherein:

8. 4. The semiconductor device according to claim 3, wherein the concentration of the impurity at the peak is 2 to 100 times the donor concentration of the semiconductor layer.

9. The semiconductor device according to claim 1 , wherein the impurity-implanted region has a guard ring structure.

10. the semiconductor element is a FET, The semiconductor device according to claim 1 , wherein the impurity-implanted region is a channel layer.

11. an ion implantation step of ion-implanting impurities into the vicinity of the surface of a semiconductor layer that is an n-type or non-doped gallium oxide-based semiconductor to form an impurity-implanted region; a heat treatment step of performing heat treatment in an inert gas atmosphere after the ion implantation step, The impurity is at least one of Ni, Co, Ti, V, Cr, Mn, and Cu.

12. The method of manufacturing a semiconductor device according to claim 11 , wherein the impurity includes Ni.

13. The method of manufacturing a semiconductor device according to claim 11, wherein the heat treatment is performed at a temperature of 500° C. or higher and lower than 1100° C.

14. The ion implantation step is performed such that the concentration of the impurity in the impurity implanted region is 1×10 １９ / cm ３ The method for manufacturing a semiconductor device according to claim 11, wherein ions are implanted so as to satisfy the above.

Images