Semiconductor device

Abstract

To provide a semiconductor device capable of improving the degree of freedom in design while suppressing the operation of a parasitic pnp bipolar transistor in a configuration incorporating a bootstrap diode (BSD).SOLUTION: The semiconductor device includes an n-type first semiconductor substrate 1, a high-side circuit 101 including a p-type first well region 26 provided on the upper surface side of the first semiconductor substrate 1, and a bootstrap diode 103 including a p-type anode region 27 provided on the upper surface side of the first semiconductor substrate 1 so as to be separated from the first well region 26.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes - The present invention discloses a configuration in which a p-type anode region of a bootstrap diode (BSD) is formed on the low potential side of a p-type region, and the BSD is built into a high voltage integrated circuit (HVIC).

[0003] Patent Document 2 describes a low-voltage diode formed in a low-side circuit region and an n-type diode that also functions as a voltage-resistant region. - We disclose a configuration in which a BSD is built into an HVIC by connecting two diffusion resistors in series. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4610786 specification (Figure 2) [Patent Document 2] Patent No. 4397602 specification (Figure 2) Summary of the Invention [Problem to be solved by the invention]

[0005] The configuration of Patent Document 1 has a vertical parasitic pnp bipolar transistor that uses the anode region of the BSD as its emitter, which causes a problem in that this parasitic pnp bipolar transistor operates every time the BSD is turned on, causing a large current to flow.

[0006] In the configuration of Patent Document 2, a low-voltage diode is used as a countermeasure against the operation of a parasitic pnp bipolar transistor that uses the anode region of the BSD as its emitter. - The junction is formed away from the mold region and a buried layer is added to this region, but this solution limits the design freedom.

[0007] In view of the above problems, an object of the present disclosure is to provide a semiconductor device that can improve design freedom while suppressing the operation of a parasitic pnp bipolar transistor in a configuration with a built-in BSD. [Means for solving the problem]

[0008] One aspect of the present disclosure is a semiconductor device including: an n-type first semiconductor substrate; a high-side circuit including a p-type first well region provided on an upper surface side of the first semiconductor substrate; and a bootstrap diode including a p-type anode region provided on the upper surface side of the first semiconductor substrate at a distance from the first well region. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a semiconductor device that can suppress the operation of a parasitic pnp bipolar transistor and improve the degree of freedom in design in a configuration with a built-in BSD. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line AA' in FIG. 2. [Figure 4] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along the line BB' in FIG. 2. [Figure 5] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along line CC' in FIG. 2. [Figure 6] 3 is a cross-sectional view of the semiconductor device according to the first embodiment taken along the line DD' in FIG. 2. [Figure 7] FIG. 10 is a circuit diagram of a semiconductor device according to a comparative example. [Figure 8] FIG. 10 is a plan view of a semiconductor device according to a comparative example. [Figure 9]9 is a cross-sectional view of the semiconductor device according to the comparative example taken along the line AA′ in FIG. 8. [Figure 10] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 12] 12 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the line AA′ in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first and second embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first and second embodiments shown below exemplify devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components described below.

[0012] In this specification, the term "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) or static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In addition, the anode region serves as the carrier supply region in a diode, static induction (SI) thyristor, or gate turn-off (GTO) thyristor. In addition, the term "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET or SIT, or the collector region of an IGBT. In a diode, SI thyristor, or GTO thyristor, the cathode region functions as the carrier receiving region.

[0013] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0014] In addition, in this specification, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type. Furthermore, the "+" or "-" attached to the "n" of n-type or the "p" of p-type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the same "n" and "n" are attached to semiconductor regions, this does not mean that the impurity concentration of each semiconductor region is strictly the same. Furthermore, in the following description, members and regions that are limited by the terms "first conductivity type," "second conductivity type," "n-type," and "p-type" mean members and regions made of semiconductor materials, even if there is no particular explicit limitation. Furthermore, in the claims, "n-type" refers to the same as "n-type" and "n" in this specification. - Type" and "n + "p-type" includes "p-type" and "p-type" - Type" and "p + It includes "type".

[0015] (First embodiment) <Circuits of semiconductor devices> 1 shows a circuit configuration of a high-voltage integrated circuit (HVIC) 100 as an example of a semiconductor device according to the first embodiment. The HVIC 100 drives, for example, a power conversion unit 200, which is one phase of a power conversion bridge circuit. The power conversion unit 200 configures a half-bridge circuit by connecting a high-side switching element T3 and a low-side switching element T4 in series. While FIG. 1 illustrates IGBTs as the high-side switching element T3 and the low-side switching element T4, other power switching elements such as metal-oxide semiconductor field-effect transistors (MOSFETs) may also be used.

[0016] The collector of the high-potential side switching element T3 is connected to a high-potential side HV potential. The emitter of the low-potential side switching element T4 is connected to a low-potential side ground potential (GND potential). A load (not shown), such as a motor, is connected to a VS potential, which is the potential at a connection point 105 (the midpoint of the half-bridge circuit) between the emitter of the high-potential side switching element T3 and the collector of the low-potential side switching element T4.

[0017] The HVIC 100 applies a drive signal to the gate of the high potential side switching element T3, which drives the gate of the high potential side switching element T3 by turning the gate on and off in response to an input signal IN from an external microcomputer, etc. The HVIC 100 includes a low potential side circuit (low side circuit) 101 and a high potential side circuit (high side circuit) 102.

[0018] The low-side circuit 101 is connected to a VCC potential, which is the potential on the positive side of a low-potential power supply (low-potential power supply) 106, and a GND potential, which is the negative side of the low-potential power supply 106. Furthermore, the gates of level shift elements (level shifters) T1 and T2 are connected to the low-side circuit 101. The low-side circuit 101 operates using the GND potential as a reference potential and the VCC potential, which is higher than the GND potential, as a power supply potential. The low-side circuit 101 generates an on / off signal with the GND potential as the reference in response to an input signal IN from an external microcomputer or the like, and outputs the signal to the gates of the level shifters T1 and T2.

[0019] The high-side circuit 102 operates using the VS potential, which is the midpoint potential of the half-bridge circuit, as its reference potential and the VB potential, which is higher than the VS potential, as its power supply potential. In response to on / off signals from the level shifters T1 and T2, the high-side circuit 102 outputs a drive signal, based on the VS potential, to the gate of the high-side switching element T3, thereby driving the gate of the high-side switching element T3. The high-side circuit 102 includes, for example, a CMOS circuit of an n-channel MOSFET and a p-channel MOSFET in its output stage.

[0020] The VB potential is the highest potential applied to the HVIC100, and is maintained about 15V higher than the VS potential under normal conditions when not affected by noise. The VS potential repeatedly rises and falls between the high-potential side HV potential (for example, about 400V to 600V) and the low-potential side GND potential as the high-potential side switching element T3 and the low-potential side switching element T4 are complementarily turned on and off, fluctuating between 0V and several hundred volts. Note that the VS potential may also become a negative potential.

[0021] The HVIC 100 includes bootstrap circuits (103, 104) so ​​that the low-potential-side power supply 106 can also be used as a high-potential power supply. The bootstrap circuits (103, 104) include a bootstrap diode (BSD) 103 and a bootstrap capacitor (BSC) 104. The anode of the BSD 103 is connected to the VCC potential on the positive side of the low-potential-side power supply 106. The cathode of the BSD 103 is connected to the VB potential, which is one end of the BSC 104. The other end of the BSC 104 is connected to the VS potential of a connection point 105. The BSD 103 prevents current from flowing into the VCC potential when the VB potential is higher than the VCC potential. The BSD 103 turns on when the VB potential becomes lower than the VCC potential, and charges the BSC 104.

[0022] The level shifters T1 and T2 transmit signals between the low-side circuit 101 and the high-side circuit 102. The level shifters T1 and T2 convert an on / off signal based on the GND potential from the low-side circuit 101 into an on / off signal based on the VS potential, and output the converted on / off signal to the high-side circuit 102. The level shifters T1 and T2 are configured, for example, with a high-voltage n-channel MOSFET.

[0023] The source of the level shifter T1 is connected to the GND potential. The drain of the level shifter T1 is connected to the high-side circuit 102 and one end of the level shift resistor R1. The other end of the level shift resistor R1 is connected to the cathode of the BSD103 and the VB potential at one end of the BSC104. The drain of the level shifter T1 and one end of the level shift resistor R1 are connected to the cathode of the diode D1. The anode of the diode D1 is connected to the VS potential at the connection point 105. The diode D1 has the function of preventing an excessive drop in the drain potential of the level shifter T1.

[0024] The source of the level shifter T2 is connected to the GND potential. The drain of the level shifter T2 is connected to the high-side circuit 102 and one end of the level shift resistor R2. The other end of the level shift resistor R2 is connected to the cathode of the BSD103 and the VB potential at one end of the BSC104. The drain of the level shifter T2 and one end of the level shift resistor R2 are connected to the cathode of the diode D2. The anode of the diode D2 is connected to the VS potential at the connection point 105. The diode D2 has the function of preventing an excessive drop in the drain potential of the level shifter T2.

[0025] The cathode of a high-voltage diode D0, called a high-voltage junction termination (HVJT), is connected to the VB potential at the other ends of the level shift resistors R1 and R2 and one end of the BSC 104. The anode of the diode D0 is connected to the GND potential.

[0026] <Structure of semiconductor device> FIG. 2 shows a planar layout of a semiconductor device according to the first embodiment corresponding to the HVIC 100 shown in FIG. 1, and FIG. 3 shows a cross section taken along line AA′ in FIG.

[0027] As shown in FIGS. 2 and 3, the HVIC 100 is a first conductivity type (n -The semiconductor substrate 1 is made of, for example, silicon (Si). The semiconductor substrate 1 may also be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), or diamond (C).

[0028] The semiconductor substrate 1 is - a semiconductor substrate and an n-type semiconductor layer formed on the semiconductor substrate; - The semiconductor substrate (epi-substrate) may be made of an epitaxially grown layer of the type. In this case, the impurity concentration of the epitaxially grown layer may be approximately the same as, higher than, or lower than the impurity concentration of the semiconductor substrate.

[0029] As shown in Figures 2 and 3, n - A well region 21 of a second conductivity type (p-type) is provided on the upper surface side of the semiconductor substrate 1. The well region 21 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 21 are not particularly limited.

[0030] As shown in FIG. 3, on the upper surface side of the p-type well region 21, there is a p + A molded pickup region (contact region) 21a is provided. A GND electrode 42 to which a GND potential, which is a reference potential of the low-side circuit 101, is applied is electrically connected to the pickup region 21a. The GND potential is applied to the well region 21 via the GND electrode 42 and the pickup region 21a. The GND electrode 42 and the pickup region 21a shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the GND electrode 42 and the pickup region 21a are not particularly limited.

[0031] 2 and 3, an n-type well region 22 is provided on the upper surface side of the well region 21 in contact with the well region 21. The well region 22 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 22 are not particularly limited.

[0032] As shown in FIG. 3, on the upper surface side of the well region 22, there is provided an n-type semiconductor layer having a higher impurity concentration than the well region 22. + A molded pickup region (contact region) 22a is provided. A VCC electrode 41 to which a VCC potential, which is a power supply potential of the low-side circuit 101, is applied is electrically connected to the pickup region 22a. The VCC potential is applied to the well region 22 via the VCC electrode 41 and the pickup region 22a. The VCC electrode 41 and the pickup region 22a shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the VCC electrode 41 and the pickup region 22a are not particularly limited.

[0033] A low-side circuit (low-side circuit region) 101 is provided in the well regions 21 and 22. Various elements included in the low-side circuit 101 are not shown in FIGS.

[0034] As shown in FIGS. 2 and 3, a p - A mold-type breakdown voltage region 23 is provided. The depth of the breakdown voltage region 23 may be formed shallower than the depth of the well region 21. The outer periphery of the breakdown voltage region 23 is in contact with the semiconductor substrate 1.

[0035] The pn junction between the breakdown voltage region 23 and the semiconductor substrate 1 forms a high-voltage junction termination (HVJT) (1, 23). The HVJT (1, 23) corresponds to the high-voltage diode D0 shown in Figure 1. The HVJT (1, 23) electrically isolates the low-side circuit 101 and the high-side circuit 102. Even if the potential of the high-side circuit 102 becomes several hundred volts higher than the potential of the low-side circuit 101, the HVJT (1, 23) ensures normal operation.

[0036] 2 and 3, a p-type well region 26 is provided on the upper surface side of the semiconductor substrate 1, separated from the voltage-resistant region 23. The well region 26 is in contact with the semiconductor substrate 1. The well region 26 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 26 are not particularly limited.

[0037] As shown in FIG. 3, on the upper surface side of the well region 26, a p + A mold pickup region (contact region) 26a is provided. A VS electrode 43 to which a VS potential, which is the reference potential of the high-side circuit 102, is applied, is electrically connected to the pickup region 26a. The VS potential is applied to the well region 26 via the VS electrode 43 and the pickup region 26a. The VS electrode 43 and the pickup region 26a shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the VS electrode 43 and the pickup region 26a are not particularly limited.

[0038] A high-side circuit (high-side circuit region) 102 is formed in a part of the semiconductor substrate 1 and in the well region 26. Various elements included in the high-side circuit 102 are not shown in FIGS.

[0039] As shown in FIG. 3, on the upper surface side of the semiconductor substrate 1 where the high-side circuit 102 is formed, there is provided an n-type semiconductor layer having a higher impurity concentration than the semiconductor substrate 1. + A molded pickup region (contact region) 28 is provided. A VB electrode 45 to which a VB potential, which is a power supply potential of the high-side circuit 102, is applied is electrically connected to the pickup region 28. The VB potential is applied to the semiconductor substrate 1 via the VB electrode 45 and the pickup region 28. The VB electrode 45 and the pickup region 28 shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the VB electrode 45 and the pickup region 28 are not particularly limited.

[0040] As shown in Fig. 3, an HO electrode 44 is provided on the upper surface of the semiconductor substrate 1, where the high-side circuit 102 is formed, to which an HO potential, which is the potential of the output stage of the high-side circuit 102, is applied. The HO electrode 44 shown in Fig. 3 is not shown in Fig. 2. The planar pattern and arrangement position of the HO electrode 44 are not particularly limited.

[0041] 2 and 3, a BSD 103 is provided on the upper surface of the semiconductor substrate 1. The BSD 103 is provided at a position where the high-side circuit 102 is sandwiched between the BSD 103 and the low-side circuit 101. The BSD 103 is provided on the upper surface of the semiconductor substrate 1 at a distance from the well region 26. - The BSD 103 includes an anode region 27 of a type, and a cathode region formed of a part of the semiconductor substrate 1 in contact with the anode region 27. When the VB potential is higher than the VCC potential, the BSD 103 ensures a breakdown voltage by depleting the depletion layer spreading from the pn junction between the anode region 27 and the semiconductor substrate 1 (cathode region) to such an extent that it does not reach the pickup region 27a and the pickup region 29. When the VB potential becomes lower than the VCC potential, the BSD 103 turns on, and a current flows from the VCC potential on the anode side to the VB potential on the cathode side, charging the BSC 104 shown in FIG. 1.

[0042] The anode region 27 has a substantially circular planar pattern. The planar pattern of the anode region 27 is not limited to a circular shape and may be, for example, a substantially rectangular shape. For example, the anode region 27 is provided at a position around the high-side circuit 102 that is farthest from the well region 26 of the high-side circuit 102. The anode region 27 is separated from the well region 26 of the high-side circuit 102 by a distance D1.

[0043] The depth of the anode region 27 may be approximately the same as the depth of the voltage-resistant region 23. The impurity concentration of the anode region 27 may be approximately the same as the impurity concentration of the voltage-resistant region 23. The anode region 27 can be formed simultaneously with the voltage-resistant region 23, which can prevent an increase in the number of steps. The anode region 27 may be formed in a different process from that for the voltage-resistant region 23. The depth of the anode region 27 may be deeper or shallower than the depth of the voltage-resistant region 23. The impurity concentration of the anode region 27 may be higher or lower than the impurity concentration of the voltage-resistant region 23.

[0044] As shown in FIG. 3, the upper surface of the anode region 27 is provided with a p + A molded pickup region (contact region) 27a is provided. A VCC electrode (anode electrode) 46 to which a VCC potential, which is a power supply potential of the low-side circuit 101, is applied is electrically connected to the pickup region 27a. The VCC potential is applied to the anode region 27 via the VCC electrode 46 and the pickup region 27a. The pickup region 27a and the VCC electrode 46 shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the pickup region 27a and the VCC electrode 46 are not particularly limited.

[0045] The VCC electrode 46 may be electrically connected to a lead frame to which the VCC potential is applied by a bonding wire (wire) or the like. The VCC electrode 46 may be electrically connected to the VCC electrode 41 of the low-side circuit 101 via a metal wiring or the like.

[0046] As shown in FIG. 3, on the upper surface side of the semiconductor substrate 1 at a position that will become the cathode region of the BSD 103, there is provided an n-type semiconductor layer having a higher impurity concentration than the semiconductor substrate 1. +A molded pickup region (contact region) 29 is provided. A VB electrode (cathode electrode) 47 to which a VB potential, which is the power supply potential of the high-side circuit 102, is applied, is electrically connected to the pickup region 29. The pickup region 27a and the VB electrode 47 shown in FIG. 3 are not shown in FIG. 2. The planar patterns and arrangement positions of the pickup region 27a and the VB electrode 47 are not particularly limited. The pickup region 27a may have, for example, a ring-shaped planar pattern surrounding the periphery of the anode region 27.

[0047] The location of BSD 103 is not limited to this. For example, BSD 103 may be provided at a position where low-side circuit 101 is sandwiched between BSD 103 and high-side circuit 102. In this case, the distance between VCC electrode 46 of BSD 103 and VCC electrode 41 of low-side circuit 101 becomes shorter, and the metal wiring connecting VCC electrode 46 and VCC electrode 41 can be shortened.

[0048] 3, the semiconductor substrate 1 is mounted on a lead frame 61 to which a VB potential is applied, and is electrically connected to the lead frame 61. The lower surface of the semiconductor substrate 1 is in contact with the lead frame 61. An electrode may be provided on the lower surface of the semiconductor substrate 1, or the electrode may be in contact with the lead frame 61. The semiconductor substrate 1 may be mounted, via an insulating adhesive or an insulating sheet, on a lead frame to which a potential different from the VB potential, such as a GND potential, is applied.

[0049] As shown in Figure 2, level shifters 10a and 10b are integrally formed in part of the voltage-resistant region 23 on the low-side circuit 101 side. The level shifters 10a and 10b are composed of high-voltage n-channel MOSFETs. The level shifters 10a and 10b correspond to the level shifters T1 and T2 shown in Figure 1.

[0050] Here, there are roughly two methods for forming the MOSFETs that constitute the level shifters T1 and T2 shown in FIG. 1: one is called the wire bonding method (WB method) and the other is called the self-shielding method (SS method). The WB method is a method in which the MOSFET is formed separately from the HVJT (1, 23), and the drain potential (Dr potential) of the MOSFET is connected to the high-side circuit 102 by a bonding wire. The SS method is a method in which the MOSFET is formed integrally with the voltage-resistant region 23. Although either method is applicable to the semiconductor device according to the first embodiment, the case in which the level shifters 10a and 10b are formed by the SS method will be illustrated.

[0051] The level shifters 10a and 10b are provided on the side of the voltage-resistant region 23 facing the high-side circuit 102. The positions of the level shifters 10a and 10b are not particularly limited.

[0052] The level shifter 10a is provided on the upper surface side of the drain region 11a and has an n-type carrier receiving region (drain region) 11a and an n-type carrier receiving region (drain region) 11b having a higher impurity concentration than the drain region 11a. + an n-type pickup region (contact region) 12a, an n-type carrier supply region (source region) 13a provided opposite to the drain region 11a, and an n-type carrier supply region (source region) 13a provided on the upper surface side of the source region 13a and having a higher impurity concentration than the source region 13a. + The mold has a pick-up area (contact area) 14a.

[0053] The level shifter 10b is provided on the upper surface side of the drain region 11b and has an n-type carrier receiving region (drain region) 11b and an n-type carrier receiving region (drain region) 11b and has a higher impurity concentration than the drain region 11b. + an n-type pickup region (contact region) 12b, an n-type carrier supply region (source region) 13b provided opposite to the drain region 11b, and an n-type carrier supply region (contact region) 13b provided on the upper surface side of the source region 13b and having a higher impurity concentration than the source region 13b. + The mold has a pick-up area (contact area) 14b.

[0054] 4 shows a cross section taken along line BB' passing through the level shifter 10a in FIG. 2. As shown in FIG. 4, an n-type drain region 11a is provided on the upper surface side of the voltage-resistant region 23. An n-type impurity layer having a higher impurity concentration than the drain region 11a is provided on the upper surface side of the drain region 11a. + A mold pickup region 12a is provided. A drain electrode 56 is electrically connected to the pickup region 12a via a contact hole provided in the insulating film 53.

[0055] An n-type source region 13a is provided on the upper surface side of the voltage-resistant region 23, spaced apart from the drain region 11a. An n-type source region 13a having a higher impurity concentration than the source region 13a is provided on the upper surface side of the source region 13a. + A mold pickup region 14a is provided. A source electrode 55 is electrically connected to the pickup region 14a via a contact hole provided in the insulating film 53.

[0056] A gate electrode 52 is provided on the upper surface of the semiconductor substrate 1 between the drain region 11a and the source region 13a, with a gate insulating film 51 interposed therebetween. A resistive field plate 54 is provided on the upper surface of the drain region 11a with insulating films 50 and 53 interposed therebetween. The field plate 54 has a spiral planar pattern. An n-type impurity layer having a higher impurity concentration than the semiconductor substrate 1 is provided on the upper surface of the semiconductor substrate 1 outside the drain region 11a. + A mold pickup region 16 is provided. A VB electrode 57 is electrically connected to the pickup region 16 via a contact hole provided in the insulating film 53.

[0057] The pickup region 16, the source electrode 55, the drain electrode 56, the VB electrode 57, the insulating films 50 and 53, the gate insulating film 51, the gate electrode 52, and the field plate 54 shown in Fig. 4 are not shown in Fig. 2. The configuration of the level shifter 10b shown in Fig. 2 is the same as the configuration of the level shifter 10a shown in Fig. 4.

[0058] Fig. 5 shows a cross section taken along line CC' in Fig. 2. As shown in Fig. 5, an n-type diffusion region 11 is provided directly below the field plate 54 on the upper surface side of the voltage-resistant region 23. Fig. 6 shows a cross section taken along line DD' in Fig. 2. As shown in Fig. 6, a drain electrode 56 is connected to a VB electrode 57.

[0059] <Comparative Example> Here, a semiconductor device according to a comparative example will be described. Fig. 7 shows the circuit configuration of an HVIC 100x as a semiconductor device according to a comparative example. As shown in Fig. 7, the HVIC 100x differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the bootstrap circuits (103, 104) are externally attached and the BSD 103 is not built-in.

[0060] Fig. 8 shows a planar layout of a semiconductor device according to a comparative example corresponding to the HVIC 100x of Fig. 7, and Fig. 9 shows a cross section taken along line AA' of Fig. 8. As shown in Figs. 8 and 9, the HVIC 100x has p - The semiconductor device according to the first embodiment shown in FIG. 2 differs from the semiconductor device according to the first embodiment shown in FIG. 2 in that it is formed on a semiconductor substrate 1x.

[0061] A GND potential is applied to the semiconductor substrate 1x via the GND electrode 42 shown in Fig. 9. An n-type well region 71 is provided on the upper surface side of the semiconductor substrate 1x. A VCC potential is applied to the well region 71 via the VCC electrode 41 shown in Fig. 9. A low-side circuit 101 is formed in a part of the semiconductor substrate 1x and in the well region 71.

[0062] An n-type well region 72 having a higher impurity concentration than the semiconductor substrate 1x is provided on the upper surface side of the semiconductor substrate 1x. A VB potential is applied to the well region 72 via a VB electrode 45 shown in FIG. 9. A p-type well region 73 is provided on the upper surface side of the well region 72. A VS potential is applied to the well region 73 via a VS electrode 43 shown in FIG. 9. A high-side circuit 102 is formed in the well regions 72 and 73. An HO electrode 44 is provided on the upper surface side of the well region 72.

[0063] On the outer periphery of the well region 72, an n-type impurity layer having a lower impurity concentration than the well region 72 is formed. - A type-type voltage-resistant region 74 is provided. A HVJT is formed by a pn junction between the voltage-resistant region 74 and the semiconductor substrate 1x. The semiconductor substrate 1x is mounted on a lead frame 62 to which a GND potential is applied.

[0064] 7 to 9, the bootstrap circuits (103, 104) are externally attached, which increases the mounting area. In contrast, in the semiconductor device according to the first embodiment, the HVIC 100 incorporates the BSD 103 of the bootstrap circuits (103, 104), which reduces the mounting area.

[0065] In addition, in Patent Document 1, a BSD is built in, but a vertical parasitic pnp bipolar transistor is formed with the anode region of the BSD as the emitter. - By using the semiconductor substrate 1 of this type, a vertical parasitic pnp bipolar transistor having the anode region 27 of the BSD 103 as an emitter is not formed, and the operation of the vertical parasitic pnp bipolar transistor can be suppressed.

[0066] Furthermore, in Patent Document 2, the operation of a vertical parasitic pnp bipolar transistor is suppressed, which limits the degree of freedom in design. In contrast, in the semiconductor device according to the first embodiment, the anode region 27 can be spaced apart from the well region 26 at the VS potential and the well region 21 at the GND potential, which can serve as the collector of a parasitic pnp bipolar transistor having the anode region 27 of the BSD 103 as its emitter, thereby improving the degree of freedom in design.

[0067] Furthermore, in the semiconductor device according to the first embodiment, the BSD 103 is provided at a position sandwiching the high-side circuit 102 between it and the low-side circuit 101. This allows the anode region 27 to be spaced apart from the p-type well region 21 of the low-side circuit 101, thereby suppressing the operation of a parasitic pnp bipolar transistor in which the anode region 27 serves as the emitter, the semiconductor substrate 1 serves as the base, and the well region 21 serves as the collector.

[0068] Furthermore, in the semiconductor device according to the first embodiment, the BSD 103 is provided at a position around the high-side circuit 102 that is away from the p-type well region 26. This makes it possible to suppress the operation of a parasitic pnp bipolar transistor that uses the anode region 27 as the emitter, the semiconductor substrate 1 as the base, and the well region 26 as the collector.

[0069] (Second embodiment) <Circuits of semiconductor devices> Fig. 10 shows the circuit configuration of an HVIC (100a, 100b) as an example of a semiconductor device according to the second embodiment. As shown in Fig. 10, the HVIC (100a, 100b) differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that it is divided into two semiconductor chips 100a, 100b.

[0070] The semiconductor chip 100a includes a low-side circuit 101 and level shifters T1 and T2. The semiconductor chip 100b includes a high-side circuit 102, a BSD 103, level shift resistors R1 and R2, and diodes D1 and D2. Because the low-side circuit 101 and the high-side circuit 102 are formed individually on the semiconductor chips 100a and 100b, the diode D0 constituting the HVJT for electrically isolating the low-side circuit 101 and the high-side circuit 102 is not provided. The other circuit configurations of the semiconductor device according to the second embodiment are substantially similar to those of the semiconductor device according to the first embodiment shown in FIG. 1, and therefore, redundant description will be omitted.

[0071] <Structure of semiconductor device> Fig. 11 shows a planar layout of a semiconductor device according to the second embodiment, which corresponds to the HVIC (100a, 100b) shown in Fig. 10. Fig. 12 shows a cross section taken along line AA' in Fig. 11. As shown in Figs. 11 and 12, the HVIC (100a, 100b) includes two semiconductor chips 100a, 100b. The semiconductor chips 100a, 100b are spaced apart from each other.

[0072] The semiconductor chip 100a is - The semiconductor substrate 1a is made of, for example, silicon (Si). The semiconductor substrate 1a may also be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), or diamond (C).

[0073] The semiconductor substrate 1a is p - a p-type semiconductor substrate and a p-type semiconductor layer formed on the semiconductor substrate; - The semiconductor substrate (epi-substrate) may be made of an epitaxially grown layer of the type. In this case, the impurity concentration of the epitaxially grown layer may be approximately the same as, higher than, or lower than the impurity concentration of the semiconductor substrate.

[0074] As shown in FIGS. 11 and 12, the upper surface of the semiconductor substrate 1a is provided with n - A mold well region 91 is provided. The well region 91 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 91 are not particularly limited.

[0075] As shown in FIG. 12, on the upper surface side of the well region 91, there is provided an n-type semiconductor layer having a higher impurity concentration than the well region 91. +A molded pickup region (contact region) 91a is provided. A VCC electrode 41 to which a VCC potential, which is a power supply potential of the low-side circuit 101, is applied is electrically connected to the pickup region 91a. The VCC potential is applied to the well region 91 via the VCC electrode 41 and the pickup region 91a. The VCC electrode 41 and the pickup region 91a shown in FIG. 12 are not shown in FIG. 11. The planar patterns and arrangement positions of the VCC electrode 41 and the pickup region 91a are not particularly limited.

[0076] A low-side circuit 101 is formed in a part of the semiconductor substrate 1a and in the well region 91. Various elements included in the low-side circuit 101 are not shown in Figures 11 and 12.

[0077] As shown in FIG. 12, the p - The upper surface of the semiconductor substrate 1a is provided with a p + A molded pickup region (contact region) 94 is provided. A GND electrode 42 to which a GND potential, which is a reference potential of the low-side circuit 101, is applied is electrically connected to the pickup region 94. The GND potential is applied to the semiconductor substrate 1a via the GND electrode 42 and the pickup region 94. The GND electrode 42 and the pickup region 94 shown in FIG. 12 are not shown in FIG. 11. The planar patterns and arrangement positions of the GND electrode 42 and the pickup region 94 are not particularly limited.

[0078] 11, the semiconductor chip 100a includes WB level shifters 80a and 80b. The level shifters 80a and 80b have a substantially circular planar pattern. The level shifters 80a and 80b are configured with high-voltage n-channel MOSFETs.

[0079] The level shifter 80a includes a p-type base region 81a, a p + Mold pickup areas (contact areas) 82a,n + a carrier supply region (source region) 83a, a gate electrode 84a, and- Drift regions 85a and n + The base region 81a has a carrier receiving region (drain region) 86a. The base region 81a has an annular planar pattern. The pickup region 82a and the source region 83a are provided inside the base region 81a and have annular planar patterns. The drift region 85a is provided in contact with the base region 81a and has a circular planar pattern. The depth of the drift region 85a may be greater than or equal to the depth of the well region 91.

[0080] The gate electrode 84a is provided above the annular p-type base region 81a sandwiched between the source region 83a and the drift region 85a, with a gate insulating film (not shown) interposed therebetween. The drain region 86a is provided on the upper surface side of the drift region 85a and has a circular planar pattern. A drain electrode 87a is provided on the upper surface side of the drain region 86a. A pad 89a of the semiconductor chip 100b is connected to the drain electrode 87a via a bonding wire 88a.

[0081] As shown in FIG. 11, the level shifter 80b includes a p-type base region 81b, a p + Pick-up area (contact area) 82b, n + a carrier supply region (source region) 83b, a gate electrode 84b, and an n - Drift regions 85b and n + The base region 81b has a carrier receiving region (drain region) 86b. The base region 81b has an annular planar pattern. The pickup region 82b and the source region 83b are provided inside the base region 81b and have annular planar patterns. The drift region 85b is provided in contact with the base region 81b and has a circular planar pattern. The depth of the drift region 85b may be greater than or equal to the depth of the well region 91.

[0082] The gate electrode 84b is provided above the annular p-type base region 81b sandwiched between the source region 83b and the drift region 85b, with a gate insulating film (not shown) interposed therebetween. The drain region 86b is provided on the upper surface side of the drift region 85b and has a circular planar pattern. A drain electrode 87b is provided on the upper surface side of the drain region 86b. A pad 89b of the semiconductor chip 100b is connected to the drain electrode 87b via a bonding wire 88b.

[0083] 12, the semiconductor substrate 1a is mounted on a lead frame 63 to which a GND potential is applied, and is electrically connected to the lead frame 63. The lower surface of the semiconductor substrate 1a is in contact with the lead frame 63. An electrode may be provided on the lower surface of the semiconductor substrate 1a, or the electrode may be in contact with the lead frame 63. The semiconductor substrate 1a may be provided on a lead frame to which a potential different from the GND potential is applied, via an insulating adhesive or an insulating sheet.

[0084] On the other hand, as shown in FIGS. 11 and 12, the semiconductor chip 100b has n - The semiconductor substrate 1b has the same configuration as the semiconductor substrate 1 of the semiconductor device according to the first embodiment.

[0085] 11 and 12, a p-type well region 92 is provided on the upper surface side of the semiconductor substrate 1b. The well region 92 has a substantially rectangular planar pattern. The planar pattern and arrangement position of the well region 92 are not particularly limited.

[0086] As shown in FIG. 12, on the upper surface side of the well region 92, a p +A molded pickup region (contact region) 92a is provided. A VS electrode 43 to which a VS potential, which is the reference potential of the high-side circuit 102, is applied, is electrically connected to the pickup region 92a. The VS electrode 44 and pickup region 92a shown in FIG. 12 are not shown in FIG. 11, and are connected to the well region 92 via the VS electrode 44 and pickup region 92a. The planar pattern and arrangement positions of the VS electrode 44 and pickup region 92a are not particularly limited.

[0087] A high-side circuit 102 is formed in a part of the semiconductor substrate 1b and in the well region 92. Various elements included in the high-side circuit 102 are not shown in Figures 11 and 12.

[0088] As shown in FIG. 12, on the upper surface side of the semiconductor substrate 1b where the high-side circuit 102 is formed, there is provided an n-type semiconductor substrate having a higher impurity concentration than the semiconductor substrate 1b. + A molded pickup region (contact region) 96 is provided. A VB electrode 46 to which a VB potential, which is a power supply potential of the high-side circuit 102, is applied is electrically connected to the pickup region 96. The VB potential is applied to the semiconductor substrate 1b via the VB electrode 46 and the pickup region 96. The VB electrode 46 and the pickup region 96 shown in FIG. 12 are not shown in FIG. 11. The planar patterns and arrangement positions of the VB electrode 46 and the pickup region 96 are not particularly limited.

[0089] 12, an HO electrode 45 is provided on the upper surface of the semiconductor substrate 1 at a position where the high-side circuit 102 is formed, to which an HO potential, which is the potential of the output stage of the high-side circuit 102, is applied. The HO electrode 45 shown in Fig. 12 is not shown in Fig. 11. The planar pattern and arrangement position of the HO electrode 45 are not particularly limited.

[0090] 11 and 12, pads 89a, 89b are provided on the side of the semiconductor chip 100b facing the semiconductor chip 100a. As shown in FIG. 12, the pad 89a on the upper surface of the semiconductor substrate 1b is electrically connected to a level shift resistor R1. The pad 89a is also connected to, for example, a gate electrode (not shown) of a MOSFET in the high-side circuit 102. The level shift resistor R1 is electrically connected to a VB electrode 43. The VB electrode 43 is made of an n-type MOSFET having a higher impurity concentration than the semiconductor substrate 1b. + It is electrically connected to a mold pickup region (contact region) 95. The pickup region 95 shown in Fig. 12 is not shown in Fig. 11. The planar pattern and arrangement position of the pickup region 95 are not particularly limited.

[0091] 11 and 12, a BSD 103 is provided on the upper surface side of the semiconductor substrate 1b. The BSD 103 is provided at a position around the high-side circuit 102 away from the p-type well region 26. The position of the BSD 103 is not limited to this. The BSD 103 is provided on the upper surface side of the semiconductor substrate 1b away from the well region 26. - The cathode region includes an anode region 93 and a part of the semiconductor substrate 1b that is in contact with the anode region 93.

[0092] As shown in FIG. 12, the upper surface of the anode region 93 is provided with a p + A molded pickup region (contact region) 93a is provided. A VCC electrode 47 to which a VCC potential, which is a power supply potential of the low-side circuit 101, is applied is electrically connected to the pickup region 93a. The VCC potential is applied to the anode region 93 via the VCC electrode 47 and the pickup region 93a. The VCC electrode 47 and the pickup region 93a shown in FIG. 12 are not shown in FIG. 11. The planar patterns and arrangement positions of the VCC electrode 47 and the pickup region 93a are not particularly limited. The VCC electrode 47 may be electrically connected to a lead frame to which the VCC potential is applied by a bonding wire or the like.

[0093] As shown in FIG. 12, the upper surface of the semiconductor substrate 1b at a position that will become the cathode region of the BSD 103 is provided with an n-type semiconductor layer having a higher impurity concentration than the semiconductor substrate 1b. + A molded pickup region (contact region) 97 is provided. The pickup region 97 is electrically connected to a VB electrode 47 to which a VB potential, which is the power supply potential of the high-side circuit 102, is applied. The VB potential is applied to the cathode region of the BSD 103 via the VB electrode 48 and the pickup region 97. The VB electrode 48 and the pickup region 97 shown in FIG. 12 are not shown in FIG. 11. The planar patterns and arrangement positions of the VB electrode 48 and the pickup region 97 are not particularly limited. The pickup region 97 may have, for example, a ring-shaped planar pattern surrounding the periphery of the anode region 93.

[0094] As shown in FIG. 12, the semiconductor substrate 1b is mounted on a lead frame 64 to which a VB potential is applied, and is electrically connected to the lead frame 64. The lower surface of the semiconductor substrate 1b is in contact with the lead frame 64. An electrode may be provided on the lower surface of the semiconductor substrate 1b, or the electrode may be in contact with the lead frame 64. The semiconductor substrate 1b may also be provided, via an insulating adhesive or an insulating sheet, on a lead frame to which a potential different from the VB potential is applied. The other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0095] According to the semiconductor device of the second embodiment, the HVICs (100a, 100b) incorporate the BSD 103 of the bootstrap circuits (103, 104), thereby reducing the mounting area. - a semiconductor chip 100a in which a low-side circuit 101 is formed on a semiconductor substrate 1a; -The semiconductor chip 100b is formed on a semiconductor substrate 1b having a high-side circuit 102 and a BSD 103. This eliminates the need for an HVJT to electrically isolate the low-side circuit 101 and the high-side circuit 102, allowing for a reduction in chip size.

[0096] Furthermore, in the semiconductor device according to the second embodiment, the high-side circuit 102 and the BSD 103 are - By providing the BSD 103 on the semiconductor substrate 1b, a vertical parasitic pnp bipolar transistor having the anode region 93 of the BSD 103 as an emitter is not formed, and the operation of the vertical parasitic pnp bipolar transistor can be suppressed.

[0097] Furthermore, according to the semiconductor device of the second embodiment, the anode region 93 can be spaced a distance D2 from the well region 92 at the VS potential, which can serve as the collector of a parasitic pnp bipolar transistor having the anode region 93 of the BSD 103 as its emitter, thereby improving the degree of freedom in design.

[0098] Furthermore, in the semiconductor device according to the second embodiment, the BSD 103 is provided at a position around the high-side circuit 102 that is away from the p-type well region 92. This makes it possible to suppress the operation of a parasitic pnp bipolar transistor that uses the anode region 93 as the emitter, the semiconductor substrate 1b as the base, and the well region 92 as the collector.

[0099] (Other embodiments) As described above, the present disclosure has been described by the first and second embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0100] For example, the semiconductor device according to the first and second embodiments has been exemplified as having a configuration including a low-side circuit 101, a high-side circuit 102, and a BSD 103 for one phase, but is not limited to this and may have a configuration including, for example, a low-side circuit, a high-side circuit, and a BSD for three phases.

[0101] When the semiconductor device according to the first embodiment is for three phases, three semiconductor chips each having a low-side circuit, a high-side circuit, and a BSD for one phase formed thereon may be used. When the semiconductor device according to the second embodiment is for three phases, three sets of one semiconductor chip each having a low-side circuit for one phase formed thereon and one semiconductor chip each having a high-side circuit and a BSD for one phase formed thereon may be used. Alternatively, one semiconductor chip each having low-side circuits for three phases formed thereon collectively and three semiconductor chips each having high-side circuits and a BSD for one phase formed thereon may be used.

[0102] Furthermore, the configurations disclosed in the first and second embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0103] 1, 1a, 1b, 1x...Semiconductor substrate (semiconductor chip) 10a, 10b...Level shifter 11...Diffusion region 11a, 11b... Carrier receiving region (drain region) 12a, 12b...Pickup area (contact area) 13a, 13b... Carrier supply region (source region) 14a, 14b...Pickup area (contact area) 16...Pickup area 21, 22...Well area 21a, 22a...Pickup area (contact area) 23...Voltage range 26...Well area 26a...Pickup area (contact area) 27...Anode region 27a, 28, 29...Pickup area (contact area) 41...VCC electrode 42...GND electrode 44…VS electrode 45...HO electrode 46…VB electrode 47...VCC electrode (anode electrode) 48...VB electrode (cathode electrode) 50, 53...Insulating film 51...Gate insulating film 52...Gate electrode 54...Field Plate 55...Source electrode 56...Drain electrode 57…VB electrode 61~64...Lead frame 71~73...Well area 80a, 80b...Level shifter 81a, 81b...base region 82a, 82b...Pickup area (contact area) 83a, 83b... Carrier supply region (source region) 84a, 84b...gate electrodes 85a, 85b...Drift region 86a, 86b... Carrier receiving regions (drain regions) 87a, 87b...Drain electrodes 88a, 88b...Bonding wire 89a, 89b...Pad 91, 92...Well area 91a, 92a...Pickup area (contact area) 93...Anode region 93a, 94 to 97...Pickup area (contact area) 100...High voltage integrated circuit (HVIC) 100a, 100b...Semiconductor chip 101...Low-side circuit (low-side circuit area) 102...High-side circuit (high-side circuit area) 103...Bootstrap diode (BSD) 104...Bootstrap capacitor (BSC) 105...Connection point 106...Power supply (low potential side power supply) 200...Power conversion section D0, D1, D2...Diodes IN...Input signal R1, R2...Level shift resistors T1, T2...Level shift element (level shifter) T3: High potential side switching element T4: Low-potential side switching element

Claims

1. an n-type first semiconductor substrate; a high-side circuit including a p-type first well region provided on an upper surface side of the first semiconductor substrate; a bootstrap diode including a p-type anode region provided on an upper surface side of the first semiconductor substrate and spaced apart from the first well region; A semiconductor device comprising:

2. a low-side circuit including a p-type second well region provided on the upper surface side of the first semiconductor substrate and spaced apart from the first well region and the anode region, and an n-type third well region provided on the upper surface side of the second well region. The semiconductor device according to claim 1 .

3. The first semiconductor substrate is electrically connected to a lead frame to which a power supply potential of the high-side circuit is applied.

3. The semiconductor device according to claim 1.

4. The bootstrap diode is disposed at a position sandwiching the high-side circuit between itself and the low-side circuit. The semiconductor device according to claim 2 .

5. The bootstrap diode is provided at a position around the high-side circuit away from the first well region.

3. The semiconductor device according to claim 1.

6. a level shifter provided on the first semiconductor substrate for transmitting signals between the low-side circuit and the high-side circuit; 3. The semiconductor device according to claim 1.

7. a p-type breakdown voltage region provided in contact with the second well region and having a lower impurity concentration than the second well region; 3. The semiconductor device according to claim 1.

8. a p-type second semiconductor substrate; a low-side circuit including an n-type fourth well region provided on an upper surface side of the second semiconductor substrate; Further provided with The low-side circuit is connected to the high-side circuit by a wire. The semiconductor device according to claim 1 .

9. the first semiconductor substrate is electrically connected to a lead frame to which a power supply potential of the high-side circuit is applied; The second semiconductor substrate is electrically connected to a lead frame to which a reference potential of the low-side circuit is applied. The semiconductor device according to claim 8 .

10. The second semiconductor substrate further includes a level shifter for transmitting signals between the low-side circuit and the high-side circuit.

10. The semiconductor device according to claim 8.

11. The anode side of the bootstrap diode is connected to the reference potential of the low-side circuit, and the cathode side of the bootstrap diode is connected to the power supply potential of the high-side circuit.

9. The semiconductor device according to claim 2 or 8.

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