Wiring board and method of manufacturing wiring board

Abstract

To provide a wiring board in which a conductor layer and an insulating layer are adhered well.SOLUTION: The wiring substrate of the embodiment includes a first insulating layer 111, a first conductor layer 121 formed on the first insulating layer 111, and a second insulating layer formed on the first insulating layer 111 and on the first conductor layer 121. The first conductor layer 121 includes a wiring having a minimum value of a wiring width of 3 μm or less and a minimum value of a wiring interval of 3 μm or less, the mesh-like irregularities (RP) are formed on the side surface of the first conductor layer 121, and the mesh-like irregularities (RP) are not formed on the upper surface of the first conductor layer 121.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a printed wiring board in which a conductor circuit is formed on a resin insulating layer. The surface of the conductor circuit is roughened with a chemical solution, and a resin insulating layer is further formed on the conductor circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-252622 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the surfaces (side and top surfaces) of the conductor circuit are roughened by etching with a chemical solution. It is thought that there are cases where it is difficult to achieve the desired wiring thickness for the wiring included in the conductor circuit. [Means for solving the problem]

[0005] The wiring board of the present invention includes a first insulating layer, a first conductor layer formed on the first insulating layer, and a second insulating layer formed on the first insulating layer and the first conductor layer. The first conductor layer includes wiring with a minimum wiring width of 3 μm or less and a minimum wiring spacing of 3 μm or less, and a mesh-like unevenness is formed on the side surface of the first conductor layer, while the mesh-like unevenness is not formed on the top surface of the first conductor layer.

[0006] The method for manufacturing a wiring board of the present invention includes forming a metal film layer on a first insulating layer, forming a resist layer having an opening on the metal film layer, and forming a plating film layer on the metal film layer within the opening. Forming the resist layer includes exposing the resist layer by direct imaging exposure to form the opening having a mesh-like unevenness on its sidewall, and forming the plating film layer includes forming an uneven shape on the side surface of the plating film layer that is patterned after the mesh-like unevenness.

[0007] According to an embodiment of the present invention, a wiring board is provided that includes wiring formed to a desired thickness because a mesh-like irregularity is formed on the side surface of the first conductor layer, thereby ensuring good adhesion between the first conductor layer and the second insulating layer, and because a mesh-like irregularity is not formed on the top surface of the first conductor layer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2] An enlarged view of region II in Figure 1. [Figure 3] FIG. 2 is a perspective view illustrating a conductor layer included in the wiring board according to the embodiment. [Figure 4] FIG. 2 is a side view illustrating a conductor layer included in the wiring board according to the embodiment. [Figure 5A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5B] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5C] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5D] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5E] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5F] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the wiring board shown in FIG. [Figure 5G]2 is a perspective view showing a resist layer in the method for manufacturing the wiring board shown in FIG. 1. [Figure 5H] 2 is a side view showing a resist layer in the method for manufacturing the wiring board shown in FIG. 1. [Figure 5I] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5J] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5K] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5L] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5M] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5N] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. [Figure 5O] 2A to 2C are diagrams illustrating an example of a method for manufacturing the wiring board shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Next, a wiring board according to an embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 1, which is an example of a wiring board according to an embodiment. Note that the wiring board 1 shown is merely an example. The layered structure of the wiring board according to the embodiment and the number of conductor layers and insulating layers are not limited to the layered structure of the wiring board 1 shown in FIG. 1 and the number of conductor layers and insulating layers included in the wiring board 1. Furthermore, the drawings referred to are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0010] The wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite the first surface 1F) that are perpendicular to its thickness direction. The wiring board 1 has insulating layers 11 and conductor layers 12 that are alternately stacked. The conductor layers 12 that face each other across one insulating layer 11 are connected by via conductors 13. In the illustrated example, the conductor layer 12 that constitutes a part of the first surface 1F is formed in a pattern having a plurality of conductor pads 12fp. The conductor layer 12 that constitutes a part of the second surface 1B is formed in a pattern having a plurality of conductor pads 12bp.

[0011] 1, the first surface 1F side of the wiring board 1 will be referred to as the "top" or "upper side," and the second surface 1B side of the wiring board 1 will be referred to as the "bottom" or "lower side." In addition, for each component, the surface facing the first surface 1F side of the wiring board 1 will also be referred to as the "top surface," and the surface facing the second surface 1B side of the wiring board 1 will also be referred to as the "bottom surface."

[0012] The insulating layer 11 may be formed using an insulating resin such as an epoxy resin or a phenolic resin, or may include any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI).

[0013] Examples of conductors constituting the conductor layer 12 and the via conductors 13 include copper and nickel, and copper is preferably used. The conductor layer 12 and the via conductors 13 have a multilayer structure. The conductor layer 12 and the via conductors 13 have a two-layer structure including a metal film layer 12a, which is preferably a copper sputtering film layer or an electroless copper plating film layer, and a plating film layer 12b, which is preferably an electrolytic copper plating film layer.

[0014] Via conductors 13 that penetrate insulating layer 11 in the thickness direction are formed by filling through holes 11a that penetrate insulating layer 11 with a conductor. In the example of Fig. 1, via conductors 13 are formed integrally with conductor layer 12 provided thereon. Therefore, via conductors 13 and conductor layer 12 can be formed from the same metal film layer and plating film layer.

[0015] In the example of FIG. 1, the wiring board 1 includes a solder resist layer Lf formed on the uppermost insulating layer 11 and conductor layer 12, and a solder resist layer Lb formed below the lowermost insulating layer 11 and conductor layer 12. The solder resist layers Lf and Lb are formed using, for example, photosensitive polyimide resin or epoxy resin. An opening Lfa is formed in the solder resist layer Lf, and a conductor pad 12fp is exposed from the opening Lfa. An opening Lba is formed in the solder resist layer Lb, and a conductor pad 12bp is exposed from the opening Lba. That is, the first surface 1F of the wiring board 1 includes the surface of the solder resist layer Lf and the surface of the conductor pad 12fp, and the second surface 1B of the wiring board 1 includes the surface of the solder resist layer Lb and the surface of the conductor pad 12bp.

[0016] The first surface 1F of the wiring board 1 constitutes a component mounting surface to which external electronic components can be connected on the wiring board 1. The second surface 1B of the wiring board 1 opposite to the component mounting surface can be a connection surface to be connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (for example, a motherboard of any electrical device).

[0017] The conductor layers 12 included in the wiring board 1 are patterned to have a predetermined conductor pattern. The conductor layers 12 include relatively fine wiring and have relatively high-density circuit wiring. Specifically, the conductor layers 12 of the wiring board 1 have wiring FW, which is high-density wiring with a relatively small wiring width and distance between wirings (wiring spacing). The minimum wiring width of the wiring FW is 3 μm or less, and the minimum wiring spacing is 3 μm or less. In the illustrated example, of the multiple conductor layers 12 included in the wiring board 1, four conductor layers 12 have wiring FW, which is high-density wiring. In the wiring board 1, any number of conductor layers 12 may have wiring FW. The number of conductor layers 12 that the wiring board 1 has with wiring FW is not limited.

[0018] When the conductor layer 12 is formed to include the wiring FW as described above, it may be preferable that the via conductors 13 connecting the opposing conductor layers 12 with the insulating layer 11 interposed therebetween are also formed at a fine pitch. Small-diameter through holes 11a for the via conductors 13 may be formed in the insulating layer 11. Therefore, although the insulating layer 11 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite, it may be preferable that the insulating layer 11 does not contain an inorganic filler so that small-diameter through holes 11a can be easily formed. It is also preferable that the insulating layer 11 does not contain a core material (reinforcement material) made of glass fiber, aramid fiber, or the like. In the wiring board 1, the thickness of the insulating layer 11 is, for example, 3 μm to 15 μm, and the thickness of the conductor layer 12 is 5 μm or less.

[0019] Next, the configuration of the conductor layer 12 included in the wiring board 1 will be described in detail with reference to Figures 2 to 4. In the description with reference to Figures 2 to 4, for ease of explanation, the lowest insulating layer among the insulating layers shown in Figure 2 will be referred to as the first insulating layer 111, and the conductor layer formed in contact with the upper surface of the first insulating layer 111 will be referred to as the first conductor layer 121. Furthermore, the insulating layer formed on the first insulating layer 111 exposed from the first conductor layer 121 and the conductor pattern of the first conductor layer 121 will be referred to as the second insulating layer 112, and the conductor layer formed in contact with the upper surface of the second insulating layer 112 will be referred to as the second conductor layer 122.

[0020] FIG. 2 shows an enlarged view of region II surrounded by a dashed line in FIG. 1. As shown in the figure, a concave-convex Wrp is formed on the side surface of the conductor pattern of the first conductor layer 121, including the wiring FW. As will be described in detail later in the description of the manufacturing method for a wiring board, the concave-convex Wrp is formed by imprinting the concave-convex shape formed on the side wall of the opening of the plating resist layer on the side surface of the plating film layer 12b during the formation of the plating film layer 12b. Therefore, the concave-convex Wrp is formed on the portion of the first conductor layer 121 that is made up of the plating film layer 12b, but is not formed on the portion that is made up of the metal film layer 12a. Furthermore, the concave-convex Wrp is not formed on the upper surface of the first conductor layer 121. Note that "imprinted" here means that an inverted shape of the concave-convex is formed on the target object (here, the plating film layer 12b).

[0021] It is believed that the formation of the uneven Wrp on the side surface of the first conductor layer 121 allows the second insulating layer 112 covering the first conductor layer 121 to adhere firmly to the side surface of the first conductor layer 121. The upper surface of the first conductor layer 121, on which the uneven Wrp is not formed, has good flatness, and therefore it is believed that the relatively fine wiring FW can be formed to a thickness that is closer to the design value. In addition, the upper surface of the second insulating layer 112 located directly above the upper surface of the first conductor layer 121 can also be formed as a surface that has good flatness. Therefore, it is believed that the conductor pattern of the second conductor layer 122 formed in contact with the upper surface of the second insulating layer 112 can also be formed to dimensions that are closer to the design value.

[0022] Next, the unevenness Wrp formed on the side surface of the first conductor layer 121 will be described in detail with reference to Figures 3 and 4. Figure 3 shows a perspective view of the first conductor layer 121 as seen from the line of sight along arrow III in Figure 2. Figure 4 shows the side surface of the first conductor layer 121 as seen from the line of sight along arrow IV perpendicular to the side surface of the first conductor layer 121 in Figure 2. Note that Figures 3 and 4 are drawn without the second insulating layer 112 covering the first conductor layer 121.

[0023] As shown in Figures 3 and 4, the irregularities Wrp formed on the side surface of the first conductor layer 121 have a mesh-like configuration. Specifically, the irregularities Wrp are formed as a mesh-like irregularity including a plurality of protrusions Wp and recesses Wr that are the boundaries between the plurality of protrusions Wp. Here, "mesh-like" refers to a pattern consisting of cells that correspond to the openings of the mesh and the boundaries between the cells that correspond to the strings (strands) of the mesh. In other words, the irregularities Wrp include a plurality of protrusions Wp that correspond to the plurality of cells of the mesh and recesses Wr that correspond to the boundaries between the cells of the mesh.

[0024] As shown in Figure 4, in the mesh-like irregularities Wrp formed on the side surface of the first conductor layer 121, the plurality of protrusions Wp corresponding to the cells of the mesh have different planar shapes (shapes recognized in the field of view of Figure 4) and planar areas (areas recognized in the field of view of Figure 4). Furthermore, the groove-shaped recesses Wr formed corresponding to the boundaries between the cells of the mesh are not limited to a specific direction in extension, but extend in irregular directions according to the planar shapes of the protrusions Wp. It is believed that the fact that the recesses Wr extend in multiple different directions can further strengthen the adhesion between the first conductor layer 121 and the second insulating layer 112 (see Figure 2).

[0025] Specifically, in the mesh-like irregularities Wrp formed on the side surface of the first conductor layer 121, the maximum value of the plane area of ​​the protrusions Wp corresponding to the mesh cells is 0.1 μm 2 It is preferable that the number of protrusions Wp per unit area on the side surface of the first conductor layer 121 is equal to or greater than the desired number. Therefore, it is believed that stronger adhesion between the first conductor layer 121 and the second insulating layer 112 (see FIG. 2) can be achieved.

[0026] The mesh-like unevenness Wrp is preferably formed so that the shortest distance in the direction perpendicular to the side surface of the first conductor layer 121 between the highest point (the point that protrudes most vertically relative to the side surface of the first conductor layer 121) of the multiple protrusions Wp constituting the unevenness Wrp and the deepest point of the recess Wr (the point that is most depressed vertically relative to the side surface of the first conductor layer 121) is 0.3 μm or more and 1.0 μm or less. By keeping the distance between the highest point of the protrusion Wp and the deepest point of the recess Wr within this range, it is believed that the width dimension of the conductor pattern of the first conductor layer 121 can be made faithful to the designed dimension, and good adhesion can be achieved between the first conductor layer 121 and the second insulating layer 112 (see FIG. 2).

[0027] In the wiring board of the embodiment, it is sufficient that any of the conductor layers 12 constituting the wiring board, including the wiring FW, has mesh-like irregularities. Also, mesh-like irregularities may be formed on all side surfaces of the conductor layers included in the wiring board.

[0028] Next, with reference to FIGS. 5A to 5O, a method for manufacturing a wiring board according to one embodiment will be described, taking the case of manufacturing the wiring board 1 shown in FIG. 1 as an example. Each component formed in the manufacturing method described below may be formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in FIG. 1, unless otherwise specified. In the following description of the method for manufacturing the wiring board 1, the side closer to the core material GS constituting the support substrate SP will be referred to as the "bottom" or "lower side," and the side farther from the support substrate SP will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting the wiring board 1 that faces the support substrate SP will be referred to as the "lower surface," and the surface facing away from the support substrate SP will also be referred to as the "upper surface." Furthermore, in describing the manufacturing method, as with the description of the wiring board with reference to Figures 2 to 4, for ease of explanation, the insulating layer closest to the support substrate SP will be referred to as the first insulating layer 111, the conductor layer formed in contact with the first insulating layer 111 will be referred to as the first conductor layer 121, the insulating layer formed in contact with the first conductor layer 121 will be referred to as the second insulating layer 112, and the conductor layer formed in contact with the second insulating layer 112 will be referred to as the second conductor layer 122.

[0029] First, as shown in FIG. 5A, a support substrate SP is prepared. In the wiring substrate manufacturing method of this embodiment, the support substrate SP used has excellent flatness on two surfaces perpendicular to its thickness direction. The support substrate SP includes a core material GS, such as a glass substrate, a first metal film layer ML1 laminated on both surfaces of the core material GS, and a second metal film layer ML2 laminated on the first metal film layer ML1 via an adhesive layer AL. The first and second metal film layers ML1 and ML2 are metal film layers formed by, for example, electroless plating or sputtering. Although the first and second metal film layers ML1 and ML2 are depicted as single layers in the illustration, they may include multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure composed of a titanium layer and a copper layer. The adhesive layer AL may include, for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation. The support substrate SP may include a silicon substrate, a metal substrate, or a ceramic substrate as a core material GS in addition to a glass substrate.

[0030] Next, as shown in FIG. 5B, a conductor layer 12 having a plurality of conductor pads 12bp is formed on the support substrate SP. In forming the conductor layer 12 in contact with the support substrate SP, for example, a plating resist is formed on the second metal film layer ML2, and openings corresponding to the formation areas of the pattern of the conductor pads 12bp are formed in the plating resist by, for example, photolithography. Next, a plating film layer is formed in the openings by electrolytic plating using the second metal film layer ML2 as a seed layer. After the plating film layer is formed, the plating resist is removed, resulting in the state shown in FIG. 5B.

[0031] Next, as shown in FIG. 5C, a first insulating layer 111 is laminated to cover the upper and side surfaces of the conductor layer 12 and the surface of the support substrate SP exposed from the conductor pattern of the conductor layer 12. For example, an insulating resin such as epoxy resin or phenol resin can be used as the first insulating layer 111. Fluorine resin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI) may also be used. The first insulating layer 111 is formed by thermocompression bonding these resins formed into a film shape. Next, through holes 11a are formed in the first insulating layer 111 at positions where the via conductors 13 (see FIG. 1) will be formed by irradiating them with, for example, carbon dioxide laser light or excimer laser light.

[0032] Although not shown, the formation of through holes 11a by irradiation with a laser such as a carbon dioxide laser beam can be performed by irradiating the laser while the upper surface of first insulating layer 111 is protected by covering it with a protective film such as a polyethylene terephthalate (PET) film. Through holes 11a are formed that penetrate the protective film and first insulating layer 111. After the formation of through holes 11a, a desmearing process may be performed to prevent a decrease in the adhesion of via conductors 13 and an increase in resistance components due to processing-induced deformation products generated at the bottom of through holes 11a. The desmearing process may preferably be a dry desmearing process using plasma gas. The desmearing process may also be performed while protecting the surface of first insulating layer 111 with a protective film such as a polyethylene terephthalate (PET) film formed on the surface of first insulating layer 111.

[0033] 5C, as well as 5D to 5F and 5I to 5O referred to below, show a laminate formed on one surface of the support substrate SP, and do not show a laminate that may be formed on the opposite surface. However, the opposite surface of the support substrate SP may also have a laminate in the same manner and number, or a different manner and number of conductor layers and insulating layers from those on one surface, or such conductor layers and insulating layers may not be formed.

[0034] 5D, a metal film layer 12a is formed on the inner wall of the through hole 11a and on the surface of the first insulating layer 111 by electroless plating, sputtering, or the like. Preferably, the metal film layer 12a may be a sputtering film formed by sputtering. Note that, if a protective film is provided on the surface of the first insulating layer 111 during the formation of the through hole 11a and / or the desmear treatment, the protective film may be peeled off and removed before the formation of the metal film layer 12a.

[0035] Next, as shown in FIG. 5E, a dry film resist containing, for example, a photosensitive epoxy resin is adhered onto the metal film layer 12a to form a resist layer RL. Subsequently, the resist layer RL is exposed to light. In the wiring board manufacturing method of the embodiment, direct imaging exposure is performed in the step of exposing the resist layer RL. In direct imaging exposure, a photomask is not used, and the resist layer RL is directly irradiated with irradiation light L. A light source for the irradiation light L may be, for example, a semiconductor laser with a wavelength of 350 nm to 410 nm or an ultra-high pressure mercury lamp. The irradiation light L is scanned according to a drawing pattern corresponding to the conductor pattern (see FIG. 1) of the first conductor layer 121 to be formed on the first insulating layer 111. During exposure, the irradiation spot of the irradiation light L is scanned repeatedly multiple times over the portion of the resist layer RL to be exposed. That is, a specific portion of the resist layer RL to be exposed is multiplexedly exposed to the irradiation light L.

[0036] 5F, a resist pattern corresponding to the conductor pattern (see FIG. 1) of the first conductor layer 121 to be formed on the first insulating layer 111 is formed on the resist layer RL. Specifically, after the above-mentioned step of exposing the resist layer RL is completed, the resist layer RL is developed with a developer made of an aqueous sodium carbonate solution that may contain, for example, a surfactant, an antifoaming agent, a small amount of an organic solvent to promote development, and the like, to form openings RLo. The openings RLo corresponding to the wiring FW to be formed on the first insulating layer 111 are formed so that the minimum opening width is 3 μm or less and the minimum spacing between the openings is 3 μm or less.

[0037] In the exposure of the resist layer RL described above with reference to FIG. 5E, when the resist layer RL is irradiated with the irradiation light L, standing waves are generated by the irradiation light L and the light reflected by the metal film layer 12a. The standing waves cause variations in the concentration of the photosensitive material contained in the resist layer RL in the thickness direction of the resist layer RL. In direct imaging exposure, the irradiation light L is repeatedly irradiated and scanned onto a specific location to be exposed. This multiple exposure with the irradiation light L is thought to result in irregular variations in the concentration of the photosensitive material contained in the resist layer RL in the thickness direction and planar direction of the resist layer RL. Therefore, an uneven shape resulting from the irregular variations in the concentration of the photosensitive material is formed on the sidewall (inner wall surface) of the opening RLo formed as a result of the development of the resist layer RL described above with reference to FIG. 5F.

[0038] FIG. 5G shows a perspective view of the resist layer RL as viewed along the arrow G in FIG. 5F. FIG. 5H shows a side view of the sidewall of the opening RLo in the resist layer RL as viewed along the arrow H, which is perpendicular to the sidewall of the opening RLo in FIG. 5F. As shown in FIG. 5G, an irregularity Rrp is formed on the sidewall of the opening RLo in the resist layer RL. Specifically, the irregularity Rrp is formed as a mesh-like irregularity including a plurality of recesses Rr and protrusions Rp that are boundaries between the plurality of recesses Rr. That is, the irregularity Rrp includes a plurality of recesses Rr corresponding to a plurality of cells of the mesh and protrusions Rp that correspond to the boundaries between the cells of the mesh.

[0039] As shown in FIG. 5H, in the mesh-like irregularities Rrp formed on the resist layer RL, the plurality of recesses Rr corresponding to the mesh cells each have a different planar shape (the shape recognized in the field of view of FIG. 5H). In addition, the plurality of recesses Rr corresponding to the mesh cells each have a different planar area (the area recognized in the field of view of FIG. 5H). In the mesh-like irregularities Rrp, the maximum planar area of ​​each recess Rr is 0.1 μm 2The projections Rp corresponding to the boundaries between the cells of the network can be formed as follows. The extension direction of the projections Rp corresponding to the boundaries between the cells of the network is not limited to a particular direction, and the projections Rp extend in irregular directions according to the planar shape of the recesses Rr. The maximum value of the planar area of ​​the recesses Rr in the projections and recesses Rrp can be adjusted by appropriately controlling the exposure conditions, such as the spot diameter, wavelength, and scanning speed of the irradiation light L, in the direct imaging exposure of the resist layer RL using the irradiation light L, as described with reference to FIG. 5E.

[0040] Next, as shown in Fig. 5I, a plating film layer 12b is formed in the opening RLo of the resist layer RL by electrolytic plating using the metal film layer 12a as a power supply layer. The inside of the through hole 11a is completely filled with the plating film 12b, forming the via conductor 13. The plating film layer 12b formed in the opening RLo is shaped in a shape that imitates the mesh-like irregularities Rrp (see Fig. 5G) formed on the side wall of the opening RLo in the portion that contacts the side wall of the opening RLo.

[0041] Next, the resist layer RL is removed using an alkaline stripping solution. Removal of the resist layer RL exposes the side surface of the plating film layer 12b, which has a mesh-like unevenness pattern that replicates the mesh-like unevenness Rrp (see FIG. 5G). After the resist layer RL is removed, the portion of the metal film layer 12a that is not covered by the plating film layer 12b is removed by etching. No mesh-like unevenness is formed on the side surface of the metal film layer 12a exposed by this etching. As shown in FIG. 5J, a first conductor layer 121 is formed, which has a two-layer structure consisting of the metal film layer 12a and the plating film layer 12b.

[0042] Next, as shown in FIG. 5K, a second insulating layer 112 is formed on the first conductor layer 121 and the first insulating layer 111 exposed from the conductor pattern of the first conductor layer 121. Furthermore, a second conductor layer 122 is formed on the second insulating layer 112 using a method similar to that for forming the first insulating layer 111 and the first conductor layer 121. When forming the second insulating layer 112, the uncured second insulating layer 112 penetrates into the recesses of the mesh-like unevenness formed on the side surface of the first conductor layer 121, thereby providing good adhesion between the second insulating layer 112 and the first conductor layer 121. The top surface of the first conductor layer 121, which does not have the mesh-like unevenness, has good flatness, and therefore the top surface of the second insulating layer 112 is also formed to have a relatively good flatness. It is believed that the conductor pattern of the second conductor layer 122 formed in contact with the top surface of the second insulating layer 112 can be formed to dimensions that are closer to the design values.

[0043] 5L, a desired number of insulating layers 11 and conductor layers 12 are stacked on the second conductor layer 122 and the second insulating layer 112 in a manner similar to the method for forming the first insulating layer 111 and the first conductor layer 121. The uppermost conductor layer 12 is formed in a pattern including conductor pads 12fp.

[0044] Next, as shown in FIG. 5M, a solder resist layer Lf is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 11 and the conductor layer 12, and openings Lfa that define the conductor pads 12fp are formed by photolithography.

[0045] In the method for manufacturing a wiring board according to the embodiment, any of the conductor layers including fine wiring may be formed by a method including direct imaging exposure to a resist layer, and openings having a mesh-like unevenness on the sidewalls may be formed. All of the conductor layers constituting the wiring board may be formed by a method including forming openings having a mesh-like unevenness by direct imaging exposure to a resist layer. Therefore, for example, in the illustrated example, the lowermost conductor layer 12 not including wiring FW (the conductor layer 12 in contact with the support substrate SP) may also be formed by a method including forming openings having a mesh-like unevenness by direct imaging exposure. Furthermore, the uppermost conductor layer 12 not including wiring FW may also be formed by a method including forming openings having a mesh-like unevenness by direct imaging exposure to a resist layer.

[0046] Next, as shown in FIG. 5N, the support substrate SP is removed. The lower surface of the second metal film layer ML2 below the conductor pad 12bp is exposed. In removing the support substrate SP, the adhesive layer AL is softened by, for example, irradiating it with laser light, and then the second metal film layer ML2 of the support substrate SP is peeled off.

[0047] Next, the second metal film layer ML2 is removed by etching, exposing the lower surfaces of the conductor pads 12bp and the lower surface of the first insulating layer 111. A solder resist layer Lb is formed on the lower surfaces of the conductor pads 12bp and the lower surface of the first insulating layer 111 by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 11 and the conductor layer 12. An opening Lba that defines the conductor pads 12bp is formed in the solder resist layer Lb by photolithography. This completes the manufacture of the wiring board 1.

[0048] The wiring board of the embodiment is not limited to the structures illustrated in the drawings or the structures and materials illustrated in this specification. For example, the wiring board of the embodiment may have any number of insulating layers and conductor layers. The uppermost and lowermost conductor layers of the wiring board may include conductor patterns in addition to conductor pads.

[0049] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to Figures 5A to 5O, and the conditions, order, and the like may be changed as desired. The method for manufacturing a wiring board according to the embodiment may include at least forming an opening having a mesh-like irregularity on the sidewall in a resist layer on a metal film layer by direct imaging exposure, and forming a plating film layer having an irregularity in which the mesh-like irregularity is molded within the opening. Depending on the structure of the wiring board to be manufactured, some steps may be omitted, or other steps may be added. [Explanation of symbols]

[0050] 1. Wiring board 11 Insulating layer 12 Conductor layer 13 Via conductor 111 First insulating layer 112 Second insulating layer 121 First conductor layer 122 Second conductor layer 12a Metal film layer 12b Plating film layer 1F, 1st floor 1B 2nd side Lf, Lb solder resist layer Wrp, Rrp unevenness Wp, Rp convex part Wr, Rr recess

Claims

1. a first insulating layer; a first conductor layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer and the first conductor layer; A wiring board comprising: the first conductor layer includes wiring having a minimum wiring width of 3 μm or less and a minimum wiring interval of 3 μm or less; A mesh-like irregularity is formed on the side surface of the first conductor layer, and the mesh-like irregularity is not formed on the top surface of the first conductor layer.

2. 2. A wiring board according to claim 1, wherein the first conductor layer includes a metal film layer in contact with the first insulating layer and a plating film layer formed on the metal film layer, and the mesh-like irregularities are formed on the plating film layer and not on the metal film layer.

3. 2. The wiring board according to claim 1, wherein the mesh-like irregularities have protrusions corresponding to the cells of the mesh and recesses corresponding to the boundaries between the cells.

4. 4. The wiring board according to claim 3, wherein the maximum value of the plane area of ​​the cell is 0.1 μm 2 The following is the result.

5. 4. The wiring board according to claim 3, wherein the shortest distance between the deepest part of the recess and the highest part of the protrusion in a direction perpendicular to the side surface is 0.3 [mu]m or more and 1.0 [mu]m or less.

6. 2. The wiring board according to claim 1, wherein a second conductor layer is formed on the second insulating layer.

7. forming a metal film layer on the first insulating layer; forming a resist layer having an opening on the metal film layer; forming a plating film layer on the metal film layer in the opening; A method for manufacturing a wiring substrate, comprising: forming the resist layer includes exposing the resist layer by direct imaging exposure to form the openings having mesh-like irregularities on their sidewalls; Forming the plating film layer includes forming an uneven shape on the side surface of the plating film layer by imitating the mesh-like unevenness.

8. 8. The method for manufacturing a wiring board according to claim 7, wherein the mesh-like irregularities have a maximum plane area of ​​0.1 μm 2 It is formed as follows:

9. 8. A method for manufacturing a wiring board according to claim 7, wherein forming the openings includes forming openings having a minimum opening width of 3 μm or less and a minimum spacing between the openings of 3 μm or less.

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