Semiconductor device and multi-channel DC / DC converter

Abstract

To suppress malfunction due to an IR drop caused by an increase in instantaneous current consumption.SOLUTION: A semiconductor memory device (10, 10A, 10B) includes a first oscillation circuit (41) configured to output a first clock signal (CLK1), a second oscillation circuit (42) configured to output a second clock signal (CLK1) different from the first clock signal (CLK2), and a logic circuit (43, CLK1, CLK2) configured to be coupled to the first oscillation circuit (43A) and the second oscillation circuit (). 43B. Logic circuits (43, 43A, 43B) control the second oscillation circuit (42) so as to generate second clock signals (CLK1) whose edges are prevented from overlapping the edges of the first clock signals (CLK2).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a multi-channel DC / DC converter. [Background technology]

[0002] Conventionally, a semiconductor device that uses a plurality of clock signals has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-116126 A

[0004] [overview] In such semiconductor devices, an increase in instantaneous current consumption can cause an IR drop, resulting in circuit malfunction, and there is an increasing demand for semiconductor devices that can suppress such malfunctions.

[0005] According to an aspect of the present disclosure, there is provided a semiconductor device including: a first oscillator circuit configured to output a first clock signal; a second oscillator circuit configured to output a second clock signal different from the first clock signal; and a logic circuit configured to connect the first oscillator circuit and the second oscillator circuit. The logic circuit may be configured to oscillate the second clock signal such that an edge of the second clock signal does not overlap with that of the first clock signal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a schematic configuration of an example of a multi-channel DC / DC converter. [Figure 2] FIG. 2 is a timing chart showing the states of the signals of the semiconductor device. [Figure 3] FIG. 3 is a schematic circuit diagram of a semiconductor device according to a first modification. [Figure 4]FIG. 4 is a timing chart showing the states of the signals in the logic circuit of the first modified example. [Figure 5] FIG. 5 is a schematic circuit diagram of a semiconductor device according to a second modification.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. A MOS field effect transistor may also be simply referred to as a MOS transistor. A P-channel MOS transistor will be referred to as a PMOS transistor, and an N-channel MOS transistor will be referred to as an NMOS transistor.

[0008] When referring to multiple parts that form a circuit, such as any elements or lines, the term "connection" includes mechanical connection as well as electrical connection, i.e., a state in which electricity flows. In other words, "connect" includes "electrical connection."

[0009] <Multi-channel DC / DC converter 100> Fig. 1 is a circuit diagram showing a schematic configuration of an example of a multi-channel DC / DC converter 100. Fig. 2 is a timing chart showing the states of each signal of the semiconductor device 10. The multi-channel DC / DC converter 100 has the semiconductor device 10 and a plurality of output units 20. In the multi-channel DC / DC converter 100, each output unit 20 is driven, and an output voltage and an output current are output from each output unit 20.

[0010] At least a portion of the output voltages and output currents output from the output units 20 may be combined and output to the outside of the multi-channel DC / DC converter 100, or each may be output independently to the outside of the multi-channel DC / DC converter 100. The multi-channel DC / DC converter 100 has four channels, and the portions corresponding to each channel are indicated with a subscript as necessary. For example, the output units 20 of each channel may be indicated as a first output unit 20_1, a second output unit 20_2, a third output unit 20_3, and a fourth output unit 20_4. In the multi-channel DC / DC converter 100 shown in FIG. 1 , only the specific configuration of the first output unit 20_1 is shown, and the specific configurations of the remaining second output unit 20_2, third output unit 20_3, and fourth output unit 20_4 are omitted because they are identical to that of the first output unit 20_1.

[0011] <Output unit 20> As shown in FIG. 1, the output section 20 includes a driver circuit 21, a bridge circuit 22, and a smoothing circuit .

[0012] <Bridge circuit 22> The bridge circuit 22 has a high-side switching element 221 and a low-side switching element 222. The high-side switching element 221 and the low-side switching element 222 are connected in series. The high-side switching element 221 and the low-side switching element 222 are NMOS transistors.

[0013] The source of the high-side switching element 221 and the drain of the low-side switching element 222 are connected. The drain of the high-side switching element 221 is connected to the input voltage. In each switching output section, the source of the low-side switching element 222 is connected to the ground voltage. The switching voltage generated at the connection point between the high-side switching element 221 and the low-side switching element 222 is the output of the bridge circuit 22.

[0014] <Driver circuit 21> The driver circuit 21 outputs a high-side drive signal to the high-side switching element 221 and a low-side drive signal to the low-side switching element 222. The high-side switching element 221 and the low-side switching element 222 are controlled based on the high-side drive signal and the low-side drive signal so that both are in the OFF state or one is in the ON state and the other is in the OFF state. Note that the high-side switching element 221 and the low-side switching element 222 are controlled so that both are not in the ON state.

[0015] That is, the high-side drive signal and low-side drive signal output from the driver circuit 21 are signals that are at high level or low level. When one of the high-side drive signal and low-side drive signal is at high level, the other is at low level. Also, a period in which both the high-side drive signal and the low-side drive signal are at low level may be included.

[0016] The smoothing circuit 23 has an inductor 231 and a smoothing capacitor 232. A first end of the inductor 231 is connected to a connection point between the high-side switching element 221 and the low-side switching element 222 of the bridge circuit 22. A second end of the inductor 231 is connected to a first end of the smoothing capacitor 232. A second end of the smoothing capacitor 232 is connected to a ground voltage. The connection point between the inductor 231 and the smoothing capacitor 232 is connected to the outside, and the output voltage and output current are output to the outside.

[0017] When the output voltages and output currents of a plurality of output sections 20 are combined and output, the inductors 231 of the combined channels may be connected to a common smoothing capacitor and output to the outside.

[0018] A control signal CNT from a control circuit 30 (described later) and an output clock signal CLKB from a digital PLL (Phase Locked Loop) circuit 44 (described later) are input to the driver circuit 21. The driver circuit 21 selects an output unit 20 that outputs an output voltage and an output current based on the control signal CNT and the output clock signal CLKB. The driver circuit 21 then outputs a high-side operating signal and a low-side driving signal that operate a high-side switching element 221 and a low-side switching element 222 of the selected output unit 20.

[0019] In the bridge circuit 22, the high-side switching element 221 and the low-side switching element 222 are both NMOS transistors, but the high-side switching element 221 may be a PMOS transistor.

[0020] <Semiconductor device 10> The semiconductor device 10 is, for example, a functional integrated circuit (IC) integrated on a single semiconductor substrate. The semiconductor device 10 includes a control circuit 30 and a clock generation circuit 40.

[0021] <Control circuit 30> The control circuit 30 generates a control signal CNT that controls the operation of the output unit 20 and outputs it to the output unit 20. An input signal SIN is input to the control circuit 30 from an external device. The input signal SIN includes information such as the channel of the output unit 20 to be driven, the output voltage, and the output current. Based on the input signal SIN, the control circuit 30 generates a control signal CNT that includes information on the channel (output unit 20) to be selected and the on-duty value of the high-side switching element 221 of the bridge circuit 22 of the selected output unit 20. The control circuit 30 then outputs the control signal CNT to the selected output unit 20.

[0022] The control circuit 30 outputs an enable signal EN to the clock generation circuit 40 based on the input of the input signal SIN. The enable signal EN is a signal that takes a high level or a low level. The enable signal EN controls whether the clock generation circuit 40 starts or stops operating. For example, the clock generation circuit 40 may be configured to operate when the enable signal EN is at a high level and to stop when the enable signal EN is at a low level. The combination of the enable signal EN and the operation of the clock generation circuit 40 is not limited to this.

[0023] <Clock generation circuit 40> The clock generation circuit 40 generates a clock signal. The semiconductor device 10 and the output unit 20 operate based on the clock signal generated by the clock generation circuit 40. The clock generation circuit 40 includes a first oscillation circuit 41, a second oscillation circuit 42, a logic circuit 43, a digital PLL circuit 44, and a reference oscillation circuit 45.

[0024] <First Oscillator Circuit 41, Second Oscillator Circuit 42, and Reference Oscillator Circuit 45> The first oscillation circuit 41, the second oscillation circuit 42, and the reference oscillation circuit 45 are all connected to the logic circuit 43. The first oscillation circuit 41 is configured to generate a first clock signal CLK1. The first clock signal CLK1 generated by the first oscillation circuit 41 is input to the logic circuit 43.

[0025] The second oscillation circuit 42 is configured to generate a second clock signal CLK2. The second clock signal CLK2 generated by the second oscillation circuit 42 is input to the logic circuit 43. Furthermore, the reference oscillation circuit 45 is configured to generate a reference clock signal CLKR. The reference clock signal CLKR generated by the reference oscillation circuit 45 is input to the logic circuit 43.

[0026] 2, the first clock signal CLK1, the second clock signal CLK2, the reference clock signal CLKR, the output clock signal CLKB (described later), and the PLL clock signal CLKP (described later) are all square-wave signals. Each signal is either high or low, and the portion where it rises to high level and the portion where it falls to low level are called an edge portion. The reference clock signal CLKR is synchronized with the first clock signal CLK1, and the frequency of the reference clock signal CLKR is k times that of the first clock signal CLK1 (k is an integer equal to or greater than 2). In the semiconductor device 10, k is set to 2, but this is not limiting.

[0027] In the semiconductor device 10, internal circuits of the semiconductor device 10, such as the control circuit 30, operate based on a first clock signal CLK1. A second clock signal CLK2 is input to the digital PLL circuit 44 and is used as a reference when generating an output clock signal CLKB that serves as a reference for each output unit 20. A reference clock signal CLKR is used to generate the second clock signal CLK2.

[0028] The first oscillator circuit 41 and the reference oscillator circuit 45 are configured so that the first clock signal CLK1 and the reference clock signal CLKR are synchronized signals.

[0029] <Logic Circuit 43> The logic circuit 43 is connected to a first oscillation circuit 41, a second oscillation circuit 42, and a reference oscillation circuit 45. The logic circuit 43 has a clock signal adjustment unit 431. To the clock signal adjustment unit 431, a first clock signal CLK1 is output from the first oscillation circuit 41 and a reference clock signal CLKR is output from the reference oscillation circuit 45. The clock signal adjustment unit 431 is configured to operate based on the first clock signal CLK1.

[0030] The clock signal adjuster 431 is also connected to the second oscillation circuit 42. The clock signal adjuster 431 outputs an enable signal SEN for starting the operation of the second oscillation circuit 42 based on the first clock signal CLK1 and the reference clock signal CLKR.

[0031] The clock signal adjusting unit 431 outputs an enable signal SEN corresponding to the reference clock signal CLKR to the second oscillation circuit 42. The second oscillation circuit 42 outputs a second clock signal CLK2 to the logic circuit 43 in synchronization with the enable signal SEN. The logic circuit 43 outputs the second clock signal CLK2 to the digital PLL circuit 44. Therefore, the second oscillation circuit 42 may be configured to output the second clock signal CLK2 directly to the digital PLL circuit 44.

[0032] 2, the first clock signal CLK1 and the second clock signal CLK2 are signals with the same frequency. The reference clock signal CLKR is a signal with twice the frequency of the first clock signal CLK1, so that the first clock signal CLK1 rises and falls twice during the period from when it rises to when it falls.

[0033] The reference clock signal CLKR is synchronized with the first clock signal CLK1. Therefore, one of the two rising edges of the reference clock signal CLKR coincides with the rising edge of the first clock signal CLK1. On the other hand, the falling edge of the reference clock signal CLKR does not coincide with either the rising edge or the falling edge of the first clock signal CLK1.

[0034] Taking advantage of this, the clock signal adjuster 431 outputs the enable signal SEN so that the rising and falling edges of the second clock signal CLK2 coincide with the falling edges of the reference clock signal CLKR. The second oscillator circuit 42 then outputs the second clock signal CLK2 upon receiving the enable signal SEN. In this way, the second clock signal CLK2 can be made not to be synchronized with the first clock signal CLK1.

[0035] <Digital PLL circuit 44> A second clock signal CLK2 is input to the digital PLL circuit 44. Using the second clock signal CLK2 as a reference, the digital PLL circuit 44 generates a PLL clock signal CLKP having a frequency m times (m is an integer equal to or greater than 2, and is assumed to be 8 in this example) that of the second clock signal CLK2 (see FIG. 2). The PLL clock signal CLKP is shifted in phase with the second clock signal CLK2 by ¼ of the period of the PLL clock signal CLKP. This prevents the timing of the edges of the PLL clock signal CLKP from overlapping with the timing of the edges of both the first clock signal CLK1 and the second clock signal CLK2.

[0036] Then, based on the PLL clock signal CLKP, output clock signals CLKB are generated and output to the output sections 20, with the phase difference shifted from each other so that the timing of the switching operations of the output sections 20 do not overlap.

[0037] The digital PLL circuit 44 is connected to the control circuit 30. The control circuit 30 outputs information about the output units 20 to be driven to the digital PLL circuit 44. The digital PLL circuit 44 outputs an output clock signal CLKB to the output units 20 to be driven. For example, when all four output units 20 are driven, the digital PLL circuit 44 outputs output clock signals CLKB_1, CLKB_2, CLKB_3, and CLKB_4. At this time, the output clock signals CLKB_1, CLKB_2, CLKB_3, and CLKB_4 are generated so that the timing of their edges does not overlap with the timing of the edges of the other output clock signals (see FIG. 2).

[0038] The semiconductor device 10 outputs a control signal CNT from the control circuit 30 and an output clock signal CLKB from the clock generation circuit 40 to each of the output sections 20 to be driven.

[0039] That is, when the output unit 20_1 is selected, a control signal CNT_1 and an output clock signal CLKB_1 are input to the output unit 20_1 from the semiconductor device 10. When the output unit 20_2 is selected, a control signal CNT_2 and an output clock signal CLKB_2 are input to the output unit 20_2 from the semiconductor device 10. When the output unit 20_3 is selected, a control signal CNT_3 and an output clock signal CLKB_3 are input to the output unit 20_3 from the semiconductor device 10. When the output unit 20_4 is selected, a control signal CNT_4 and an output clock signal CLKB_4 are input to the output unit 20_4 from the semiconductor device 10.

[0040] The logic circuit 43 has a circuit portion that operates based on the first clock signal CLK1 and a circuit portion that operates based on the second clock signal CLK2. These circuits use complementary metal-oxide semiconductor (CMOS), which can cause a short-circuit current to flow when the circuits are driven. If the short-circuit currents flow at the same time, the instantaneous current consumption increases, causing a load current to flow to the power supply and ground, resulting in an IR drop. This can result in a voltage drop in the power supply voltage and a voltage rise in the ground voltage, which can cause the voltage applied to the circuit to become insufficient and lead to circuit malfunction.

[0041] In the semiconductor device 10 of the present disclosure, the timing of the edge of the first clock signal CLK1 does not overlap with the timing of the edge of the second clock signal CLK2. This allows the timing of the increase in the instantaneous current consumption value of the circuit based on the first clock signal CLK1 to be shifted from the timing of the increase in the instantaneous current consumption value of the circuit based on the second clock signal CLK2, thereby reducing the IR drop. As a result, malfunction of the circuit is suppressed.

[0042] <First Modification> A semiconductor device 10A of a first modified example will be described with reference to the drawings. FIG. 3 is a schematic circuit diagram of the semiconductor device 10A of the first modified example. The semiconductor device 10A shown in FIG. 3 differs from the semiconductor device 10 in that the configuration of the clock signal adjuster 431A of the logic circuit 43A of the clock generation circuit 40A is different from the clock signal adjuster 431 and that the semiconductor device 10A does not have a reference oscillation circuit 45. Other than this, the semiconductor device 10A has the same configuration as the semiconductor device 10. Therefore, parts of the semiconductor device 10A that are substantially the same as those of the semiconductor device 10 are given the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0043] 3, the clock signal adjusting unit 431A of the logic circuit 43A of the semiconductor device 10A has a flip-flop 432 and a buffer 433. A first clock signal CLK1 is input to a set terminal of the flip-flop 432. A second clock signal CLK2 is input to a reset terminal of the flip-flop 432. An output terminal of the flip-flop 432 is connected to the buffer 433. The buffer 433 is a delay circuit that outputs a signal that is delayed by a predetermined time from an input signal.

[0044] Next, the operation of the logic circuit 43A will be described with reference to the drawings. Fig. 4 is a timing chart showing the states of each signal in the logic circuit 43A of the first modified example. As shown in Fig. 4, at time T1, the first oscillation circuit 41 switches the first clock signal CLK1 output at time T1 to high level. The first clock signal CLK1 output from the first oscillation circuit 41 is a square wave configured to remain high for a certain period of time, and after rising to high level, falls to low level after a certain period of time has elapsed.

[0045] At time T1, the output signal Fout of the flip-flop 432 switches to high level. After time T1, the output signal Fout of the flip-flop 432 is maintained at high level until time T2, which will be described later.

[0046] Then, at time T1, the output signal Fout of the flip-flop 432 is input to the buffer 433. Note that before time T1, the buffer 433 outputs a low level. At time T1, a high level output signal Fout is input to the buffer 433. Then, the output signal Bout output from the buffer 433 switches to a high level at time T2, which is a predetermined time after time T1.

[0047] The output signal Bout of the buffer 433 is an enable signal for the second oscillation circuit 42, and the second clock signal CLK2 output from the second oscillation circuit 42 rises to high level at time T2 when the output signal Bout switches to high level. The second oscillation circuit 42 outputs a signal of a predetermined oscillation frequency from time T2. When the second clock signal CLK2 rises to high level, the flip-flop 431 is reset, and the output signal Fout falls to low level. In this manner, the first clock signal CLK1 and the second clock signal CLK2 can be signals with a delay time difference.

[0048] Time T2 is determined by the delay time of the buffer 433. In the logic circuit 43A, the delay time of the buffer 433 is determined so that the timing of the edge portion of the second clock signal CLK2 does not coincide with the timing of the edge portion of the first clock signal CLK1.

[0049] This allows the timing at which the instantaneous current consumption value of the circuit based on the first clock signal CLK1 increases to be offset from the timing at which the instantaneous current consumption value of the circuit based on the second clock signal CLK2 increases, thereby keeping the IR drop low and preventing malfunction of the circuit.

[0050] <Second Modification> A semiconductor device 10B of a second modified example will be described with reference to the drawings. FIG. 5 is a schematic circuit diagram of the semiconductor device 10B of the second modified example. The semiconductor device 10B shown in FIG. 5 differs from the semiconductor device 10 in that the configuration of the clock signal adjuster 431B of the logic circuit 43B of the clock generation circuit 40B is different from that of the clock signal adjuster 431 and that the semiconductor device 10B does not have a reference oscillation circuit 45. Other than this, the semiconductor device 10B has the same configuration as the semiconductor device 10. Therefore, parts of the semiconductor device 10B that are substantially the same as those of the semiconductor device 10 are given the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0051] 5, a clock signal adjuster 431B of a logic circuit 43B of the semiconductor device 10B includes a trimming circuit 434 and a storage unit 435. The storage unit 435 stores information about the frequency of the first clock signal CLK1. The storage unit 435 may be, for example, a register, but is not limited to this. In the semiconductor device 10B, the logic circuit 43B can detect a first frequency f1, which is the frequency of the first clock signal CLK1. The detected first frequency f1 is then stored in the storage unit 435.

[0052] The trimming circuit 434 reads information about the first frequency f1 of the first clock signal CLK1 stored in the storage unit 435, generates information about a second frequency f2 that is slightly higher or slightly lower than the first frequency f1 of the first clock signal CLK1, and outputs the information to the second oscillation circuit 42. The second oscillation circuit 42 outputs a second clock signal CLK2 that corresponds to the second frequency f2 to the logic circuit 43B. For example, the semiconductor device 10B can adjust the second frequency f2 to 3.9 MHz when the first frequency f1 is 4.0 MHz.

[0053] In the semiconductor device 10B, the timing of the edge of the second clock signal CLK2 and the timing of the edge of the first clock signal CLK1 are unlikely to coincide.

[0054] This allows the timing at which the instantaneous current consumption value of the circuit based on the first clock signal CLK1 increases to be offset from the timing at which the instantaneous current consumption value of the circuit based on the second clock signal CLK2 increases, thereby keeping the IR drop low and preventing malfunction of the circuit.

[0055] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present invention is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0056] <Additional Notes> The semiconductor device (10, 10A, 10B) described above includes a first oscillator circuit (41) configured to output a first clock signal (CLK1), a second oscillation circuit (42) configured to output a second clock signal (CLK2) different from the first clock signal (CLK1); a logic circuit (43, 43A, 43B) to which a first oscillation circuit (CLK1) and a second oscillation circuit (CLK2) are connected; This is a configuration (first configuration) in which the logic circuit (43, 43A, 43B) controls the second oscillation circuit (42) to generate a second clock signal (CLK2) whose edges are prevented from overlapping with the first clock signal (CLK1).

[0057] In the semiconductor device (10) of the first configuration, the logic circuit (43) may be configured (second configuration) to control the second oscillation circuit (42) to generate the second clock signal (CLK2) in response to a reference clock signal (CLKR) having a frequency that is an integer multiple of the frequency of the first clock signal (CLK1).

[0058] In the semiconductor device (10) of the second configuration, the reference clock signal (CLKR) may be configured to be synchronized with the first clock signal (CLK1) (third configuration).

[0059] In the semiconductor device (10A) having the first configuration, the logic circuit (43A) has a buffer circuit (433) configured to delay a signal, The logic circuit (43A) may be configured (fourth configuration) to control the second oscillation circuit (42) so as to generate a second clock signal (CLK2) delayed by a certain time from the first clock signal (CLK1).

[0060] In the semiconductor device (10B) of the first configuration, the logic circuit (43B) may be configured (fifth configuration) to include a trimming circuit (434) that controls the second oscillation circuit (42) so that the frequency (f2) of the second clock signal (CLK2) is different from the frequency (f1) of the first clock signal (CLK1).

[0061] The multi-channel DC / DC converter (100) described above includes a semiconductor device (10, 10A, 10B) having any one of the first to fifth configurations described above, a plurality of output sections (20) configured to be connected to the semiconductor devices (10, 10A, 10B); The logic circuits (43, 43A, 43B) have circuits configured to operate based on a first clock signal (CLK1) and a second clock signal (CLK2), The output section (20) may be configured (sixth configuration) to operate based on a clock signal based on one of the first clock signal (CLK1) and the second clock signal (CLK2). [Explanation of symbols]

[0062] 100 Multi-Channel DC / DC Converter 10, 10A, 10B Semiconductor device 20 Output section 21 Driver circuit 22 Bridge Circuit 221 High-side switching element 222 Low-side switching element 23 Smoothing circuit 231 Inductor 232 smoothing capacitor 30 Control circuit 32 Bridge Circuit 40 Clock generation circuit 41 First oscillator circuit 42 Second oscillator circuit 43, 43A, 43B Logic circuit 431, 431A, 431B Clock signal adjustment section 432 Flip-Flop 433 Buffer 434 Trimming Circuit 435 Storage section 44 Digital PLL circuit 45 Reference Oscillator Circuit Bout output signal Fout output signal CLK1 First clock signal CLK2 Second clock signal CLKR Reference clock signal CLKB Output clock signal CNT control signal SEN Enable signal SIN input signal f1 First frequency f2 Second frequency

Claims

1. a first oscillator circuit configured to output a first clock signal; a second oscillation circuit configured to output a second clock signal different from the first clock signal; a logic circuit to which the first oscillation circuit and the second oscillation circuit are connected, The logic circuit controls the second oscillation circuit to generate the second clock signal whose edges are prevented from overlapping with the first clock signal.

2. 2. The semiconductor device according to claim 1, wherein the logic circuit controls the second oscillation circuit to generate the second clock signal in response to a reference clock signal having a frequency that is an integer multiple of the first clock signal.

3. 3. The semiconductor device according to claim 2, wherein the reference clock signal is synchronized with the first clock signal.

4. the logic circuit has a buffer circuit configured to delay a signal; 2. The semiconductor device according to claim 1, wherein the logic circuit controls the second oscillation circuit to generate a second clock signal that is delayed by a certain time from the first clock signal.

5. 2. The semiconductor device according to claim 1, wherein the logic circuit includes a trimming circuit that controls the second oscillator circuit so that the frequency of the second clock signal is different from the frequency of the first clock signal.

6. A semiconductor device according to any one of claims 1 to 5, a plurality of output units configured to be connected to the semiconductor device; the logic circuit has a circuit configured to be operated based on the first clock signal and the second clock signal; The multi-channel DC / DC converter is configured such that the output section operates based on a clock signal that is based on one of the first clock signal and the second clock signal.

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