All-around gate field effect transistor and method of manufacturing the same

Abstract

The present invention provides a GateAll-AroundFieldEffectTransistor (GAAFET) and a manufacturing method thereof.SOLUTION: The GAAFET includes a substrate, a first sacrificial layer, a channel layer, a protective layer, a composite field oxide layer, drain and source electrodes, and a gate deposition layer. The first sacrificial layer is disposed on the substrate, and the channel layer is disposed on the first sacrificial layer and spans from the drain region to the source region. The protection layer is disposed on the channel layer and located in the drain region and the source region. The composite field oxide layer is disposed on the passivation layer and located in the drain region and the source region, and has a drain opening and a source opening exposing the passivation layer. The drain electrode and the source electrode are respectively disposed in the drain opening and the source opening and are electrically connected to the passivation layer. The gate deposition layer is disposed on the substrate and located in the channel region and surrounds the channel layer.SELECTED DRAWING: Figure 33

Description

[Technical Field]

[0001] The present invention relates to a transistor and a method thereof, and more particularly to a gate-all-around field effect transistor and a method of manufacturing the same. [Background technology]

[0002] Amorphous indium gallium zinc oxide (a-IGZO) has attracted widespread attention in recent years, mainly due to its low processing temperature, moderate mobility, and high uniformity. Due to its highly uniform amorphous properties, a-IGZO has great potential for monolithic 3D (M3D) alignment applications.

[0003] Although a-IGZO has a relatively high bandgap, resulting in a very low turn-off current, its mobility limits the increase in breakover current. Therefore, the existing a-IGZO gate-all-around (GAA) structure can not only increase the breakover current, but also improve the gate controllability, thereby reducing the subthrehold swing (SS) and turn-off current.

[0004] However, in the existing a-IGZO gate-all-around (GAA) structure, the material properties of the channel layer are easily affected during the manufacturing process, leading to poor electrical characteristics, and the size of the electrode opening is also limited by the manufacturing process, resulting in a relatively high series resistance in the final device, which affects the device characteristics. Therefore, how to improve the manufacturing process and structure to overcome the above drawbacks has become one of the key issues that companies are trying to solve. Summary of the Invention [Problem to be solved by the invention]

[0005] The technical problem that the present invention aims to solve is to provide a gate-all-around field-effect transistor with favorable electrical characteristics and a method for manufacturing the same, in response to the shortcomings of the prior art. [Means for solving the problem]

[0006] In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to form a first sacrificial layer, a channel layer and a protective layer on a substrate in this order; to perform a first patterning process on the first sacrificial layer, the channel layer and the protective layer to form a fin structure; and to perform a composite field oxidation process. a gate-all-around field-effect transistor (GAAFET) fabrication method, the method comprising the steps of: forming a gate-all-around (FOX) layer to cover the fin structure and the substrate, wherein the composite FOX layer simultaneously surrounds the fin structure; performing a second patterning process on the composite FOX layer to remove a portion of the composite FOX layer in the channel region and leave the composite FOX layer in the drain and source regions located on both sides of the channel region; removing the composite FOX layer, the protective layer, and the first sacrificial layer in the channel region to open the channel layer; forming a gate deposition layer on the composite FOX layer in the drain and source regions, on the substrate in the channel region, and on a surface of the channel layer; performing a third patterning process on the gate deposition layer to remove the gate deposition layer in the drain and source regions; performing a fourth patterning process on the composite FOX layer to form a drain opening in the drain region and a source opening in the source region; and forming a drain electrode and a source electrode in the drain opening, the drain electrode and the source electrode being electrically connected to the protective layer, respectively.

[0007] To solve the above technical problems, another technical solution adopted by the present invention is to provide a gate all-around field effect transistor (GAAFET) including a substrate, a first sacrificial layer, a channel layer, a protective layer, a composite field oxide (FOX) layer, drain and source electrodes, and a gate stack layer. The substrate defines a channel region and drain and source regions located on either side of the channel region. The first sacrificial layer is disposed on the substrate and is located within the drain and source regions. The channel layer is disposed on the first sacrificial layer and spans from the drain region to the source region. The protective layer is disposed on the channel layer and is located within the drain and source regions. The composite field oxide (FOX) layer is disposed on the protective layer and is located within the drain and source regions. The composite FOX layer has a drain opening located within the drain region and a source opening located within the source region, with the drain and source openings exposing the protective layer. The drain electrode and the source electrode are disposed in the drain opening and the source opening, respectively, and are electrically connected to the protective layer. The gate stack layer is disposed on the substrate, positioned in the channel region, and surrounding the channel layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a flowchart of a method for manufacturing a gate-all-around field-effect transistor according to one embodiment of the present invention. [Figure 2] FIG. 1 is a top view of the process of step S10 according to an embodiment of the present invention. [Figure 3] FIG. 4 is a cross-sectional view of the process of step S10 according to an embodiment of the present invention. [Figure 4] 10 is a detailed flowchart of step S11. [Figure 5] FIG. 10 is a top view of the process of step S110 according to an embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view of the process of step S110 according to an embodiment of the present invention. [Figure 7]FIG. 10 is a top view of the process of step S111 according to an embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view of the process of step S111 according to an embodiment of the present invention. [Figure 9] FIG. 10 is a top view of the process of step S12 according to an embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view of the process of step S12 according to an embodiment of the present invention. [Figure 11] 10 is a detailed flowchart of step S13. [Figure 12] FIG. 10 is a top view of the process of step S130 according to an embodiment of the present invention. [Figure 13] FIG. 10 is a cross-sectional view of the process of step S130 according to one embodiment of the present invention. [Figure 14] FIG. 10 is a top view of the process of step S131 according to an embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view of the process of step S131 according to an embodiment of the present invention. [Figure 16] FIG. 10 is a top view of the process of step S14 according to an embodiment of the present invention. [Figure 17] FIG. 10 is a cross-sectional view of the process of step S14 according to an embodiment of the present invention. [Figure 18] FIG. 10 is a top view of the process of step S16 according to an embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view of the process of step S16 according to an embodiment of the present invention. [Figure 20] 10 is a detailed flowchart of step S17. [Figure 21] FIG. 10 is a top view of the process of step S170 according to one embodiment of the present invention. [Figure 22] FIG. 10 is a cross-sectional view of the process of step S170 according to one embodiment of the present invention. [Figure 23] FIG. 10 is a top view of the process of step S172 according to one embodiment of the present invention. [Figure 24] FIG. 10 is a cross-sectional view of the process of step S172 according to one embodiment of the present invention. [Figure 25] 10 is a detailed flowchart of step S18. [Figure 26] FIG. 10 is a top view of the process of step S180 according to one embodiment of the present invention. [Figure 27] FIG. 10 is a cross-sectional view of the process of step S180 according to one embodiment of the present invention. [Figure 28] FIG. 10 is a top view of the process of step S181 according to one embodiment of the present invention. [Figure 29] FIG. 10 is a cross-sectional view of the process of step S181 according to one embodiment of the present invention. [Figure 30] FIG. 10 is a top view of the process of step S19 according to an embodiment of the present invention. [Figure 31] FIG. 10 is a cross-sectional view of the process of step S19 according to one embodiment of the present invention. [Figure 32] FIG. 2 is a top view of a gate all-around field effect transistor (GAAFET) according to another embodiment of the present invention. [Figure 33] 2 is a cross-sectional view of a gate all-around field effect transistor (GAAFET) according to another embodiment of the present invention; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] To better understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings, which are provided for reference and explanation only and do not limit the scope of the present invention.

[0010] The following describes the implementation of the "gate-all-around field-effect transistor and its manufacturing method" provided by the present invention through specific examples, and those skilled in the art can understand the advantages and benefits of the present invention based on the disclosure herein. The present invention can be implemented or applied through other different specific examples, and various modifications and changes can be made to the details herein based on different perspectives and applications without departing from the concept of the present invention. Please note that the accompanying drawings are for simple schematic illustrations and are not drawn to scale. The technical content of the present invention will be described in more detail based on the following examples, but the disclosure does not limit the scope of protection of the present invention. The term "or" used in this specification may include any one or more combinations of the related listed items depending on the actual situation.

[0011] The main object of the present invention is to provide a gate-all-around field-effect transistor that can have low series resistance, high breakover current and mobility, and can be manufactured with high yield by overcoming the limitations of existing manufacturing processes, and a manufacturing method thereof.

[0012] 1 is a flow chart of a method for manufacturing a gate-all-around field-effect transistor (GAAFET) according to an embodiment of the present invention. Referring to FIG. 1, the method for manufacturing a gate-all-around field-effect transistor (GAAFET) according to an embodiment of the present invention includes the following steps:

[0013] In step S10, a first sacrificial layer, a channel layer, and a protective layer are formed on a substrate in this order. FIGS. 2 and 3 are a top view and a cross-sectional view, respectively, of step S10 according to one embodiment of the present invention. Here, FIG. 3 is a cross-sectional view taken along the cross-sectional line CS1. Unless otherwise specified, the remaining cross-sectional views are all taken along the cross-sectional line CS1 and will not be described separately. Referring to FIGS. 2 and 3, the substrate 100 can be made of a material such as silicon, germanium, or glass.

[0014] In step S10, a first sacrificial layer 101, a channel layer 102, and a protective layer 103 are formed on a substrate 100. The material of the first sacrificial layer 101 can include one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide. The thickness of the first sacrificial layer 101 can be in the range of 1 nm to 1 μm and can be deposited by atomic layer deposition (ALD), sputtering, plasma-enhanced chemical vapor deposition (PECVD), or epitaxy. The channel layer 102 can be made of amorphous indium gallium zinc oxide (IGZO), a II-VI material, a III-V material, a IV material, or a two-dimensional material. The thickness of the channel layer 102 can be in the range of 1 nm to 1000 nm and can be deposited by atomic layer deposition (ALD) or sputtering.

[0015] For example, after depositing a thermal oxide layer on the surface of a silicon wafer substrate, a 200 nm thick silicon nitride layer (first sacrificial layer 101) can be deposited by plasma-enhanced chemical vapor deposition (PECVD) at a temperature of 300° C. Subsequently, the channel layer 102 can be deposited by co-sputtering target materials of In2O3 and IGZO (for example, the atomic composition ratio is In:Ga:Zn:O=1:1:1:4 mol%).

[0016] It should be emphasized that the material of the protective layer 103 is different from the material of the channel layer 102. The material of the protective layer 103 may include one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide, and the thickness of the protective layer 103 is in the range of 1 nm to 1000 nm. The protective layer 103 can prevent adverse effects on the channel layer 102 during the photoresist stripping process and can serve as an etching stop layer. Note that, in consideration of subsequent processes, any material that can be removed by SF6 gas can be used as the protective layer 103.

[0017] In step S11, the first sacrificial layer, the channel layer, and the protective layer are subjected to a first patterning process to form a fin structure.

[0018] 4 is a detailed flowchart of step S11. Referring to FIG. 3, in detail, in step S11, the first patterning process may include the following steps: In step S110, a first mask layer having a fin pattern defined thereon is formed on the protective layer. FIGS. 5 and 6 are top and cross-sectional views, respectively, of step S110 according to one embodiment of the present invention. For example, referring to FIGS. 5 and 6, the first mask layer 104 may be a photoresist layer (which may be made of a photoresist material or, for example, Si3N4), and the first mask layer 104 having the fin pattern defined thereon may be formed by e-beam lithography. From a top view, the substrate 100 may define a channel region A1 and drain and source regions A2 and A3 located on either side of the channel region A1. The fin pattern may have a shape approximating a funnel defined in the channel region A1. In step S111, the first sacrificial layer, the channel layer, and portions of the protective layer not covered by the first mask layer are removed to form a fin structure. Figures 7 and 8 show a top view and a cross-sectional view, respectively, of step S111 according to one embodiment of the present invention. Referring to Figures 7 and 8, in this step, a fin structure F1 can be formed by reactive ion etching (RIE). In step S112, the first mask layer 104 is removed. The first mask layer 104 can be removed by wet etching or dry etching. Wet etching may include the use of buffered oxide etch (BOE) or hot phosphoric acid (H3PO4), and dry etching may include the use of RIE or inductively coupled plasma etching (ICP-RIE).

[0019] It should be emphasized that the protective layer 103 plays a key role in device performance. Without the protective layer 103, the oxygen doping concentration in the channel layer 102 would increase during the photoresist removal process, further increasing the content of weakly bonded oxygen. In oxide semiconductors such as IGZO (In-Ga-Zn-O), the bonds between oxygen atoms and metals in the material are relatively weak, resulting in localized negatively charged centers. The Coulomb force acts on free carriers, increasing electron scattering and reducing carrier mobility, ultimately resulting in increased series resistance and a decrease in breakover current. The use of the protective layer 103 can prevent excessive oxygen from doping the channel layer 102 during the removal of the first mask layer 104. Additionally, the protective layer 103 can also serve as an etch stop layer during the removal of the first mask layer 104.

[0020] In step S12, a composite field oxide (FOX) layer is formed to cover the fin structure and the substrate. At the same time, the composite FOX layer CF surrounds the fin structure F1. FIGS. 9 and 10 are top and cross-sectional views, respectively, of the process of step S12 according to one embodiment of the present invention. Referring to FIGS. 9 and 10, in step S12, the composite FOX layer CF includes a second sacrificial layer 105 (e.g., silicon nitride (SiN)) and a field oxide layer 106 (e.g., silicon dioxide (SiO2)) stacked in this order on the substrate 100 and the fin structure F1, and the thicknesses of the second sacrificial layer 105 and the field oxide layer 106 range from 1 nm to 1000 nm. The composite FOX layer CF can be deposited by PECVD, thermal oxidation, or ALD techniques.

[0021] In step S13, the composite FOX layer is subjected to a second patterning process to remove a portion of the composite FOX layer in the channel region and leave the composite FOX layer in the drain and source regions located on either side of the channel region. The second patterning process is performed to remove only the field oxide layer 106 in the channel region, leaving mainly the composite FOX layer CF in the drain and source regions located on both sides of the channel region. Figure 11 is a detailed flowchart of step S13. As shown in Figure 11, the second patterning process may include the following steps: In step S130, a second mask layer 107 is formed on the composite FOX layer. The second mask layer 107 defines a channel region A1, a drain region A2, and a source region A3 corresponding to the fin structure F1. FIGS. 12 and 13 are top and cross-sectional views, respectively, of the process of step S130 according to one embodiment of the present invention. More specifically, referring to FIGS. 12 and 13, the pattern formed by the second mask layer 107 covers only the drain region A2 and the source region A3, but does not cover the channel region A1. In step S131, a portion of the composite FOX layer in the channel region is removed to expose the second sacrificial layer, while leaving the composite FOX layer in the drain and source regions. 14 and 15 are top and cross-sectional views, respectively, of step S131 of the process according to one embodiment of the present invention. Referring to FIGS. 14 and 15, a buffered oxide etchant (BOE) can be used in this step. During the BOE etching process, the etching rate of SiN (second sacrificial layer 105) is slower than that of SiOx (field oxide layer 106), so the etching is stopped at SiN (as shown in FIG. 15). Without the field oxide layer 106, subsequent etching of the gate stack layer may result in sidewall residue or even serious gate leakage current.

[0022] In step S14, the composite FOX layer, the protective layer, and the first sacrificial layer in the channel region are removed to open the channel layer. In step S14, the composite FOX layer CF, the protective layer 103, and the first sacrificial layer 101 in the channel region A1 are selectively etched away to form a gate-all-around structure, with the channel portion of the channel layer 102 located in the channel region A1 floating (e.g., separated by a predetermined distance) above the substrate 100. FIGS. 16 and 17 are top and cross-sectional views, respectively, of step S14 according to one embodiment of the present invention. For example, referring to FIGS. 16 and 17, the channel layer 102 can be opened using SF6 gas while using inductively coupled plasma etching (ICP-RIE). Because fluorine radicals react with SiN / SiOx to form gaseous products, and the a-IGZO fluoride remains in a solid state, highly selective etching can be achieved. SiN is selected as the material for the sacrificial layer due to its relatively fast etching rate.

[0023] The composite FOX layer CF in the drain region A2 and the source region A3 is made of SiO x Because the etching rate in RIE is relatively slow, the channel layer 102 (e.g., a-IGZO) remains unaffected by this etching process. Furthermore, due to the bonding characteristics of the a-IGZO material (e.g., the low bond energy of the indium-oxygen (In-O) bond and / or the weak local bond energy of certain oxygen bonds), oxygen atoms are relatively easy to disengage, forming a large number of oxygen vacancies in the channel layer 102. Preferably, the etching process uses SF gas for an extended period of time, allowing fluorine atoms to passivate the channel layer 102 and fill the oxygen vacancies in the channel layer 102, thereby improving control of the electrical properties of the channel layer 102 and reducing the series resistance of the device.

[0024] In step S15, the opened channel layer is subjected to an oxygen-assisted annealing process. Similarly, as mentioned above, the bonding properties of the a-IGZO material favor the formation of a large number of oxygen vacancies in the channel layer 102. Further reduction of the oxygen vacancies through oxygen-assisted annealing (e.g., low-temperature annealing (200°C-400°C) or high-temperature annealing (450°C-600°C) with a predetermined annealing time and oxygen flow rate to allow oxygen molecules to react with the internal oxygen vacancies on the a-IGZO material surface, resulting in self-alignment of oxygen atoms) can improve control of the electrical properties of the channel layer 102 and reduce the series resistance of the device.

[0025] In step S16, a gate stack layer is formed on the composite FOX layer in the drain and source regions, on the substrate in the channel region, and on the surface of the channel layer. 18 and 19 are top and cross-sectional views, respectively, of step S16 according to one embodiment of the present invention. Referring to FIGS. 18 and 19, in this step, a gate insulating layer 108, a first gate metal layer 109, and a second gate metal layer 110 are sequentially formed by an ALD process on the composite FOX layer CF, the substrate 100 in the channel region A1, and the surface of the channel layer 102. The three layers are combined to form a gate stack layer GS. The gate insulating layer 108 is disposed to surround the channel layer 102 and is formed of a high-k dielectric layer (e.g., Al2O3, HfO2, TiO2, or ZrO2) with a thickness ranging from 1 nm to 1000 nm. Depositing the gate insulating layer 108 by ALD can improve gate control over the channel. The first gate metal layer 109 is disposed to surround the gate insulating layer 108 and can be made of titanium nitride, its thickness can be controlled within a range of 1 nm to 1000 nm, and can be deposited by ALD or PVD techniques. The second gate metal layer 110 is disposed to surround the first gate metal layer 109 and can be made of titanium nitride (TiN), tungsten, aluminum, or titanium, its thickness can be controlled within a range of 1 nm to 1000 nm, and can be deposited by ALD or PVD techniques.

[0026] In step S17, the gate deposition layer is subjected to a third patterning process to remove the gate deposition layer in the drain and source regions. 20 is a detailed flowchart of step S17. As shown in FIG. 20, the third patterning process includes the following steps: In step S170, a third mask layer is formed on the gate deposition layer and positioned in the channel region. In step S171, the gate deposition layer in the drain and source regions is removed, leaving the gate deposition layer in the channel region while exposing the composite FOX layer in the drain and source regions. In step S172, the third mask layer is removed.

[0027] 21 and 22 are respectively a top view and a cross-sectional view of step S170 according to an embodiment of the present invention. In the above process, as shown in FIGS. 21 and 22, a third mask layer 111 located in the channel region A1 is formed on the gate deposition layer GS, and then the gate deposition layer GS in the drain region A2 and the source region A3 is removed to leave the gate deposition layer in the channel region A1, while exposing the composite FOX layer CF in the drain region A2 and the source region A3. After that, the third mask layer 111 is removed. As shown in FIGS. 23 and 24, FIGS. 23 and 24 are respectively a top view and a cross-sectional view of step S172 according to an embodiment of the present invention.

[0028] In step S18, the composite FOX layer is subjected to a fourth patterning process to form a drain opening in the drain region and a source opening in the source region. 25 is a detailed flowchart of step S18. As shown in FIG. 25, the fourth patterning process includes the following steps: In step S180, a fourth mask layer is formed on the gate stack layer and the composite FOX layer. FIGS. 26 and 27 are top and cross-sectional views, respectively, of the process of step S180 according to one embodiment of the present invention. Referring to FIGS. 26 and 27, the fourth mask layer 112 covers the entire channel region A1 but only partially covers the drain region A2 and the source region A3, defining a drain opening region A4 located in the drain region A2 and a source opening region A5 located in the source region A3. The fourth mask layer 112 is, for example, photoresist. In step S181, the composite FOX layer in the drain opening region and the source opening region is removed to form the drain opening and the source opening. FIGS. 28 and 29 are top and cross-sectional views, respectively, of step S181 according to one embodiment of the present invention. Referring to FIGS. 28 and 29, the drain opening DO and the source opening SO each expose the protective layer 103. The protective layer 103 can also serve as an etch stop layer during the process of removing the composite FOX layer CF in the drain opening region A4 and the source opening region A5. Preferably, the widths of the drain opening DO and the source opening SO are within the range of 10 nm to 500 nm. Without the protective layer 103, the widths of the drain opening DO and the source opening SO are typically limited to a few nanometers to prevent the relatively thin channel layer 102 from being destroyed during the etching process. This limits the size of the drain and source to be formed later and increases the electrical resistance of the device. Therefore, by providing the protective layer 103 as an etching stop layer, the widths of the drain opening DO and the source opening SO can be increased, which in turn reduces the series resistance of the device and prevents the channel layer 102 from being destroyed during the etching process, thereby improving the process yield.

[0029] In step S19, drain and source electrodes electrically connected to the protective layer are formed in the drain and source openings, respectively. FIGS. 30 and 31 are top and cross-sectional views, respectively, illustrating the process of step S19 according to one embodiment of the present invention. As shown in FIGS. 30 and 31, in this step, the source and drain metal layers can be selected from TiN, Al, Ti, tungsten (W), indium titanium oxide (ITO), or indium oxide (InO), and can be deposited by ALD or sputtering techniques with a thickness ranging from 1 nm to 1000 nm, ensuring good ohmic contact between the protective layer 103 and the drain and source electrodes DE and SE.

[0030] 32 and 33 are a top view and a cross-sectional view, respectively, of a gate all-around field effect transistor (GAAFET) provided by another embodiment of the present invention. Here, FIG. 33 is a cross-sectional view taken along section line CS2. Referring to FIGS. 32 and 33, the present invention provides a GAAFET 2 including a substrate 200, a first sacrificial layer 201, a channel layer 202, a protective layer 203, a composite field oxide (FOX) layer CF, a drain electrode DE, a source electrode SE, and a gate stack layer GS.

[0031] A channel region A1, a drain region A2 and a source region A3 located on either side of the channel region A1 are defined in the substrate 200. A first sacrificial layer 201 is disposed on the substrate 200 and is located in the drain region A2 and the source region A3.

[0032] The channel layer 202 is disposed on the first sacrificial layer 201 and spans from the drain region A2 to the source region A3. The channel layer 202 is located in the channel region A1 and has a channel portion spaced a predetermined distance from the substrate 200. As described in the above embodiment, the channel portion may be processed by self-aligned fluorine doping and oxygen-assisted annealing. Specifically, during the etching process of the opened channel layer 202, the fluorine atoms passivate the channel layer 202 by using SF gas for an extended period of time, and oxygen vacancies in the channel layer 202 are filled. The opened channel layer 202 is then subjected to an oxygen-assisted annealing process, whereby oxygen molecules react with the surface of the a-IGZO material and the oxygen vacancies within the channel layer 202. This improves the controllability of the electrical properties of the channel layer 202 and reduces the series resistance of the GAAFET 2.

[0033] The protective layer 203 is disposed on the channel layer 202 and is located in the drain region A2 and the source region A3. The protective layer 203 not only serves as an etching stop layer in multiple steps in the manufacturing process of the GAAFET 2 to improve yield, but also reduces limitations on the widths of the drain opening DO and the source opening SO, allowing for good ohmic contact characteristics between the protective layer 203 and the drain electrode DE and the source electrode SE, thereby reducing the series resistance of the GAAFET 2 and improving the breakover current of the GAAFET 2.

[0034] Meanwhile, a composite field oxide (FOX) layer CF is disposed on the protective layer and located in the drain region A2 and the source region A3, and the composite FOX layer CF includes a second sacrificial layer 205 and a FOX layer 206, which are arranged in this order, and has a drain opening DO located in the drain region A2 and a source opening SO located in the source region A3, and the drain opening DO and the source opening SO expose the protective layer 203. A drain electrode DE and a source electrode SE are disposed in the drain opening DO and the source opening SO, respectively, and are electrically connected to the protective layer 203.

[0035] A gate stack layer GS is disposed on the substrate 200 as the gate of the GAAFET 2 and is located in the channel region A1. The gate stack layer GS is disposed to surround the channel layer 202 to form a gate-all-around (GAA) structure. The gate-all-around structure can not only increase the breakover current but also improve gate controllability, thereby reducing the subthreshold swing (SS) and turn-off current. Similar to the above embodiment, the gate stack layer GS may include a gate insulating layer 208, a first gate metal layer 209, and a second gate metal layer 210.

[0036] It is anticipated that other embodiments of the present invention provide a single channel layer 202 as an example, but the present invention is not limited thereto. Multiple channel layers 202 may be arranged in the GAAFET 2. Specifically, when multiple channel layers 202 are provided, the multiple channel layers 202 are arranged in a stacked configuration, and a gate stack layer GS is disposed to surround all of the channel layers 202, enhancing control over each channel layer 202. A sacrificial layer and a spacer layer may be disposed between adjacent channel layers 202. Here, the spacer layer may be made of Al2O3, SiN, or SiO2 to support the channel layers 202 and control parasitic effects. A drain electrode DE and a source electrode SE must also be in electrical contact with each channel layer 202. [Industrial Applicability]

[0037] [Beneficial Effects of Examples] One of the beneficial effects of the present invention is that the GAAFET and its manufacturing method provided by the present invention have low SS, good scaling ability, low turn-off current, high breakover current / turn-off current ratio, forward gate threshold voltage, and good saturation characteristics under high drain voltage. In addition, the series resistance can be further reduced and the breakover current can be improved, so that the manufacturing yield is relatively high and the GAAFET can be applied to large-scale mass production.

[0038] The above disclosure is merely a preferred embodiment of the present invention, and the scope of the claims of the present invention is not limited thereto. Therefore, any equivalent technical modifications made by utilizing the specification and drawings of the present invention are included in the scope of the claims of the present invention. [Explanation of symbols]

[0039] S10~S19, S110~S112, S130, S131, S170~S172, S180, S181...Process 2...GAAFET 100,200...substrate 101,201...First sacrificial layer 102,202...Channel layer 103,203...protective layer 104...First mask layer 105,205...Second sacrificial layer 106,206...field oxide layer 107...Second mask layer 108,208...Gate insulating layer 109,209...first gate metal layer 110, 210...Second gate metal layer 111...Third mask layer 112...Fourth mask layer CF...Composite Field Oxide Layer DE...Drain electrode SE...Source electrode DO...Drain opening SO...Source opening GS...Gate deposition layer A1...Channel region A2...Drain area A3...Source area A4...Drain opening area A5...Source aperture area CS1,CS2...section line F1...fin structure

Claims

1. forming a first sacrificial layer, a channel layer, and a protective layer in this order on a substrate; performing a first patterning process on the first sacrificial layer, the channel layer, and the protective layer to form a fin structure; forming a composite field oxide (FOX) layer covering the fin structure and the substrate, the composite FOX layer simultaneously surrounding the fin structure; performing a second patterning process on the composite FOX layer to partially remove the composite FOX layer in the channel region and leave the composite FOX layer in the drain and source regions on either side of the channel region; removing the composite FOX layer, the protective layer, and the first sacrificial layer in the channel region to release the channel layer; forming a gate stack layer on the composite FOX layer in the drain and source regions, on the substrate in the channel region, and on a surface of the channel layer; performing a third patterning process on the gate deposition layer to remove the gate deposition layer in the drain and source regions; performing a fourth patterning process on the composite FOX layer to form a drain opening in the drain region and a source opening in the source region; forming a drain electrode and a source electrode electrically connected to the protective layer in the drain opening and the source opening, respectively; Fabrication of gate-all-around field-effect transistors.

2. performing an oxygen-assisted annealing process on the released channel layer; and performing an inductively coupled plasma etching (ICP-RIE) process to remove a portion of the composite FOX layer, the protective layer, and the first sacrificial layer in the channel region; In the ICP-RIE process, SF ６ and completing self-aligned fluorine doping using the gas. The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

3. The first patterning process comprises: forming a first mask layer on the protective layer, the first mask layer having a fin pattern defined therein; removing the first sacrificial layer, the channel layer, and portions of the protective layer not covered by the first mask layer to form the fin structure; removing the first mask layer; the protective layer serves as an etch stop layer during the process of removing the first mask layer; The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

4. The second patterning process comprises: forming a second mask layer on the composite FOX layer, the second mask layer defining the channel region, the drain region, and the source region corresponding to the fin structure; partially removing the composite FOX layer in the channel region to expose a second sacrificial layer of the composite FOX layer while leaving the composite FOX layer in the drain and source regions. The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

5. 2. The method for manufacturing a gate-all-around field-effect transistor according to claim 1, wherein the channel layer is located in the channel region and includes a channel portion spaced a predetermined distance from the substrate.

6. The third patterning process comprises: forming a third mask layer on the gate deposition layer located in the channel region; removing the gate stack in the drain and source regions to leave the gate stack in the channel region and to expose the composite FOX layer in the drain and source regions; removing the third mask layer. The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

7. The fourth patterning process comprises: forming a fourth mask layer on the gate stack layer and the composite FOX layer, the fourth mask layer defining a drain opening region in the drain region and a source opening region in the source region; removing the composite FOX layer in the drain opening region and the source opening region to form the drain opening and the source opening, and the drain opening and the source opening respectively expose the protection layer; the protective layer serves as another etch stop layer during the process of removing the composite FOX layer in the drain opening region and the source opening region; The method for manufacturing the GAAFET of claim 1 .

8. the width of the drain opening and the source opening is in the range of 10 nm to 500 nm, the thickness of the protection layer is in the range of 1 nm to 1000 nm, the material of the protection layer is different from the material of the channel layer, and the material of the protection layer includes one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide; The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

9. the composite FOX layer includes a second sacrificial layer and a FOX layer stacked in this order, the material of the second sacrificial layer including one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon oxide, and the material of the FOX layer including one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide; The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

10. The material of the channel layer includes one or more of amorphous indium gallium zinc oxide, a II-VI material, a III-V material, a IV material, and a two-dimensional material; The method for manufacturing a gate-all-around field-effect transistor according to claim 1 .

11. a substrate defining a channel region and drain and source regions located on opposite sides of the channel region; a first sacrificial layer disposed on the substrate and positioned within the drain region and the source region; a channel layer disposed on the first sacrificial layer and spanning from the drain region to the source region; a protection layer disposed on the channel layer and positioned within the drain region and the source region; a composite field oxide (FOX) layer disposed on the protective layer and positioned within the drain region and the source region, the composite field oxide (FOX) layer having a drain opening positioned in the drain region and a source opening positioned in the source region, the drain opening and the source opening exposing the protective layer; a drain electrode and a source electrode disposed in the drain opening and the source opening, respectively, and electrically connected to the protective layer; a gate stack layer disposed on the substrate, positioned in the channel region, and surrounding the channel layer; Gate-all-around field-effect transistor.

12. The gate stack layer comprises: a gate insulating layer disposed so as to surround the channel layer; a first gate metal layer disposed so as to surround the gate insulating layer; a second gate metal layer disposed so as to surround the first gate metal layer; 12. The gate-all-around field effect transistor of claim 11.

13. the channel layer is located in the channel region and has a channel portion spaced a predetermined distance from the substrate; 12. The gate-all-around field effect transistor of claim 11.

14. the channel portion of the channel layer has been processed by a process of self-aligned fluorine doping and oxygen assist annealing; 14. The gate-all-around field effect transistor of claim 13.

15. the width of the drain opening and the source opening is in the range of 10 nm to 500 nm; 12. The gate-all-around field effect transistor of claim 11.

16. The thickness of the protective layer is in the range of 1 nm to 1000 nm.

12. The gate-all-around field effect transistor of claim 11.

17. The material of the protection layer is different from the material of the channel layer, and the material of the protection layer includes one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide.

12. The gate-all-around field effect transistor of claim 11.

18. the composite FOX layer includes a second sacrificial layer and a FOX layer stacked in this order; 12. The gate-all-around field effect transistor of claim 11.

19. the material of the second sacrificial layer includes one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon oxide; and the material of the FOX layer includes one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide; 20. The gate-all-around field effect transistor of claim 18.

20. The material of the channel layer includes one or more of amorphous indium gallium zinc oxide, a II-VI material, a III-V material, a IV material, and a two-dimensional material; 12. The gate-all-around field effect transistor of claim 11.

Images