Support substrate, composite substrate, electronic device, and module

Abstract

To provide a support substrate, a composite substrate, an electronic device, and a module having a specific crystal grain density condition for suppressing generation of fragments due to insufficient strength of the support substrate.SOLUTION: The support substrate 11 is composed of a polycrystalline material and has a grain density of 1,000 grains / mm2 or more and a grain boundary volume ratio of 8% to 40%. As a result, the strength of the support substrate can be increased, and the problem of generation of fragments due to insufficient strength can be reduced. This makes it possible to improve the quality and efficiency during production.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the technical field of processing and manufacturing electronic devices, and in particular to support substrates, composite substrates, electronic devices and modules. [Background technology]

[0002] Some acoustic wave filters, such as SAW (Surface Acoustic Wave) filter devices, especially TC-SAW (Temperature-Compensated SAW) filters, require the use of a composite substrate obtained by bonding a piezoelectric layer to a support substrate. In the manufacturing process of SAW devices, the strength of the support substrate is an important parameter. If the strength is insufficient, debris is likely to be generated during subsequent processes, such as the bonding process or the process of forming electrodes on the composite substrate. This not only adversely affects production efficiency and quality, but also may increase manufacturing costs. Summary of the Invention

[0003] The present invention aims to solve the problem that fragments are likely to be generated due to insufficient strength of the support substrate. To achieve this object, the present invention provides a support substrate, a composite substrate, an electronic device, and a module that enable a support substrate having high strength to be realized, thereby improving the quality and efficiency of production.

[0004] One embodiment of the present invention provides a support substrate made of a polycrystalline material, wherein the density of crystal grains in the support substrate is 1000 grains / mm 2 or more, and the volume ratio of the grain boundaries is 8% to 40% or less.

[0005] One embodiment of the present invention provides a composite substrate including the support substrate and a piezoelectric layer provided on the support substrate.

[0006] One embodiment of the present invention provides an electronic device comprising the support substrate or composite substrate.

[0007] One embodiment of the present invention provides a module including a wiring substrate, a plurality of external connection terminals, an integrated circuit component, an inductor, and a sealing portion, and further including the electronic device.

[0008] The above-described embodiments of the present invention have at least one or more of the following advantageous effects: by providing a support substrate with specific grain density conditions, the flexural strength of the support substrate can be improved, the generation of debris in the subsequent bonding process can be suppressed, and production quality and efficiency can be ensured. [Brief explanation of the drawings]

[0009] Specific embodiments of the present invention will be described in detail below with reference to the drawings.

[0010] FIG. 1 is a schematic diagram showing the configuration of a support substrate according to an embodiment of the present invention.

[0011] FIG. 2 is a diagram showing the microstructure of a support substrate according to an embodiment of the present invention.

[0012] FIG. 3 is a schematic diagram showing the configuration of a composite substrate according to an embodiment of the present invention.

[0013] FIG. 4 is a schematic diagram showing the configuration of an electronic device according to an embodiment of the present invention.

[0014] FIG. 5 is a schematic diagram showing the configuration of another electronic device according to an embodiment of the present invention.

[0015] FIG. 6 is a schematic diagram showing the configuration of yet another electronic device according to an embodiment of the present invention.

[0016] FIG. 7 is a schematic diagram showing the configuration of another electronic device according to an embodiment of the present invention.

[0017] FIG. 8 is a schematic diagram showing the configuration of a module according to an embodiment of the present invention.

[0018] FIG. 9 is a schematic diagram showing areas designated during a yield rate inspection of electronic devices according to an embodiment of the present invention.

[0019] [Explanation of symbols]

[0020] 1000: Module 100: Electronic Devices 10: Composite board 11: Support substrate 111: Main support surface 112: Back 12: Piezoelectric layer 121: Main surface 13: Middle class 20: Electrode 21:IDT electrode 22: Electrode pad 30: Sealing substrate 41:First sealing structure 42:Second sealing structure 51: Bump 52: First conductive part 53: 1st external terminal electrode 54: Second conductive part 55: 2nd external terminal electrode 60:Void 70: Lid 400: Inductor 500: Sealing part 600: Integrated circuit parts 700: Wiring board 701: External connection terminal [Example]

[0021] In order to make the above-mentioned objects, features and advantages of the present invention clearer and easier to understand, specific embodiments of the present invention will be described in detail below with reference to the drawings.

[0022] In order to allow those skilled in the art to more clearly understand the technical solutions of the present invention, the technical configuration of the present invention will be clearly and completely described below with reference to the drawings according to the embodiments of the present invention, however, the embodiments described herein are only some examples of the present invention and do not cover all the embodiments. Other embodiments that can be conceived by those skilled in the art based on the embodiments of the present invention without any creative efforts should also fall within the scope of protection of the present invention.

[0023] In addition, terms such as "first" and "second" used in this specification, claims, and drawings are intended to distinguish between similar objects and do not necessarily indicate a specific order or chronological relationship. Such terms can be used interchangeably as appropriate, and configurations other than those shown or described can also be implemented as embodiments of the present invention. Furthermore, terms such as "comprise" and "have" (and variations thereof) are intended to be non-exclusive inclusive, meaning that even if a configuration includes multiple steps or components, it may also include other steps or components not described, or elements inherently included in the technical field.

[0024] It should be further explained that the distinction between the multiple embodiments in the present invention is for the sake of convenience and does not imply any particular limitation, and the features of each embodiment can be combined or referenced with each other as long as there is no contradiction between the embodiments.

[0025] (Embodiment 1)

[0026] A first embodiment of the present invention provides a method for manufacturing a support substrate, the support substrate obtained by the method comprising a main support surface for supporting a piezoelectric layer and a back surface opposite to the main support surface.

[0027] The method for manufacturing the support substrate comprises the following steps:

[0028] Step S11: An ingot is formed using the raw crystal powder, and the ingot is processed to prepare a pre-treated substrate.

[0029] Step S12: Polishing is performed on each of the two opposing surfaces of the pre-treated substrate.

[0030] Step S13: One of the two polished surfaces of the pre-treated substrate is subjected to sandblasting to obtain a support substrate.

[0031] The raw material crystalline powder used in step S11 may be, for example, a polycrystalline powder, and the polycrystalline powder may be any of polycrystalline magnesium aluminate spinel, polycrystalline sapphire, polycrystalline aluminum nitride, polycrystalline magnesium oxide, and polycrystalline quartz. Specifically, in step S11, the raw material powder is formed into an ingot by a method such as CIP (Cold Isostatic Pressing) or HIP (Hot Isostatic Pressing), and the ingot is then subjected to dicing and polishing to obtain a pre-processed substrate.

[0032] For example, the two opposing surfaces of the pre-treated substrate polished in step S12 are referred to as the first and second surfaces, respectively. The first surface is used as the main support surface for supporting the piezoelectric layer in the subsequent process. In step S12, for example, the first surface is polished to a surface roughness Sa of 0.6 nm or less, thereby enabling stable bonding with the subsequent piezoelectric layer. As specified in ISO 25178, surface roughness can be expressed by parameters such as the arithmetic mean height Sa, the maximum height Sz, the root-mean-square height Sq, and the maximum peak height Sp. In this specification, surface roughness Sa refers to the arithmetic mean height Sa in ISO 25178.

[0033] In the first embodiment of the present invention, the total thickness variation (TTV) on the surface of the pre-treated substrate after the process in step S12 can reach 1 μm or less, which can further reduce the influence on the film thickness uniformity of the piezoelectric layer in the subsequent process.

[0034] As mentioned above, in step S13, the second surface of the pre-treated substrate is sandblasted, and upon completion of this process, the second surface becomes the back surface of the support substrate. This sandblasting process breaks down the crystal grains present on the second surface, thereby roughening the second surface, thereby enabling the surface roughness Sz of the back surface 112 of the support substrate to be adjusted to the desired specifications. In this specification, surface roughness Sz refers to the maximum height Sz defined in ISO 25178.

[0035] In the first embodiment of the present invention, first, both opposing surfaces of the pre-processed substrate are polished, and then the surface that will form the back surface of the support substrate is sandblasted and roughened. By performing double-sided polishing, it is possible to minimize the TTV and simultaneously reduce the transmittance of the support substrate. This reduces the TTV while avoiding alignment difficulties in subsequent manufacturing processes.

[0036] The first embodiment of the present invention further provides a method for manufacturing a composite substrate, which can produce a composite substrate including a piezoelectric layer and a support substrate, in which the piezoelectric layer is disposed on the support substrate, more specifically, the piezoelectric layer is disposed on a major support surface of the support substrate.

[0037] The method for manufacturing a composite substrate according to embodiment 1 of the present invention includes the following steps:

[0038] Step S11: An ingot is prepared using the raw crystal powder, and the ingot is processed to obtain a pre-treated substrate.

[0039] Step S12: Polishing the two opposing surfaces of the pre-treated substrate.

[0040] Step S14: The polished pre-treated substrate is brought into contact with the piezoelectric substrate.

[0041] Step S15: The surface of the polished pre-treated substrate that does not face the piezoelectric substrate is subjected to sandblasting, thereby obtaining a composite substrate.

[0042] For specific details of steps S11 and S12, please refer to the descriptions of steps S11 and S12 in the aforementioned method for manufacturing a support substrate. The piezoelectric substrate used in step S14 may be a finished piezoelectric substrate obtained by dicing, grinding, polishing, and reducing a crystalline ingot made of, for example, lithium tantalate material. Furthermore, step S16, for example, may be included before step S15. In step S16, the piezoelectric substrate is polished to thin it, resulting in a piezoelectric layer with a desired thickness. The thickness of this piezoelectric layer is, for example, 3 μm. Based on the description of step S12 above, the TTV of the pre-processed substrate processed in step S12 is kept to 1 μm or less, so the thickness of the piezoelectric layer obtained in step S16 can be controlled to 3±0.3 μm, i.e., in the range of 2.7 to 3.3 μm. For step S15, please refer to the description of step S13, but step S15 differs in that it is performed after bonding the polished pre-processed substrate to the piezoelectric substrate. In contrast, step S13 is performed before bonding the polished pre-treated substrate to the piezoelectric substrate. By performing the sandblasting treatment in step S15, the pre-treated substrate becomes the support substrate described above, and the treated surface becomes the back surface.

[0043] In the composite substrate manufacturing method according to the first embodiment of the present invention, the double-side polishing process in step S12 minimizes the TTV, while simultaneously reducing the transmittance of the resulting composite substrate in step S15. This reduces the TTV while avoiding alignment difficulties in subsequent manufacturing processes. Furthermore, in the composite substrate manufacturing method according to this embodiment, the back surface of the substrate is already roughened by the sandblasting process performed after step S14, ensuring the desired surface roughness. Therefore, thinning treatment is not required for the back surface of the pre-processed substrate or the resulting support substrate 11. As a result, warpage of the support substrate can be reduced, and the degree of warpage of the support substrate in the composite substrate 10 can be kept to 200 μm or less. This allows for a wider process window in the subsequent packaging and testing processes.

[0044] (Embodiment 2)

[0045] Prior to the proposal of the support substrate manufacturing method and composite substrate manufacturing method of the first embodiment described above in this application, conventional methods for fabricating a composite substrate using a support substrate and a piezoelectric substrate had a problem in that if the support substrate was too thin during the bonding process, fragments were likely to be generated during bonding. Therefore, conventional techniques typically used a relatively thick support substrate to bond to the piezoelectric substrate, and then thinned the surface of the support substrate opposite the piezoelectric substrate after bonding. However, this thinning process involves residual processing stress, and excessive warpage can occur if the remaining thickness of the support substrate is too thin. Excessive warpage can make automated packaging difficult. Therefore, conventional techniques typically maintained the support substrate at a thickness of 300 μm or more even after thinning, making it difficult to further reduce the thickness.

[0046] Therefore, when manufacturing a composite substrate by the manufacturing method of the support substrate or the manufacturing method of the composite substrate according to the first embodiment described above in the present application, it is not necessary to perform a thinning process on the support substrate, and it is possible to minimize warpage. As a result, it is possible to bond a thinner support substrate to the piezoelectric layer than before. However, if a support substrate with a thickness of 300 μm or less is directly manufactured using existing manufacturing processes, or if an existing support substrate is thinned to 300 μm or less and used, the support substrate will not be strong enough, and fragments will be more likely to be generated during the joining process with the piezoelectric substrate and subsequent manufacturing processes.

[0047] Therefore, in embodiment 2 of the present invention, a stronger support substrate 11 is provided. Fig. 1 is a schematic diagram showing the structure of support substrate 11, and Fig. 2 is a diagram showing the microstructure of a region of support substrate 11 according to embodiment 2 of the present invention. The size shown in Fig. 2 is 50 µm x 50 µm.

[0048] The material of the support substrate 11 is, for example, a polycrystalline material, specifically, polycrystalline magnesium aluminate spinel, polycrystalline sapphire, polycrystalline aluminum nitride, polycrystalline magnesium oxide, or polycrystalline quartz. The support substrate 11 contains a plurality of crystal grains, and the crystal grain density is, for example, 1000 grains / mm. 2 More than 2000 pieces / mm 2 More than 20000 pieces / mm 2 More than 80000 pieces / mm 2 More than 250000 pieces / mm 2 At least 1000 pieces / mm 2 The corresponding volume ratios of the grain boundaries are as shown in Table 1, and these grain densities and grain boundary volume ratios can be measured using an electron backscatter diffraction (EBSD) device. In this embodiment, the grain boundary volume occupancy rate in the support substrate 11 is 8 to 40%.

[0049] In the embodiment of the present invention, the crystal grain density is defined as the total number N (unit: pieces) of crystal grains present in a specific region on the surface of the support substrate 11 divided by the area S (unit: mm 2 ) and is defined as the crystal grain density in the support substrate 11. Therefore, when the crystal grain density is 1000 grains / mm 2 Above means N / S≧1000 pieces / mm 2 In actual measurements, a relatively large observation area in a microstructure image of the surface of the support substrate 11 is divided into a number of small areas, each of which is, for example, 50 μm × 50 μm, and the number of crystal grains in each small area is counted individually. The numbers of crystal grains in the small areas are then summed to calculate the total number of crystal grains in the large area, and the crystal grain density can be calculated based on this.

[0050] The multiple crystal grains in the support substrate 11 each have a different crystal orientation and are connected to each other via crystal grain boundaries. In other words, the crystal grain boundaries are the boundary surfaces between the crystal grains, and the crystal boundary volume can be understood as the volume of the gaps between the crystal grains. The crystal boundary volume fraction refers to the ratio of the crystal boundary volume to the total volume of a given region of the support substrate 11. In other words, the crystal boundary volume is the total volume V0 of the region minus the total volume V1 of the multiple crystal grains contained therein, and the crystal boundary volume V2 = V0 - V1. In this case, the crystal boundary volume fraction is expressed as (V0 - V1) / V0. The volume of each crystal grain in the support substrate 11 can be measured, for example, by electron backscatter diffraction (EBSD). In this embodiment, the crystal boundary volume occupancy rate (i.e., crystal boundary volume fraction; the percentage of the crystal boundary volume relative to the total volume in the material) of the support substrate 11 is, for example, 10%, 15%, 20%, 30%, 35%, 40%, etc. In this way, by controlling the numerical value of the crystal boundary volume in the support substrate 11 through design, the mechanical strength of the support substrate 11 can be optimized.

[0051] 1, the support substrate 11 has a main support surface 111 and an opposing back surface 112. The main support surface 111 is a surface for supporting a piezoelectric layer. The thickness of the support substrate 11 is defined by the distance between the main support surface 111 and the back surface 112. Table 1 lists data on the crystal grain density, crystal boundary volume fraction, thickness, and corresponding flexural strength for several support substrates 11 according to embodiment 2 of the present invention.

[0052] The flexural strength in this specification is measured based on the test method specified using a flexural strength testing machine manufactured by Jinan Zhongchuang Co., Ltd. Note that there is a variation of about 10% in the grain density.

[0053] [Table 1]

[0054] As is clear from Table 1, when the grain density is constant, the bending strength tends to improve as the thickness increases. For example, referring to the data of Experiments 1 to 3, when the grain density is about 200 particles / mm 2 When the grain boundary volume fraction is about 6%, the thickness must be 300 μm or more to achieve a bending strength of 180 MPa or more. On the other hand, in the data of Experiments 4 to 6, when the grain density is about 1000 particles / mm 2 If the grain boundary volume fraction is about 8%, a bending strength of 200 MPa or more can be secured even with a thickness of 250 μm. Furthermore, according to the data of Experiment No. 12, when the grain density is about 20,000 pieces / mm 2 When the grain boundary volume fraction is about 8%, the bending strength reaches 180 MPa or more even when the thickness is reduced to 200 μm. In addition, as is clear from a comparison of Experiments 3, 6, 9, 12, and 15, even with the same thickness, the grain density is about 80,000 particles / mm 2The support substrate 11 having the above structure exhibits a flexural strength exceeding 200 MPa. Therefore, the support substrate 11 according to the second embodiment of the present invention has superior flexural strength and can effectively prevent the generation of debris in the subsequent bonding process. This makes it possible to ensure manufacturing quality and production efficiency.

[0055] Based on the experimental results shown in Table 1 above, in some embodiments, the thickness of the support substrate 11 is 300 μm or less. For example, the thickness of the support substrate 11 can be 300 μm, 250 μm, 200 μm, etc. More specifically, the thickness of the support substrate 11 can be 200 μm or less. For example, the thickness can be 200 μm, 180 μm, 150 μm, etc. By thinning the support substrate 11 in this way, it is possible to further improve the heat dissipation performance of the product while maintaining manufacturing quality.

[0056] In some embodiments, the bending strength of the support substrate 11 provided herein is 180 MPa or more, which can prevent the generation of fragments. For example, the bending strength of the support substrate 11 may be 180 MPa, 200 MPa, 250 MPa, etc.

[0057] In some embodiments, the grain density in the support substrate 11 is 80,000 grains / mm 2 Furthermore, the bending strength of support substrate 11 is 200 MPa or more. With this configuration, even if support substrate 11 is manufactured to be even thinner, sufficient strength can be achieved, and the heat dissipation requirements of the product can be met while ensuring manufacturing quality.

[0058] In some embodiments, the Young's modulus of the support substrate 11 is 250 GPa or more. The Young's modulus is an index showing the deformation resistance of a material, and if the Young's modulus of the support substrate 11 is 250 GPa or more, it can have excellent strength characteristics.

[0059] In some embodiments, the grain size of the crystal grains in the support substrate 11 is preferably 10 μm or less.

[0060] The second embodiment of the present invention also provides a manufacturing method for manufacturing the above-mentioned support substrate 11. The manufacturing method includes the following steps.

[0061] Step S21: An ingot is produced using a crystalline material powder having a particle size of 0.1 to 1 μm.

[0062] Step S22: The ingot is diced and polished to obtain a diced substrate.

[0063] Step S23: The diced substrate is polished to obtain a support substrate.

[0064] In step S21, the crystalline material powder can be, for example, a powder of a polycrystalline material such as polycrystalline magnesium-aluminum spinel. In step S21, the polycrystalline material powder is formed into a green body by, for example, CIP (Cold Isostatic Pressing), and then the green body is sintered into an ingot by HIP (Hot Isostatic Pressing). The CIP temperature is 1400 to 1500°C, and the pressing pressure is 10,000 to 100,000 psi (pounds-force per square inch). The HIP temperature is 1650 to 1850°C, and the ambient pressure is 150 to 250 MPa. In step S22, the thickness of the cut substrate is 250 to 300 μm, and it is preferable to use silicon carbide (SiC) or boron carbide (B4C) powder with a grit size of 1200 to 1500 for polishing. In step S23, the polished surface is the surface used for bonding with the piezoelectric layer, and the surface roughness of the resulting bonding surface (i.e., the main support surface 111) is Sa≦0.6 nm and TTV≦2 μm. In this way, the final product thickness of the support substrate 11 is 200 to 250 μm.

[0065] In some embodiments, the TTV of the main support surface 111 of the support substrate 11 is 2 μm or less, and the surface roughness Sa of the main support surface 111 is 0.6 nm or less.

[0066] The method for manufacturing the support substrate 11 according to the embodiment of the present invention uses a crystalline material with a specific grain size, making it possible to manufacture the support substrate 11 and ensure appropriate mechanical strength even when the substrate is thin, thereby improving production efficiency and product yield.

[0067] In some embodiments, the method for manufacturing a support substrate according to embodiment 1 can be combined with the method for manufacturing support substrate 11 according to embodiment 2. For example, in step S22, after polishing both opposing surfaces of the cut substrate, sandblasting is performed on the surface that will later become back surface 112 of support substrate 11, thereby adjusting the surface roughness of back surface 112 to an appropriate state. This makes it possible to reduce warpage of support substrate 11.

[0068] Alternatively, in another embodiment, in step S22, polishing may be performed only on the surface to be bonded to the piezoelectric layer, and the support substrate 11 may be obtained as is. However, the present embodiment is not limited to this.

[0069] When the method for manufacturing a support substrate disclosed in embodiment 1 is combined with the method for manufacturing a support substrate 11 according to embodiment 2, the resulting support substrate 11 can have the same effects as the support substrate obtained in embodiment 1. Therefore, the support substrate 11 also has corresponding properties in terms of TTV, surface roughness Sz, amount of warpage, transmittance, etc.

[0070] For example, in some embodiments, the TTV of the major support surface 111 of the support substrate 11 can be 1 μm or less.

[0071] For example, in some embodiments, the amount of warping of the support substrate 11 is 200 μm or less.

[0072] For example, in some embodiments, the transmittance of the support substrate 11 in the wavelength band of 240 to 780 nm is 9% or less. Specifically, the transmittance in the wavelength band of less than 550 nm is 0.1% or less. This reduces the difficulty of subsequent processes.

[0073] For example, in some embodiments, the surface roughness Sz of the rear surface 112 of the support substrate 11 is 3 μm or more, and the surface roughness Sa of the rear surface 112 is 0.2 μm or more, which not only makes it possible to achieve a low degree of warping, but also enables effective reflection and scattering of body waves, thereby preventing the generation of noise.

[0074] For example, in some embodiments, the surface roughness Sz of the rear surface 112 of the support substrate 11 is equal to or greater than the average grain size of the crystal grains in the support substrate 11. For example, if the average grain size of the crystal grains in the support substrate 11 is 3 μm, the surface roughness Sz of the rear surface 112 of the support substrate 11 is equal to or greater than 3 μm. Furthermore, in some embodiments, the thickness of the support substrate 11 is equal to or greater than twice the maximum crystal grain size in the support substrate. For example, if the maximum crystal grain size in the support substrate 11 is 60 μm, the thickness of the support substrate 11 is equal to or greater than 120 μm.

[0075] Referring to FIG. 3 , a second embodiment of the present invention further provides a composite substrate 10. The composite substrate 10 includes a piezoelectric layer 12 and a support substrate 11 according to the second embodiment. The piezoelectric layer 12 is disposed on the support substrate 11. Specifically, the piezoelectric layer 12 is bonded to a main support surface 111 of the support substrate 11. The two may be directly bonded by van der Waals forces. The piezoelectric layer 12 may be made of, for example, lithium tantalate or lithium niobate. By using the support substrate 11 in the composite substrate 10, the strength of the support substrate 11 is high and the substrate is less susceptible to breakage, improving the yield of the composite substrate 10. Furthermore, the support substrate 11 can be formed thin, enabling the composite substrate 10 to achieve excellent heat dissipation.

[0076] Composite substrate 10 may be obtained, for example, by directly bonding support substrate 11 and piezoelectric layer 12, or by activating the bonding surfaces of support substrate 11 and piezoelectric layer 12 (activating the surfaces where they are bonded to each other) and then bonding them face-to-face at room temperature in a vacuum environment. In this case, the surface activation treatment bonds atoms on the surfaces of support substrate 11 and piezoelectric layer 12 to form covalent bonds, resulting in a highly bonded and almost completely integrated structure. This allows for a higher quality composite substrate 10 to be obtained.

[0077] In some embodiments, after bonding the support substrate 11 and the piezoelectric layer 12, the piezoelectric layer 12 may be further polished to reduce its thickness. In this case, the thickness of the piezoelectric layer 12 is, for example, 0.5 to 3.5 μm, and can be selected depending on the frequency band to be used. The piezoelectric layer 12 has, for example, a main surface 121 facing away from the support substrate 11. After the piezoelectric layer 12 is thinned and polished, an electrode can be formed directly on the main surface 121. This eliminates the need to further thin the support substrate 11, simplifying the process and saving materials.

[0078] Referring to FIG. 4 , a second embodiment of the present invention further provides an electronic device 100 including a support substrate 11 or a composite substrate 10 according to the above-described embodiment. In the composite substrate 10, the electronic device 100 may further include an electrode 20 provided on, for example, the main surface 121, and the electrode 20 may include, for example, an IDT electrode 21. IDT stands for interdigital transducer, and the electronic device 100 is, for example, a SAW device. The electronic device 100 includes the support substrate 11 according to the above-described embodiment. Since the support substrate 11 has high strength and is resistant to breakage, the yield of the electronic device 100 is high. Furthermore, since the support substrate 11 can be thinned, the electronic device 100 can also achieve excellent heat dissipation effects.

[0079] In some embodiments, in the electronic device 100, the crystal grain density in the support substrate 11 is 20,000 grains / mm 2 As described above, the thickness of the support substrate 11 is 250 μm or less.

[0080] Referring to Table 2, Table 2 shows the noise suppression status of the electronic device 100 manufactured using the support substrate 11 corresponding to Experiment Nos. 1 to 18 in Table 1, where a higher noise suppression ratio indicates a higher noise suppression effect. A noise suppression ratio of 100% means that there is no noise effect. The noise suppression ratio data in Table 2 is based on the pass rate obtained by a performance extraction test for a specified area of ​​the test sample (electronic device 100).

[0081] For example, the designated areas are the 21 areas numbered 1 to 21 shown in Fig. 9, and if the pass rate test results for all of these 21 areas are pass, the corresponding noise suppression ratio is 100%. The circled areas in Fig. 9 are the piezoelectric layer 12 in the electronic device 100.

[0082] [Table 2]

[0083] Referring to Tables 1 and 2 together, the data corresponding to Experiments 1 to 3 show that the grain density is approximately 200 grains / mm 2 It can be seen that because the grain boundary volume is small, the wave cannot be completely reflected during filtering, resulting in a certain amount of noise loss. In the data corresponding to Experiments 4 to 6, the grain density was approximately 1000 pieces / mm 2 Since the grain boundary volume is 8% or more, the reflection of the body waves is almost completely achieved, but there is still a small amount of noise loss. On the other hand, in the data corresponding to Experiments 10 to 18, the grain density is 20,000 pieces / mm 2 As mentioned above, it has been confirmed that due to the large volume of the grain boundaries, the body waves are completely reflected during filter operation, and no noise loss occurs. When body waves propagate, a certain amount of energy is lost when they pass through the grain boundaries, but if there are a sufficient number of grain boundaries in the support substrate, it is possible to completely suppress the conduction of body waves, thereby reducing noise.

[0084] Referring to FIG. 5, an electronic device 100 (composite substrate 10) according to another embodiment of the present invention may include an intermediate layer 13. The intermediate layer 13 is disposed between the piezoelectric layer 12 and the support substrate 11. Here, the acoustic velocity in the intermediate layer 13 is lower than that in the piezoelectric layer 12. That is, the propagation velocity of the body waves in the intermediate layer 13 is slower than that of the body waves propagating in the piezoelectric layer 12. In this embodiment, by providing the intermediate layer 13 with a low acoustic velocity, the acoustic velocity of the elastic waves as a whole can be reduced, and thus the elastic wave energy can be concentrated in the medium with a low acoustic velocity (i.e., the intermediate layer 13). As a result, loss is reduced and the Q value (quality factor) is improved.

[0085] The material of the intermediate layer 13 may be silicon dioxide, silicon nitride oxide, tantalum oxide, or a material containing any of these as its main components. In some embodiments, silicon dioxide is used as the intermediate layer 13, and lithium tantalate is used as the material of the piezoelectric layer 12. Lithium tantalate has a negative temperature coefficient of elasticity, while silicon dioxide has a positive temperature coefficient. Therefore, by combining these materials, the absolute value of the temperature coefficient of thermal conductivity (TCF) of the acoustic wave device can be reduced. Furthermore, the specific acoustic impedance of silicon dioxide is smaller than that of lithium tantalate, so the electromechanical coupling coefficient in electronic components can be increased.

[0086] In some embodiments, the thickness of the intermediate layer 13 is 0.5λ or more, where λ represents the wavelength of the acoustic wave determined based on the electrode period of the IDT electrode 21. Specifically, the thickness of the intermediate layer 13 may be 0.6 to 0.8λ. In some embodiments, the thickness of the piezoelectric layer 12 may be 2λ or less, specifically less than 1λ. In one specific embodiment, when λ is 2.25 μm, the thickness of the piezoelectric layer 12 is 0.1 to 1λ, and the thickness of the intermediate layer 13 is 0.6λ.

[0087] The electronic device 100 according to this embodiment may be configured by applying CSP (Chip Scale Package) or WLP (Wafer Level Package) sealing.

[0088] For example, FIG. 6 is a structural schematic diagram of an electronic device 100 employing CSP sealing. The electronic device 100 includes an element (comprising a composite substrate 10 and an electrode 20), a sealing substrate 30, a first sealing structure 41, and a first external terminal electrode 53. The sealing substrate 30 is disposed opposite the surface of the element on which the electrode 20 is formed (i.e., the main surface 121 of the piezoelectric layer 12), and a gap 60 is formed between the sealing substrate 30 and the main surface 121. The first sealing structure 41 is provided on the side of the sealing substrate 30 facing the element, covers the side surface of the element and the surface opposite to the surface facing the sealing substrate 30, and seals the gap 60 to hermetically seal the element. The electrode 20 includes an electrode pad 22 electrically connected to the IDT electrode 21. The electrode pad 22 is electrically connected via a bump 51 to a first conductive portion 52 formed in a wiring pattern on the sealing substrate 30. Furthermore, the first conductive portion 52 is electrically connected to a first external terminal electrode 53 formed on the surface of the sealing substrate 30 opposite the element, thereby enabling the electronic device 100 to be electrically connected to an external device via the first external terminal electrode 53.

[0089] Here, the materials of the sealing substrate 30 and the first sealing structure 41 can refer to substrate materials and sealing materials commonly used in existing CSP sealing. The electrode pads 22, the bumps 51, the first conductive portions 52, and the first external terminal electrodes 53 are all made of materials with excellent conductivity. This embodiment is not limited to the above examples.

[0090] FIG. 7 is a schematic diagram showing the structure of an electronic device 100 employing CSP sealing. The electronic device 100 includes an element (including a composite substrate 10 and an electrode 20), a lid 70, a second sealing structure 42, and a second external terminal electrode. The lid 70 is disposed opposite the surface of the element on which the electrode 20 is provided (i.e., the principal surface 121 of the piezoelectric layer 12), and a gap 60 is formed between the lid 70 and the principal surface 121. The electrode 20 includes an electrode pad 22 electrically connected to an IDT electrode 21. The area on the principal surface 121 where the IDT electrode 21 is provided is referred to as the effective area, and the second sealing structure 42 is disposed between the lid 70 and the element, surrounding this effective area. The second sealing structure 42 surrounds the electrode pad 22 to seal the element. The second external terminal electrode 55 provided on the surface of the lid body 70 opposite the element is connected to the electrode pad 22 via the second conductive portion 54 that penetrates the lid body 70 and the second sealing structure 42, allowing the electronic device 100 to be electrically connected to an external device through the second external terminal electrode 55.

[0091] The materials of the lid 70 and the second sealing structure 42 can refer to the lid material and sealing material currently used in WLP sealing. The electrode pad 22, the second conductive portion 54, and the second external terminal electrode 55 are all made of highly conductive materials. This embodiment is not limited to the above example.

[0092] Referring to FIG. 8 , the present invention provides a module 1000. The module 1000 includes a wiring substrate 700, a plurality of external connection terminals 701, an integrated circuit component 600, an electronic device 100 (including a composite substrate 10), an inductor 400, and a sealing portion 500. The plurality of external connection terminals 701 are formed on one side of the wiring substrate 700 and are mounted on a motherboard of a predetermined mobile communication terminal. The integrated circuit component 600 (which may also be referred to as an IC) is mounted inside the wiring substrate 700 and includes a switch circuit and a noise amplifier. The electronic device 100 is mounted on the main surface of the wiring substrate 700. The inductor 400 is used for impedance matching and is, for example, an integrated passive device (IPD). The sealing portion 500 is used to seal the plurality of electronic components, including the electronic device 100, on the wiring substrate 700.

[0093] The module 1000 provided by this embodiment includes the electronic device 100, that is, includes the support substrate 11, and has the same effects as the support substrate 11. A detailed description thereof will be omitted in this specification.

[0094] The above is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Although the present invention has been disclosed above as a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make slight changes or modifications based on the technical content disclosed above without departing from the technical scope of the present invention to achieve substantially the same embodiment. Therefore, any simple modifications, substantially equivalent changes and modifications made to the above embodiment based on the technical essence of the present invention are intended to be included in the technical scope of the present invention.

Claims

1. It is made of polycrystalline material and has a grain density of 1000 pieces / mm 2 The supporting substrate is characterized in that the volume ratio of the grain boundaries is 8% to 40%.

2. 2. The support substrate according to claim 1, having a thickness of 300 μm or less.

3. 2. The supporting substrate according to claim 1, having a bending strength of 180 MPa or more.

4. 2. The support substrate according to claim 1, wherein the material is any one of polycrystalline magnesium aluminate spinel, polycrystalline sapphire, polycrystalline aluminum nitride, polycrystalline magnesium oxide, and polycrystalline quartz.

5. Grain density is 80,000 pieces / mm 2 2. The supporting substrate according to claim 1, wherein the thickness is equal to or greater than 100 μm and the bending strength is 200 MPa or more.

6. 2. The support substrate according to claim 1, having a main support surface, the surface roughness of the support surface being 0.6 nm or less.

7. 2. The support substrate according to claim 1, having a main support surface, the main support surface having a TTV of 2 μm or less.

8. 2. The support substrate according to claim 1, wherein the Young's modulus is 250 GPa or more.

9. 2. The support substrate according to claim 1, wherein the transmittance in the wavelength range of 240 nm to 780 nm is less than 9%.

10. 10. The supporting substrate according to claim 9, wherein the transmittance in a wavelength band of 550 nm or less is 0.1% or less.

11. 11. A composite substrate comprising: a support substrate according to claim 1; and a piezoelectric layer provided on the support substrate.

12. An electronic device comprising the composite substrate according to claim 11.

13. 13. The electronic device according to claim 12, further comprising an IDT electrode, the IDT electrode being disposed on a main surface of the piezoelectric layer opposite to the support substrate.

14. 14. The electronic device according to claim 13, further comprising an intermediate layer disposed between the support substrate and the piezoelectric layer, wherein the acoustic velocity of the intermediate layer is lower than the acoustic velocity of the piezoelectric layer.

15. 15. The electronic device according to claim 14, wherein the thickness of the intermediate layer is 0.5λ or more, where λ is the wavelength of an acoustic wave defined based on the electrode period of the IDT electrode.

16. 14. The electronic device according to claim 13, wherein the thickness of the piezoelectric layer is 2λ or less, where λ is the wavelength of an acoustic wave defined based on the electrode period of the IDT electrode.

17. The grain density of the support substrate is 20,000 grains / mm 2 14. The electronic device according to claim 13, wherein the thickness of the support substrate is 250 μm or less.

18. 18. A module comprising a wiring board, a plurality of external connection terminals, an integrated circuit component, an inductor, and a sealing portion, and further comprising the electronic device according to any one of claims 12 to 17.

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