Thermal break for electrostatic discharge clamp and method of making same

Abstract

To provide a system and method for protecting an electrostatic discharge (ESD) clamp from a fault voltage when operating at a high temperature.SOLUTION: The circuit 200 includes a first power rail 210, a second power rail 212, an electrical protection component conductively coupled between the first and second power rails, the actFET cell 214 monitoring a voltage characteristic of the power rails and thereby detecting an electrical event, and a thermal protection circuit 216 conductively coupled between the power rails and to the electrical protection component. The thermal protection circuit includes a transistor BJTQ1 that is a temperature sensitive element that changes an electrical characteristic of the electrical protection component in response to a temperature change.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to electrostatic overstress circuits in semiconductor devices. [Background technology]

[0002] Integrated circuits (ICs) can be severely damaged by electrostatic overstress (EOS) events, including electrostatic discharge (ESD) events. Sources of EOS events include discharges from the human body or metal objects, power-on events, etc. During an EOS event, spikes in voltage and / or current at the IC can occur. The current and / or voltage spikes may have a shorter rise time than expected, which tends to place greater stress on the IC than normal. Rapid charging or discharging of voltage and / or current from the IC tends to stress the IC. This stress tends to degrade and / or damage the IC's components. ESD circuitry is coupled to the IC to mitigate the stress and damage caused by voltage and / or current spikes at the IC. Summary of the Invention

[0003] A device disclosed herein includes a first power rail, a second power rail, an electrical protection component conductively coupled between the first and second power rails, the electrical protection component configured to monitor voltage characteristics of the power rails and thereby detect electrical events, and a thermal protection component conductively coupled between the first and second power rails and to the electrical protection component, the thermal protection component including a temperature sensitive transistor configured to alter an electrical characteristic of the electrical protection component in response to a change in temperature of the device.

[0004] Further disclosed herein is a device including a power rail, a reference rail, an ESD protection component conductively coupled to the power rail and the reference rail, and a thermal protection component. The thermal protection component includes a first transistor including a first gate terminal conductively coupled to the reference rail, and a bipolar junction transistor (BJT). The BJT includes a base conductively coupled to the first transistor, a collector configured to provide a control signal to a control terminal of the ESD protection component, and an emitter conductively coupled to the reference rail, and the BJT is configured to modify the control signal in response to temperature changes of the device.

[0005] Also disclosed herein is a method of manufacturing an integrated circuit, the method including forming an ESD protection circuit on or above a substrate, the ESD protection circuit configured to operate in response to a transient electrical event on a power rail, and forming a thermal protection circuit on or above the substrate, the thermal protection circuit connected to a control terminal of the ESD protection circuit, the thermal protection circuit including a temperature sensitive component configured to adjust a control voltage at the control terminal in response to temperature changes of the integrated circuit.

[0006] The foregoing features and elements can be combined in any combination without exclusivity, unless expressly stated otherwise herein. These features and elements, as well as the operation of the disclosed examples, will become more apparent in light of the following description and accompanying drawings. [Brief explanation of the drawings]

[0007] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale and which illustrate various examples employing the principles described herein, but which are not intended to limit the scope of the claims.

[0008] [Figure 1] FIG. 2 is a functional diagram of a circuit, according to various examples.

[0009] [Figure 2]2 is a schematic diagram of a circuit in accordance with the functional diagram of FIG. 1 and various examples associated therewith.

[0010] [Figure 3] 2 is a schematic diagram of a circuit in accordance with the functional diagram of FIG. 1 and various examples associated therewith.

[0011] [Figure 4A] 3 is a graph illustrating circuit and voltage characteristics related to the functioning of the schematic diagram of FIG. 2 and various examples associated therewith. [Figure 4B] 3 is a graph illustrating circuit and voltage characteristics related to the functioning of the schematic diagram of FIG. 2 and various examples associated therewith.

[0012] [Figure 5A] 4 is a graph illustrating circuit and voltage characteristics related to the functioning of the schematic diagram of FIG. 3 and various examples associated therewith. [Figure 5B] 4 is a graph illustrating circuit and voltage characteristics related to the functioning of the schematic diagram of FIG. 3 and various examples associated therewith.

[0013] [Figure 6] 4 is a flowchart illustrating a method of forming an integrated circuit in accordance with the schematic diagrams of FIGS. 2 and 3 and various examples associated therewith.

[0014] [Figure 7] 3 illustrates various components of the schematic diagram of FIG. 2 and various example timing diagrams associated therewith.

[0015] [Figure 8] 4 illustrates various components of the schematic diagram of FIG. 3 and various example timing diagrams associated therewith. DETAILED DESCRIPTION OF THE INVENTION

[0016] The following detailed description is provided for purposes of illustration and not limitation. Benefits, advantages, and / or solutions to problems may be described with reference to various examples. The detailed description makes use of various examples and refers to the accompanying drawings, which illustrate various examples described herein. The drawings, descriptions, and examples are described in sufficient detail to enable the present disclosure to be practiced. The connecting lines shown in the various figures are intended to represent example functional relationships and / or physical couplings between the various elements, although it should be understood that other relationships and / or couplings are possible while remaining within the scope of the present disclosure. It should also be understood that for simplicity and clarity of the detailed description herein, the various figures may not be drawn to scale. It should also be understood that the descriptions and examples contained herein may employ logical, chemical, and / or mechanical changes to implement other examples without departing from the spirit and scope of the present disclosure. For example, steps recited in method and process descriptions may be performed in a different order, additional process steps may be added, and / or process steps may be eliminated while remaining within the scope of the present disclosure.

[0017] Reference to a singular item and / or example may include a plurality of items and / or examples, and reference to a plurality of items and / or examples may include a singular item and / or example. Similarly, reference to "a," "an," or "the" may include one or more of the referenced items unless otherwise specified. References to connected, coupled, fixed, attached, or similar words and / or phrases may include partially, fully, temporarily, removably, permanently, or other connection options. References to contact or similar phrases may include minimal contact or reduced contact. All ranges used herein may include both the upper and lower limits of the range, including percentage limitations disclosed herein. Recited values ​​may include at least expected variations in the art in which this disclosure is practiced, and may be understood and accepted to include values ​​within 10% of the recited value. Similarly, the use of "approximately," "about," "substantially," or other similar terms refers to an amount that is close to a stated value and can still achieve the stated or desired result and / or perform the stated or desired function, and can refer to an amount within 10% of the stated value.

[0018] The accompanying drawings and detailed description of the drawings may contain reference numerals that may be repeated among multiple examples. The repetition of reference numerals is intended for brevity and clarity of the description and is not intended to form or indicate a relationship between different examples described herein. The examples and descriptions provided herein are intended to be illustrative and not limiting beyond the scope of the claims. The use of terms such as "on" and "above" may indicate that a first feature is formed directly adjacent to a second feature, or may indicate a relationship between the first and second features without the first and second features being directly adjacent, for example, an additional feature may be formed between the two features.

[0019] For example, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "below," "below," "below," "above," "below," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downward," "upward," etc.) are used herein for ease of description and are not intended to limit the orientation of various components, systems, apparatus, devices, or other features. Accordingly, it is understood and appreciated that the use of spatially relative terms to embody the present disclosure in various different orientations remains within the scope of the present disclosure.

[0020] Rate-triggered ESD clamps or circuits can unintentionally turn on during rapid supply rail ramp-up (e.g., an ESD event), which can result in EOS failure. Some such ESD clamps include high-voltage transistors, such as drain-extended (DE) nMOS (DENMOS) transistors. The EOS robustness of an ESD clamp can be improved by designing the high-voltage transistor to have a safe operating area (SOA) margin higher than the operating voltage. That is, the high-voltage transistor can be oversized for the intended purpose of the application to provide a high SOA margin. However, some high-voltage transistors exhibit poor SOA performance at high temperatures (e.g., above about 150°C).

[0021] Disclosed herein are systems and methods for protecting ESD clamps from failure voltages when operating at high temperatures. In various examples, the described systems and methods provide circuit-based solutions for protecting the ESD clamp. In various examples, a thermal isolation component is included as part of the ESD clamp. In various examples, the thermal isolation modifies the electrical characteristics (e.g., gate voltage) of the ESD clamp in response to an increase in the temperature of the ESD clamp. In various examples, the thermal isolation component improves the failure voltage of the ESD clamp by reducing the gate drive of a high-voltage transistor in response to operation at high temperatures.

[0022] In various examples, thermal isolation components can be used to reduce leakage current through the ESD clamp, which can result from operation at high temperatures (e.g., from about 175° C. to about 225° C.). In various examples, by including thermal isolation components, high-power transistors can be made smaller than would otherwise be possible. That is, the SOA of the high-power transistors can be smaller, and therefore physically smaller, when the thermal isolation components are present.

[0023] In various examples, the thermal isolation component includes a pull-down circuit conductively coupled to the gate terminal of the high-voltage transistor. In various examples, the pull-down circuit includes a bipolar transistor, such as an NPN bipolar junction transistor (BJT). In various examples, the pull-down circuit is configured to weakly pull down the gate voltage of the high-voltage transistor at room temperature ("RT," e.g., about 27°C) and to turn on more strongly at elevated temperatures (e.g., about 175°C to about 225°C). In various examples, such operation tends to reduce the effective gate bias for the high-voltage transistor at elevated temperatures, thereby increasing the breakdown voltage of the high-power transistor.

[0024] Throughout this disclosure, reference is made to various concepts such as voltages, temperatures, time frames, physical dimensions, etc. It should be understood that these design parameters, operating ranges, and use ranges associated with each of the above concepts are intended to be illustrative and not limiting. In various examples, reference may be made to ambient, room temperature, elevated temperature, etc. These references are intended to be illustrative, as the temperature range that constitutes elevated or ambient temperature may be a matter of design choice or specific to the intended application. The descriptions and examples contained within this disclosure may be adapted to the particular integrated circuit being designed while remaining within the scope of the present disclosure.

[0025] 1, a functional diagram of a circuit 100 is illustrated in accordance with various examples of the present disclosure. The circuit 100 includes a first pad 102, a second pad 104, an ESD protection circuit 106, a load 108, a first power rail 110, and a second power rail 112. In various examples, the first power rail 110 may be configured to provide a positive voltage, a negative voltage, or a ground. In various examples, the second power rail 112 may be configured to provide a positive voltage, a negative voltage, or a ground. For purposes of explanation and simplicity, the first power rail 110 will be referred to as V dd and the second power rail 112 has a high voltage, sometimes referred to as V ss , a low voltage, sometimes referred to as a "voltage differential." In various examples, the load 108 may be a circuit or other component powered by a potential difference between a first power rail 110 and a second power rail 112. The ESD protection circuit 106 provides ESD or EOS protection for the load 108. As shown, the ESD protection circuit 106 is conductively coupled to the first power rail 110, the second power rail 112, and the load 108.

[0026] ESD protection circuit 106 further includes protection circuit 114 and thermal protection circuit 116. Protection circuit 114 and similar protection circuits may be referred to herein, without limitation, as actFET cells. Additional aspects of actFET cells are described in U.S. Patent No. 8,804,290, which is incorporated herein by reference in its entirety. [Patent Document 1] U.S. Patent No. 8,804,290

[0027] Both actFET cell 114 and thermal protection circuit 116 are conductively coupled to first power rail 110 and second power rail 112. actFET cell 114 is configured to protect load 108 from EOS events, including ESD events. Thermal protection circuit 116 is configured to protect actFET cell 114, and more broadly, ESD protection circuit 106, from the adverse effects of an increase in temperature of ESD protection circuit 106. Thermal protection circuit 116 is conductively coupled to actFET cell 114 by control line 118. Thermal protection circuit 116, in various examples, can send a signal to actFET cell 114 in response to the temperature of ESD protection circuit 106, including thermal protection circuit 116 and actFET cell 114, exceeding a predetermined threshold temperature.

[0028] During operation, power may be first applied to the circuit 100 (“power on”) by the first pad 102 and the second pad 104 (e.g., when the first pad 102 is connected to V dd (The first pad 110 and the second pad 104 are connected to ground.) In such operation, the voltage and / or current is expected to increase at a known rate. Under normal circumstances, the ESD protection circuit 106 does not affect the voltage and / or current between the first power rail 110 and the second power rail 112, and the load 108 can then operate as expected.

[0029] During fast transient events, such as ESD events, abnormal power-up events, and / or power supply noise, the voltage and / or current on the first power rail 110 may increase at a much faster rate than normal or spike for a short period of time. During such fast transient events, the ESD protection circuit 106 may be activated and configured to shunt current from the first power rail 110 to the second power rail 112 to rapidly reduce the magnitude of the voltage spike, thereby minimizing wear and / or damage to the load 108. However, when operating at high temperatures, such as may occur in an industrial or automotive environment, the SOA of the high-voltage transistors in the actFET cells 114 may decrease. As such, increased temperature may cause wear and / or damage to the components of the ESD protection circuit 106, including the actFET cells 114. Thermal protection circuit 116 may be configured to respond to this increase in temperature and adjust the operation of actFET cells 114 via control lines 118 to actFET cells 114 to reduce and / or minimize the effects of the increased temperature and avoid damage to ESD protection circuit 106, including actFET cells 114. Specifically, thermal protection circuit 116 is configured to reduce the turn-on sensitivity of actFET cells 114 at elevated temperatures, thereby partially disabling ESD protection circuit 106 at elevated temperatures. For simplicity, the functionality of ESD protection circuit 106 may be described below with respect to ESD events, although it should be understood that other fast transient events are also within the scope of this disclosure.

[0030] Referring now to FIG. 2, a schematic diagram of a circuit 200 is illustrated in accordance with various examples of the present disclosure. Circuit 200 includes several similar components to circuit 100 described above in FIG. 1, including a first pad 202, a second pad 204, an ESD protection circuit 206, a load 208, a first power rail 210, a second power rail 212, an actFET cell 214, a thermal protection circuit 216, and a control line 218, the descriptions of which may not be repeated below. Circuit 200, in various examples, may be particularly effective for mitigating problems associated with sudden changes in voltage EOS events as operating temperatures increase. Additional details of actFET cell 214 and thermal protection circuit 216 and their operation are described below, in accordance with various examples. It should be understood that the configurations of actFET cell 214 and thermal protection circuit 216 may differ from those illustrated and described below while remaining within the scope of the present disclosure.

[0031] The actFET cell 214 includes a first transistor M1, a second transistor M2, a first resistor R1, and a second resistor R2, interconnected as shown. The first transistor M1 includes a first gate terminal 220, a first drain terminal 222, a first body terminal 223, and a first source terminal 224. In various examples, the first transistor M1 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a power MOSFET, an insulated-gate bipolar transistor (IGBT), a laterally diffused MOSFET (LDMOS), a complementary metal-oxide semiconductor (CMOS), a drain-extended MOSFET (DEMOS), or another transistor. That is, the first transistor M1 may be designed to handle large currents, such as those associated with an ESD event. In various examples, the first transistor M1 may be a high-voltage transistor. In various examples, the SOA of the first transistor M1 may decrease as temperature increases due to the inherent physical effects of temperature on the transistor's construction materials. Generally, the physical dimensions of the first transistor M1 are related to the SOA, so that a transistor with a narrower SOA may be larger to provide a desired given breakdown voltage, while a transistor with a wider SOA may be smaller for the same breakdown voltage. Thus, in various examples, the SOA and physical dimensions may be selected for the intended application. The SOA of a semiconductor device (e.g., the first transistor M1) defines the voltage and current conditions under which the semiconductor device can operate without being damaged. Some high-voltage transistors (e.g., IGBTs) tend to experience significant degradation in SOA at temperatures above RT (e.g., above about 27°C).

[0032] In various examples, the second transistor M2 includes a second gate terminal 226, a second drain terminal 228, a second body terminal 229, and a second source terminal 230. In various examples, the second transistor M2 may be a field effect transistor (FET), a MOSFET, or another transistor. In various examples, the second transistor M2 may be designed to handle a smaller current than the first transistor M1. In various examples, the second transistor M2 may be a high-voltage transistor having a lower maximum voltage than the first transistor M1. The second transistor M2 also forms a source follower circuit with the first transistor M1, allowing the first transistor M1 to be biased at a higher voltage for a longer period of time than would otherwise be possible. For this reason, in various examples, the second transistor M2 may be physically smaller than the first transistor M1.

[0033] The thermal protection circuit 216 includes a third transistor M3, a bipolar junction transistor (BJT) Q1, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, interconnected as shown. The third transistor M3 includes a third gate terminal 232, a third drain terminal 234, a third body terminal 235, and a third source terminal 236. In various examples, the second transistor M2 and the third transistor M3 may be nominally identical instances of the same component, such as a FET, a MOSFET, or another transistor. In various examples, the third transistor M3 may be the same size as the second transistor M2 or may be different (e.g., smaller or larger) than the second transistor M2. The relatively small size of the third transistor M3 compared to the transistor M1 helps reduce the area of ​​the thermal protection circuit 216. The BJT Q1 includes a base 238, a collector 240, and an emitter 242. 2, the first transistor M1, the second transistor M2, and the third transistor M3 are n-type MOSFET (NMOS) transistors. In various examples, the first transistor M1, the second transistor M2, and / or the third transistor M3 may be p-type MOSFET (pMOS) transistors depending on the intended application.

[0034] 2 , for actFET cell 214, the second gate terminal 226 is conductively coupled to the second resistor R2 and the collector 240 via control line 218. The second drain terminal 228 is conductively coupled to the first power rail 210. The second body terminal 229 is conductively coupled to the first body terminal 223, the first source terminal 224, and the second power rail 212. The second source terminal 230 is conductively coupled to the first gate terminal 220 and the first resistor R1. The first gate terminal 220 is conductively coupled to the second source terminal 230 and the first resistor R1. The first drain terminal 222 is conductively coupled to the first power rail 210. The first body terminal 223 is conductively coupled to the second body terminal 229, the first source terminal 224, and the second power rail 212. The first source terminal 224 is conductively coupled to the first body terminal 223 and the second power rail 212. A first end of the first resistor R1 is conductively coupled to the first gate terminal 220 and the second source terminal 230, and a second end of the first resistor R1 is conductively coupled to the first power rail 210. A first end of the second resistor R2 is conductively coupled to the second gate terminal 226 and the collector 240, and a second end of the second resistor R2 is conductively coupled to the first power rail 210. While this is one implementation of an actFET cell 214, it should be understood that other rate-triggered circuit implementations are contemplated and within the scope of the present disclosure. In various other examples, the first body terminal 223 and / or the second body terminal 229 may be conductively coupled to the first power rail 210, the second power rail 212, and / or other power rails and / or ground rails, among other electrical components.

[0035] 2, with respect to the thermal protection circuit 216, the third gate terminal 232 is conductively coupled to the third resistor R3. The third drain terminal 234 is conductively coupled to the fourth resistor R4. The third body terminal 235 is conductively coupled to the third source terminal 236, the base 238, and the fifth resistor R5. The third source terminal 236 is conductively coupled to the third body terminal 235, the base 238, and the fifth resistor R5. The base 238 is conductively coupled to the third body terminal 235, the third source terminal 236, and the fifth resistor R5. The collector 240 is conductively coupled to the second gate terminal 226 and the second resistor R2 via the control line 218. The emitter 242 is conductively coupled to the second power rail 212. A first end of the third resistor R3 is conductively coupled to the third gate terminal 232, and a second end of the third resistor R3 is conductively coupled to the second power rail 212. A first end of the fourth resistor R4 is conductively coupled to the third drain terminal 234, and a second end of the fourth resistor R4 is conductively coupled to the first power rail 210. A first end of the fifth resistor R5 is conductively coupled to the third body terminal 235, the third source terminal 236, and the base 238, and a second end of the fifth resistor R5 is conductively coupled to the second power rail 212. This is one implementation of the thermal protection circuit 216, however it should be understood that other configurations are possible while remaining within the scope of the present disclosure. In various other examples, the third body terminal 235 may be conductively coupled to the first power rail 210, the second power rail 212, and / or other power and / or ground rails, among other electrical components. In various other examples, the base 238 of Q1 may be conductively coupled to other components and / or be part of a different circuit layout while remaining within the scope of the present disclosure.

[0036] 2, as previously described, actFET cell 214 provides the ESD protection functionality of ESD protection circuit 206, and thermal protection circuit 216 provides the thermal protection functionality of ESD protection circuit 206. As previously described, in various examples, second transistor M2 affects the bias voltage of first transistor M1. As will be explained in more detail below, during an ESD event, second transistor M2 turns on first, which creates a voltage drop across first resistor R1 and turns on first transistor M1.

[0037] A capacitance C is provided between the second gate terminal 226 and the second drain terminal 228. gd1 There are resistors R2 and C gd1 is V at the second gate terminal 226 dd During an ESD event, the voltage at the second gate terminal 226 of the first transistor M1 is applied across the second resistor R2 and the capacitance C gd1 As the voltage increases, the second transistor M2 provides current to the first resistor R1, turning on the first transistor M1. When the first transistor M1 is turned on, it provides a path to shunt current associated with the ESD event from the first power rail 210 to the second power rail 212. That is, during the sudden rise in voltage on the first power rail 210 caused by the ESD event, the capacitance C gd1is charged, causing the voltage at the second gate terminal 226 to exceed the threshold voltage of the second transistor M2, thereby turning on the second transistor M2. In response to the second transistor M2 turning on, current flows from the first power rail 210 through the second transistor M2 to the second power rail 212, more specifically from the second drain terminal 228 to the second source terminal 230. During such an ESD event, the first resistor R1 generates a voltage at the first gate terminal 220, and when the voltage at the first gate terminal 220 exceeds the threshold voltage of the first transistor M1, the first transistor M1 turns on. When the first transistor M1 turns on, the actFET cell 214 shunts current from the first power rail 210 to the second power rail 212 through the first transistor M1, more specifically from the first drain terminal 222 to the first source terminal 224. As mentioned above, the ESD protection circuit may have an operating environment with an ambient temperature that is implementation-dependent. The operating temperature of the ESD protection circuit 206 may reflect the ambient temperature and may also be affected by power dissipation during an ESD event as the first transistor M1 shunts current between the first power rail 210 and the second power rail 212. This power dissipation may increase the operating temperature of the actFET cell 214, particularly the first transistor M1.

[0038] To prevent damage to ESD protection circuit 206 due to a decrease in the breakdown voltage of first transistor M1 caused by an increase in temperature, thermal protection circuit 216 provides thermal shutdown capability to ESD protection circuit 206. That is, as the operating temperature of the IC increases, thermal protection circuit 216 provides a signal via control line 218 to actFET cell 214 to reduce the operating voltage of actFET cell 214 by reducing the voltage at second gate terminal 226, thereby tending to protect actFET cell 214, and more specifically, first transistor M1, from premature failure.

[0039] The operation of the thermal protection circuit 216 is similar to that of the actFET cell 214. During normal operation (e.g., when the IC is operating within its design limits), the thermal protection circuit 216 is inactive. During an ESD event, the thermal protection circuit 216 operates in the same manner as described above for the actFET cell 214. That is, the third transistor M3 has a gate-drain capacitance C between the third drain terminal 234 and the third gate terminal 232 that is charged in response to an ESD event. gd2 The third transistor M3, like the second transistor M2, is charged by the voltage on the first power rail 210 and provides current through the fifth resistor R5 to turn on the BJT Q1. At normal operating temperatures (e.g., room temperature), the BJT Q1 diverts a small amount of current or charge from the second resistor R2. The current diverted by the BJT Q1 may be small enough to allow the second transistor M2 to continue operating as described above. As the operating temperature increases, the gain current gain, or β, increases. Thus, as the temperature of the IC (including the temperature of the thermal protection circuit 216) increases, the pull-down strength of the BJT Q1 increases, diverting more current from the second resistor R2, effectively reducing the resistance between the second gate terminal 226 and the second power rail 212 (e.g., ground). This reduced resistance reduces the maximum gate voltage at the second gate terminal 226. By reducing the maximum gate voltage at the second gate terminal 226, the current through the first resistor R1 is also reduced, thereby reducing the peak gate voltage at the first gate terminal 220 during a voltage transient event. Therefore, it is expected that reducing the maximum gate voltage at the first gate terminal 220 during an ESD event may reduce or prevent damage to the actFET cell 214.

[0040] In various examples, the fourth resistor R4 of the thermal protection circuit 216 limits the gate voltage of the third transistor M3 (e.g., the third gate terminal 232) across a variety of different ramp rates of an ESD event to prevent overdrive and / or temperature insensitivity of the BJT Q1. That is, the fourth resistor R4 tends to reduce the sensitivity of the third transistor M3 to the voltage and / or current ramp rates of the thermal protection circuit 216 while maintaining the sensitivity of the third transistor M3 to increasing temperatures.

[0041] In various examples, actFET cell 214 and thermal protection circuit 216 may be a single integrated circuit. In some other examples, actFET cell 214 and thermal protection circuit 216 may be separate integrated circuits. In still other examples, the separate circuits may be thermally coupled such that the operation of thermal protection circuit 216 reflects the thermal environment of actFET cell 214.

[0042] As described above, thermal protection circuit 216 allows actFET cell 214 to operate over a wider temperature range than would otherwise be the case. As the operating temperature of ESD protection circuit 206 increases, the shunt current provided by BJT Q1 is treated as a control signal provided by control line 218 that modifies or adjusts the operating characteristics of actFET cell 214. Specifically, in various examples, the modified operating characteristics include a decrease in the peak gate voltage at first gate terminal 220, a decrease in the peak gate voltage at second gate terminal 226, and / or a decrease in the peak current flowing through second resistor R2. Thus, as the operating temperature of ESD protection circuit 206 increases, thermal protection circuit 216 draws more current from actFET cell 214, lowering the gate voltages of first transistor M1 and second transistor M2 and reducing the sensitivity of first transistor M1 to high temperatures.

[0043] 3, a schematic diagram of a circuit 300 is illustrated in accordance with various alternatives of the present disclosure. Circuit 300 includes similar components to circuit 200 described above in FIG. 2, including a first pad 302, a second pad 304, an ESD protection circuit 306, a load 308, a first power rail 310, a second power rail 312, an actFET cell 314, a thermal protection circuit 316, and a control line 318, the descriptions of which may not be repeated below. 2, including a first transistor M11, a second transistor M22, a first resistor R11, a second resistor R22, a first gate terminal 320, a first drain terminal 322, a first body terminal 323, a first source terminal 324, a second gate terminal 326, a second drain terminal 328, a second body terminal 329, and a second source terminal 330, the description of which may not be repeated below. While this is one implementation of actFET cell 314, it should be understood that other rate trigger circuit implementations are contemplated and within the scope of the present disclosure. In various other examples, first body terminal 323 and / or second body terminal 329 may be conductively coupled to first power rail 310, second power rail 312, and / or other power and / or ground rails, among other electrical components. 2 , including a third transistor M33, a BJT Q11, a third resistor R33, a fourth resistor R44, a fifth resistor R55, a third gate terminal 332, a third drain terminal 334, a third body terminal 335, a third source terminal 336, a base 338, a collector 340, and an emitter 342, the descriptions of which may not be repeated below. This is one implementation of the thermal protection circuit 316, but it should be understood that other configurations are possible while remaining within the scope of this disclosure. In various other examples, the third body terminal 335 may be conductively coupled to the first power rail 310, the second power rail 312, and / or other power and / or ground rails, among other electrical components.

[0044] In various examples, circuit 300 differs from circuit 200 in that collector 340 is conductively coupled to first gate terminal 320, second source terminal 330, and first resistor R11 via control line 318. This connection of control line 318 allows ESD protection circuit 306 to have a lower leakage current than ESD protection circuit 206.

[0045] During normal or quiescent operation (e.g., when no ESD event is occurring), leakage currents of low-power transistors, such as the second transistor M22, tend to be larger at higher temperatures. In response to an increase in temperature of the IC, leakage current through the second transistor M22 can cause the voltage at the first gate terminal 320 to increase, thereby partially turning on the first transistor M11. This turning on of the first transistor M11 can allow current to flow from the first power rail 310 to the second power rail 312 through the first transistor M11. This current path is connected to a V dd This may drain energy from the source, potentially shortening the operational life of the device of which circuit 300 is a part, and / or may cause circuit 300 to heat up, among other effects.

[0046] The thermal protection circuit 316 reduces leakage current through the actFET cell 314 that may otherwise occur during increased operating temperatures. In this regard, the control line 318, and more specifically the collector 340, is conductively coupled to the first gate terminal 320, thereby decreasing the gate bias of the first transistor M11, thereby decreasing the drain-to-source conductivity of the first transistor M11. As the temperature of the circuit 300 increases (either during an ESD event or during normal operation), leakage current through the first transistor M11, the second transistor M22, and the third transistor M33 may increase. As the leakage current through the second transistor M22 increases, a positive voltage develops across the first resistor R11 at the first gate terminal 320 of the first transistor M11. As the voltage at the first gate terminal 320 increases, the first transistor M11 turns on, and more current may leak through the first transistor M11. Similarly, increasing leakage current through third transistor M33 generates a positive voltage across fifth resistor R55 at base 338 of BJT Q11. As the voltage at base 338 increases at higher temperatures, BJT Q11 may conduct more current between collector 340 and emitter 342, thereby shunting some of the leakage current from second transistor M22 to ground (via control line 318) and decreasing the voltage at first gate terminal 320. Reducing the voltage at first gate terminal 320 reduces and / or eliminates leakage current through first transistor M11.

[0047] Thus, thermal protection circuit 316 can reduce or prevent leakage current through actFET cell 314 as operating temperatures increase. The sink current through control line 318 is considered a control signal provided by thermal protection circuit 316 that alters or adjusts the operating characteristics of actFET cell 314. Specifically, in various examples, control line 318, and more specifically collector 340, can be conductively coupled to first gate terminal 320, causing thermal protection circuit 316 to reduce the gate bias of first transistor M11 to reduce leakage current through actFET cell 314 as temperatures increase.

[0048] 4A and 4B, the operating voltage (V) of a fabricated ESD protection circuit in which the high voltage transistor is implemented as an IGBT is measured at two different temperatures. dd -V ss Graphs illustrating voltage (V) vs. current characteristics (VI) are shown. FIG. 4A shows a first graph 400 illustrating the VI characteristics of a baseline ESD protection circuit, as exemplified by actFET cell 214 without thermal protection circuit 216. First graph 400 has a voltage axis 402 (e.g., x-axis), a current axis 404 (e.g., y-axis), a first line 406, and a second line 408. First line 406 and second line 408 terminate at different maximum temperatures representing different failure voltages of the corresponding transistors. First line 406 includes a plurality of points illustrating the VI characteristics of a baseline ESD protection circuit operating at approximately RT (e.g., about 27°C). Second line 408 includes a plurality of points illustrating the VI characteristics of a baseline ESD protection circuit operating at a temperature consistent with operation in an industrial or automotive environment (e.g., about 200°C, referred to without limitation as "high temperature"). A first line 406 (RT) represents a first failure voltage, and a second line 408 (HT) represents a second, lower failure voltage. The difference between the first and second failure voltages represents an example baseline of the reduced failure voltage for an actFET, such as actFET cell 214, without the protection of a thermal protection circuit.

[0049] 4B shows a second graph 420 illustrating the VI characteristics of a thermally protected ESD protection circuit, as exemplified by ESD protection circuit 206 including both actFET cell 214 and thermal protection circuit 216. Second graph 420 has a voltage axis 422 (e.g., x-axis), a current axis 424 (e.g., y-axis), a first line 426, and a second line 428. Voltage axes 402 and 422 have the same scale. First line 426 includes a plurality of points representing the VI characteristics of a thermally protected ESD protection circuit operating at RT, and second line 428 includes a plurality of points representing the VI characteristics of a thermally protected ESD protection circuit operating at approximately 200°C. As before, first line 426 and second line 428 terminate at different maximum temperatures representing different failure voltages of the corresponding thermally protected ESD protection circuits. First line 426 shows a first failure voltage similar to (somewhat higher than) the voltage of first line 406 (unprotected actFET cell at RT). However, second line 428 shows a second, lower failure voltage that is relatively close to the failure voltage of first line 426 and significantly higher than the failure voltage of second line 408 (unprotected actFET cell at high temperature). The higher failure voltage of second line 428 represents a significant improvement in the expected reliability of ESD protection circuits, including thermal protection circuits exemplified by thermal protection circuit 216.

[0050] 5A and 5B, graphs illustrating simulated VI characteristics of leakage current as a function of operating voltage for a circuit including an actFET, such as exemplified by actFET cell 314, are shown. FIG. 5A shows a first graph 500 having a voltage axis 502 (e.g., x-axis), a leakage current axis 504 (e.g., y-axis), a first line 506, and a second line 508. The first graph 500 illustrates leakage current as a function of operating voltage for an actFET when operating at RT. The first line 506 illustrates the VI characteristics of an actFET in an ESD protection circuit without a thermal shutdown circuit. The second line 508 illustrates the VI characteristics of an ESD protection circuit including an actFET and a thermal protection circuit, exemplified by thermal protection circuit 316, interconnected with the actFET via a control line, such as exemplified by control line 318 in ESD protection circuit 306. As shown by lines 506 and 508, the leakage current of the ESD protection circuit, including the thermal protection circuit, increases only slightly with increasing operating voltage at RT.

[0051] FIG. 5B is a second graph 520 having a voltage axis 522 (e.g., x-axis), a leakage current axis 524 (e.g., y-axis), a first line 526, and a second line 528. The voltage axis 522 has the same scale as the voltage axis 502, and the leakage current axis 524 has the same scale as the leakage current axis 504. The second graph 520 illustrates the leakage current characteristics of an ESD protection circuit without (first line 526) and with (second line 528) a thermal protection circuit operating at 200° C. The leakage currents of both circuits are higher than the leakage current shown in the first graph 500, except near the top of the voltage range illustrated. However, the second line 528 shows that the leakage current of the ESD protection circuit with the thermal protection circuit is up to 20% less than the leakage current of the unprotected actFET illustrated by the first line 526. Therefore, in implementations where leakage current is a concern, such as low-power or battery-powered devices, thermal protection circuits can significantly extend operational lifetime.

[0052] Referring now to FIG. 6 , a flowchart of a method 600 for forming an ESD circuit including a protection circuit and a thermal shutdown circuit is illustrated in accordance with various examples of the present disclosure. In various examples, the method 600 can be used to form the ESD protection circuit 206 and / or the ESD protection circuit 306. In step 602, an ESD protection circuit is formed on a semiconductor substrate. The ESD protection circuit is configured to shunt current from a first power rail to a second power rail in the event of an ESD event. In step 604, a thermal protection circuit is formed on the substrate. The thermal protection circuit is electrically coupled to the ESD protection circuit, and the thermal protection circuit includes a temperature-sensitive component configured to modify an electrical characteristic of the ESD protection circuit in response to a change in temperature.

[0053] 7, a timing diagram 700 of an ESD protection circuit is shown, in accordance with various examples of the present disclosure. The timing diagram 700 illustrates the operation of the ESD protection circuit 206 described above with respect to FIG. 2 and is used for purposes of illustration and explanation only. That is, the timing diagram 700 has been simplified for clarity. As such, it should be understood that the timing diagram 700 may not fully illustrate the electrical signals of interest that may occur in an actual device. Instead, the timing diagram 700 illustrates the relative timing of different events that occur in the ESD protection circuit 206 in response to an ESD event.

[0054] The timing diagram 700 has a time axis 702 (e.g., x-axis) and a y-axis 704 that qualitatively reflects the magnitude of a device parameter of interest, such as voltage, current, or temperature. At time t0, the initial operating temperature of the ESD protection circuit is relatively constant and reflects the operating conditions of the device of which the ESD protection circuit is a part. For example, in an automotive or industrial implementation, the initial operating temperature may be 200°C or higher.

[0055] At time t1, the power supply voltage (e.g., the first power rail 210) increases to a first voltage as part of a transient event, such as an ESD event. The gate voltage of the second transistor M2 and the gate voltage of the third transistor M3 are both charged by the power supply voltage transient, thereby turning on the second transistor M2 and the third transistor M3, as described above. Current from the second transistor M2 generates a gate voltage in the first transistor M1, which turns on the first transistor M1 and shunts current between the power rails of the ESD protection circuit. Additionally, current from the third transistor M3 energizes a control terminal, e.g., the base, of the BJT Q1, turning on the BJT Q1.

[0056] At time t2, the temperature of the circuit may begin to increase. The increase above the initial operating temperature may depend on the length and magnitude of the ESD event and, therefore, the power dissipated by transistor M1. At time t3, BJT Q1 draws more current in response to the temperature increase. At time t4, the increased current drawn by BJT Q1 causes a voltage drop across second transistor M2, which in turn causes a voltage drop across first transistor M1 as previously described. The voltage drop across first transistor M1 protects first transistor M1 from damage caused by high voltage at higher temperatures (e.g., temperatures greater than approximately 175°C) by ensuring that first transistor M1 remains within its SOA. At time t4, the temperature reaches a steady state and the current drawn by BJT Q1 remains stable. At time t6, the transient event ends and the power supply voltage returns to its original state. First transistor M1, second transistor M2, third transistor M3, and BJT Q1 each turn off in response to the power supply voltage drop.

[0057] Referring now to FIG. 8 , a timing diagram 800 of an ESD protection circuit is illustrated in accordance with various examples of the present disclosure. Similar to the timing diagram 700 described above in FIG. 7 , timing diagram 800 illustrates the operation of ESD protection circuit 306 described above with respect to FIG. 3 and is used for illustrative and descriptive purposes only. Timing diagram 800 illustrates similar concepts to timing diagram 700, including voltage, current, and temperature of an ESD circuit (e.g., ESD protection circuit 106 and ESD protection circuit 306) as a function of time. Timing diagram 800 includes similar components to timing diagram 700, including a time axis 802 (e.g., x-axis) and a y-axis 804, although the values ​​on y-axis 804 may vary depending on the components. At time t0, the initial operating temperature of the ESD protection circuit is relatively constant, reflecting the operating conditions of the device of which the ESD protection circuit is a part.

[0058] At time t1, the power supply voltage (e.g., the first power rail 310) increases to a first voltage as part of a transient event, such as a power-on event. The first transistor M11, the second transistor M22, and the third transistor M33 operate in a similar manner as described above in response to the transient event. At time t2, in response to a steady power-on condition, the first transistor M11, the second transistor M22, and the third transistor M33 each turn off. At time t3, the temperature of the circuit begins to increase. As the temperature increases, the voltage at the gate of the first transistor M11 increases due to leakage current through the second transistor M22. Also, as described above, the current flowing through the BJT Q11 increases in response to the increase in temperature. At time t4, in response to the increase in current flowing through the BJT Q11, the gate voltage of the first transistor M11 begins to decrease. At time t5, the temperature reaches a steady state, the current drawn by BJT Q1 remains stable, and the gate voltage of first transistor M11 remains stable, thereby minimizing leakage current through first transistor M11. At time t6, the power supply voltage returns to its original state (e.g., powered off). First transistor M11 turns off, BJT Q11 turns off, and the temperature begins to drop.

[0059] Thus, the circuits and methods disclosed herein provide an ESD circuit that includes a protection component and a thermal blocking component to protect the circuit from ESD events. In various examples disclosed herein, the thermal blocking component protects the ESD circuit from damage caused by high temperatures by modifying an electrical characteristic (e.g., gate voltage) of the protection component in response to an increase in temperature. In various examples disclosed herein, the thermal blocking component reduces current leakage caused by higher operating temperatures of the ESD circuit by modifying an electrical characteristic (e.g., gate voltage) of the protection component in response to an increase in temperature.

[0060] Finally, it should be understood that any of the above-described concepts can be used alone or in combination with any or all of the other above-described concepts. While various examples have been disclosed and described, it is understood, appreciated, and / or considered that certain modifications are within the scope of the present disclosure. Accordingly, this description is not exhaustive and is not intended to limit the principles described or illustrated herein to the particular form. Many modifications and variations are possible in light of the above teachings.

Claims

1. A device, a first power rail; a second power rail; and an electrical protection component conductively coupled between the first power rail and the second power rail, the electrical protection component configured to monitor a voltage characteristic of the first power rail thereby detecting an electrical event; a thermal protection component conductively coupled between the power rails and to the electrical protection component, the thermal protection component including a temperature sensitive component configured to modify an electrical characteristic of the electrical protection component in response to a change in temperature of the device; Including, the device.

2. 10. The device of claim 1, wherein the temperature sensitive component is a bipolar junction transistor (BJT).

3. 10. The device of claim 1, wherein the electrical characteristic is a breakdown voltage of the electrical protection component.

4. 10. The device of claim 1, wherein the electrical characteristic is a bias voltage at a control terminal of the electrical protection component.

5. 3. The device of claim 2, wherein the BJT comprises: a base conductively coupled to the first power rail; a collector conductively coupled to a control terminal of the electrical protection component; an emitter conductively coupled to the second power rail; Devices containing:

6. 6. The device of claim 5, wherein the thermal protection component further comprises: a first transistor having a first gate terminal, a first source / drain terminal, and a second source / drain terminal, the second source / drain terminal conductively coupled to the base of the BJT; a first resistor conductively coupled between the first power rail and the first source / drain terminal of the first transistor; a second resistor conductively coupled between the first gate terminal of the first transistor and the second power rail; a third resistor conductively coupled between a node connecting the base of the BJT and the second source / drain terminal of the first transistor and the second power rail; Including, the device.

7. 7. The device of claim 6, wherein the first transistor is a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor.

8. 6. The device of claim 5, wherein the electrical protection component comprises: a first transistor having a first gate terminal; a second transistor having a second gate terminal; Including, a device, wherein the collector of the BJT is electrically coupled to the first gate terminal of the first transistor to adjust the voltage at the second gate terminal in response to the temperature change of the device.

9. 6. The device of claim 5, wherein the electrical protection component comprises: a first transistor having a first gate terminal; a second transistor having a second gate terminal; Including, The device, wherein the collector of the BJT is conductively coupled to the second gate terminal of the second transistor to vary a bias voltage of the second transistor in response to changes in the temperature of the device.

10. 2. The device of claim 1, wherein the monitored voltage characteristic of the first power rail is a transient change in voltage between the first power rail and the second power rail; the electrical protection component is configured to discharge a current associated with the transient change in voltage to the second power rail, provided that a characteristic of the transient change in voltage differs from a predetermined value by a predetermined difference value.

11. A device, Power rails; A reference rail; an electrostatic discharge (ESD) protection component conductively coupled to the power rail and the reference rail; a thermal protection component; Including, the thermal protection component a first transistor including a first gate terminal conductively coupled to the reference rail; a bipolar junction transistor (BJT); Including, The BJT is a base conductively coupled to the first transistor; a collector configured to provide a control signal to a control terminal of the ESD protection component; an emitter conductively coupled to the reference rail; wherein the BJT is configured to modify the control signal in response to a change in temperature of the device. device.

12. 12. The device of claim 11, the ESD protection component includes a second transistor having a second gate terminal; The device, wherein the collector is conductively coupled to the second gate terminal to modify the breakdown voltage of the ESD protection component in response to changes in the temperature of the device.

13. 13. The device of claim 12, the ESD protection component further includes a third transistor having a third gate terminal, the third gate terminal conductively coupled to the second transistor; the breakdown voltage of the ESD protection component is the breakdown voltage of the third transistor.

14. 12. The device of claim 11, the ESD protection component includes a second transistor having a second gate terminal; The device, wherein the collector is conductively coupled to the second gate terminal to vary the bias voltage of the second transistor in response to an increase in temperature of the device.

15. 15. The device of claim 14, wherein the ESD protection component further comprises a third transistor conductively connected to the second gate terminal of the second transistor, the third transistor configured to activate the second transistor in response to an ESD event on the power rail or the reference rail, the third transistor having a different threshold voltage than the second transistor.

16. 12. The device of claim 11, wherein the thermal protection component further comprises: a first resistor conductively coupled between the power rail and the first transistor; a second resistor conductively coupled between the reference rail and the first transistor; a third resistor conductively coupled between the first transistor, the base of the BJT, and the reference rail; Devices containing:

17. 1. A method of manufacturing an integrated circuit, comprising: forming an electrostatic discharge (ESD) protection circuit on or above the substrate, the ESD protection circuit configured to operate in response to a transient electrical event on a power rail; forming a thermal protection circuit on or above the substrate, the thermal protection circuit being connected to a control terminal of the ESD protection circuit; Including, The method, wherein the thermal protection circuit includes a temperature sensitive component configured to adjust a control voltage at the control terminal in response to a change in temperature of the integrated circuit.

18. 18. The method of claim 17, forming the thermal protection circuit on the substrate; forming a first transistor conductively coupled between the power rail and a ground rail; forming a bipolar junction transistor (BJT) conductively coupled between the first transistor and the ESD protection circuit; A method comprising:

19. 20. The method of claim 18, wherein forming the ESD protection circuit on the substrate includes forming a second transistor conductively coupled between the power rail and the ground rail and to a collector of the BJT.

20. 20. The method of claim 17, wherein forming the temperature sensitive component comprises forming a transistor selected from the group consisting of a bipolar junction transistor (BJT) and an insulated gate bipolar transistor (IGBT).

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