Active discharge method and power conversion system

Abstract

To provide an active discharge method and a power conversion system capable of safely discharging a bus capacitor without increasing cost.SOLUTION: The active discharge method is executed in a discharge period after a discharge instruction signal for instructing discharge of the bus capacitor Cbus is input. The active discharge method is a method of generating a PWM signal PS1H having a switching frequency for discharge different from a normal switching frequency and a PWM signal PS1L which is a complementary signal of the PWM signal PS1H toward the high-side gate driver GD-H and the low-side gate driver GD-L.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an active discharge method and a power conversion system. [Background technology]

[0002] Patent Document 1 discloses a gate driver IC including an isolator. The isolator has a primary coil driven by a transmitter circuit. The transmitter circuit uses an N-channel MOS transistor with a load resistor and a source resistor inserted therein to output high-speed, high-current pulses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-64106 Summary of the Invention [Problem to be solved by the invention]

[0004] Active discharge is generally known as a function for discharging the voltage of a bus capacitor to a safe voltage. For example, electric vehicles, unlike conventional gasoline-powered vehicles, are equipped with many high-voltage components. Therefore, electric vehicles require safety measures to protect people from high-voltage components, for example, in the event of a vehicle collision. As one such measure, electric vehicles use active discharge to discharge the bus capacitor that maintains the battery voltage in the event of a vehicle collision.

[0005] One possible method for achieving active discharge is to pass a through current through an existing power transistor. Another possible method is to add a circuit for active discharge. However, such a method has the risk of damaging the power transistor and increasing costs.

[0006] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A power conversion system according to one embodiment includes a first power supply line supplying a high-potential side power supply voltage, a second power supply line supplying a low-potential side power supply voltage, a bus capacitor, first and second power transistors, and first and second gate drivers. The bus capacitor is connected between the first power supply line and the second power supply line. The first power transistor is connected between the first power supply line and an output node. The second power transistor is connected between the second power supply line and the output node. The first gate driver controls the switching of the first power transistor with a first drive signal based on a first PWM signal. The second gate driver controls the switching of the second power transistor with a second drive signal based on a second PWM signal. Here, the active discharging method in the power conversion system is performed during a discharging period after inputting a discharge instruction signal instructing discharging of the bus capacitor. The active discharging method generates a first PWM signal having a discharging switching frequency different from a normal switching frequency, and a second PWM signal that is a complementary signal of the first PWM signal, for a first gate driver and a second gate driver. [Effects of the Invention]

[0008] According to the embodiment, the bus capacitor can be safely discharged without increasing costs. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a main part of a power conversion system according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram showing an example of the configuration of a vehicle to which the power conversion system in FIG. 1 is applied. [Figure 3] FIG. 3 is a schematic diagram showing a configuration example of an inverter device to which the power conversion system in FIG. 1 is applied. [Figure 4] FIG. 4 is a flow chart showing an example of the outline of the processing contents of the controller in FIGS. [Figure 5] FIG. 5 is a supplementary diagram to FIG. 4, and is a timing chart showing an example of main signals transmitted within the power conversion system. [Figure 6] FIG. 6 is a schematic diagram showing the operating principle of active discharge performed during the discharge period in FIG. [Figure 7A] 7A is a cross-sectional view showing an example of the configuration of a package in which the gate driver is mounted in FIG. [Figure 7B] FIG. 7B is a cross-sectional view showing an example of a package configuration different from that shown in FIG. 7A. [Figure 8A] FIG. 8A is a schematic diagram showing an example of an active discharging method in a power conversion system serving as a first comparative example. [Figure 8B] FIG. 8B is a schematic diagram showing an example of an active discharging method in a power conversion system serving as a second comparative example. [Figure 9] FIG. 9 is a schematic diagram showing an example of an implementation method in a power conversion system serving as a third comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0011] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] In the following embodiments, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET are also referred to as a pMOS transistor and an nMOS transistor, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to explain the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted.

[0013] <Power conversion system configuration> Fig. 1 is a schematic diagram showing an example of the configuration of the main parts of a power conversion system according to one embodiment. The power conversion system PCS shown in Fig. 1 includes a controller CTR, isolators ISO-H and ISO-L, gate drivers GD-H and GD-L, switching elements SW-H and SW-L, high-potential side power supply wiring PL-H and low-potential side power supply wiring PL-L, and a bus capacitor Cbus.

[0014] The high-potential side power supply wiring (first power supply wiring) PL-H transmits a power supply voltage (high-potential side power supply voltage) VP. The low-potential side power supply wiring (second power supply wiring) PL-L transmits a second ground voltage (low-potential side power supply voltage) GND2. The bus capacitor Cbus is connected between the high-potential side power supply wiring PL-H and the low-potential side power supply wiring PL-L and maintains the power supply voltage VP. The power supply voltage VP has a voltage value of, for example, several hundred volts or more with respect to the second ground voltage GND2.

[0015] The switching element SW-H provided on the high side, in other words, the upper arm, includes a power transistor (first power transistor) QT-H and a body diode DD-H. Similarly, the switching element SW-L provided on the low side, in other words, the lower arm, includes a power transistor (second power transistor) QT-L and a body diode DD-L. The power transistors QT-H and QT-L are, for example, n-channel MOSFETs formed on a Si substrate or a SiC substrate. However, the power transistors QT-H and QT-L may also be IGBTs (Insulated Gate Bipolar Transistors) or GaN FETs, etc.

[0016] 1, the power transistors QT-H and QT-L are n-channel MOSFETs. The power transistor QT-H is connected between a high-potential side power supply wiring PL-H and an output node Nout. The power transistor QT-L is connected between a low-potential side power supply wiring PL-L and the output node Nout. The power transistors QT-H and QT-L supply power to an external load, such as a motor (not shown), which is connected to the output node Nout.

[0017] More specifically, the source and drain of the power transistor QT-H are connected to the output node Nout and the high-potential side power supply wiring PL-H, respectively. The source and drain of the power transistor QT-L are connected to the low-potential side power supply wiring PL-L and the output node Nout, respectively. The body diode DD-H is connected between the source and drain of the power transistor QT-H with its source side serving as the anode. Similarly, the body diode DD-L is connected between the source and drain of the power transistor QT-L with its source side serving as the anode.

[0018] The gate driver (first gate driver) GD-H controls the switching of the power transistor QT-H with a gate drive signal (first drive signal) GS-H. The gate driver GD-H is supplied with an output voltage VO at an output node Nout and a power supply voltage VCC2 generated based on the output voltage VO. Similarly, the gate driver (second gate driver) GD-L controls the switching of the power transistor QT-L with a gate drive signal (second drive signal) GS-L. The gate driver GD-L is supplied with a second ground voltage GND2 and a power supply voltage VCC2 generated based on the second ground voltage GND2.

[0019] For example, the power supply voltage VCC2 is 15 [V] or 20 [V]. As a result, when the power transistors QT-H and QT-L are driven on, a voltage of 15 [V] or 20 [V] is input between the gate and source. On the other hand, although not shown, when the power transistors QT-H and QT-L are driven off, a negative voltage (-VEE) may be input between the gate and source to prevent false firing. In this case, for example, the power transistor QT-H inputs to its gate a voltage that is several volts lower than the output voltage VO. The power transistor QT-L inputs to its gate a voltage that is several volts lower than the second ground voltage GND2.

[0020] The controller CTR is, for example, a microcontroller unit (MCU) or an SoC (System on Chip). In this case, the controller CTR includes, for example, a processor PRC, a memory MEM, an analog-to-digital converter ADC, an external communication interface CIF, a PWM (Pulse Width Modulation) signal generator PWMG, and a bus BS connecting these. The processor PRC includes a CPU (Central Processing Unit) and may also include a DSP (Digital Signal Processor). The memory MEM is configured, for example, by combining a volatile memory such as an SRAM and a non-volatile memory such as a flash memory.

[0021] The memory MEM stores a control program PRG. The processor PRC executes the control program PRG. Based on the control program PRG, the controller CTR generates a PWM signal (first PWM signal) PS1H for the gate driver GD-H and a PWM signal (second PWM signal) PS1L for the gate driver GD-L. The controller CTR then controls the switching of the power transistors QT-H and QT-L via the isolators ISO-H and ISO-L and the gate drivers GD-H and GD-L, thereby controlling the power supplied to an external load.

[0022] As an example, the controller CTR performs feedback control of an external load based on the control program PRG. In this case, the controller CTR uses an analog-to-digital converter ADC to acquire a detection signal from the external load or the like, i.e., a feedback value, as a digital value. The controller CTR determines the duty ratios of the PWM signals PS1H and PS1L so that the error between the feedback value and a predetermined target value approaches zero. Then, the controller CTR uses a PWM signal generator PWMG to generate and output the PWM signals PS1H and PS1L having the determined duty ratios.

[0023] The controller CTR is supplied with a first ground voltage GND1 and a power supply voltage VCC1 generated based on the first ground voltage GND1. The power supply voltage VCC1 is, for example, 5 V. The controller CTR is not limited to a microcontroller unit or the like, and may be a programmable logic device such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like.

[0024] The isolator (first isolator) ISO-H transmits a PWM signal PS1H from the controller CTR to the gate driver GD-H while isolating the controller CTR from the gate driver GD-H. Specifically, the isolator ISO-H converts the PWM signal PS1H, which transitions based on a first ground voltage GND1, into a PWM signal PS2H, which transitions based on the ground voltage of the gate driver GD-H, i.e., the output voltage VO.

[0025] Similarly, the isolator (second isolator) ISO-L transmits the PWM signal PS1L from the controller CTR to the gate driver GD-L while isolating the controller CTR from the gate driver GD-L. Specifically, the isolator ISO-L converts the PWM signal PS1L, which transitions based on the first ground voltage GND1, into a PWM signal PS2L, which transitions based on the second ground voltage GND2 in the gate driver GD-L.

[0026] The gate driver GD-H receives a PWM signal PS2H from the isolator ISO-H and controls the switching of the power transistor QT-H based on the PWM signal PS2H and the PWM signal PS1H from the controller CTR. Similarly, the gate driver GD-L receives a PWM signal PS2L from the isolator ISO-L and controls the switching of the power transistor QT-L based on the PWM signal PS2L and the PWM signal PS1L from the controller CTR.

[0027] The isolators ISO-H and ISO-L are, for example, digital isolators that transmit signals using magnetic coupling. In this case, each of the isolators ISO-H and ISO-L includes, for example, a primary coil L1, a secondary coil L2, a transmission circuit TX, and a reception circuit RX. Taking the isolator ISO-H as an example, the transmission circuit TX drives the primary coil L1 based on a PWM signal PS1H. The reception circuit RX detects a signal magnetically coupled to the secondary coil L2 and outputs a PWM signal PS2H. However, the isolators ISO-H and ISO-L are not limited to this magnetic coupling method and may be configured using, for example, a capacitive coupling method.

[0028] Here, the control program PRG includes a program for performing active discharge, as will be described in detail later. Furthermore, although not necessarily limited to this, each of the isolators ISO-H and ISO-L is mounted in a package PKGa. Each of the gate drivers GD-H and GD-L is mounted in a package PKGb. That is, the gate driver GD-H and the isolator ISO-H are mounted in separate packages PKGb and PKGa. Similarly, the gate driver GD-L and the isolator ISO-L are mounted in separate packages PKGb and PKGa.

[0029] <Application to vehicles> Fig. 2 is a schematic diagram showing a configuration example of a vehicle VCL to which the power conversion system PCS in Fig. 1 is applied. The vehicle VCL shown in Fig. 2 is, for example, an automobile such as an HEV (Hybrid Electric Vehicle), a PHV (Plug-in Hybrid Vehicle), or a BEV (Battery Electric Vehicle). The vehicle VCL includes a main battery BATm, a motor MT and an inverter device INVD, a sub-battery BATs and a DC-DC converter DCDC, an on-board charger OBC, and multiple electronic control units ECU.

[0030] The main battery BATm generates a power supply voltage of 400 V or higher, for example, 400 V, 800 V, or 1200 V. The motor MT is, for example, a three-phase motor that drives the vehicle VCL. The inverter device INVD converts DC power from the main battery BATm into three-phase (u-phase, v-phase, and w-phase) AC power and drives the motor MT with the AC power. The sub-battery BATs generates a power supply voltage of, for example, 12 V. The DC-DC converter DCDC converts, for example, the voltage value of the main battery BATm to the voltage value of the sub-battery BATs and charges the sub-battery BATs using the converted voltage value.

[0031] The onboard charger OBC converts AC power obtained from a charging station into DC power to charge the main battery BATm. Multiple electronic control units ECU control the entire vehicle VCL, for example, based on detection signals from various sensors. One of the electronic control units ECU generates and outputs a discharge instruction signal DIS that instructs the bus capacitor Cbus shown in FIG. 1 to discharge. Specifically, the electronic control unit ECU generates the discharge instruction signal DIS as one of the collision detection signals, for example, when a collision of the vehicle VCL is detected by a collision detection sensor.

[0032] Here, the power conversion system PCS shown in Fig. 1 is applied to, for example, an inverter device INVD, a DC-DC converter DCDC, or an on-board charger OBC. For example, assume that the power conversion system PCS is applied to the inverter device INVD. Fig. 3 is a schematic diagram showing a configuration example of the inverter device INVD to which the power conversion system PCS in Fig. 1 is applied.

[0033] As shown in Fig. 3, the switching elements SW-H, SW-L, gate drivers GD-H, GD-L, and isolators ISO-H, ISO-L shown in Fig. 1 are provided for each of the three phases (u-phase, v-phase, w-phase) that make up the inverter device INVD. Meanwhile, a controller CTR is provided in common to all three phases. A three-phase output voltage VO(u, v, w) from the inverter INV, which is composed of the three-phase switching elements SW-H, SW-L, is applied to the motor MT, which is an external load of the inverter device INVD.

[0034] In detail, the controller CTR generates and outputs three-phase PWM signals PS1H(u,v,w) via a three-phase isolator ISO-H(u,v,w) to a three-phase gate driver GD-H(u,v,w) provided on the high side, and also generates and outputs three-phase PWM signals PS1L(u,v,w) via a three-phase isolator ISO-L(u,v,w) to a three-phase gate driver GD-L(u,v,w) provided on the low side.

[0035] The three-phase isolator ISO-H(u,v,w) provided on the high side inputs a three-phase PWM signal PS1H(u,v,w) and outputs a three-phase PWM signal PS2H(u,v,w). Similarly, the three-phase isolator ISO-L(u,v,w) provided on the low side inputs a three-phase PWM signal PS1L(u,v,w) and outputs a three-phase PWM signal PS2L(u,v,w).

[0036] A three-phase gate driver GD-H(u,v,w) provided on the high side controls the switching of three-phase switching elements SW-H(u,v,w) with three-phase gate drive signals GS-H(u,v,w) based on the input three-phase PWM signals PS2H(u,v,w). Each of the three-phase gate drivers GD-H(u,v,w) includes a pMOS transistor MP-H and an nMOS transistor MN-H. For example, consider a case where the u-phase gate driver GD-Hu is used to drive the gate of the power transistor QT-H included in the u-phase switching element SW-Hu.

[0037] In this case, the pMOS transistor MP-H pulls up the gate voltage of the power transistor QT-H to a power supply voltage VCC2. This power supply voltage VCC2 is determined based on the u-phase output voltage VOu. On the other hand, the nMOS transistor MN-H pulls down the gate voltage of the power transistor QT-H to a negative voltage (-VEE). This negative voltage (-VEE) is set to a voltage that is several volts or more lower than the u-phase output voltage VOu. Note that the pMOS transistor MP-H can also be replaced by a combination of an nMOS transistor and a boost power supply such as a charge pump that drives its gate.

[0038] The three-phase gate driver GD-L(u,v,w) provided on the low side controls the switching of the three-phase switching element SW-H(u,v,w) with a three-phase gate drive signal GS-L(u,v,w) based on the input three-phase PWM signal PS2L(u,v,w). Here, each of the three-phase gate drivers GD-L(u,v,w) also includes a pMOS transistor MP-L and an nMOS transistor MN-L. For example, consider a case where the u-phase gate driver GD-Lu is used to drive the gate of the power transistor QT-L included in the u-phase switching element SW-Lu.

[0039] In this case, the pMOS transistor MP-L pulls up the gate voltage of the power transistor QT-L to a power supply voltage VCC2. The power supply voltage VCC2 is determined based on the second ground voltage GND2. On the other hand, the nMOS transistor MN-L pulls down the gate voltage of the power transistor QT-L to a negative voltage (-VEE). The negative voltage (-VEE) is set to a voltage that is several volts or more lower than the second ground voltage GND2, for example. The pMOS transistor MP-L can also be configured by combining an nMOS transistor and a boosted power supply.

[0040] Furthermore, a power supply voltage VP is supplied to the three-phase switching elements SW-H (u, v, w) provided on the high side via a high-potential side power supply wiring PL-H. A second ground voltage GND2 is supplied to the three-phase switching elements SW-L (u, v, w) provided on the low side via a low-potential side power supply wiring PL-L. Here, the power supply voltage VP and the second ground voltage GND2 are generated by the main battery BATm.

[0041] In the example shown in FIG. 3, a contactor CSW, in other words, a switch, is inserted in the power supply path between the main battery BATm and the bus capacitor Cbus in the high-potential power supply wiring PL-H. The main battery BATm generates a bus voltage Vbus. When the contactor CSW is turned on, it transmits the bus voltage Vbus to the bus capacitor Cbus as a power supply voltage VP. When the vehicle VCL shown in FIG. 2 detects a collision, it turns off the contactor CSW and outputs a discharge instruction signal DIS. This allows active discharge to occur while the bus capacitor Cbus is isolated from the main battery BATm.

[0042] The DC-DC converter DCDC in FIG. 2 can be configured, for example, by a full-bridge or half-bridge LLC converter. For example, assume that the power conversion system PCS shown in FIG. 1 is applied to a full-bridge LLC converter. In this case, switching elements SW-H and SW-L, gate drivers GD-H and GD-L, and isolators ISO-H and ISO-L are provided for each of the two phases that drive the primary side of the transformer. Meanwhile, a controller CTR is provided in common for the two phases. The power supply voltage VP is generated by the main battery BATm. The output nodes Nout of the two phases are connected to both ends of the primary coil of the transformer, respectively.

[0043] Thus, to ensure safety, active discharge is required, particularly in a power conversion system PCS supplied with a high power supply voltage VP from the main battery BATm. Active discharge is a function that discharges the bus capacitor Cbus within a predetermined discharge time in response to a discharge instruction signal DIS, such as a collision detection signal. The discharge time is determined by the laws and regulations of each country. For example, the inverter device INVD is required to discharge the power supply voltage VP to 60 V or less within 3.0 seconds in response to the discharge instruction signal DIS.

[0044] <Active discharge method (comparison example)> Fig. 8A is a schematic diagram showing an example of an active discharge method in a power conversion system serving as a first comparative example. Similar to the power conversion system shown in Fig. 1, the power conversion system shown in Fig. 8A includes a bus capacitor Cbus, power transistors QT-H and QT-L, gate drivers GD-H and GD-L, isolators ISO-H and ISO-L, and a controller CTRc. In response to a discharge instruction signal DIS, the controller CTRc controls both power transistors QT-H and QT-L to the on state via the isolators ISO-H and ISO-L and the gate drivers GD-H and GD-L.

[0045] This allows the power conversion system to discharge the charge in the bus capacitor Cbus to the second ground voltage GND2 through the power transistors QT-H and QT-L in the ON state. However, this active discharge method causes a large through-current to flow through the power transistors QT-H and QT-L as a discharge current Idis. This may damage the power transistors QT-H and QT-L. Furthermore, gate drivers GD-H and GD-L with special functions for active discharge may be required. For example, gate drivers GD-H and GD-L often have various protection functions to prevent through-current. These various protection functions may need to be modified when performing active discharge.

[0046] Fig. 8B is a schematic diagram showing an example of an active discharge method in a power conversion system serving as a second comparative example. The power conversion system shown in Fig. 8B includes a bus capacitor Cbus, power transistors QT-H and QT-L, gate drivers GD-H and GD-L, isolators ISO-H and ISO-L, and a controller CTRd, similar to the case of Fig. 1. In addition, the power conversion system includes a resistor Rd, a power transistor QT-D, a gate driver GD-D, and an isolator ISO-D that constitute an active discharge circuit.

[0047] The resistor element Rd and the power transistor QT-D are connected in series between the high-potential side power supply wiring PL-H and the low-potential side power supply wiring PL-L. In response to a discharge instruction signal DIS, the controller CTRd controls the power transistor QT-D to the on state via the isolator ISO-D and the gate driver GD-D. This allows the power conversion system to discharge the charge in the bus capacitor Cbus to the second ground voltage GND2 via the on-state power transistor QT-D. However, this active discharge method may result in increased costs due to the addition of an active discharge circuit.

[0048] <Active Discharge Method (Embodiment)> Fig. 4 is a flow diagram showing an example of the general processing content of the controller CTR in Fig. 1 and Fig. 3. The flow shown in Fig. 4 is realized, for example, by the processor PRC in the controller CTR executing the control program PRG stored in the memory MEM. However, without being limited to this, the flow may also be realized, for example, by the operation of various logic circuits and the like that constitute the controller CTR.

[0049] Figure 5 is a supplementary diagram to Figure 4 and is a timing chart showing an example of the main signals transmitted within the power conversion system PCS. Figure 5 shows the u-phase PWM signals PS1Hu and PS1Lu from the controller CTR in Figure 3 and the gate drive signals GS-Hu and GS-Lu from the u-phase gate drivers GD-Hu and GD-Lu. Figure 5 also shows the v-phase PWM signals PS1Hv and PS1Lv from the controller CTR and the gate drive signals GS-Hv and GS-Lv from the v-phase gate drivers GD-Hv and GD-Lv. Note that signal transmission delays are ignored in Figure 5.

[0050] The PWM signals PS1Hu, PS1Lu, PS1Hv, and PS1Lv are signals that transition between a first ground voltage GND1 and a power supply voltage VCC1. The power supply voltage VCC1 is set to, for example, 5 V with respect to the first ground voltage GND1. The high-side gate drive signals GS-Hu and GS-Hv are signals that transition between a negative voltage (-VEE) with respect to the output voltages VOu and VOv, and the power supply voltage VCC2. The power supply voltage VCC2 is set to, for example, 20 V with respect to the output voltages VOu and VOv. The low-side gate drive signals GS-Lu and GS-Lv are signals that transition between a negative voltage (-VEE) with respect to the second ground voltage GND2, and the power supply voltage VCC2.

[0051] 4, during a normal operation period in which the discharge instruction signal DIS is not input (step S102: No), the controller CTR generates and outputs PWM signals PS1H and PH1L for normal operation for each phase (step S101). The PWM signals PS1H and PH1L for normal operation have a normal switching frequency FswN and a variable duty ratio. That is, as shown in FIG. 5, during the normal operation period Tn, a PWM period TswN based on the normal switching frequency FswN is used. The duty ratio is determined for each phase and for each PWM period TswN, for example, based on feedback control or the like.

[0052] 4, during the discharge period after receiving the discharge instruction signal DIS (step S102: Yes), the controller CTR generates and outputs common-phase PWM signals PS1H and PH1L for active discharge (step S103). The PWM signals PS1H and PH1L for active discharge have a discharging switching frequency FswD that is different from the normal switching frequency FswN. Furthermore, the PWM signals PS1H and PH1L for active discharge have a fixed duty ratio, such as 50%.

[0053] Then, the controller CTR repeats the process of step S103 until the discharge of the bus capacitor Cbus is completed (step S104). In step S104, the controller CTR may determine that the discharge is completed simply based on the length of the discharge period, for example, without monitoring the power supply voltage VP.

[0054] In the discharge period Td shown in FIG. 5, a PWM cycle TswD based on the discharge switching frequency FswD is used. The discharge switching frequency FswD is higher than the normal switching frequency FswN, for example, five times or more the normal switching frequency FswN. As a specific example, the normal switching frequency FswN and the discharge switching frequency FswD are 10 kHz and 100 kHz, respectively. Furthermore, in the discharge period Td, unlike the normal operation period Tn, a common-phase PWM signal with a fixed duty ratio of, for example, 50% is generated.

[0055] That is, the controller CTR generates high-side common-phase PWM signals (first PWM signals) PS1Hu and PS1Hv using a discharge switching frequency FswD and a fixed duty ratio such as 50%. The controller CTR also generates low-side common-phase PWM signals (second PWM signals) PS1Lu and PS1Lv. The low-side PWM signals PS1Lu and PS1Lv are complementary to the high-side PWM signals PS1Hu and PS1Hv.

[0056] The high-side gate drivers GD-Hu and GD-Hv generate gate drive signals GS-Hu and GS-Hv based on the high-side PWM signals PS1Hu and PS1Hv. Similarly, the low-side gate drivers GD-Lu and GD-Lv generate gate drive signals GS-Lu and GS-Lv based on the low-side PWM signals PS1Lu and PS1Lv.

[0057] As shown in Figure 5, the PWM period TswD is composed of a high-side on-period TonH during which the high-side power transistor QT-H is on and a low-side on-period TonL during which the low-side power transistor QT-L is on. Although not shown, a dead time is provided in the gate drive signals GS-Hu and GS-Lu of each phase, for example, the u-phase, to prevent overlap between the high-side on-period TonH and the low-side on-period TonL. This dead time is provided regardless of the normal operation period Tn and the discharge period Td.

[0058] Furthermore, the fixed duty ratio during the discharge period Td is not limited to 50% and may be several percent or more. For example, when the discharge switching frequency FswD is 100 kHz, the PWM period TswD is 10 μs. As will be described in detail below, in the active discharge method according to the embodiment, the lengths of the high-side on period TonH and the low-side on period TonL may be set to, for example, 40 ns or more based on "Ti." This length can be ensured even when the duty ratio is 1%, i.e., when the high-side on period TonH is 100 ns.

[0059] Fig. 6 is a schematic diagram showing the operating principle of active discharging performed during the discharging period Td in Fig. 5. Fig. 6 shows the power transistors QT-H, QT-L and gate drivers GD-H, GD-L for one phase, the bus capacitor Cbus, the contactor CSW, and the main battery BATm in Fig. 3. Fig. 6 also shows the operation during the high-side on period TonH in Fig. 5 and the operation during the period transitioning from the high-side on period TonH to the low-side on period TonL.

[0060] 6, for example, when a collision is detected, the contactor CSW is turned off, thereby isolating the bus capacitor Cbus from the main battery BATm. Furthermore, the power transistors QT-H and QT-L have gate-drain parasitic capacitances CgdH and CgdL, and drain-source parasitic capacitances CdsH and CdsL, respectively. In the system of this embodiment, high-speed switching control is used to charge and discharge these parasitic capacitances CgdH, CgdL, CdsH, and CdsL, thereby actively discharging the bus capacitor Cbus.

[0061] Specifically, first, during the high-side on period TonH, the gate voltage of the power transistor QT-H is set to the power supply voltage VCC2 via the pMOS transistor MP-H, which is in the on state. The output voltage VO is set to the power supply voltage VP via the power transistor QT-H, which is in the on state. Also, the gate voltage of the power transistor QT-L is set to a negative voltage (-VEE) via the nMOS transistor MN-L, which is in the on state.

[0062] As a result, the parasitic capacitance CgdH is charged with the gate side of the power transistor QT-H as the positive electrode. The parasitic capacitance CdsH is not particularly charged. On the other hand, the parasitic capacitance CgdL is charged with the drain side of the power transistor QT-L as the positive electrode. The parasitic capacitance CdsL is charged with the drain side of the power transistor QT-L as the positive electrode.

[0063] In this state, let us consider a transition from the high-side on period TonH to the low-side on period TonL. The gate voltage of the power transistor QT-H changes to a negative voltage (-VEE2) via the nMOS transistor MN-H, which is in the on state. As a result, a current I2 flows from the high-potential power supply wiring PL-H toward the parasitic capacitance CgdH. In addition, the output voltage VO changes to the second ground voltage GND2 via the power transistor QT-L, which is in the on state. As a result, a current I3 flows from the high-potential power supply wiring PL-H toward the parasitic capacitance CdsH.

[0064] As a result, a current I1, which is the sum of the currents I2 and I3, flows through the high-potential power supply wiring PL-H. The current I1 is expressed by equation (1) using the combined capacitance Coss (=CgdH+CdsH) of the parasitic capacitances CgdH and CdsH and the slew rate (dv / dt) of the voltage change in the parasitic capacitances CgdH and CdsH. Note that equation (1) is used when three-phase power transistors are simultaneously controlled to be on or off, as shown in Figures 3 and 5. I1 = Coss x (dv / dt) x 3 …(1)

[0065] Furthermore, if the time during which current I1 flows is "Ti," the average current Iave that flows through the high-potential side power supply wiring PL-H in one PWM period TswD is expressed by equation (2). That is, current I1 flows not only during the period when the high-side on period TonH transitions to the low-side on period TonL, but also during the period when the low-side on period TonL transitions to the high-side on period TonH. During the latter period, current I1 flows from the high-potential side power supply wiring PL-H toward the parasitic capacitances CgdL and CdsL via the power transistor QT-H that is in the on state. Iave = I1 x (Ti / TswD) x 2 …(2)

[0066] As a result, the discharge time Tdis required to reduce the power supply voltage VP to 60 V or less is expressed by equation (3). In equation (3), "CBUS" is the bus capacitance value of the bus capacitor Cbus. The bus capacitance value CBUS is usually 100 μF or more. "Vbus" is the bus voltage of the main battery BATm, and is the initial value of the power supply voltage VP before discharge. Tdis = CBUS x (Vbus - 60) / Iave…(3)

[0067] Representative numerical examples include the following values: Coss=1500[pF], dv / dt=20[V] / [ns] Ti=40[ns], TswD(FswD)=10[us](100[kHz]) CBUS=500[uF], Vbus=800[V] In this case, the current I1 based on formula (1) is 90 [A], the average current Iave based on formula (2) is 360 [mA], and the discharge time Tdis based on formula (3) is 1.0 [s].

[0068] In this way, by controlling the switching of the power transistors QT-H and QT-L using a high-speed switching frequency FswD of, for example, 100 kHz during the discharge period Td, active discharge can be completed in a discharge time Tdis of, for example, 1.0 s. This fully satisfies the standard requirements for active discharge, such as a discharge time of 3.0 s or less. In the above-mentioned numerical example, the required specifications can be met even if the switching frequency FswD is 50 kHz. In this case, the discharge time Tdis is 2.0 s.

[0069] During active discharge, the through current (discharge current Idis) shown in Figure 8A does not flow. Furthermore, if the isolators ISO-H, ISO-L and gate drivers GD-H, GD-L are compatible with the high-speed switching frequency FswD, there is no need to provide the gate drivers GD-H, GD-L with a special function for active discharge. Furthermore, there is no need for an additional active discharge circuit like the one shown in Figure 8B. As a result, the bus capacitor Cbus can be safely discharged without increasing costs.

[0070] <About mounting method (comparison example)> Fig. 9 is a schematic diagram showing an example of a mounting method for a power conversion system serving as a third comparative example. In the power conversion system shown in Fig. 9, the high-side isolator ISO-H and gate driver GD-H are mounted in the same package PKGc. The low-side isolator ISO-L and gate driver GD-L are also mounted in the same package PKGc.

[0071] Here, the package PKGc incorporating the isolators ISO-H and ISO-L cannot be equipped with a heat dissipation component such as a heat sink due to insulation standards, specifically creepage distance restrictions. For this reason, for example, a shrink small outline package (SSOP) without a heat sink is used for the package PKGc. Meanwhile, the gate drivers GD-H and GD-L generate more heat as the switching frequency increases. Therefore, as mentioned above, when using a high-speed switching frequency FswD such as 100 kHz, it is necessary to provide gate resistors Rg-H and Rg-L outside the package PKGc to dissipate heat from the package PKGc, as shown in FIG. 9.

[0072] To further improve heat dissipation, it is advisable to increase the resistance values ​​of the gate resistors Rg-H and Rg-L. However, the higher the resistance value, the lower the slew rate, which reduces the switch frequency that can be supported and increases switching loss. For this reason, with the configuration shown in Figure 9, it may be difficult to ensure sufficient heat dissipation and increase the switch frequency that can be supported at the same time.

[0073] <About the mounting method (formation)> On the other hand, in the power conversion system PCS shown in Fig. 1, the high-side gate driver GD-H and isolator ISO-H are mounted in separate packages PKGb and PKGa, respectively. Similarly, the low-side gate driver GD-L and isolator ISO-L are mounted in separate packages PKGb and PKGa, respectively.

[0074] 7A is a cross-sectional view showing an example of the configuration of a package PKGb in FIG. 1 on which gate drivers GD-H and GD-L are mounted. FIG. 7B is a cross-sectional view showing an example of the configuration of a package PKGb different from that shown in FIG. 7A. The packages PKGb1 and PKGb2 shown in FIGS. 7A and 7B are, for example, HQFPs (Quad Flat Packages with Heat Sinks). However, the packages PKGb1 and PKGb2 may also be HQFNs (Quad Flat Non-leaded packages with Heat Sinks) or HVQFNs (Very Thin Quad Flat Non-leaded packages with Heat Sinks), etc.

[0075] The package PKGb1 shown in FIG. 7A includes a semiconductor chip CP, a heat sink HS, leads LD, bonding wires BW, and a resin RN that seals them. The heat sink HS is an example of a heat dissipation member HM. The heat sink HS is installed so that a portion of the heat sink HS, specifically the area on the mounting surface side to the circuit board, is exposed to the outside. For example, a high-side gate driver GD-H is formed on the semiconductor chip CP. The semiconductor chip CP is mounted on the heat sink HS. The bonding wires BW connect the external terminals of the semiconductor chip CP to the leads LD.

[0076] The package PKGb2 shown in Fig. 7B has a configuration in which the heat sink HS in Fig. 7A is replaced with a die pad DP. The die pad DP, in other words, an ePAD (Exposed PAD), is another example of the heat dissipation member HM. Unlike a typical die pad, the die pad DP is also installed so that a portion of the die pad DP, specifically the area on the mounting surface side to the circuit board, is exposed to the outside.

[0077] By providing the heat dissipation member HM in this way, the allowable loss of the packages PKGb1 and PKGb2 can be increased to, for example, about 5 [W]. On the other hand, the allowable loss of the package PKGc, which does not include the heat dissipation member HM, is, for example, about 500 [mW]. Here, the power consumption Psw of the gate driver GD-H when using a switching frequency FswD of 100 [kHz] is expressed by equation (4). In equation (4), it is assumed that the charge Qg charged and discharged to the gate of the power transistor QT-H is 2 [uC] and the power supply voltage VCC2 is 20 [V]. In this case, the power consumption Psw is 4 [W]. Psw = FswD x Qg x VCC2 …(4)

[0078] As described above, by mounting the gate drivers GD-H, GD-L and the isolators ISO-H, ISO-L in separate packages, the heat dissipation material HM can be mounted on the package PKGb that mounts the gate drivers GD-H, GD-L. As a result, sufficient heat dissipation can be ensured without using gate resistor elements Rg-H, Rg-L as shown in Figure 9, and the compatible switching frequency can be increased.

[0079] The gate resistor element (first resistor element) Rg-H is inserted in the transmission path of the high-side gate drive signal GS-H. The gate resistor element Rg-L (second resistor element) is inserted in the transmission path of the low-side gate drive signal GS-L. The gate resistor elements Rg-H and Rg-L may play a role in reducing switching noise by adjusting the slew rate of the gate drive signals GS-H and GS-L. From this perspective, the gate resistor elements Rg-H and Rg-L may be provided as shown in FIG. 1.

[0080] However, in this case, the resistance value of the gate resistors Rg-H and Rg-L may be, for example, less than 5 ohms, or even less than 2 ohms. That is, in the configuration shown in FIG. 9, gate resistors Rg-H and Rg-L of about 5 ohms are provided to ensure heat dissipation assuming a normal switching frequency FswN, for example, 10 kHz. On the other hand, in a package equipped with a heat dissipation member HM, heat dissipation can be ensured without providing gate resistors Rg-H and Rg-L. Therefore, gate resistors Rg-H and Rg-L of less than 5 ohms may be provided to increase the switching frequency while reducing switching noise.

[0081] <Major effects of each embodiment> As described above, the method of the embodiment can realize active discharge by generating high-side and low-side PWM signals with a discharging switching frequency different from the normal switching frequency. This allows the bus capacitor to be safely discharged without increasing costs. Furthermore, in a power conversion system having an isolator and a gate driver, mounting the isolator and the gate driver in separate packages can increase the discharging switching frequency while ensuring heat dissipation of the gate driver. This shortens the discharge time of active discharge.

[0082] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0083] The above-mentioned program may be stored in a non-transitory, tangible, computer-readable recording medium and then supplied to a computer. Examples of such a recording medium include magnetic recording media such as hard disk drives, optical recording media such as DVDs (Digital Versatile Discs) and Blu-ray Discs, and semiconductor memories such as flash memories and SSDs (Solid State Drives). [Explanation of symbols]

[0084] BATm Main battery CSW Contactor CTR Controller Cbus bus capacitor DIS discharge instruction signal GD-H, GD-L gate drivers GND2 Second ground voltage (low potential power supply voltage) GS-H, GS-L gate drive signal HM heat dissipation material INVD Inverter device ISO-H, ISO-L isolators Nout output node PCS Power Conversion System PKGb package PL-H High potential side power supply wiring (first power supply wiring) PL-L Low potential side power supply wiring (second power supply wiring) PS1H,PS1L PWM signal QT-H, QT-L power transistors Rg-H, Rg-L gate resistor element Td Discharge period Tn Normal operating period VCL vehicle VP power supply voltage (high potential side power supply voltage) Vbus bus voltage

Claims

1. a first power supply line for supplying a high-potential power supply voltage; a second power supply line that supplies a low-potential power supply voltage; a bus capacitor connected between the first power supply wiring and the second power supply wiring; a first power transistor connected between the first power supply wiring and an output node; a second power transistor connected between the second power supply wiring and the output node; a first gate driver that controls switching of the first power transistor with a first drive signal based on a first PWM signal; a second gate driver that controls switching of the second power transistor with a second drive signal based on a second PWM signal; 1. An active discharge method in a power conversion system comprising: during a discharge period after inputting a discharge instruction signal instructing discharge of the bus capacitor, the first PWM signal having a switching frequency for discharge different from a normal switching frequency and the second PWM signal being a complementary signal of the first PWM signal are generated for the first gate driver and the second gate driver; Active discharge method.

2. 2. The active discharging method of claim 1, The discharging switching frequency is higher than the normal switching frequency. Active discharge method.

3. 3. The active discharging method according to claim 2, The discharging switching frequency is five times or more the normal switching frequency. Active discharge method.

4. 2. The active discharging method of claim 1, generating the first PWM signal and the second PWM signal having a fixed duty ratio during the discharge period; Active discharge method.

5. 2. The active discharging method of claim 1, The power conversion system includes a plurality of phases; each of the plurality of phases includes the first power transistor, the second power transistor, the first gate driver, and the second gate driver; generating, during the discharge period, the first PWM signal common to all phases for the plurality of first gate drivers included in the plurality of phases, and generating the second PWM signal common to all phases for the plurality of second gate drivers included in the plurality of phases; Active discharge method.

6. a first power supply line that transmits a high-potential power supply voltage; a second power supply line for transmitting a low-potential power supply voltage; a bus capacitor connected between the first power supply wiring and the second power supply wiring; a first power transistor connected between the first power supply wiring and an output node; a second power transistor connected between the second power supply wiring and the output node; a first gate driver that controls switching of the first power transistor with a first drive signal; a second gate driver that controls the switching of the second power transistor with a second drive signal; a controller that generates a first PWM signal for the first gate driver and a second PWM signal for the second gate driver; a first isolator that transmits the first PWM signal to the first gate driver while isolating the controller from the first gate driver; a second isolator that transmits the second PWM signal to the second gate driver while isolating the controller from the second gate driver; Equipped with the controller is configured to generate, during a discharge period after inputting a discharge instruction signal instructing discharge of the bus capacitor, the first PWM signal having a switching frequency for discharge different from a normal switching frequency, and the second PWM signal which is a complementary signal of the first PWM signal. Power conversion systems.

7. 7. The power conversion system according to claim 6, The discharging switching frequency is higher than the normal switching frequency. Power conversion systems.

8. 8. The power conversion system according to claim 7, The switching frequency for discharging is 50 kHz or more. Power conversion systems.

9. 7. The power conversion system according to claim 6, the controller is configured to generate the first PWM signal and the second PWM signal having a fixed duty ratio during the discharge period. Power conversion systems.

10. 7. The power conversion system according to claim 6, With multiple phases, each of the plurality of phases is provided with the first power transistor, the second power transistor, the first gate driver, the second gate driver, the first isolator, and the second isolator; the controller is configured to generate, during the discharge period, the first PWM signal common to all phases for the first gate drivers included in the plurality of phases, and generate the second PWM signal common to all phases for the second gate drivers included in the plurality of phases. Power conversion systems.

11. 7. The power conversion system according to claim 6, the first gate driver and the first isolator are mounted in separate packages; the second gate driver and the second isolator are mounted in separate packages; a package in which the first gate driver or the second gate driver is mounted includes a heat dissipation member that is installed so that a part of the area is exposed to the outside; Power conversion systems.

12. 12. The power conversion system according to claim 11, a first resistor element is inserted in a transmission path of the first drive signal; a second resistive element is inserted in a transmission path of the second drive signal; The resistance value of the first resistive element or the second resistive element is less than 5 ohms. Power conversion systems.

13. 7. The power conversion system according to claim 6, the power conversion system is for a vehicle, a battery that generates the high-potential side power supply voltage; a contactor inserted in a power supply path between the battery and the bus capacitor in the first power supply wiring; Equipped with When the vehicle detects a collision, the vehicle controls the contactor to be turned off and outputs the discharge instruction signal to the controller. Power conversion systems.

14. 14. The power conversion system according to claim 13, The high-potential power supply voltage is 400 V or more, The capacitance of the bus capacitor is 100 μF or more. Power conversion systems.

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