Test conductive film

Abstract

To provide a conductive film for testing.SOLUTION: A test conductive film according to the present invention includes a first metal layer and a second metal layer, wherein the second metal layer includes a circuit structure disposed on the first metal layer, a protrusion disposed on the circuit structure and protruding from the circuit structure, and an insulating layer disposed to surround the first metal layer and the second metal layer. The protrusion overlaps with the second metal layer, and at least a portion of the insulating layer is disposed between the second metal layer and the protrusion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a conductive test membrane, and more particularly to a cushioned conductive test membrane. [Background technology]

[0002] The probe card structure or test conductive film used in the test is usually used to connect the printed circuit board and the probe card structure or test conductive film so as to provide the force required for planarity well contact during the test process. Summary of the Invention [Problem to be solved by the invention]

[0003] However, conventional probe card structures or test conductive films are designed without a buffer between different metals, so they are prone to wear and tear when touched or bumped, and the test conductive films used in wafer testing can further abrade the wafer.

[0004] Therefore, the present inventors believed that the above drawbacks could be improved, and as a result of extensive research, they came up with the proposal of the present invention, which effectively improves the above problems through rational design.

[0005] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to solve the above problems. That is, an object of the present disclosure is to provide a test conductive film. [Means for solving the problem]

[0006] To achieve the above object, a test conductive film according to one embodiment of the present disclosure includes a first metal layer and a second metal layer, the second metal layer having a circuit structure disposed on the first metal layer, a protrusion disposed on the circuit structure and protruding from the circuit structure, and an insulating layer disposed so as to surround the first metal layer and the second metal layer, the protrusion overlapping the second metal layer, and at least a portion of the insulating layer being disposed between the second metal layer and the protrusion.

[0007] At least the following points will become clear from the description and drawings to be described later. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram illustrating an electronic measurement system including a test conductive film according to one embodiment of the present disclosure. [Figure 2] FIG. 1 is a top view showing a test conductive film according to one embodiment of the present disclosure. [Figure 3] FIG. 10 is a schematic diagram illustrating an electronic measurement system including a test conductive film according to another embodiment of the present disclosure. [Figure 4] 1A-1C are schematic diagrams of portions showing test conductive films according to different embodiments of the present disclosure. [Figure 5] 1A-1C are schematic diagrams of portions showing test conductive films according to different embodiments of the present disclosure. [Figure 6] 1A-1C are schematic diagrams of portions showing test conductive films according to different embodiments of the present disclosure. [Figure 7] 1A-1C are schematic diagrams of portions showing test conductive films according to different embodiments of the present disclosure. [Figure 8] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a test conductive film according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following describes in detail the embodiments of the present disclosure, but the present disclosure is not limited thereto, and various modifications are possible within the scope of the description, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0010] In this specification, unless otherwise specified, "including one" element does not mean "including one element" but may mean "including one or more elements." Furthermore, ordinal numbers such as "first" and "second" used in the specification and claims are used to modify the claimed elements and do not have any meaning in themselves, nor do they imply that the claimed elements have any ordinal number, nor do they indicate the order of a claimed element relative to other claimed elements, nor do they indicate the order of a manufacturing method. These ordinal numbers are merely used to clearly distinguish a claimed element with a component name from other claimed elements with the same component name.

[0011] Some terms used in the specification and claims of this disclosure refer to specific components. Those skilled in the art understand that the same components may be referred to by different names depending on the manufacturer of the electronic device. This specification does not distinguish between components that have the same function but different names. Hereinafter, in the specification and claims, terms such as "comprises," "includes," and "has" are open terms and are understood to mean "including, but not limited to." Thus, when the terms "comprises," "includes," and / or "has" are used in describing this disclosure, they refer to the presence of corresponding features, regions, steps, operations, and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0012] As used herein, the terms "about," "approximately," "substantially," and "roughly" typically mean within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Here, the given quantity is a rough estimate, and even in the absence of a specific explanation, the terms "about," "approximately," "substantially," and "roughly" may include the meanings of "about," "approximately," "substantially," and "roughly." Furthermore, the terms "a range from a first numerical value to a second numerical value" and "a range between a first numerical value and a second numerical value" indicate that the range includes the first numerical value, the second numerical value, and any other numerical values ​​therebetween.

[0013] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure belongs. Incidentally, these terms are terms defined in commonly used dictionaries, for example, and are understood to have a meaning consistent with the context and surrounding text of the relevant art and this disclosure, and should not be understood in an idealized or overly formal manner unless specifically defined.

[0014] Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" used in the examples describe the relative relationship between one component and another component in the drawings. It should be noted that if the device in the drawings is inverted and turned upside down, the component on the "lower" side will become the component on the "upper" side. When a corresponding component (e.g., a film layer or region) is "on another component," it may be directly on the other component, or there may be another component between the two. When a component is "directly on another component," there is no component between the two. Note that when a component is "on another component," the two components are in a vertical relationship from a bird's-eye view, and the component is above or below the other component, and the vertical relationship is determined by the orientation of the device.

[0015] In the present disclosure, distance, width, length, and thickness may be measured using an optical microscope or cross-sectional image measurement using an electron microscope, but the present disclosure is not limited thereto. Furthermore, when comparing two values ​​or directions, a certain degree of error may exist. When a first value is equal to a second value, this means that there may be an error of approximately 10% between the first and second values. When the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80° and 100°. When the first direction is parallel to the second direction, the angle between the first and second directions may be between 0° and 10°.

[0016] In the following specification, the technical methods provided in different embodiments can be used interchangeably, in combination, or mixed together, and constitute other embodiments as long as they do not deviate from the spirit of the present disclosure.

[0017] 1 is a schematic diagram illustrating an electronic measurement system including a test conductive film according to one embodiment of the present disclosure. In the example of FIG. 1, all components except for a control device 3 are shown in schematic cross-section.

[0018] As shown in FIG. 1 , the electronic measurement system according to the present disclosure includes a test conductive film 1, a test head 2 having a circuit board 21 disposed thereon and electrically connected to the circuit board 21 via an electrical connection element 22, and a control device 3 electrically connected to the test head 2. In one embodiment, the electrical connection element 22 may be a solder ball, but the present disclosure is not limited thereto. When detecting a device under test 4 using the electronic measurement system shown in FIG. 1 , the control device 3 can control the test head 2 to move toward the device under test 4 so that the test conductive film 1 connected to the test head 2 contacts the device under test 4. The control device 3 can provide a detection signal to the test head 2, and the test head 2 transmits the detection signal to the test conductive film 1 to detect the device under test 4. The obtained detection signal is then transmitted by the test conductive film 1 to the test head 2 and then to the control device 3.

[0019] In one embodiment, DUT 4 may be a semiconductor device such as a wafer. In other embodiments, DUT 4 may be an electronic device, such as a display device, a sensing device, an antenna device, a touch device, a tile device, or other suitable electronic device, but the present disclosure is not limited thereto. The display device according to the present disclosure may be a non-emissive display device or a self-emissive display device, such as a liquid crystal display (LCD), a cholesteric liquid crystal display (CLC), an electrophoretic display (EPD), an organic light emitting diode display (OLED), or an LED display (LED), but the present disclosure is not limited thereto. The display device may include a light emitting diode (LED), a light conversion layer, or other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a mini LED, a micro LED, or a quantum dot LED (QLED, QDLED), but the present disclosure is not limited thereto. The light conversion layer may include a wavelength conversion material and / or a light filtering material, and the light conversion layer may include, for example, a fluorescence, a phosphor, a quantum dot (QD), other suitable materials, or a combination of the above, but the present disclosure is not limited thereto. The sensing device may include, for example, a biosensor, a touch control sensor, a fingerprint sensor, other suitable sensors, or a combination of the above types of sensors. The antenna device may be, for example, a liquid crystal antenna or other types of antennas, but the present disclosure is not limited thereto. The tile device may include, for example, a tile display device or a tile antenna device, but the present disclosure is not limited thereto.The electronic device may include an electronic element, which may be a passive element, an active element, or a combination thereof, such as a capacitor, a resistor, an inductor, a variable capacitance diode, a variable capacitor, a filter, a diode, a transistor, a sensor, a microelectromechanical system (MEMS), a chip, etc., but the present disclosure is not limited thereto. It should be noted that the electronic device according to the present disclosure may be any combination of the above-mentioned devices, but the present disclosure is not limited thereto. The electronic device according to the present disclosure may be applied to, for example, a power module or a semiconductor package device, but the present disclosure is not limited thereto. The electronic device may include, but is not limited to, a system on a chip (SoC), a system in a package (SiP), an antenna in package (AiP), or any combination of the above-mentioned devices.

[0020] The configuration of the test conductive film 1 of the present disclosure will be described in detail below.

[0021] In one embodiment, a test conductive film 1 according to the present disclosure includes a first metal layer 121 and a second metal layer 122. The second metal layer 122 includes a circuit structure 12 disposed on the first metal layer 121, a protrusion 13 disposed on the circuit structure 12 and protruding from the circuit structure 12, and an insulating layer 14 disposed to surround the first metal layer 121 and the second metal layer 122. The protrusion 13 overlaps the second metal layer 122, and at least a portion of the insulating layer 14 is disposed between the second metal layer 122 and the protrusion 13 (see FIG. 1 ).

[0022] In the present disclosure, the test conductive film 1 may further include another insulating layer 11 and a third metal layer 15, which may be disposed under the circuit structure 12, and the third metal layer 15 may be electrically connected to the circuit structure 12. In other embodiments of the present disclosure, the test conductive film 1 may further include another insulating layer and a metal layer (not shown), achieving the purpose of further expanding the circuit rewiring and / or circuit fan-out area.

[0023] In the present disclosure, the material of insulating layer 11 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, ceramic material, glass, silicon wafer, or other suitable materials or combinations thereof, and the present disclosure is not limited thereto.

[0024] In the present disclosure, the elongation percentage of the insulating layer 14 may range from 20% to 900%. When the elongation percentage of the insulating layer 14 is within the aforementioned range, by disposing at least a portion of the insulating layer 14 between the second metal layer 122 and the protrusion 13, the at least a portion of the insulating layer 14 can provide elastic-like cushioning properties, reducing the effects of contact wear on the test conductive film 1 and improving the durability of the test conductive film 1. In some embodiments, the stiffness of the insulating layer 11 may be higher than that of the insulating layer 14, and the elongation percentage of the insulating layer 11 may be lower than that of the insulating layer 14, allowing the insulating layer 11 to provide support and extend the service life of the test conductive film 1, but the present disclosure is not limited thereto.

[0025] In the present disclosure, the elongation of the insulating layer 14 can be determined using a universal testing machine. Here, the elongation of the insulating layer 14 may be its elongation at break, which is a percentage of the total elongation at break and can be used as an indicator for comparing the plasticity of materials. The higher the elongation at break, the more plastic the plastic material. Alternatively, the elongation of the insulating layer 14 may be its elongation at yield, which is the elongation ratio at the yield point, which is the maximum elongation before permanent deformation occurs.

[0026] In the present disclosure, the elongation of the insulating layer 14 can be tested using other test methods, such as, but not limited to, ASTM D3039 / D3039M (Standard Test Methods for Polymer Matrix Composites), ASTM D638 (Standard Test Methods for Tensile Properties of Plastic Materials), ASTM D828 (Standard Test Methods for Paper and Paperboard Using a Constant Rate of Elongation Apparatus), ASTM D882 (Standard Test Methods for Tensile Properties of Sheets of Plastic Materials), or ISO 37 (Vulcanized or Thermoplastic Rubber - Determination of Tensile Stress and Strain Properties).

[0027] In the present disclosure, the insulating layer 14 may include polyimide, photoresist, silane, polymer, epoxy resin, combinations of the above, or other suitable materials. In one embodiment, the insulating layer 14 may include polyimide. However, the present disclosure is not limited thereto, and any material for the insulating layer 14 may provide elastic cushioning properties as long as its elongation meets the aforementioned conditions.

[0028] In the present disclosure, the first metal layer 121, the second metal layer 122, and the third metal layer 15 may have a single-layer or multi-layer structure, and the material may include a metal material, a metal oxide material, an alloy thereof, or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), aluminum zinc oxide (AZO), or a combination thereof, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the material of the first metal layer 121 is copper. In one embodiment of the present disclosure, the material of the second metal layer 122 is nickel.

[0029] In the present disclosure, the at least partial insulating layer 14 has a first thickness T1, and the second metal layer 122 has a second thickness T2, where the ratio of the first thickness T1 to the second thickness T2 is 0.1 or more and 0.5 or less (0.1≦T1 / T2≦0.5). The second metal layer 122 has a recess 122a, and the at least partial insulating layer 14 is disposed in the recess 122a. The recess 122a is located on a sidewall 122b of the second metal layer 122. According to some embodiments, the extension direction of the recess 122a is perpendicular to the normal direction (Z direction) of the test conductive film 1, and the design of the gradually changing width of the recess 122a can provide buffering properties.

[0030] In the present disclosure, when the at least partial insulating layer 14 is disposed in the recess 122a in the sidewall 122b of the second metal layer 122, the insulating layer 14 has a certain elongation rate, and therefore the at least partial insulating layer 14 can provide cushioning properties similar to an elastic body, thereby reducing the influence of contact wear on the test conductive film 1 and improving the durability of the test conductive film 1. Specifically, in the normal direction (Z direction) of the test conductive film 1, the at least partial second metal layer 122 and the at least partial protrusion 13, and the at least partial insulating layer 14, are overlapped with each other to form a sandwich structure. That is, the at least partial insulating layer 14 is disposed between the at least partial second metal layer 122 and the at least partial protrusion 13.

[0031] In the present disclosure, the first thickness T1 of the at least partial insulating layer 14 is the maximum thickness of the at least partial insulating layer 14 from the surface 121c of the first metal layer 121 to the protrusion 13. In the present disclosure, the "first thickness T1 of the at least partial insulating layer 14" and the "second thickness T2 of the second metal layer 122" are the maximum thicknesses of the at least partial insulating layer 14 (more specifically, the insulating layer 14 disposed in the recess 122a on the sidewall 122b of the second metal layer 122) and the second metal layer 122, respectively, measured in the normal direction (e.g., Z direction) of the test conductive film 1.

[0032] In the present disclosure, the protrusion 13 may include a first layer 131 and a second layer 132. The first layer 131 is disposed between the second metal layer 122 and the second layer 132, and the thickness T4 of the second layer 132 is less than the thickness T3 of the first layer 131 (i.e., T4 < T3). In the present disclosure, the "thickness T4 of the second layer 132" and the "thickness T2 of the first layer 131" are the maximum thicknesses measured for the first layer 131 and the second layer 132 respectively in the normal direction of the test conductive film 1 (e.g., the extending direction of the virtual line L1 along the Z direction).

[0033] In the present disclosure, the second layer 132 of the protrusion 13 is in contact with the side portion 131a of the first layer 131 of the protrusion 13. In an embodiment of the present disclosure, the second layer 132 of the protrusion 13 can at least partially cover the side portion 131a of the first layer 131 exposed outside the insulating layer 14. In an embodiment of the present disclosure, the second layer 132 of the protrusion 13 can completely cover the side portion 131a of the first layer 131 exposed outside the insulating layer 14.

[0034] In the present disclosure, the materials of the first layer 131 and the second layer 132 of the protrusion 13 may each be a metal material. For example, they may include gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, or alloys thereof. In an embodiment of the present disclosure, the hardness (HD2) of the second layer 132 of the protrusion 13 may be less than the hardness (HD1) of the first layer 131 of the protrusion 13 (i.e., HD2 < HD1). In an embodiment of the present disclosure, the inefficiency (R2) of the second layer 132 of the protrusion 13 may be less than the inefficiency (R1) of the first layer 131 of the protrusion 13 (i.e., R2 < R1). In an embodiment of the present disclosure, the material of the first layer 131 of the protrusion 13 may be palladium, and the material of the second layer 132 of the protrusion 13 may be gold, but the present disclosure is not limited thereto.

[0035] In the present disclosure, the surface 121c of the first metal layer 121 has a recess 121d, and at least a portion of the second metal layer 122 is disposed in the recess 121d. In another embodiment of the present disclosure, the surface 121c of the first metal layer 121 may have a plurality of recesses 121d (not shown) and have a wavy shape. When the surface 121c of the first metal layer 121 has the recess 121d or has a wavy shape, the second metal layer 122 and the protrusion 13 formed above the first metal layer 121 may also have a recess or have a wavy shape, thereby improving the contact effect between the conductive film for test 1 and the test object 4.

[0036] In the present disclosure, the depth R1 of the recess 121d may be 0.2 μm or more and 10 μm or less (0.2 μm≦R1≦10 μm). In the present disclosure, the “depth R1 of the recess 121d” may be the maximum depth of the recess 121d measured in a normal direction (e.g., the Z direction) of the test conductive film 1. According to some embodiments, the hardness of the first layer 131 of the protrusion 13 is higher than that of the second metal layer 122. If the hardness of the first layer 131 of the protrusion 13 is higher than that of the second metal layer 122, it may have favorable contact quality during testing. Furthermore, if the second metal layer 122 is designed with a recess, it may buffer stress caused by pressure during testing, preventing damage to the test conductive film 1 or extending the shelf life of the test conductive film 1, but the present disclosure is not limited thereto. More specifically, if the hardness of the first layer 131 of the protrusion 13 is higher than that of the second metal layer 122 and the second layer 132 of the protrusion 13, respectively, the test conductive film 1 may have suitable contact and buffer properties during measurement, but the present disclosure is not limited thereto.

[0037] In the present disclosure, the circuit structure 12 of the test conductive film 1 may be, for example, a redistribution layer and may include at least one conductive layer (e.g., a first metal layer 121 and a third metal layer 15) and at least one insulating layer (e.g., an insulating layer 11 and an insulating layer 14) to facilitate circuit redistribution and / or further expand the circuit fan-out area. The redistribution layer is intended to extend wiring to wider spacings or distribute the redistribution path of a wiring to other wiring with different spacings. Also, in one embodiment of the present disclosure, as shown in FIG. 1, the first metal layer 121 may include a conductive bump 121b and a circuit 121a, where the conductive bump 121b is electrically connected to the circuit 121a, and the second metal layer 122 is disposed on the conductive bump 121b.

[0038] In the present disclosure, there is no particular limitation on the position where the second metal layer 122 and the protrusion 13 are disposed on the conductive bump 121b of the first metal layer 121, and the second metal layer 122 and the protrusion 13 may be disposed in the center of the conductive bump 121b or may not be disposed in the center of the conductive bump 121b. For example, in one embodiment of the present disclosure, as shown in FIG. 1, the second metal layer 122 and the protrusion 13 do not have to be disposed in the center of the conductive bump 121b, i.e., they do not have to be disposed on the cross section of the test conductive film 1, and the distance D1 between the second metal layer 122 and the sidewall 121S1 of the first metal layer 121 is unequal to another distance D2 between the second metal layer 122 and the sidewall 121S2 of the first metal layer 121, but the present disclosure is not limited thereto.

[0039] 1 illustrates an example in which the test conductive film 1 has three protrusions 13, but the present disclosure is not limited to this. The test conductive film 1 can be designed with different numbers of protrusions 13 based on test requirements.

[0040] FIG. 2 is a top view showing a test conductive film according to one embodiment of the present disclosure. A cross section of the test conductive film 1 is shown in FIG. 1, and its description will not be repeated here. In the example of FIG. 2, the test conductive film 1 may include a plurality of circuits 121a and a plurality of conductive bumps 121b, where partial circuits 121a and conductive bumps 121b can be electrically connected to each other and partial circuits 121a and conductive bumps 121b can be electrically insulated from each other. In one embodiment of the present disclosure, partial conductive bumps 121b can be redundant pads, but the present disclosure is not limited thereto.

[0041] 3 is a schematic diagram illustrating an electronic measurement system including a test conductive film according to another embodiment of the present disclosure, in which all components except for a control device 3 are shown in a bird's-eye view.

[0042] 3, the electronic measurement system includes a test conductive film 1, a test head 2 above which a circuit board 21 is placed and electrically connected to the circuit board 21 via conductive wires 23, and a control device 3 electrically connected to the test head 2. The test conductive film 1 has been described above, and its description will not be repeated here.

[0043] In this embodiment, the DUT 4 is placed on the detection platform 5 for detection, but the present disclosure is not limited thereto. The DUT 4 may further include a test pad 41. For detection, the conductive film 1 can be placed on the test pad 41 and electrically connected to the test pad 41. When detecting the DUT 4 using the electronic measurement system shown in FIG. 3 , the control device 3 can provide a detection signal to the test head 2, which then transmits the detection signal to the conductive film 1 to detect the DUT 4. The acquired detection signal is then transmitted by the conductive film 1 to the test head 2 and then to the control device 3. The DUT 4 has been described above, and its description will not be repeated here.

[0044] 4 is a partial schematic diagram showing a test conductive film according to one embodiment of the present disclosure. The test conductive film according to this embodiment is similar to the test conductive film of FIG. 1, and the differences are described below.

[0045] 4, in the present disclosure, the surface 132a of the second layer 132 of the protrusion 13 may have an arc shape. Also, the distance D1 between the second metal layer 122 and the sidewall 121S1 of the first metal layer 121 may be equal to another distance D2 between the second metal layer 122 and the sidewall 121S2 of the first metal layer 121, and the present disclosure is not limited thereto. The remaining features of the test conductive film according to the present disclosure are as described above, and the description thereof will not be repeated here.

[0046] 5 is a partial schematic diagram showing a test conductive film according to one embodiment of the present disclosure. The test conductive film according to this embodiment is similar to the test conductive film of FIG. 1, and the differences are described below.

[0047] 5, in the present disclosure, the surface 132a of the second layer 132 of the protrusion 13 may be flat. This can improve the contact effect between the test conductive film 1 and the test object 4. The remaining features of the test conductive film according to the present disclosure are as described above, and the description thereof will not be repeated here.

[0048] 6 is a partial schematic diagram showing a test conductive film according to another embodiment of the present disclosure. The test conductive film according to this embodiment is similar to the test conductive film of FIG. 1, with the differences being described below.

[0049] As shown in FIG. 6 , in the present disclosure, the surface 132a of the second layer 132 of the protrusion 13 may have an arcuate shape. The test conductive film according to the present disclosure may further include a passivation layer 16 disposed on the exposed surface 14a of the insulating layer 14. More specifically, the passivation layer 16 may be disposed on the surface 14a of the insulating layer 14 that is not covered by another layer, for example, on the surface 14a that contacts the outside world. In the present disclosure, the passivation layer 16 may be a water-blocking layer, and the water vapor transmission rate of the passivation layer 16 may be lower than that of the insulating layer 14, reducing the possibility of the insulating layer 14 absorbing moisture, further reducing the swelling problem of the test conductive film, and increasing the service life of the test conductive film.

[0050] In the present disclosure, the passivation layer 16 may have a single-layer or multi-layer structure. The passivation layer 16 may also include an organic material, an inorganic material, or a combination thereof. For example, the passivation layer 16 may include silicon oxide, silicon nitride, silicon oxynitride, an epoxy resin, a polymer, or a combination thereof. In one embodiment of the present disclosure, the passivation layer 16 may be a silicon nitride layer, a silicon oxide layer, or a combination thereof. In another embodiment of the present disclosure, the passivation layer 16 may have a layered structure of inorganic material-organic material-inorganic material, for example, a three-layer structure of silicon nitride-colloid-silicon nitride.

[0051] In the present disclosure, the thickness of the passivation layer 16 may range between 10 nm and 5 μm (10 nm≦thickness≦5 μm). The remaining characteristics of the test conductive film according to the present disclosure are as described above, and the description thereof will not be repeated here.

[0052] FIG. 7 is a schematic diagram of a portion showing a test conductive film according to different embodiments of the present disclosure.

[0053] 7 , a test conductive film according to the present disclosure includes a first metal layer 121 and a second metal layer 122. The second metal layer 122 includes a circuit structure 12 disposed on the first metal layer 121, a protrusion 13 disposed on the circuit structure 12 and protruding from the circuit structure 12, and an insulating layer 14 disposed to surround the first metal layer 121 and the second metal layer 122. The protrusion 13 overlaps the second metal layer 122, and at least a portion of the insulating layer 14 is disposed between the first metal layer 121 and the protrusion 13. According to some embodiments, the phrase "A surrounds B" in the present disclosure refers to a state in which member A contacts at least a partial side of member B in a cross-sectional direction.

[0054] In the present disclosure, the first metal layer 121 may include a plurality of conductive bumps 121b and a plurality of circuits 121a, the conductive bumps 121b being electrically connected to the circuits 121a, and the second metal layer 122 being disposed on the conductive bumps 121b. In the present disclosure, at least a partial insulating layer 14 is disposed between adjacent conductive bumps 121b. As described above, the insulating layer 14 has a certain elongation rate, so that the at least partial insulating layer 14 can provide cushioning properties similar to an elastic body, thereby reducing the influence of contact wear on the test conductive film 1 and improving the durability of the test conductive film 1.

[0055] In the present disclosure, three conductive bumps 121b are electrically connectable to each other and are integrally bonded to the surface 14a of the insulating layer 14, and then the second metal layer 122 and the protrusions 13 are formed thereon. However, the present disclosure is not limited thereto, and multiple conductive bumps 121b may be electrically connected to each other and integrally bonded to the surface 14a of the insulating layer 14, which can be determined according to needs.

[0056] In the present disclosure, the test conductive film may further include a fourth metal layer 17 disposed under the third metal layer 15 and electrically connected to the third metal layer 15. The material of the fourth metal layer 17 is the same as that of the third metal layer 15 described above, and the description thereof will not be repeated here.

[0057] In the present disclosure, the test conductive film may further include a carrier C disposed under the circuit structure 12. When the test conductive film includes a carrier C, the supportability or operability of the test conductive film may be improved. The elongation of the carrier C may be less than 20%. The material of the carrier C may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other suitable materials, or combinations of the above materials, but the present disclosure is not limited thereto. When the carrier C includes an organic material, the elongation of the carrier C can be adjusted by adding filler particles between the organic material layers. The filler particles may include oxides, nitrides, or carbides, but the present disclosure is not limited thereto.

[0058] In the present disclosure, the test conductive film may further include a buffer layer C' disposed between the circuit structure 12 and the carrier C. The material of the buffer layer C' may include, for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, and the present disclosure is not limited thereto. The remaining features of the test conductive film according to the present disclosure are as described above, and the description thereof will not be repeated here.

[0059] FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a test conductive film according to one embodiment of the present disclosure.

[0060] First, a temporary substrate C1 is provided, and a carrier C is placed on the temporary substrate C1. The material of the temporary substrate C1 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethylmethacrylate (PMMA), other suitable materials, or combinations of the above materials, but the present disclosure is not limited thereto. The material of the carrier C has been described above, and its description will not be repeated here. In one embodiment of the present disclosure, the temporary substrate C1 is a glass substrate, and the carrier C is a polyimide substrate, but the present disclosure is not limited thereto.

[0061] Then, a buffer layer C' is formed on the carrier C. The buffer layer C' can cover all remaining surfaces of the carrier C except the surface facing the temporary substrate C1, but the present disclosure is not limited thereto. In another embodiment of the present disclosure, the buffer layer C' can cover only the upper surface opposite to the surface facing the temporary substrate C1. The material of the buffer layer C' has been described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the buffer layer C' can include silicon nitride, but the present disclosure is not limited thereto.

[0062] Next, a plurality of circuits 121a are formed on the buffer layer C', and then a plurality of conductive bumps 121b are formed on the circuits 121a, thereby forming the first metal layer 121. The material of the first metal layer 121 is as described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the first metal layer 121 may be a copper metal layer, but the present disclosure is not limited thereto.

[0063] After the first metal layer 121 is formed, an insulating layer 14 is formed on the first metal layer 121, and an insulating layer 14 is further formed between adjacent circuits 121a and between adjacent conductive bumps 121b. The material of the insulating layer 14 has been described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the insulating layer 14 may include polyimide, but the present disclosure is not limited thereto.

[0064] Then, a passivation layer 16 is formed on the insulating layer 14. The passivation layer 16 is formed on the surface of the insulating layer 14 that is not covered by other layers, for example, on the surface that contacts the outside world. The passivation layer 16 is also formed on the side surface of the carrier C. More specifically, the passivation layer 16 is further formed on the buffer layer C' on the side surface of the carrier C. The material of the passivation layer 16 has been described above, and its description will not be repeated here. In one embodiment of the present disclosure, the passivation layer 16 may have a layered structure of inorganic material-organic material-inorganic material, for example, a three-layer structure of silicon nitride-colloidal-silicon nitride, although the present disclosure is not limited thereto.

[0065] After the insulating layer 14 and the passivation layer 16 are patterned, the second metal layer 122 and the protrusion 13 (e.g., including the first layer 131 and the second layer 132 shown in FIG. 1 ) are sequentially formed. The materials of the second metal layer 122 and the protrusion 13 are as described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the second metal layer 122 may be a nickel metal layer, and the protrusion 13 may be a palladium-gold laminated metal layer.

[0066] Next, a carrier film C2 is formed on the second metal layer 122 and the protrusions 13. The material of the carrier film C2 can refer to the material of the temporary substrate C1 or the carrier C described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the carrier film C2 is a polyimide thin film, but the present disclosure is not limited thereto.

[0067] After the structure on the temporary substrate C1 is inverted, another passivation layer 16' is formed on the surface of the carrier C. The material of the passivation layer 16' can refer to the material of the passivation layer 16 described above, and the description thereof will not be repeated here. In one embodiment of the present disclosure, the material of the passivation layer 16' may be similar to the material of the passivation layer 16, and both have a layered structure of inorganic material-organic material-inorganic material (e.g., a three-layer structure of silicon nitride-colloidal-silicon nitride), but the present disclosure is not limited thereto.

[0068] Finally, the temporary substrate C1 and the carrier film C2 are removed to obtain the test conductive film according to the present disclosure. In the present disclosure, the formed test conductive film may include a carrier C to improve the supportability or operability of the test conductive film. However, in other embodiments of the present disclosure, the test conductive film may not include a carrier C. For example, the carrier C is removed after the structure on the temporary substrate C1 is inverted and before the passivation layer 16′ is formed.

[0069] 8, in one embodiment of the present disclosure, the passivation layer 16 and the passivation layer 16' of the test conductive film may have a laminated structure of inorganic material-organic material-inorganic material, for example, a three-layer structure of silicon nitride-colloid-silicon nitride. This prevents the organic material from absorbing water and prevents the test conductive film from being affected by the environment during use, which could cause the alignment of the test conductive film and the test object to be lost.

[0070] In the present disclosure, each of the above-mentioned layers can be formed using a suitable method, which may include, but is not limited to, electroplating, chemical plating, chemical vapor deposition, physical vapor deposition, atomic layer deposition (ALD), sputtering, lamination, coating, photolithography, lift-off technology, or a combination thereof. The "coating method" may include, but is not limited to, dip coating, spin coating, roller coating, blade coating, spray coating, or a combination thereof.

[0071] To summarize the above, in the test conductive film according to the present disclosure, at least a partial insulating layer is placed between the metal layer and the protrusion, which enables the at least partial insulating layer to provide cushioning properties similar to those of an elastic body, thereby reducing the effects of contact wear on the test conductive film and improving the durability of the test conductive film.

[0072] Although the embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes and the like are also included within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0073] 1. Test conductive film 11 Insulating layer 12 Circuit structure 121 1st metal layer 121a circuit 121b Conductive bump 121c surface 121d recess 121S1 Side wall 121S2 side wall 122 2nd metal layer 122a Recess 122b side wall 13 Protrusion 131 1st layer 131a Side 132 2nd layer 132a surface 14 Insulating layer 14a surface 15 Third metal layer 16 Passivation Layer 16' passivation layer 17 4th metal layer 2 Test Head 21 Circuit Board 22 Electrical connection element 23 Conductive wire 3. Control device 4 Test Subject 41 Test Pad 5. Detection Platform C Carrier C' buffer layer C1 Temporary board C2 Carrier Film D1 Distance D2 distance L1 Virtual Line T1 First thickness T2 Second thickness T3 Thickness T4 thickness R1 Depth

Claims

1. a circuit structure including a first metal layer and a second metal layer, the second metal layer being disposed on the first metal layer; a protrusion disposed on the circuit structure and protruding from the circuit structure; an insulating layer disposed so as to surround the first metal layer and the second metal layer; A test conductive film characterized in that the protrusion overlaps the second metal layer, and at least a portion of the insulating layer is located between the second metal layer and the protrusion.

2. 2. The test conductive film of claim 1, wherein at least a portion of the insulating layer has a first thickness, the second metal layer has a second thickness, and the ratio of the first thickness to the second thickness is greater than or equal to 0.1 and less than or equal to 0.

5.

3. 2. The test conductive film of claim 1, wherein the surface of the first metal layer has a recess, and at least a portion of the second metal layer is located in the recess.

4. 2. The test conductive film of claim 1, wherein the protrusion comprises a first layer and a second layer, the first layer being positioned between the second metal layer and the second layer, and the second layer contacting a side of the first layer.

5. 2. The test conductive film of claim 1, wherein the protrusion comprises a first layer and a second layer, the first layer being positioned between the second metal layer and the second layer, and the hardness of the second layer being less than the hardness of the first layer.

6. 10. The test conductive film of claim 1, further comprising a passivation layer disposed on the exposed surface of the insulating layer.

7. 2. The test conductive film according to claim 1, wherein the elongation of the insulating layer is in the range of 20% to 900%.

8. 2. The test conductive film of claim 1, wherein the second metal layer has a recess, and at least a portion of the insulating layer is disposed in the recess.

9. The test conductive film according to claim 9 , wherein the recess is located on a sidewall of the second metal layer.

10. 2. The test conductive film of claim 1, wherein the first metal layer comprises a conductive bump and a circuit, the conductive bump being electrically connected to the circuit, and the second metal layer is disposed on the conductive bump.

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