Matching network tuning in prediction of semiconductor manufacturing process steps

Abstract

To provide a system for controlling a matching network of a semiconductor manufacturing system.SOLUTION: The matching network comprises an electronic variable reactance element (EVRE) that varies its total reactance using different matching configurations. The plasma chamber performs a process on a substrate, the process including process steps including at least a first process step and a second process step. The memory stores, for each process step, instructions for performing the process step. The control circuitry, while sequentially performing each of the process steps of the process, changes the matching configuration to a new matching configuration based on the instructions for performing the second process step upon predicting that the plasma chamber will transition from the first process step to the second process step.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] To produce semiconductor devices such as microprocessors, memory chips, or other integrated circuits and devices, semiconductor device manufacturing processes use plasma processing at different stages of production. Plasma processing involves energizing a gas mixture by introducing RF (radio frequency) energy into the gas mixture, imparting energy to the gas molecules. The gas mixture is typically contained within a vacuum chamber, also called a plasma chamber, and RF energy is introduced into the chamber through electrodes or other means. In a typical plasma process, an RF source generates electrical power at a desired RF frequency and RF power, which is transmitted to the plasma chamber through RF cables and networks.

[0002] To provide efficient power transfer from the RF source to the plasma chamber, a matching network is positioned between the RF source and the plasma chamber. The purpose of the matching network is to transform the plasma impedance to a value appropriate for the RF source. Often, especially in semiconductor manufacturing processes, RF power is transmitted through a 50 ohm (Ω) coaxial cable, and the RF source's system impedance (output impedance) is also 50 ohms. However, the impedance of the plasma driven by the RF power varies. The impedance at the input side of the matching network must be transformed to a non-reactive 50 ohms (i.e., 50 + j0) for maximum power transfer. The matching network accomplishes this task by continuously transforming the plasma impedance to 50 ohms relative to the RF source.

[0003] In a typical matching network for a semiconductor manufacturing process, the matching configuration and tuning parameters are set at the beginning of the process. However, as the process becomes more complex, using different power levels and different gas chemistries, the matching requirements for different steps of the process change. Typical matching networks that use electromechanical components, such as vacuum variable capacitors (VVCs), cannot change the matching configuration midway through the process (e.g., between process steps) due to the slow switching speed of the mechanical components. For such matching networks, the time required to transition to a new matching configuration depends on the speed of physical movement of the mechanical elements, which can take hundreds of milliseconds to several seconds to move from one position to another. Such slow changes in the matching configuration during the process can disrupt the plasma and the overall semiconductor manufacturing process. If the transition to a new process step involves a significant change in the power provided by the RF source, additional steps may be added to the process to prevent a sudden change in power that cannot be handled by the electromechanical matching network, but such a solution slows down the entire process. Summary of the Invention

[0004] The present disclosure is directed to utilizing solid-state matching networks that can be repositioned in submillisecond time to anticipate new process steps and enable in-process matching configuration changes without disrupting the process being performed by a semiconductor manufacturing system. By enabling matching configuration changes for different process steps, matching network parameters can be optimized for each process, rather than simply a one-size-fits-all parameter set that enables all process steps to be performed. Such an approach avoids interruptions to the plasma or the entire semiconductor manufacturing process. Changing the matching configuration before changing the process step reduces adjustment time and enables more efficient power transfer. The present disclosure offers particular advantages when transitioning to a new process step that involves significant changes in the power provided by the RF source. The speed of solid-state matching networks (e.g., matching networks utilizing electronic variable capacitors) allows for rapid adjustment to changed power, thus ensuring efficient power transfer without disrupting the plasma.

[0005] In one aspect, the present disclosure may be directed to a system for controlling a matching network of a semiconductor manufacturing system, the system comprising: a matching network configured to provide radio frequency (RF) power from an RF source to a plasma chamber, the matching network comprising an Electronically Variable Reactance Element (EVRE) configured to provide a variable total reactance, the EVRE comprising individual reactance elements configured to switch inputs and outputs of the matching network to vary the total reactance provided by the EVRE and thereby enable the matching network to provide different match configurations; a plasma chamber configured to perform a process on a substrate, the process including at least a first process step and a second process step; a memory configured to store, for each process step, instructions for performing the process step; and a control circuit configured to change the match configuration to a new match configuration based on the instructions for performing the second process step when the plasma chamber anticipates transitioning from the first process step to the second process step while sequentially performing each of the process steps of the process.

[0006] In another aspect, a method for controlling a matching network in a semiconductor manufacturing system is disclosed, the method including: providing RF power from an RF source to a plasma chamber through a matching network, the matching network including an electronically variable reactance element (EVRE) configured to provide a variable total reactance, the EVRE including individual reactance elements configured to switch inputs and outputs of the matching network to vary the total reactance provided by the EVRE, thereby enabling the matching network to provide different match configurations; and the plasma chamber configured to perform a process on a substrate, the process including at least a first process step and a second process step; storing, for each process step, instructions for performing the process step; and, while sequentially performing each of the process steps of the process, changing the match configuration to a new match configuration based on the instructions for performing the second process step when the plasma chamber anticipates transitioning from the first process step to the second process step.

[0007] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of one embodiment of a semiconductor processing system including a system for controlling a matching network of the semiconductor processing system. [Figure 2] FIG. 1 is a block diagram of one embodiment of a semiconductor processing system having an L-configuration matching network. [Figure 3] FIG. 1 is a block diagram of one embodiment of a semiconductor processing system having a pi configuration matching network. [Figure 4] FIG. 1 is a block diagram of one embodiment of an electronic circuit for providing variable capacitance using an electronically variable capacitor. [Figure 5]FIG. 1 is a schematic diagram of a variable capacitance system for switching individual capacitors in and out of an electronically variable capacitor. [Figure 6] 1 is a flow chart illustrating one embodiment of a process for matching impedance by varying variable capacitance. [Figure 7] 1 is a flowchart of a method for controlling a matching network in a semiconductor manufacturing system. [Figure 8A] Graphs are provided comparing the rate of a Plasma Enhanced Atomic Layer Deposition (PEALD) semiconductor process with and without the disclosed system for controlling a matching network of a semiconductor processing system. [Figure 8B] Graphs are provided comparing the rate of a plasma-enhanced atomic layer deposition (PEALD) semiconductor process with and without the disclosed system for controlling a matching network of a semiconductor processing system. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the present invention(s) in any manner. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered part of the entire written description. Any reference to direction or orientation in the description of the exemplary embodiments disclosed herein is intended merely for convenience of description and is in no way intended to limit the scope of the present invention. The discussion herein describes and illustrates several possible non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term "or" as used herein should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, as used herein, the phrase "based on" should be interpreted as meaning "based at least in part on" and therefore is not limited to being interpreted as "based entirely on."

[0010] Features of the present invention may be implemented in software, hardware, firmware, or a combination thereof. The computer programs described herein are not limited to any particular embodiment and may be implemented in an operating system, an application program, a foreground or background process, a driver, or any combination thereof. The computer programs may be implemented on a single computer or server processor, or on multiple computer or server processors.

[0011] A processor as described herein may be any central processing unit (CPU), microprocessor, microcontroller, computer, or programmable device or circuitry configured to execute computer program instructions (e.g., code). Various processors may be implemented in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual ancillary components required to form a functional data processing device, including, but not limited to, a bus, software, and data storage such as volatile and non-volatile memory, input / output devices, a graphical user interface (GUI), removable data storage, and wired and / or wireless communication interface devices, including Wi-Fi, Bluetooth, LAN (Local Area Network), etc.

[0012] The computer-implementable instructions or programs (e.g., software or code) and data described herein may be programmed into and tangibly embodied in non-transitory computer-readable media accessible to and retrievable by each processor as described herein, which configures and directs the processor to perform desired functions and processes by executing the instructions encoded in the media. A device implementing a programmable processor configured into such non-transitory computer-implementable instructions or programs may be referred to as a "programmable device" or "device," and multiple programmable devices in communication with each other may be referred to as a "programmable system." It should be noted that a non-transitory "computer-readable medium" as described herein may include, but is not limited to, any suitable volatile or non-volatile memory, including Random Access Memory (RAM) and its various types, Read Only Memory (ROM) and its various types, Universal Serial Bus (USB) flash memory, and magnetic or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tape, CD (Compact Disc)-ROMs, DVD (Digital Versatile Disc)-ROMs, optical disks, ZIP® drives, Blu-ray® disks, and others) that may be written to and / or read by a processor operably connected to the medium.

[0013] In certain embodiments, the present invention may be embodied in the form of computer-implemented processes and apparatuses, such as processor-based data processing and communication systems or computer systems for performing those processes. The present invention may also be embodied in the form of software or computer program code embodied in a non-transitory computer-readable storage medium, which, when loaded into and executed by a data processing and communication system or computer system, the computer program code segments configure a processor to create specific logic circuits configured to perform the processes.

[0014] The ranges used throughout are used as a shorthand expression to describe all values ​​within the range. Any value within the range can be selected as the end of the range. In addition, all references cited herein are incorporated by reference in their entirety. If there is any discrepancy between the definitions in this disclosure and those of the cited references, this disclosure shall prevail.

[0015] In the following description, where circuits are shown and described, those skilled in the art will recognize that, for clarity, not all peripheral circuits or components are shown in the figures or described in the description. Furthermore, the terms "coupled" and "operably coupled" can refer to a direct or indirect coupling of two components of a circuit.

[0016] The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the invention in any way. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are to be considered part of the entire written description. Any reference to direction or orientation in the description of the exemplary embodiments disclosed herein is intended merely for convenience of description and is not intended to limit the scope of the invention in any way. Relative terms such as "lower," "upper," "horizontal," "vertical," "above," "below," "up," "down," "left," "right," "top," "bottom," "front," and "rear," as well as derivatives thereof (e.g., horizontally," "downwardly," "upwardly," etc.), should be construed as referring to the orientation being described or shown in the drawings under consideration. These relative terms are for convenience of description only and do not require that a device be constructed or operated in a particular orientation unless explicitly stated. Terms such as "attached," "affixed," "connected," "coupled," "interconnected," "secured," and other similar terms refer to both a relationship in which structures are fixed or attached to one another, either directly or indirectly through intervening structures, as well as a movable or rigid attachment or relationship, unless expressly stated otherwise. The discussion herein describes and illustrates several possible non-limiting combinations of features that may exist alone or in combination with other features. Furthermore, the term "or" as used in this disclosure should be interpreted as a logical operator that yields true if one or more of its operands are true. Furthermore, as used herein, the phrase "based on" should be interpreted as meaning "based at least in part on" and therefore is not limited to being interpreted as "fully based on."

[0017] The ranges used throughout are used as a shorthand expression to describe all values ​​within the range. Any value within the range can be selected as the end of the range. In addition, all references cited herein are incorporated by reference in their entirety. If there is any discrepancy between the definitions in this disclosure and those of the cited references, this disclosure shall prevail.

[0018] [Semiconductor Processing System] 1 , a semiconductor device processing system 85 utilizing an RF source 15 is shown. The system 85 includes the RF source 15 and a semiconductor processing tool 86. The semiconductor processing tool 86 includes a matching network 11 and a plasma chamber 19. In other embodiments, the RF source 15 or other power source may form part of the semiconductor processing tool. For the semiconductor processing system and its components (e.g., matching networks, EVCs (Electronic Variable Capacitors), and EVREs) discussed herein, applicants incorporate by reference U.S. Patent Publication No. 2024 / 0177970 in its entirety.

[0019] The semiconductor device may be a microprocessor, memory chip, or other type of integrated circuit or device. A substrate 27 may be placed in a plasma chamber 19, which is configured to deposit a material layer on or etch a material layer from the substrate 27. Plasma processing involves activating a gas mixture by introducing RF energy into the gas mixture and imparting energy to the gas molecules. The gas mixture is typically contained in a vacuum chamber (plasma chamber 19), and RF energy is typically introduced into the plasma chamber 19 through electrodes. Thus, a plasma can be activated by coupling RF power from an RF source 15 into the plasma chamber 19 to perform deposition or etching.

[0020] In a typical plasma process, RF source 15 generates power at a radio frequency, typically in the range of 3 kHz to 300 GHz, and this power is transmitted to plasma chamber 19 through RF cables and networks. To provide efficient transfer of power from RF source 15 to plasma chamber 19, an intermediate circuit is used to match the fixed impedance of RF source 15 with the variable impedance of plasma chamber 19. Such intermediate circuits are commonly referred to as RF impedance matching networks, or more simply, matching networks. The purpose of matching network 11 is to transform the variable plasma impedance to a value that more closely matches the fixed impedance of RF source 15. Commonly owned U.S. application Ser. No. 14 / 669,568, the disclosure of which is incorporated herein by reference in its entirety, provides an example of such a matching network.

[0021] [Matching network] 2 is a block diagram of one embodiment of a semiconductor processing system 85 having a semiconductor processing tool 86 including an L-configuration matching network 11. The matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 may be connected between the matching network 11 and the RF source 15. An RF output sensor 49 may be connected between the matching network 11 and the plasma chamber 19 so that the RF output from the impedance matching network and the plasma impedance presented by the plasma chamber 19 may be monitored. Certain embodiments may include only one of the input sensor 21 and the output sensor 49. The functions of these sensors 21, 49 are described in more detail below.

[0022] As described above, matching network 11 functions to help maximize the amount of RF power transferred from RF source 15 to plasma chamber 19 by matching the impedance at RF input 13 to a fixed impedance of RF source 15. Matching network 11 may consist of a single module in a single housing designed for electrical connection to RF source 15 and plasma chamber 19. In other embodiments, components of matching network 11 may be located in different housings, some components may be outside the housing, and / or some components may share a housing with components outside the matching network.

[0023] The plasma in the plasma chamber 19 typically undergoes certain variations outside of operational control, such that the impedance presented by the plasma chamber 19 is a variable impedance. Because the variable impedance of the plasma chamber 19 cannot be fully controlled, an impedance matching network may be used to create an impedance match between the plasma chamber 19 and the RF source 15. Furthermore, the impedance of the RF source 15 may be fixed at a set value depending on the design of the particular RF source 15. Although the fixed impedance of the RF source 15 may undergo slight variations during use, for example, due to temperature or other environmental variations, the impedance of the RF source 15 is still considered a fixed impedance for purposes of impedance matching because the variations do not significantly change the fixed impedance from its original set impedance value. Other types of RF sources 15 may be designed so that the impedance of the RF source 15 may be set at or during use. The impedance of these types of RF sources 15 is still considered fixed because it can be controlled by the user (or at least by a programmable controller) and the impedance set point may be known at any time during operation, so the set point is effectively a fixed impedance.

[0024] RF source 15 may include an RF generator configured to generate an RF signal at a frequency and power appropriate for the process being performed in plasma chamber 19. RF source 15 may be electrically connected to RF input 13 of matching network 11 using a coaxial cable, which will have the same fixed impedance as RF source 15 for impedance matching purposes.

[0025] The plasma chamber 19 includes a first electrode 23 and a second electrode 25, which, in conjunction with an appropriate control system (not shown) and the plasma within the plasma chamber 19, enable one or both of the deposition of material onto the substrate 27 and the etching of material from the substrate 27 in processes well known in the art.

[0026] In the exemplary embodiment, matching network 11 includes a series variable capacitor 31, a shunt variable capacitor 33, and a series inductor 35, forming an "L" type matching network. Shunt variable capacitor 33 is shown shunted to a reference potential, which in this embodiment is ground 40.

[0027] Alternatively, matching network 11 may be configured in other matching network configurations, such as a "T" configuration or a "π" or "pi" configuration, as shown in Figure 3. In certain embodiments, the variable capacitors and switching circuitry described below may be included in any suitable configuration for the matching network.

[0028] 2, in an exemplary embodiment, each of the series variable capacitor 31 and the shunt variable capacitor 33 may be an electronically variable capacitor (EVC), as described in U.S. Patent No. 7,251,121, where the EVC is effectively a capacitor array formed by a plurality of individual capacitors. The series variable capacitor 31 is coupled in series between the RF input 13 and the RF output 17 (which is also in parallel between the RF source 15 and the plasma chamber 19). The shunt variable capacitor 33 is coupled between the RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 may be coupled in parallel between the RF output 17 and ground 40. Other configurations may also be implemented without departing from the functionality of the matching network. In yet other configurations, the shunt variable capacitor 33 may be coupled in parallel between a reference potential and one of the RF input 13 and the RF output 17.

[0029] The series variable capacitor 31 is connected to the series RF choke and filter circuit 37 and to the series driver circuit 39. Similarly, the shunt variable capacitor 33 is connected to the shunt RF choke and filter circuit 41 and to the shunt driver circuit 43. The series driver circuit 39 and the shunt driver circuit 43 are each connected to a control circuit 45, which is configured with an appropriate processor and / or signal generation circuitry to provide input signals for controlling the series driver circuit 39 and the shunt driver circuit 43. A power supply 47 is connected to each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45, and provides operating power to each of these components at a designed current and voltage. The voltage levels provided by the power supply 47, and therefore the voltage levels employed by each of the RF input sensor 21, the series driver circuit 39, the shunt driver circuit 43, and the control circuit 45 to perform their respective designated tasks, are a matter of design choice. In other embodiments, different electronic components can be used to enable the control circuit 45 to send commands to the variable capacitors. Additionally, although driver circuits 39, 43 and RF chokes and filters 37, 41 are shown separate from control circuit 45, these components may be considered to be part of control circuit 45. Control circuit 45 may include or be coupled to memory 46. Memory 46 may store instructions for control circuit 45 as well as other data that may be utilized by control circuit 45.

[0030] In the exemplary embodiment, control circuitry 45 includes a processor. The processor may be any type of appropriately programmed processing device, such as a computer or microprocessor, configured to execute computer program instructions (e.g., code). The processor may be implemented in any suitable type of computer and / or server hardware (e.g., desktop, laptop, notebook, tablet, mobile phone, etc.) and may include all the usual ancillary components necessary to form a functional data processing device, including, but not limited to, buses, software and data storage (such as volatile and non-volatile memory), input / output devices, a graphical user interface (GUI), removable data storage, and wired and / or wireless communication interface devices, including Wi-Fi, Bluetooth, and LAN. The processor of the exemplary embodiment is configured with specific algorithms that enable matching network 11 to perform the functions described in this disclosure.

[0031] Using a combination of the series variable capacitor 31 and the shunt variable capacitor 33, the combined impedance of the matching network 11 and the plasma chamber 19 may be controlled to match, or at least substantially match, the fixed impedance of the RF source 15 using the control circuit 45, the series driver circuit 39, and the shunt driver circuit 43.

[0032] The control circuit 45 operates the matching network 11 and receives multiple inputs from sources such as the RF input sensor 21 and the series variable capacitor 31 and shunt variable capacitor 33, performs the necessary calculations to calculate changes to the series variable capacitor 31 and shunt variable capacitor 33, and delivers commands to the series variable capacitor 31 and shunt variable capacitor 33 to create the impedance match. The control circuit 45 is of the type commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. Any differences in the control circuit 45 compared to prior art control circuits reside in differences in programming due to the speed at which the matching network 11 can switch the variable capacitors 31, 33 and perform the impedance match.

[0033] Each of the series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 is configured to allow DC (Direct Current) signals to pass between the series driver circuit 39 and the shunt driver circuit 43 and the respective series variable capacitor 31 and shunt variable capacitor 33, while at the same time blocking RF signals from the RF source 15 to prevent RF signals from leaking to the outputs of the series driver circuit 39 and the shunt driver circuit 43 and the output of the control circuit 45. The series RF choke and filter circuit 37 and the shunt RF choke and filter circuit 41 are of a type known to those skilled in the art.

[0034] Figure 3 is a block diagram of one embodiment of a semiconductor processing system 85A having a pi-configuration matching network 11A, as opposed to the L-configuration matching network of Figure 2. For ease of understanding, this diagram omits the RF chokes and filters, driver circuitry, and power supplies of Figure 2. Where the same reference numerals are used in Figure 3 as those of Figure 2, it will be understood that the associated components may have a similar configuration to that discussed with respect to Figure 2.

[0035] The most notable difference between the L and pi configurations is that the L configuration utilizes a series capacitor 31 and a shunt capacitor 33, while the pi configuration utilizes two shunt capacitors 31A, 33A. Nevertheless, the control circuit 45 can vary the capacitance of these shunt variable capacitors 31A, 33A to provide impedance matching. Each of these shunt variable capacitors 31A, 33A can be an EVC, as described above. They may be controlled by chokes, filters, and drivers similar to the method described above with respect to FIG. 2.

[0036] [EVC Capacitor Array] FIG. 4 illustrates an electronic circuit 650 for providing variable capacitance according to one embodiment. The circuit 650 utilizes an EVC 651 including two capacitor arrays 651 a, 651 b. The first capacitor array 651 a may include a plurality of individual first capacitors, each having a first capacitance value. The second capacitor array 651 b may include a plurality of individual second capacitors, each having a second capacitance value. The first capacitance value differs from the second capacitance value such that the EVC 651 provides coarse and fine control of the capacitance generated by the EVC 651. The first capacitor array 651 a and the second capacitor array 651 b are coupled in parallel between the signal input 613 and the signal output 630.

[0037] The first and second capacitance values ​​may be any values ​​sufficient to provide a desired overall capacitance value for the EVC 651. In one embodiment, the second capacitance value is less than or equal to one-half (½) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (⅓) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (¼) of the first capacitance value.

[0038] The electronic circuit 650 further includes a control circuit 645, which may have similar features to the control circuit 45 described above. The control circuit 645 is operably coupled to the first capacitor array 651 a and the second capacitor array 651 b by a command input 629, which is operably coupled to the first capacitor array 651 a and the second capacitor array 651 b. In the exemplary embodiment, the command input 629 has a direct electrical connection to the capacitor arrays 651 a, 651 b, although in other embodiments, this connection may be an indirect connection. The coupling of the control circuit 645 to the capacitor arrays 651 a, 651 b is described in further detail below.

[0039] The control circuit 645 is configured to vary the variable capacitance of the EVC 651 by controlling the on and off states of (a) each individual capacitor of the plurality of individual first capacitors 651a and (b) each individual capacitor of the plurality of individual second capacitors 651b. As described above, the control circuit 645 can have features similar to those described with respect to the control circuit 45 of FIGS. 2-3. For example, the control circuit 645 can receive inputs from the capacitor arrays 651a, 651b, perform calculations to calculate changes to the capacitor arrays 651a, 651b, and deliver commands to the capacitor arrays 651a, 651b to vary the capacitance of the EVC 651. The EVC 651 of FIG. 4 can include multiple electronic switches. Each electronic switch can be configured to activate and deactivate one or more individual capacitors.

[0040] Similar to the control circuit 45 of FIGS. 2-3 , the control circuit 645 may also be connected to a driver circuit 639 and an RF choke and filter circuit 637. The control circuit 645, the driver circuit 639, and the RF choke and filter circuit 637 may have capabilities similar to those discussed with respect to FIGS. 2-3 . In an exemplary embodiment, the driver circuit 639 is operably coupled between the control circuit 645 and the first capacitor array 651 a and the second capacitor array 651 b. The driver circuit 639 is configured to vary the variable capacitance based on a control signal received from the control circuit 645. The RF filter 637 is operably coupled between the driver circuit 639 and the first capacitor array 651 a and the second capacitor array 651 b. In response to the control signal sent by the control unit 645, the driver circuit 639 and the RF filter 637 are configured to send a command signal to the command input 629. The command signal is configured to vary the variable capacitance by directing at least one of the electronic switches to activate or deactivate (a) at least one individual capacitor of the plurality of individual first capacitors, or (b) at least one individual capacitor of the plurality of individual second capacitors.

[0041] In an exemplary embodiment, the driver circuit 639 is configured to switch the on or off state of the high voltage source in less than 15 μs, and the high voltage source controls the electronic switches of each of the first and second capacitor arrays to vary the variable capacitance. However, the EVC 651 may be configured to be switched by any of the means or speeds discussed herein.

[0042] The control circuit 645 may be configured to calculate the coarse and fine capacitance values ​​provided by each capacitor array 651 a, 651 b. In an exemplary embodiment, the control circuit 645 is configured to calculate the coarse capacitance value provided by controlling the on and off states of the first capacitor array 651 a. Additionally, the control circuit is configured to calculate the fine capacitance value provided by controlling the on and off states of the second capacitor array 651 b. In other embodiments, the capacitor arrays 651 a, 651 b can provide alternative levels of capacitance. In other embodiments, the EVC can utilize additional capacitor arrays.

[0043] EVC651 of Figure 4 can be used in a majority of systems requiring varying capacitance. For example, EVC651 can be used as the series EVC and / or shunt EVC in matching network 11 of Figure 2, or as one or both of the shunt EVCs in matching network 11A of Figure 3. It is often desirable for the difference between capacitance values ​​to allow both sufficiently fine resolution of the overall capacitance of the circuit and a wide range of capacitance values ​​that allows for better impedance matching at the input of the matching network, and EVC651 allows this.

[0044] EVC 651 may also be used in systems or methods for manufacturing semiconductors, methods for controlling variable capacitance, and / or methods for controlling matching networks. Such methods may include varying at least one of the series variable capacitance and the shunt variable capacitance to a calculated series capacitance value and a shunt capacitance value, respectively. This variation may be achieved by controlling the on and off states of each individual capacitor of each of the plurality of individual capacitors for each of the series EVC and the shunt EVC. In other embodiments, EVC 651 and circuit 650 may be used in other methods and systems to provide variable capacitance.

[0045] [Switching individual capacitors in and out to vary EVC capacitance] As mentioned above, an EVC is a type of variable capacitor that can use multiple switches (each of which is used to create an open circuit or a short circuit) along with individual series capacitors to vary the capacitance of the variable capacitor. The switches can be mechanical (such as a relay) or solid-state (such as a PIN (Positive Intrinsic Negative) diode, transistor, or other switching device). Below is a discussion of methods for configuring an EVC or other variable capacitor to provide a varying capacitance.

[0046] In what is sometimes called the "accumulation setup" of an EVC or other variable capacitor, the approach to linearly increasing capacitor values ​​from a minimum starting point (where all switches are open) is to progressively increase the number of fine-tuning capacitors switched into the input to the circuit. Once the maximum number of fine-tuning capacitors have been switched into the input to the circuit, the coarse-tuning capacitors are switched into the input and the fine-tuning capacitors are switched into the output. The process begins again with increasing numbers of fine-tuning capacitors switched into the input to the circuit until all fine-tuning and coarse-tuning capacitors have been switched into the input, at which point another coarse-tuning capacitor is switched into the input and a fine-tuning capacitor is switched into the output. This process can continue until all coarse-tuning and fine-tuning capacitors have been switched into the input.

[0047] In this embodiment, all of the fine-tuning capacitors have the same or substantially similar values, and all of the coarse-tuning capacitors have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuning capacitor is approximately equal to the combined capacitance value of all of the fine-tuning capacitors and additional fine-tuning capacitors in the circuit, thus allowing for a linear increase in capacitance. However, the embodiment is not so limited. The fine-tuning capacitors (and the coarse-tuning capacitors) need not have the same or substantially similar values. Furthermore, the capacitance value of one coarse-tuning capacitor need not be equal to the combined capacitance value of all of the fine-tuning capacitors and additional fine-tuning capacitors. In one embodiment, the coarse and fine capacitance values ​​have a ratio substantially similar to 10:1. In another embodiment, the second capacitance value is less than half (½) of the first capacitance value. In another embodiment, the second capacitance value is less than one-third (⅓) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0048] An example of the above embodiment in an ideal setting would be when the fine tuning capacitor is equal to 1 pF (picofarad) and the coarse tuning capacitor is equal to 10 pF. In this ideal setting, when all switches are open, the capacitance is equal to 0 pF. When the first switch is closed, there is 1 pF in the circuit. When the second switch is closed, there is 2 pF in the circuit, and so on until all nine fine tuning switches are closed, giving 9 pF. Next, the first 10 pF capacitor is switched into the input to the circuit, and the nine fine tuning switches are opened, giving a total capacitance of 10 pF. Next, the fine tuning capacitor is switched from 11 pF to 19 pF into the input to the circuit. Next, another coarse tuning capacitor can be switched into the input to the circuit, and all fine tuning capacitors can be switched out of the circuit, giving 20 pF. This process may be repeated until the desired capacitance is reached.

[0049] This can also be taken one step further. Using the previous embodiment with nine 1 pF and nine 10 pF capacitors, the variable capacitor circuit can now have an even larger value of 100 pF to switch between the input and output of the circuit. This would allow the previous capacitor array to increase to 99 pF, and then the 100 pF capacitor can be used for the next increment. This can be repeated using larger increments, and may also be used in conjunction with any scaling system. According to the cumulative setup, increasing the total capacitance of the variable capacitor is achieved by switching more coarse or fine tuning capacitors into the input than are already switched into the input, without switching the coarse tuning capacitors already switched into the output. Furthermore, as the total variable capacitance increases and the control circuit does not switch more coarse tuning capacitors into the input than are already switched into the input, the control circuit switches more fine tuning capacitors into the input than are already switched into the input, without switching the fine tuning capacitors already switched into the output.

[0050] FIG. 5 is a schematic diagram of a variable capacitance system 655 with a cumulative setup. Where this figure uses the same reference numerals as those in FIG. 4, it is understood that the associated components may have features similar to those discussed in FIG. 4. The variable capacitance system 655 includes a variable capacitor 651 for providing a varying capacitance. The variable capacitor 651 has an input 613 and an output 630. The variable capacitor 651 includes a plurality of individual capacitors 653 operably coupled in parallel. The plurality of capacitors 653 includes a first (fine tuning) capacitor 651a and a second (coarse tuning) capacitor 651B. The variable capacitor 651 further includes a plurality of switches 661. One of the switches 661 is operably coupled in series to each of the plurality of capacitors to switch the input and output of each capacitor, thereby enabling the variable capacitor 651 to provide a varying total capacitance. The variable capacitor 651 has a variable total capacitance that increases when an individual capacitor 653 is switched to the input and decreases when an individual capacitor 653 is switched to the output.

[0051] The switch 661 can be coupled to a switch driver circuit 639 to drive the switch on and off. The variable capacitance system 655 can further include a control unit 645 operably coupled to the variable capacitor 651. Specifically, the control unit 645 can be operably coupled to the driver circuit 639 to instruct the driver circuit 639 to switch one or more of the switches 661, thereby turning one or more of the capacitors 653 on or off. In one embodiment, the control unit 645 can form part of a control unit that controls the variable capacitors (such as a control unit that instructs the variable capacitors of a matching network to change capacitance to achieve impedance matching). The driver circuit 639 and the control unit 645 can have features similar to those discussed above with reference to FIG. 4 and therefore can also utilize RF chokes and filters as discussed above.

[0052] In one embodiment, the control circuit 645 is configured to calculate a desired coarse capacitance for the coarse tuning capacitors, calculate a desired fine capacitance for the fine tuning capacitors, and, after calculating the desired coarse capacitance and the desired fine capacitance, vary the total variable capacitance by switching the input and output of at least one of the plurality of fine tuning capacitors and / or switching the input and output of at least one of the plurality of coarse tuning capacitors. In other embodiments, the coarse tuning and fine tuning may occur in different stages.

[0053] In an exemplary embodiment, the first capacitors 651a are fine-tuned capacitors each having a capacitance value substantially similar to a fine-tuned capacitance value, and the second capacitors 651b are coarse-tuned capacitors each having a capacitance value substantially similar to a coarse-tuned capacitance value, the coarse-tuned capacitance value being greater than the fine-tuned capacitance value. For purposes of this application, capacitance and other values ​​are considered to be substantially similar if one value is not fifteen percent (15%) greater than or less than the other value.

[0054] The variable capacitance system 655 can form part of an impedance matching network, including, but not limited to, the impedance matching networks of FIGS. 1-3. The variable capacitance system can also form part of a method for controlling an impedance matching network (such as the impedance matching network of FIGS. 1-3). The method can include providing a matching network that includes determining an increased total capacitance provided by one of the EVCs and increasing the variable total capacitance of one EVC by switching more coarse tuning capacitors or fine tuning capacitors to the input than are already switched to the input, without switching the coarse tuning capacitors already switched to the input to the output. Furthermore, the variable capacitance system can form part of methods and systems for manufacturing semiconductors (see FIGS. 1-3).

[0055] Using the variable capacitance system discussed above with an impedance matching network can offer several advantages over other approaches. As an alternative to the above approach, all capacitor values ​​are different, with the first value equal to the desired minimum change in capacitance. Then, each successive capacitor value is increased, doubling the change in capacitance from the previous value to the desired maximum capacitor value when all capacitors are switched into the input. This approach can result in using fewer capacitors to switch the input and output of the circuit while achieving the same resolution and range. However, a potential problem with this setup is that once a capacitor reaches a certain value, the voltage and / or current on that particular capacitor, or the current on the switch, can become higher than the specifications allow. This forces the EVC to use multiple capacitors in parallel for each lower-value switch. This problem is particularly acute when high voltages and / or currents are used. The cumulative setup discussed above avoids this level of stress on the lower-capacitance capacitor and switch by switching in additional capacitors rather than replacing the lower-capacitance capacitor with a higher-capacitance capacitor.

[0056] [Calculating capacitance value to achieve matching] FIG. 6 is a flowchart illustrating a process 500A for matching impedance according to one embodiment. The matching network may include components similar to those discussed above. In one embodiment, the matching network of FIG. 2 is utilized. In the first step of the illustrated process 500A of FIG. 6, an input impedance at RF input 13 is calculated (step 501A). The input impedance is based on an RF input parameter detected by an RF input sensor 21 at RF input 13. The RF input sensor 21 may be any sensor configured to detect an RF input parameter at RF input 13. The input parameter may be any measurable parameter at RF input 13, including voltage, current, or phase at RF input 13. In an exemplary embodiment, RF input sensor 21 detects the voltage, current, and phase at RF input 13 of matching network 11. Based on the RF input parameter detected by RF input sensor 21, control circuit 45 calculates the input impedance.

[0057] Next, the control circuit 45 calculates the plasma impedance presented by the plasma chamber 19 (step 502A). In one embodiment, the calculation of the plasma impedance is based on the input impedance (determined in step 501A), the capacitance of the series EVC 31, and the capacitance of the shunt EVC 33. In another embodiment, the determination of the plasma impedance may be performed using a power sensor 49 operably coupled to the RF output, the RF power sensor 49 configured to detect an RF power parameter. The RF power parameter may be any measurable parameter at the RF output 17, including the voltage, current, or phase at the RF output 17. The RF power sensor 49 may detect the output parameter at the RF output 17 of the matching network 11. Based on the RF power parameter detected by the RF power sensor 49, the control circuit 45 may calculate the plasma impedance. In yet another embodiment, the determination of the plasma impedance may be based on both the RF power parameter and the RF input parameter.

[0058] Once the variable impedance of the plasma chamber 19 is known, the control circuit 45 can calculate changes to make to the variable capacitance of one or both of the series and shunt EVCs 31, 33 in order to achieve impedance matching. Specifically, the control circuit 45 calculates a first capacitance value for the series variable capacitance and a second capacitance value for the shunt variable capacitance (step 503A). These values ​​represent new capacitance values ​​for the series EVC 31 and the shunt EVC 33 to enable impedance matching, or at least substantial impedance matching. In an exemplary embodiment, the calculation of the first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0059] Once the first and second capacitance values ​​have been calculated, the control circuit 45 generates a control signal to change at least one of the series variable capacitance and the shunt variable capacitance to the first and second capacitance values, respectively (step 504A). This occurs at approximately t=-5 μsec. The control signal instructs the switching circuit to change the variable capacitance of one or both of the series EVC 31 and the shunt EVC 33.

[0060] This change in EVC 31, 33 takes a total of approximately 9-11 μs, compared to approximately 1-2 seconds for a matching network using VVC. Once the switch to a different variable capacitance is complete, there is a wait period while the additional individual capacitors that make up the EVC couple and charge the circuit. This portion of the match tuning process takes approximately 55 μs. Finally, just before t=56 μs, RF power profile 403 shows a decrease from approximately 380 mV peak-to-peak to approximately 100 mV peak-to-peak. This decrease in RF power profile 403, representing a decrease in reflected power 407, occurs over a period of approximately 10 μs, at which point the match tuning process is considered complete.

[0061] Varying the series and shunt variable capacitances may include sending control signals to a series driver circuit 39 and a shunt driver circuit 43 to control the series and shunt variable capacitances, respectively, with the series driver circuit 39 operably coupled to the series EVC 31 and the shunt driver circuit 43 operably coupled to the shunt EVC 43. When the EVCs 31 and 33 are switched to their desired capacitance values, the input impedance may match a fixed RF source impedance (e.g., 50 ohms), thus providing impedance matching. If sufficient impedance matching does not occur due to variations in plasma impedance, the 500A process may be repeated one or more times to achieve impedance matching, or at least substantial impedance matching.

[0062] Using a matching network 11 (such as that shown in FIG. 2), the input impedance can be expressed as:

number

[0063] In the formula, Z in is the input impedance, and Z P is the plasma impedance, and Z L is the series inductor impedance, and Z 直列 is the series EVC impedance, and Z 分路 is the shunt EVC impedance. In an exemplary embodiment, the input impedance (Z in ) is calculated using the RF input sensor 21. EVC impedance (Z 直列 and Z 分路 ) is known at any given time by the control circuit, since the control circuit is used to command the various individual capacitors in each of the series and shunt EVCs to turn on or off. Additionally, the series inductor impedance (Z L ) are fixed values. Therefore, the system uses these values ​​to calculate the plasma impedance (Z P ) can be solved.

[0064] This determined plasma impedance (Z P ) and known desired

number

number

number

number

[0065] The newly calculated

number

number

[0066] The exemplary method for calculating the desired first and second capacitance values ​​and arriving at those values ​​in one step is significantly faster than incrementally moving the two EVCs to either zero the error signal or minimize the reflected power / reflection coefficient. In semiconductor plasma processing, where faster tuning schemes are desirable, this approach provides a significant improvement in the tuning speed of the matching network.

[0067] It should be noted that the present invention is not limited to the above process for matching impedances, for example, the process may use the parameter matrix detailed in Figure 7 of U.S. Patent Application Publication No. 2024 / 0177970, which is incorporated herein by reference in its entirety.

[0068] Those skilled in the art will recognize that several factors can contribute to the sub-millisecond elapsed time of the impedance matching process for a matching network using an EVC. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the driver circuit used. Other factors not listed may also contribute to the overall elapsed time of the impedance matching process. Therefore, the duration of the entire match tuning process for a matching network with an EVC is expected to be approximately 500 μs or less to complete from the start of the process (i.e., measuring with the control circuit and calculating the adjustments necessary to create the impedance match) to the end of the process (the point at which the efficiency of the RF power coupled into the plasma chamber increases due to the impedance match and reduced reflected power). Even with a match tuning process on the order of 500 μs, this process time still represents a significant improvement over a matching network using a VVC.

[0069] Table 1 presents data comparing the operating parameters of one example of an EVC with those of one example of a VVC. As can be seen, the EVC offers several advantages in addition to enabling fast switching for matching networks.

[0070] [Table 1]

[0071] As can be seen, in addition to the high speed switching capabilities enabled by EVC, EVC also provides reliability benefits, current handling benefits, and size benefits. Further advantages of EVC and / or matching networks that use the switching circuitry itself for EVC include:

[0072] Because the disclosed matching network does not contain any moving parts, the possibility of mechanical failure is reduced to that of other complete electrical circuits that may be used as part of a semiconductor manufacturing process. For example, a typical EVC may be formed from a durable ceramic substrate with copper metallization to form individual capacitors. The elimination of moving parts also increases resistance to breakdown due to thermal fluctuations during use.

[0073] EVCs are compact in size compared to VVCs, and the resulting weight and volume reduction can save valuable space within manufacturing facilities.

[0074] The design of EVCs provides an improved ability to customize matching networks for the specific design needs of a particular application. EVCs may be configured with custom capacitance ranges, one example of which is a nonlinear capacitance range. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. As another example, custom capacitance ranges may provide more resolution in specific regions of impedance matching. Custom capacitance ranges may also enable the generation of higher ignition voltages for easier plasma strike.

[0075] A short matching tuning process (approximately 500 μsec or less) allows the matching network to better withstand plasma changes within the manufacturing process, thereby increasing plasma stability and resulting in more controlled power for the manufacturing process.

[0076] · The use of digitally controlled EVCs rather than mechanical devices in the matching network provides more opportunities to fine-tune the control algorithm through programming.

[0077] EVC exhibits superior low frequency (kHz) performance compared to VVC.

[0078] Controlling the matching network to adjust the configuration between process steps 7 is a flowchart of a method 50 for controlling a matching network of a semiconductor manufacturing system, the method 50 enabling the matching network to change its matching configuration in anticipation of a new process step. The method is described with respect to the embodiment provided in FIGS. 1-6 and its system 87 for controlling the matching network 11, which includes the matching network 11, control circuitry 45, and memory 46, although the invention is not limited to such a configuration. It should be noted that the control circuitry and / or memory may be part of the matching network (FIG. 2) or may be separate from the matching network (FIG. 1).

[0079] In a first operation 51, the matching network 11 provides RF power from the RF source 15 to the plasma chamber 19. The matching network includes an electronically variable reactance element (EVRE) configured to provide a variable total reactance. In this example, the EVRE is an electronically variable capacitor (EVC) 31, 33, although the invention is not so limited. Generally, the EVRE can include one or more discrete reactive elements, where the reactive elements are capacitors or inductors or similar reactive devices. In this embodiment, referring to FIG. 5 , the EVC 651 (which may be used for the EVCs 31, 33) includes a discrete capacitor 653 configured to switch the input and output of the matching network 11 to change the total capacitance provided by the EVC 651, thereby allowing the matching network 11 to provide different match configurations. The change in match configuration reduces the RF power reflected back to the RF source 15.

[0080] In the exemplary embodiment, the matching network 11 includes two EVCs 31, 33, although the present invention is not limited to a particular number of EVCs or EVREs. In embodiments with two or more EVREs, each of the EVREs has a different position depending on which of the individual reactive elements are switched to input and output. Different matching configurations of the matching network are different combinations of matching positions of the EVREs. Thus, if a matching network has two EVREs, the matching configuration of that matching network at any given time is a combination of the matching position of the first EVRE and the matching position of the second EVRE. If a matching network has one EVRE, the matching configuration of that matching network at any given time is simply the matching position of a single EVRE.

[0081] The plasma chamber 19 is configured to perform a process on the substrate 27, the process including process steps including at least a first process step and a second process step. As described above, the plasma chamber 19 may, for example, deposit a material layer on the substrate 27 or etch a material layer from the substrate 27. The process step may be a deposition step, an etching step, a diffusion step, another processing step, or any other type of step in a process performed by the plasma chamber.

[0082] In a second operation 52, for each process step, memory 46 stores instructions for performing the process step. These instructions may include different parameters or recipes for the associated process. For example, the instructions for a given step may include instructions regarding the power level of RF power from RF source 15. The instructions may also include instructions indicating the type of power to be provided, such as a continuous wave signal or a pulsed RF signal.

[0083] In a third operation 53, while sequentially performing each of the process steps of the process, when the control circuit predicts that the plasma chamber will transition from a first process step to a second process step, the control circuit changes the matching configuration to a new matching configuration based on the instructions for performing the second process step. For example, different steps may require different power levels provided by the RF source 15. One process step may have a high power (e.g., 1000 W), while another process may be performed at a lower power level (e.g., 300 W). The transition from one power to another may be very rapid. When power is interrupted between processing steps, the time for which power is interrupted may be very short (e.g., tens of milliseconds). As discussed below, depending on the speed at which the EVC or other EVRE can be switched, the transition between steps provides an opportunity to change to one more suitable for the new process being initiated. The control circuit may predict a transition in a process step in various ways. For example, the control circuit may store or provide data indicating the timing of the transition.

[0084] Sequentially performing each of the process steps may be understood as continuing the process step until a predetermined result is achieved on the substrate. The result may include, for example, a desired thickness of a film or other material layer, a desired uniformity of coverage, a desired etch on the substrate, or a desired material property. Sequentially performing each of the process steps may also be understood as performing a series of process steps while the plasma chamber remains ignited. Sequentially performing each of the process steps may also be understood as a series of process steps in which RF power is not interrupted for more than a specific period, such as 500 microseconds or 100 microseconds. Note that the matching configuration change may occur before the plasma chamber begins the second process step or during the short time between the first and second process steps.

[0085] In addition to (or instead of) changing the matching configuration as the plasma chamber anticipates transitioning between process steps, the control circuit may be configured to change the tuning parameters of the matching network to new tuning parameters, where the new tuning parameters are based on instructions for performing a new (e.g., second) process step. The tuning parameters may be, for example, predetermined conditions for when impedance matching is initiated. For example, impedance matching may be configured to begin when a predetermined amount of reflected power (or a related parameter indicative of reflected power, such as a reflection coefficient) is exceeded, or when output power or a related parameter at the output of the matching network falls below a specific level. The tuning parameters may also be predetermined conditions for when impedance matching is terminated. For example, impedance matching may be configured to terminate when a predetermined amount of reflected power or a related parameter is exceeded, or when output power or a related parameter increases beyond a specific level. The tuning parameters may also be predetermined conditions for when impedance matching should be restarted after being stopped. For example, impedance matching may be configured to restart when a predetermined amount of reflected power or a related parameter is exceeded, or when output power or a related parameter is exceeded, for more than a specific number of control loops (e.g., two control loops) or for more than a specific time.

[0086] 8A-B provide graphs 71 and 75 comparing the speed of a plasma-enhanced atomic layer deposition (PEALD) semiconductor process with and without the disclosed system for controlling the matching network of a semiconductor processing system. Graph 71 in FIG. 8A illustrates a PEALD process without the disclosed method of adjusting the matching configuration in anticipation of a new process step. Waveform 72 represents the gases delivered to the plasma chamber, and waveform 73 represents the RF power delivered to the plasma chamber. These parameters are shown for the delivery, purge, plasma, and purge stages. The total cycle time is 0.8 seconds.

[0087] Graph 75 in FIG. 8B illustrates a PEALD process using the disclosed method of adjusting the matching configuration in prediction of a new process step. Waveform 76 represents the gas supplied to the plasma chamber, and waveform 77 represents the RF power supplied to the plasma chamber. These parameters are shown over the same supply, purge, plasma, and purge stages as in first graph 71. As can be seen, the total cycle time is 0.7 seconds, thus 0.1 seconds faster than a process without using the disclosed method. For the reasons discussed above, this shortened cycle time is expected because the rapid change in the matching configuration in prediction of a new process step allows for faster impedance matching during transitional process steps, thereby enabling more efficient power delivery to the plasma chamber during process changes.

[0088] It should be noted that while the matching network embodiments discussed herein have used an L or pi configuration, the claimed matching networks may be configured in other matching network configurations, such as a "T" configuration. Unless otherwise stated, the variable capacitors, switching circuits, and methods discussed herein may be used in any suitable configuration for a matching network.

[0089] It should be noted that while the embodiments discussed herein use one or more variable capacitors in a matching network to achieve impedance matching, any variable reactive element can be used. The variable reactive element can include one or more discrete reactive elements, which can be capacitors or inductors or similar reactive devices.

[0090] While the present invention has been described in terms of specific embodiments, including the presently preferred implementations of the invention, those skilled in the art will recognize numerous variations and modifications of the above-described systems and techniques. It is to be understood that other embodiments may be utilized, and structural and functional changes may be made, without departing from the scope of the present invention. Therefore, the spirit and scope of the present invention should be construed broadly as set forth in the appended claims.

Claims

1. 1. A system for controlling a matching network of a semiconductor manufacturing system, comprising: a matching network configured to provide radio frequency power from a radio frequency source to a plasma chamber, the matching network comprises an electronically variable reactance element configured to provide a variable total reactance; the electronically variable reactance elements comprise individual reactance elements configured to switch inputs and outputs of the matching network to vary the total reactance provided by the electronically variable reactance elements, thereby enabling the matching network to provide different matching configurations; the plasma chamber is configured to perform a process on a substrate; the process includes process steps including at least a first process step and a second process step; a memory configured to store, for each process step, instructions for performing said process step; and control circuitry configured to change the matching configuration to a new matching configuration based on instructions to perform the second process step when the plasma chamber predicts a transition from the first process step to the second process step while sequentially performing each of the process steps of the process.

2. performing the process steps sequentially to achieve a predetermined result on the substrate; The system of claim 1 , wherein the predetermined result comprises a predetermined film thickness, a predetermined coverage uniformity, a predetermined etch on the substrate, or a predetermined material property.

3. 10. The system of claim 1, wherein the plasma in the plasma chamber remains ignited while the process steps are performed sequentially.

4. 10. The system of claim 1, wherein said radio frequency power is not interrupted for more than 500 microseconds during continuous performance of said process steps.

5. 10. The system of claim 1, wherein the alteration of the alignment configuration occurs before the plasma chamber transitions to the second process step.

6. the control circuit is further configured to change a tuning parameter of the matching network to a new tuning parameter when the control circuit anticipates that the plasma chamber will transition from the first process step to the second process step while sequentially performing each of the process steps of the process; The system of claim 1 , wherein the new tuning parameters are based on instructions for performing the second process step.

7. The tuning parameters are: a predetermined condition when impedance matching begins; A predetermined condition when impedance matching ends, or a predetermined condition when impedance matching should be restarted after it has stopped.

8. The system of claim 1 , wherein the process step comprises at least one of a deposition process, a removal process, or a treatment process.

9. 10. The system of claim 1, wherein the instructions for performing the first process step and the instructions for performing the second process step include instructions for different power levels of the radio frequency power of the radio frequency source.

10. the instructions for performing the first process step include instructions for the radio frequency power to be provided by a pulsed radio frequency signal; 10. The system of claim 1, wherein the instructions for performing the second process step include instructions for the radio frequency power to be provided by a continuous wave signal.

11. The system of claim 1 , wherein changing the match network to the new match configuration reduces radio frequency power reflected back to the radio frequency source.

12. the matching network further comprising a second electronically variable reactance element; the second electronically variable reactance element comprises a discrete reactance element configured to switch inputs and outputs of the matching network to vary the total reactance provided by the second electronically variable reactance element; each of the electronically variable reactance elements has a different position depending on which of the individual reactance elements is switched into or out of the matching network; The system of claim 1 , wherein different matching configurations of the matching network include different combinations of matching positions of the electronically variable reactance elements.

13. 1. A method for controlling a matching network in a semiconductor manufacturing system, comprising: providing radio frequency power from a radio frequency source to a plasma chamber through a matching network; the matching network comprises an electronically variable reactance element configured to provide a variable total reactance; the electronically variable reactance elements comprise individual reactance elements configured to switch inputs and outputs of the matching network to vary the total reactance provided by the electronically variable reactance elements, thereby enabling the matching network to provide different matching configurations; the plasma chamber is configured to perform a process on a substrate; the process includes process steps including at least a first process step and a second process step; providing radio frequency power; storing, for each process step, instructions for performing said process step; while sequentially performing each of the process steps of the process, when it is predicted that the plasma chamber will transition from the first process step to the second process step, changing the matching configuration to a new matching configuration based on instructions for performing the second process step.

14. performing the process steps sequentially to achieve a predetermined result on the substrate; The method of claim 13 , wherein the predetermined result comprises a predetermined thickness of the film, a predetermined uniformity of coverage, or a predetermined material property.

15. 14. The method of claim 13, wherein the plasma in the plasma chamber remains ignited while the process steps are performed sequentially.

16. 14. The method of claim 13, wherein the radio frequency power is not interrupted for more than 100 microseconds during the continuous performance of the process steps.

17. 14. The method of claim 13, wherein the alteration of the alignment configuration occurs before the plasma chamber transitions to the second process step.

18. and, while sequentially performing each of the process steps of the process, when the plasma chamber anticipates transitioning from the first process step to the second process step, changing a tuning parameter of the matching network to a new tuning parameter; The method of claim 13 , wherein the new tuning parameters are based on instructions for performing the second process step.

19. The tuning parameters are: a predetermined condition when impedance matching begins; A predetermined condition when impedance matching ends, or 20. The method of claim 18, wherein the predetermined condition is when impedance matching should be restarted after it has stopped.

20. The method of claim 13 , wherein the process step comprises at least one of a deposition process, a removal process, or a treatment process.

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