Semiconductor device

Abstract

To provide a storage device capable of holding data for a long period.SOLUTION: The semiconductor device includes a memory element and a transistor functioning as a switching element for controlling supply, holding, and release of electric charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode and includes an oxide semiconductor in an active layer; therefore, the off-state current is extremely low. In the above memory device, data is stored not by injecting charge into a floating gate surrounded by an insulating film at high voltage but by controlling the amount of charge in a memory element through a transistor with extremely low off-state current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile semiconductor memory device, and to the configuration of a memory cell that stores data. [Background technology]

[0002] Semiconductor memory devices (hereinafter simply referred to as memory devices) include DRAM, which is classified as volatile memory. , SRAM, mask ROM, EPROM, EEPROM, which are classified as non-volatile memory, Flash memory, ferroelectric memory, etc., which are formed using a single crystal semiconductor substrate. Many of these memories are already in practical use. Among the semiconductor memories mentioned above, flash The memory allows data to be written and erased repeatedly, and can operate without power supply. It is a non-volatile memory that can retain data, making it highly convenient and resistant to physical shocks. Because of its strength, it is mainly used for portable storage media such as USB memory and memory cards, and It is widely available in

[0003] There are two types of flash memory: NAND type, which has a structure in which multiple memory cells are connected in series, and There are two types of memory cells: one is a NOR type, and the other is a type in which multiple memory cells are connected in a matrix. Each flash memory has a transistor that functions as a memory element in each memory cell. The transistor that functions as this memory element is called a floating gate. The electrode for storing the electric charge is provided between the gate electrode and the semiconductor film which is the active layer. This allows data storage by storing charge on the floating gate.

[0004] The following Patent Documents 1 and 2 disclose floating gates formed on a glass substrate. A thin film transistor having [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 6-021478 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-322899 Summary of the Invention [Problem to be solved by the invention]

[0006] By the way, in nonvolatile memory, the absolute value of the voltage applied to the memory element when writing data is However, it tends to be around 20V, which is generally larger than volatile memory. In the case of flash memory, which can be repeatedly When erasing data, it is necessary to apply a large voltage to the transistor used as the memory element. Therefore, when flash memory is operated, such as when writing or erasing data, The power consumed is high, which is why electronic devices that use flash memory as storage devices This is one of the factors that hinders the reduction of power consumption, especially in portable electronic devices such as cameras and mobile phones. When using flash memory for this purpose, the high power consumption has the disadvantage of shortening the continuous use time. Connected to Litt.

[0007] Although flash memory is non-volatile, data can be lost due to minute leakage of electric charges. Therefore, the current data retention period is said to be about 5 to 10 years. Therefore, there is a demand for a flash memory that can ensure a longer data retention period.

[0008] Furthermore, flash memory allows data to be written and erased repeatedly. However, when charges are stored in the floating gate, the gate insulating film deteriorates due to the tunnel current. Therefore, the number of times data can be rewritten in one memory element is tens of thousands to hundreds of thousands. Realization of flash memory that can withstand many more rewrites, with a limit of about 1000 times is desired.

[0009] In view of the above-mentioned problems, the present invention provides a storage device capable of reducing power consumption, One of the objects of the present invention is to provide a semiconductor device using the same. One of the objects of the present invention is to provide a memory device capable of storing data and a semiconductor device using the memory device. The invention relates to a storage device that can increase the number of times data can be rewritten, a semiconductor device using the storage device, One of the objects is to provide a semiconductor device. [Means for solving the problem]

[0010] A memory device according to one embodiment of the present invention includes a memory element and a memory cell for supplying and holding charge to the memory element. and a transistor that functions as a switching element for controlling the emission. In memory devices, charges are injected at high voltage into the floating gate surrounded by an insulating film. Instead, the amount of charge in a memory element is controlled via a transistor with extremely low off-state current. , and stores the data.

[0011] Specifically, the transistor has a wider band gap than silicon and a higher intrinsic carrier density. The semiconductor material has a lower conductivity than silicon in the channel forming region. By including a semiconductor material having the above-described characteristics in the channel formation region, Such semiconductor materials include: For example, oxide semiconductors and silicon carbide semiconductors have a band gap approximately three times larger than that of silicon. Silicon, gallium nitride, etc. Transistors using the above semiconductor materials are usually Compared with transistors made of semiconductor materials such as silicon and germanium, The flow can be extremely low.

[0012] Furthermore, the transistor that functions as a switching element has a threshold voltage in addition to the normal gate electrode. The transistor is characterized in that it is provided with a second gate electrode for controlling the voltage. The transistor may be an insulated gate field effect transistor, specifically, a first gate a second gate electrode and a semiconductor layer located between the first gate electrode and the second gate electrode; a first insulating film located between the first gate electrode and the semiconductor film; and a second gate electrode. a second insulating film located between the semiconductor film and the source electrode and the drain electrode connected to the semiconductor film; With the above configuration, the potential difference between the source electrode and the second gate electrode can be controlled. By doing so, the threshold voltage can be adjusted so that the off-state current of the transistor is reduced. .

[0013] By reducing the off-state current of the transistor that functions as a switching element, During the period in which the data is held (holding period), the charge stored in the memory element is This can prevent leakage through the transistor.

[0014] In addition, impurities such as water or hydrogen, which act as electron donors (donors), are reduced, and oxygen is The reduction of defects results in a highly purified oxide semiconductor (purified oxide Semiconductors are i-type (intrinsic semiconductors) or very close to i-type. Therefore, a transistor including the oxide semiconductor has a characteristic of having an extremely low off-state current. Specifically, the highly purified oxide semiconductor is analyzed by secondary ion mass spectrometry (SIMS). Measurement of hydrogen concentration by Condary Ion Mass Spectrometry The value is 5 x 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 The following is more preferable: is 5 x 10 17 / cm 3 or less, more preferably 1 × 10 16 / cm 3 The following applies. Also, The carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 Not yet The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. The concentration of impurities such as moisture and hydrogen is sufficiently reduced. Furthermore, the oxide semiconductor film is highly purified by reducing oxygen vacancies. As a result, the off-state current of the transistor can be reduced.

[0015] Here, analysis of the hydrogen concentration in the oxide semiconductor film will be described. Hydrogen concentration is measured using SIMS. SIMS, by its very nature, is unable to measure hydrogen near the surface of a sample or in areas where the material is different. It is known that it is difficult to obtain accurate data on the vicinity of the laminated interface with the other film. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, In the range where there is no extreme fluctuation in the value and a nearly constant value is obtained, The average value is used as the hydrogen concentration. When it is not possible to find a region where a nearly constant value is obtained due to the influence of the hydrogen concentration in the adjacent film In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is determined as the value of the hydrogen concentration. The hydrogen concentration in the film is used as the maximum value. If there is no mountain-shaped peak or valley-shaped peak with a minimum value, the value of the inflection point is taken as the hydrogen concentration. Adopted as.

[0016] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer The low value can be proved by various experiments. For example, when the channel width is 1×10 6 μm Even in a device with a channel length of 10 μm, the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the detection limit, i.e., 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-current density, which corresponds to the value obtained by dividing the off-current by the channel width of the transistor, is 100 It can be seen that the capacitance is less than zA / μm. A circuit that controls the charge flowing into or out of a capacitor element using the transistor is used. The off-state current density was measured. The capacitance element is used in the active layer of a transistor, and the amount of charge per unit time of the capacitance element is used to determine the capacitance of the transistor. The off-state current density of the transistor was measured. It was found that an even lower off-state current density of several tens of yA / μm was obtained when the voltage was 3 V. Therefore, in the semiconductor device according to one embodiment of the present invention, a highly purified oxide semiconductor film is The off-state current density of the transistor used as the active layer was measured by changing the voltage between the source and drain electrodes. Depending on the application, it may be 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably 1 Therefore, the highly purified oxide semiconductor film can be used as an active layer. The transistor used as the gate electrode has an off-state current of crystalline silicon. is significantly lower than

[0017] As the oxide semiconductor, an oxide semiconductor containing In or Zn is preferably used. It is preferable to use an oxide semiconductor containing In and Ga, or an oxide semiconductor containing In and Z. It is preferable to use an oxide semiconductor containing n. In order to make the oxide semiconductor film i-type (intrinsic), Dehydration or dehydrogenation, which will be explained later, is effective. In addition to these, gallium nitride is used as a stabilizer to reduce the variation in the electrical characteristics of the capacitors. It is preferable that the alloy contains tin (Sn) as a stabilizer. It is also preferable that hafnium (Hf) is contained as a stabilizer. It is also preferable that aluminum (Al) is contained as a stabilizer.

[0018] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Tetrium) (Lu).

[0019] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The oxide semiconductor may contain silicon.

[0020] For example, an In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In-Ga-Zn oxides have a sufficiently high resistance in the absence of an electric field, and Since the current can be made sufficiently small and the mobility is high, it is suitable for use in memory devices or semiconductor devices. It is suitable as a semiconductor material for use in semiconductor devices.

[0021] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m Materials expressed as (m>0) M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and In addition, Mn, Ga, Co, etc. can be used as the oxide semiconductor. SnO5(ZnO) n (n>0, and n is an integer) may be used. Please note that the above composition is derived from the crystal structure and is merely an example. The following is added.

[0022] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0023] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate. [Effects of the Invention]

[0024] The transistor with low off-state current is used as a switch for holding charge stored in a memory element. By using it as a switching element, it is possible to prevent leakage of charges from the memory element. The present invention provides a memory device capable of storing data for a long period of time and a semiconductor device using the memory device. It can be provided.

[0025] The voltage required to write and read data to the memory element is controlled by the switching element. The operating voltage of the transistor that functions as the A storage device that can reduce power consumption by significantly lowering the operating voltage compared to a conventional storage device. A semiconductor device using the memory device can be provided.

[0026] In addition, the degradation of the gate insulating film caused by tunnel current is suppressed compared to conventional flash memory. Therefore, the number of times data can be rewritten can be increased. It is possible to provide a semiconductor device using the device. [Brief explanation of the drawings]

[0027] [Figure 1] Circuit diagram of a memory cell and cross-sectional view of a transistor. [Figure 2] A circuit diagram of a transistor and a graph showing the value of the drain current Id versus the gate voltage Vgs. [Figure 3] Circuit diagram of a cell array. [Figure 4]1 is a timing chart of a cell array. [Figure 5] 1 is a timing chart of a cell array. [Figure 6] Circuit diagram of a cell array. [Figure 7] FIG. 2 is a diagram showing the configuration of a second word line driving circuit. [Figure 8] Circuit diagram of a memory cell. [Figure 9] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 10] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 11] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 12] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 13] FIG. [Figure 14] FIG. 1 is a block diagram of a storage device. [Figure 15] FIG. [Figure 16] Block diagram of an RF tag. [Figure 17] FIG. 2 is a diagram showing the configuration of a storage medium. [Figure 18] Electronic equipment illustration. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications of the details may be made. The present invention is not to be construed as being limited to the description of the following embodiments.

[0029] In addition, integrated circuits such as microprocessors and image processing circuits, RF tags, storage media, and semiconductors Any and all semiconductor devices that can use memory devices, such as display devices, can be used in the present invention. The semiconductor display devices include liquid crystal display devices and organic light emitting diode (OLED) devices. Light-emitting devices with light-emitting elements, such as those represented by l Micromirror Device), PDP (Plasma Display) Panel), FED (Field Emission Display), etc. A semiconductor display device having a circuit element using a semiconductor film in a pixel section or a driving circuit falls into this category. Included.

[0030] (Embodiment 1) FIG. 1A is a circuit diagram illustrating an example of a configuration of a memory cell of a memory device according to one embodiment of the present invention. In the circuit diagram shown in FIG. 1A, the memory cell 100 functions as a switching element. a transistor 101 functioning as a memory element, a transistor 103 functioning as a capacitor, The transistor 103 functioning as a memory element has a gate electrode and an active layer Data is stored by accumulating charges in the gate capacitance formed between the gate electrodes.

[0031] The transistor 101 that functions as a switching element has a first gate electrode and a threshold voltage. A second gate electrode is provided for controlling the voltage. a first gate electrode, a second gate electrode, and a semiconductor located between the first gate electrode and the second gate electrode; a first insulating film located between the first gate electrode and the semiconductor film; and a second gate electrode. a second insulating film located between the semiconductor film and a source electrode and a drain electrode connected to the semiconductor film; The transistor 101 has a first gate electrode, a second gate electrode, a source Various operations of the memory device can be controlled by applying potentials to the gate electrode and drain electrode.

[0032] The memory cell 100 may include transistors, diodes, resistors, capacitors, It may also include other circuit elements such as inductors.

[0033] The source electrode and the drain electrode of the transistor are connected to each other by the polarity and the voltage of the transistor. The name changes depending on the difference in potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. Hereinafter, either the source electrode or the drain electrode will be referred to as the first terminal, and the other as the second terminal. The memory cell 100 includes a transistor 101, a capacitor 102, and a transistor 10 The connection relationship of 3 is explained below.

[0034] In the memory cell 100 shown in FIG. 1A, A potential of a signal including data is applied to a node connected to the second terminal of the transistor 101. The capacitor 102 has a pair of gate electrodes connected to the gate electrodes of the transistors 103. One of the electrodes is connected to the gate electrode of the transistor 103, and the other is given a predetermined potential. connected to a node that is

[0035] The transistor 103 may be either an n-channel type or a p-channel type.

[0036] Note that the memory cell 100 shown in FIG. 1A does not necessarily include the capacitor 102 as a component. By providing the capacitor element 102 in the memory cell 100, a longer storage period can be achieved. On the other hand, by not providing the capacitor element 102 in the memory cell 100, This allows for increased storage capacity per unit area.

[0037] FIG. 1B shows a circuit diagram of a memory cell configuration different from that shown in FIG. 1A. In the circuit diagram shown in FIG. 1B, the memory cell 100 functions as a switching element. The memory element includes a transistor 101 that functions as a memory element and a capacitor 102 that functions as a memory element. Data is stored by accumulating charges in the capacitor 102 which functions as a capacitor.

[0038] The transistor 101 illustrated in FIG. 1B has the same structure as the transistor 101 illustrated in FIG. In addition to the first gate electrode, a second gate electrode is provided to control the threshold voltage. Poles are provided.

[0039] In the memory cell 100 shown in FIG. 1B, A potential of a signal including data is applied to the node where the capacitor 102 is connected. One of the pair of electrodes is connected to the second terminal of the transistor 101, and the other is connected to a predetermined potential. is connected to the given node.

[0040] In this specification, connection means electrical connection, and the current, voltage, or potential is This corresponds to a state where the signal can be supplied or transmitted. Therefore, the connected state is a direct connection. does not necessarily refer to the state in which a current, voltage, or potential is available or transferable. To enable transmission, the signal is transmitted through elements such as wiring, conductive films, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0041] Also, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is used for connecting a plurality of components. In this specification, the term "connection" refers to such a single conductive film. However, if a product combines the functions of multiple components, it is also included in this category.

[0042] In one embodiment of the present invention, a semiconductor device that functions as the switching element shown in FIG. 1(A) or FIG. 1(B) is The channel forming region of the transistor 101 has a band gap wider than that of silicon. , characterized in that it contains a semiconductor material having an intrinsic carrier density lower than that of silicon. By including a semiconductor material with such characteristics in the channel formation region, the off-current is extremely low. The transistor 101 can be realized.

[0043] Note that, as in one embodiment of the present invention, the amount of charge stored in the memory element can be controlled. In the case of a storage device that stores data, the supply of charge to the storage element and the discharge of charge from the storage element are The discharge of the charge and the retention of the charge in the memory element are controlled by a transistor that functions as a switching element. The length of the data retention period is controlled by the transistor 101. The amount of charge stored in the transistor 101 depends on the amount of charge leaking through the transistor 101. In this case, the off-state current of the transistor 101 can be significantly reduced as described above. Therefore, the leakage of the electric charge can be prevented, and the data retention period can be extended. .

[0044] Unless otherwise specified, the off-state current in this specification refers to the off-state current in an n-channel transistor. In this case, the drain electrode is set to a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is set to 0 or less. This refers to the current that flows between the source and drain electrodes when the gate is on.

[0045] A semiconductor material with a wider bandgap than silicon and a lower intrinsic carrier density than silicon Examples of materials include oxide semiconductors, silicon carbide (SiC), gallium nitride (GaN ) and other compound semiconductors. Oxide semiconductors include silicon carbide and gallium nitride. Unlike compound semiconductors such as silicon, it can be produced by sputtering or wet methods. It has the advantage of being easy to mass-produce. Also, unlike silicon carbide or gallium nitride, Since oxide semiconductors can be deposited at room temperature, they can be deposited on glass substrates or silicon substrates. It is possible to form films on integrated circuits using a silicon substrate. It is also possible to accommodate larger substrates. Therefore, oxide semiconductors are particularly suitable for mass production compared to the above-mentioned silicon carbide and gallium nitride. It also has the advantage of improving transistor performance (e.g., field-effect mobility). Even when trying to obtain a crystalline oxide semiconductor, the temperature must be between 250 and 800°C. A crystalline oxide semiconductor can be easily obtained by the treatment.

[0046] In the following description, the semiconductor film of the transistor 101 is an oxide film having the above-described advantages. The case where a compound semiconductor is used is given as an example.

[0047] In one embodiment of the present invention, at least a transistor functioning as a switching element 101 has a wide-gap semiconductor material such as the oxide semiconductor in the active layer. On the other hand, the transistor 103 functioning as a memory element has an active layer containing an oxide semiconductor. A conductor may be used, or an amorphous, microcrystalline, or polycrystalline material other than an oxide semiconductor may be used. Alternatively, a semiconductor such as silicon or germanium, which is either monocrystalline or single crystal, may be used. By using an oxide semiconductor film for the active layer of all the transistors in the memory cell 100, In addition, the transistor 103 functioning as a memory element can be The active layer is made of a material having a higher conductivity than an oxide semiconductor, such as polycrystalline or single-crystalline silicon. By using a semiconductor material that provides mobility, data can be read from the memory cell 100. can be performed at high speed.

[0048] In addition, in FIG. 1B, the memory cell 100 is a transistor that functions as a switching element. Although the present invention is not limited to a single configuration, the present invention is not limited to this configuration. In one embodiment, each memory cell has at least one transistor that functions as a switching element. It is sufficient to provide one transistor, and the number of the transistors may be plural. When the 00 has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel, in series, or both in series. Parallel connections may also be combined.

[0049] In this specification, the state in which transistors are connected in series means, for example, Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. The state in which transistors are connected in parallel is when the first terminal of the first transistor is connected to the second transistor. the second terminal of the first transistor is connected to the second terminal of the second transistor; It means that it is connected to a child.

[0050] The transistor 103 functioning as a memory element functions as a switching element. Unlike the transistor 101, it has at least a gate electrode that is located on only one side of the active layer. However, the present invention is not limited to this configuration, and any transistors that function as memory elements may be used. The transistor 103 is also active like the transistor 101 which functions as a switching element. There may be a pair of gate electrodes sandwiching the layer therebetween.

[0051] Next, FIG. 1C shows a cross-sectional view of the transistor 101 shown in FIGS. 1A and 1B. An example of the figure is shown.

[0052] In FIG. 1C, the transistor 101 is formed on a substrate 110 having an insulating surface. A gate electrode 111, an insulating film 112 on the first gate electrode 111, and a gate insulating film 112 therebetween an oxide semiconductor film 113 that functions as an active layer and overlaps the first gate electrode 111; , a source electrode 114 and a drain electrode 115 on the oxide semiconductor film 113, and the oxide semiconductor film 113, an insulating film 116 on the source electrode 114 and the drain electrode 115, and The second gate electrode 117 overlaps with the oxide semiconductor film 113 . In FIG. 1C, an insulating film 118 is formed on the second gate electrode 117. The transistor 101 may include an insulating film 118 as one of its components.

[0053] Note that FIG. 1C illustrates the case where the transistor 101 has a single-gate structure. However, the transistor 101 has a plurality of gate electrodes electrically connected to each other. A multi-gate structure having a plurality of channel forming regions may also be used.

[0054] Then, the threshold voltage of the transistor 101 is changed by changing the potential of the second gate electrode. First, a circuit diagram of a transistor 101 is shown in FIG. In FIG. 2A, the potential of the first gate electrode is Vcg, the potential of the second gate electrode is Vbg, The potential of the source electrode is Vs, the potential of the drain electrode is Vd, and The potential of each electrode is shown.

[0055] FIG. 2B shows the value of the drain current Id of the transistor 101 relative to the gate voltage Vgs. The gate voltage Vgs is the voltage at the first gate when the potential Vs of the source electrode is used as a reference. This corresponds to the difference between the potential Vcg of the ground electrode and the potential Vs of the source electrode.

[0056] The solid line 120 indicates the potential Vbg of the second gate electrode and the potential Vs of the source electrode. The figure shows the value of the drain current Id relative to the gate voltage Vgs when the The dashed line 121 indicates the potential Vbg of the second gate electrode and the potential Vs of the source electrode. The figure shows the value of the drain current Id relative to the gate voltage Vgs when the gate voltage Vgs is lower than , the line 120 and the line 121 are the same in potential Vs of the source electrode and the drain The potentials Vd of the electrodes are also assumed to be the same.

[0057] As shown in FIG. 2B, the potential Vbg of the second gate electrode of the transistor 101 is low. Indeed, the threshold voltage shifts to the positive side and the off-current is reduced. The higher the potential Vbg of the second gate electrode of the transistor 101, the more negative the threshold voltage of the transistor 101. The gate shifts to the negative side, and the off-state current increases, i.e., the on-state resistance decreases.

[0058] In the memory device according to one embodiment of the present invention, as described above, the length of the data retention period is determined by the memory element. The amount of charge stored in the transistor 101 leaks through the transistor 101. In one embodiment, the potential Vbg of the second gate electrode of the transistor 101 is controlled. Since the off-state current can be significantly reduced, the leakage of the charge can be prevented. This allows for a longer data retention period.

[0059] Next, an example of the configuration of a memory device having a plurality of memory cells and a method for driving the memory device will be described. do.

[0060] FIG. 3 is a circuit diagram of a cell array 200 having a plurality of memory cells 100 shown in FIG. 1(A). The configuration of the memory cell 100 is the same as that described in the first embodiment. can be taken into consideration.

[0061] In the cell array 200 shown in FIG. 3, a plurality of first word lines WL CG , a plurality of second word lines W L BG , a plurality of bit lines BL, a plurality of capacitance lines CL, a plurality of source lines SL, and other wirings. A signal or potential from the drive circuit is transmitted to each memory cell 10 via these wirings. 0 is supplied.

[0062] First word line WL CG is connected to the first gate electrode of the transistor 101. 2 word lines WL BG is connected to the second gate electrode of the transistor 101. The output line BL is connected to a first terminal of the transistor 101 and a first terminal of the transistor 103. The source line SL is connected to the second terminal of the transistor 103. L is one of the pair of electrodes of the capacitor 102 connected to the second terminal of the transistor 101. The electrode is connected to a different electrode than the one to which it is connected.

[0063] The number of wirings can be determined depending on the number and arrangement of the memory cells 100. Specifically, in the case of the cell array 200 shown in FIG. 3, memory cells are arranged in a matrix of y rows and x columns. connected to the first word line WL CG 1~WL CG y, second word line WL BG 1~WL BG y, capacitance lines CL1 to CLy, source lines SL1 to SLy, and bit lines BL1 to BLx, The case where the cells are arranged in the cell array 200 is shown as an example.

[0064] Next, the operation of the cell array 200 shown in FIG. 3 will be described using the timing chart of FIG. In FIG. 4, the memory cell in the first row and the first column, the memory cell in the first row and the xth column, Data is written and stored in the memory cell at row y, column 1 and the memory cell at row y, column x. In FIG. 4, the transistor 103 is a p-channel transistor. 1 shows an example of a channel transistor.

[0065] The shaded areas in the timing chart of Figure 4 indicate whether the potential is high or low. But it means a good period.

[0066] First, the operation of the cell array 200 during the data write period Ta will be described.

[0067] Data is written row by row. In FIG. 4, the memory cell in the first row and the first column The data is written to the memory cell in the yth row and the 1st column first. 10 illustrates an example in which data is written to a memory cell located at the yth row and the xth column.

[0068] First, the first word line WL CG 1 and capacitance line Specifically, in FIG. 4, the first word line WL CG 1 to high level potential V H is applied to the other first word lines WL CG 2~WL CG The ground potential GND is applied to y. Therefore, the first word line WL CG The first gate electrode of the transistor 1 is connected to Only the resistor 101 is selectively turned on. The ground potential GND is applied to the capacitance line CL1. A high-level potential VDD is applied to the other capacitance lines CL2 to CLy.

[0069] And the first word line WL CG During the period when the bit 1 and the capacitance line CL1 are selected, The potential of a signal containing data is applied to the bit lines BL1 and BLx. The level of the potential applied to the bit line B naturally differs depending on the data content. A high-level potential VDD is applied to L1, and a ground potential GND is applied to the bit line BLx. The potential applied to the bit lines BL1 and BLx is One of the electrodes of the capacitor 102 and the gate of the transistor 103 are connected to each other through the capacitor 101. Then, the voltage is applied to one of the electrodes of the capacitor 102 and the transistor 103. If the node to which the gate electrode of By controlling the amount of charge stored in the node FG, the memory cell in the first row and the first column Data is written to the memory cells in the xth column.

[0070] Next, the first word line WL CG A ground potential GND is applied to the first word line WL CG 1 The transistor 101, whose first gate electrode is connected to the

[0071] Next, the first word line WL CG y and capacity Specifically, in FIG. 4, the first word line WL CG High level potential on y VH is applied, and the other first word lines WL CG 1~WL CG (y-1) has ground potential GND is applied. Therefore, the first word line WL CG The first gate electrode is connected to y. Only the transistor 101 connected to the capacitor line CLy is selectively turned on. GND is applied, and the other capacitance lines CL1 to CL(y-1) are applied with a high-level potential VDD. can be obtained.

[0072] And the first word line WL CG During the period when the bit line CLy and the capacitance line CLy are selected, The potential of a signal containing data is applied to the bit lines BL1 and BLx. A ground potential GND is applied to the bit line BL1, and a high-level potential VDD is applied to the bit line BLx. The potential applied to the bit lines BL1 and BLx is One of the electrodes of the capacitor 102 and the gate electrode of the transistor 103 are connected via the gate electrode 101. The amount of charge stored in node FG is controlled according to the potential of the signal. By controlling this, data is written to the memory cell at row y, column 1 and the memory cell at row y, column x. The loading is carried out.

[0073] During the write period Ta, the ground potential GND is applied to all the source lines SL. With the above configuration, when the ground potential GND is applied to the node FG, the bit line BL This can suppress the generation of a current in the source line SL.

[0074] In addition, in order to prevent incorrect data from being written to the memory cells, the first word line WL CG After the selection period of the capacitance line CL is over, the potential of a signal including data is input to the bit line BL. It is desirable to end the period of time during which the

[0075] Next, the operation of the cell array 200 during the data retention period Ts will be described.

[0076] During the retention period Ts, all the first word lines WL CG At this time, transistor 101 is turned off. A potential of a certain level, specifically, a ground potential GND, is applied. During the retention period Ts, the second word line WL BG All of these have a lower potential than the ground potential GND. Therefore, the transistor 101 has a threshold voltage of 1 / 2 V. The off-state current of the transistor 101 is low because the off-state current is shifted to the negative side. As a result, the charge stored in node FG is less likely to leak, and data is stored for a long period of time. Retention can be performed.

[0077] Next, the operation of the cell array 200 during the data read period Tr will be described.

[0078] First, the capacitance line CL1 of the memory cell in the first row from which data is to be read is selected. In FIG. 4, the ground potential GND is applied to the capacitance line CL1, and the other capacitance lines CL2 to CLy are During the read period Tr, a high-level potential VDD is applied to all the first word lines. WL CG is in a non-selected state when the ground potential GND is applied. During the period when the source line CL1 is selected, a high level voltage is applied to all the source lines SL. The potential VR is given. The potential VR is either the same as the potential VDD or higher than the potential VDD. It is assumed to be a low potential higher than the ground potential GND.

[0079] The resistance between the source and drain electrodes of the transistor 103 is a function of the voltage stored at the node FG. Therefore, the bit lines BL1 and BLx depend on the charge stored in the node FG. Then, by reading the difference in the amount of charge from the potential, Data can be read from the memory cell in the first row and first column and the memory cell in the first row and xth column. do.

[0080] Next, the capacitance line CLy of the memory cell in the y-th row from which data is to be read is selected. In FIG. 4, the ground potential GND is applied to the capacitance line CLy, and the other capacitance lines CL1 to CL(y A high-level potential VDD is applied during the read period T In r, all the first word lines WL CG is deselected by applying the ground potential GND. In addition, while the capacitance line CLy is selected, all the source A high level potential VR is applied to the line SL.

[0081] The resistance between the source and drain electrodes of the transistor 103 is a function of the voltage stored at the node FG. Therefore, the bit lines BL1 and BLx depend on the charge stored in the node FG. Then, by reading the difference in the amount of charge from the potential, Data can be read from the memory cell at row y, column 1 and the memory cell at row y, column x. do.

[0082] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is contains the data actually read from the cell array.

[0083] In addition, in FIG. 4, the write period Ta, the hold period Ts, and the read period Tr are all Then, the second word line WL BG For example, if a low-level potential VSS is applied to all of the However, in one aspect of the present invention, the second word line WL BG For example, a low level potential VSS is applied to the memory cell. To speed up data writing, the second word is written to the row where data is written. Dosen WL BG The potential of the transistor 101 is set higher than the potential VSS to lower the threshold voltage of the transistor 101. You may also do so.

[0084] The timing chart shown in FIG. 5 shows the second word line WL BG Electricity Only the position is different from that of FIG. 4. Specifically, in FIG. 5, in the write period Ta, WL CG While 1 is selected, the second word of the memory cell in the row to be written line WL BG A ground potential GND is applied to the first word line WL CG y selected During this period, the second word line WL BG y The ground potential GND is applied to the data. Since the threshold voltage of the transistor 101 can be lowered during the hold period Ts While suppressing the leakage of charge during the write period Ta, This can speed up writing.

[0085] Next, another example of the configuration of a memory device having a plurality of memory cells and its driving method will be described. explain.

[0086] FIG. 6 is a circuit diagram of a cell array 300 having a plurality of memory cells 100 shown in FIG. 1(B). The configuration of the memory cell 100 is the same as that described in the first embodiment. can be taken into consideration.

[0087] In the cell array 300 shown in FIG. 6, a plurality of first word lines WL CG , a plurality of second word lines W L BG , a plurality of bit lines BL, a plurality of capacitance lines CL, and other wirings are provided. A signal or potential from the circuit is supplied to each memory cell 100 via these wirings.

[0088] First word line WL CG is connected to the first gate electrode of the transistor 101. 2 word lines WL BG is connected to the second gate electrode of the transistor 101. The capacitor line BL is connected to a first terminal of the transistor 101. The capacitor line CL is connected to a first terminal of the capacitor element 102. One of the pair of electrodes of the transistor 102 is connected to the second terminal of the transistor 101. is connected to a different electrode.

[0089] The number of wirings can be determined depending on the number and arrangement of the memory cells 100. Specifically, in the case of the cell array 300 shown in FIG. 6, memory cells are arranged in a matrix of y rows and x columns. connected to the first word line WL CG 1~WL CG y, second word line WL BG 1~WL BG y, capacitance lines CL1 to CLy, and bit lines BL1 to BLx are arranged in the cell array 300. This example shows a case where

[0090] Next, the operation of the cell array 300 shown in FIG. 6 will be described.

[0091] First, the operation of the cell array 300 during the data write period will be described. During the write period, the first word line WL CG When a signal with a pulse is input to 1, the pulse The potential of the first word line WL CG connected to 1 This is applied to the first gate electrode of the transistor 101. Therefore, the first word line WL CG 1 All of the transistors 101 having their first gate electrodes connected to

[0092] Next, a signal including data is input to the bit lines BL1 to BLx. The potential level of the signal input to BLx naturally differs depending on the data content. The potential input to BL1 to BLx is transferred to the capacitor element 101 via the transistor 101 that is turned on. A fixed potential is applied to all the capacitance lines CL. The amount of charge stored in the capacitor 102 is controlled according to the potential of the signal. By controlling this, data is written to the capacitor 102.

[0093] First word line WL CG When the input of the pulsed signal to the first word line W L CG All the transistors 101 having their first gate electrodes connected to 1 are turned off. And the first word line WL CG 2~WL CG A signal having a pulse is input to y in sequence, First word line WL CG 2~WL CG In the memory cell 100 having y, the above-described operation is repeated in the same way.

[0094] Next, the operation of the cell array 300 during the data retention period will be described. In this case, all the first word lines WL CG 1~WL CG y, transistor 101 is off A potential of a level at which the potential becomes low, specifically a low level potential, is applied. In this case, during the retention period, all the second word lines WL BG A low-level potential VSS is applied to Therefore, the threshold voltage of the transistor 101 is shifted to the positive side, When the off-state current of the transistor 101 is low, the capacitor 102 accumulates the charge. The stored charge is less likely to leak, allowing data to be retained for a long period of time. do.

[0095] Next, the operation of the cell array 300 during the data read period will be described. During the data read period, the first word line WL CG 1~WL CG y A signal having a pulse is input in sequence. The potential of the pulse, specifically, a high-level potential However, the first word line WL CG 1 to the first gate electrode of transistor 101 connected to When applied, all of the transistors 101 are turned on.

[0096] When the transistor 101 is turned on, the voltage stored in the capacitor element 102 is transferred via the bit line BL. The difference in the amount of charge is then read from the potential of the bit line BL. The data can be read out by

[0097] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is contains the data actually read from the storage unit.

[0098] In this embodiment, each of the write, hold, and read operations is performed on a plurality of memory cells 100. Although the driving method in which the driving is performed in sequence has been described, the present invention is not limited to this configuration. Alternatively, the above operation may be performed only in the memory cell 100 at the specified address.

[0099] Also, as in the case of the timing chart shown in FIG. 5, data is written to the memory cell. In order to speed up the write operation, the second word line WL BG Electricity The threshold voltage of the transistor 101 can be reduced by setting the potential higher than the potential VSS. good.

[0100] Note that a memory device according to one embodiment of the present invention has the configuration of the memory cell 100 shown in FIGS. 3 and 6. Not limited.

[0101] FIG. 8A shows another example of the configuration of the memory cell 100. The recell 100 includes a transistor 101, a capacitor 102, and a transistor 103. The first gate electrode of the transistor 101 is connected to the first word line WL CG connected to The second gate electrode of the transistor 101 is connected to the second word line WL BG connected to The first terminal of the transistor 101 is connected to the bit line BL. The second terminal of the transistor 101 is connected to the gate electrode of the transistor 103. The first terminal of the transistor 103 is connected to the data line DL. The second terminal of the transistor 103 is The capacitor 102 has a pair of electrodes, one of which is connected to the transistor 101 and the other is connected to the source line SL. The other end is connected to the gate electrode of the transistor 103, and the other end is connected to the capacitance line CL.

[0102] In the case of the memory cell 100 shown in FIG. 8A, a capacitor 102 and a The amount of charge held by the transistor 103 is read by the potential of the data line DL. It is possible.

[0103] Next, FIG. 8B shows another example of the configuration of the memory cell 100. The memory cell 100 shown in FIG. 1 includes a transistor 101, a capacitor 102, and a transistor 103. In addition, a transistor that functions as a switching element to control data reading is also included. The first gate electrode of the transistor 101 is connected to the first word line WL CG The second gate electrode of the transistor 101 is connected to the second word line W. L BG The first terminal of the transistor 101 is connected to the bit line BL. The second terminal of the transistor 101 is connected to the gate electrode of the transistor 103. The first terminal of the transistor 103 is connected to the second terminal of the transistor 104. The second terminal of the transistor 103 is connected to the source line SL. The first terminal of transistor 104 is connected to data line DL. , the third word line WL SW The capacitor 102 has a pair of electrodes, one of which is connected to The first terminal is connected to the gate electrode of the transistor 103, and the other terminal is connected to the capacitance line CL. do.

[0104] In the case of the memory cell 100 shown in FIG. 8B, when data is read, the third word line WL SW The transistor 104 is turned on by the change in the potential of The amount of charge held by the functioning capacitor 102 and transistor 103 is The potential of the data line DL can be read.

[0105] A storage device according to one aspect of the present invention is configured to write new data to the storage device so as to overwrite previously written data. Therefore, unlike conventional flash memory, data can be written One of the advantages is that there is no need to erase previously written data when rewriting. is.

[0106] In addition, in the case of general flash memory, the floating gate that stores the charge is an insulating Therefore, the floating gate is covered with a film and is in an insulating state. In order to store electric charges, a high voltage of about 20 V must be applied to the memory element. However, in one embodiment of the present invention, a highly purified oxide semiconductor film is used as an active layer of a transistor. The switching element used as the switching element allows data to be written and read. Therefore, the voltage required for the memory device to operate is only a few volts, significantly reducing power consumption. It can be done.

[0107] In a semiconductor device using a general flash memory, Because the required voltage (operating voltage) is high, a voltage boost circuit is usually used to However, in the memory device according to one embodiment of the present invention, the operation of the memory device is Since the operating voltage can be kept low, power consumption can be reduced. This reduces the load on external circuits, such as boost circuits, involved in the operation of the storage device. This allows for the functionality of external circuits to be expanded, thereby enabling the semiconductor device to have higher performance. .

[0108] In this embodiment, a driving method for handling binary digital data has been described. However, the storage device of the present invention can also handle multi-valued data with three or more values. In the case of multi-value data with more than 1000 values, as the value increases to 4 or 5, the charge amount between each value increases. Therefore, if a small off-state current exists, it becomes difficult to maintain the accuracy of the data. However, in one embodiment of the present invention, the off-state current is significantly Since a significantly reduced transistor is used as a switching element, the holding period associated with multi-values ​​is reduced. This can prevent the shortening of the time.

[0109] Next, the second word line WL BG Regarding the configuration of the second word line driving circuit for controlling the potential of An example of the circuit diagram of the second word line driving circuit 150 will be described below. vinegar.

[0110] The second word line driving circuit 150 shown in FIG. 7 includes a transistor 15 that functions as a diode. 1 (transistor for driving circuit) and a capacitance element 152 (capacitance element for driving circuit). A first terminal of the transistor 151 is supplied with the potential VSS via a terminal A. The first gate electrode and the second gate electrode of the transistor 151 are connected to the The capacitor element 152 has a pair of electrodes. One of the electrodes is connected to the second terminal of the transistor 151, and the other A predetermined potential is applied to the second terminal of the transistor 151. Wire WL BG is connected to.

[0111] Specifically, in FIG. 7, the second word line driving circuit 150 includes a transistor 151 and a capacitor 15 2 (m is a natural number equal to or greater than 2). The terminal has n (n is a natural number greater than or equal to 1) second word lines WLBG is connected.

[0112] Second word line WL BG When the potential of the first input terminal is higher than the potential VSS, the first input terminal is connected to the first output terminal through the transistor 151. 2 word lines WL BG A current flows from the second word line WL B G The potential is set to a potential higher than the potential VSS by the threshold voltage of the transistor 151. This potential is sufficiently lower than the potential of the source electrode of transistor 101 in memory cell 100. If the threshold voltage of the transistor 101 can be set to be higher, the threshold voltage of the transistor 101 will be shifted to a higher value. The off-state current of the transistor 101 is reduced. Therefore, the retention characteristics of the memory device can be improved. This can be done.

[0113] The supply of the potential VSS to the second word line driving circuit 150 is stopped, and the potential of the terminal A is set to the second Word line WL BG If the potential becomes higher than Since a voltage of this value is applied, only an off-state current flows through the transistor 151. The current charges the capacitor 152, and the second word line WL BG The potential of Finally, the source electrode and the second gate electrode of the transistor 101 are connected to each other. Since the potential difference between the However, the capacitive element 152 is not connected to the outside of the cell array. Since it can be arranged in the portion, it has a larger capacitance value than the capacitance element 102 in the memory cell. Therefore, the capacitance value of the capacitor 152 can be secured by If the capacitance of the capacitor 102 is increased by, for example, 100 times, the capacitance of the second word line WL BG Electricity It is possible to increase the time it takes for the rank to reach the upper limit by 100 times. If the period during which the supply of the potential VSS is stopped is short, the data stored in the storage device will be This allows you to avoid losing data.

[0114] Note that the transistor 151 does not necessarily have to have a second gate electrode. 7, a second gate electrode is provided in the transistor 151, and the second gate Connecting the electrode to the second terminal of transistor 151 is desirable for the following reasons: When the above configuration is adopted, the transistor 151, which functions as a diode, is forward biased. When a voltage of 1 V is applied to the transistor 151, the threshold voltage of the transistor 151 becomes low and the transistor 151 is turned on. The current becomes high and the second word line WL BG It is possible to increase the current supply capacity to When the above configuration is adopted, a reverse bias voltage is applied to the transistor 151. At this time, the threshold voltage of the transistor 151 is increased, so that the off-state current is reduced. Wire WL BG This can extend the time it takes for the potential of the electrode to reach its upper limit.

[0115] 7, as shown in the timing chart of FIG. 4, the second word line WL BG constant 1 illustrates the configuration of the second word line driving circuit 150 when supplying the potential VSS. As shown in the timing chart of FIG. 5, during the write period, the second word line WL BG Electric When supplying VSS and GND, terminal A in Figure 7 is used as a DC power supply. Connect to a signal source.

[0116] (Embodiment 2) In this embodiment, a transistor 101 using an oxide semiconductor and a transistor 102 using silicon are A method for manufacturing a memory device having the transistor 103 will be described.

[0117] However, the transistor 103 may be made of silicon, germanium, silicon germanium, Semiconductor materials such as single crystal silicon carbide may also be used. The transistor 103 is made of a single crystal semiconductor substrate such as a silicon wafer by an SOI method. It is formed using a silicon thin film manufactured by vapor deposition or a silicon thin film manufactured by vapor deposition. Alternatively, in one embodiment of the present invention, all the transistors constituting the memory cell can be An oxide semiconductor may be used for the insulating layer.

[0118] In this embodiment, first, as shown in FIG. 9(A), an insulating film 701 and a single layer are formed on a substrate 700. An island-shaped semiconductor film 702 separated from the crystalline semiconductor substrate is formed.

[0119] There is no significant limitation on the material that can be used for the substrate 700, but at least it is necessary to use a material that can be used for subsequent processing. The substrate 700 must have heat resistance sufficient to withstand the heat treatment. Glass substrates manufactured by the fusion method or float method, quartz substrates, semiconductor substrates, ceramic A glass substrate can be used when the temperature of the subsequent heat treatment is high. It is advisable to use a material with a strain point of 730°C or higher.

[0120] In this embodiment mode, the semiconductor film 702 is made of single crystal silicon. A method for manufacturing the transistor 103 will be described below. An example of a method for manufacturing the film 702 will be briefly described. An ion beam consisting of ions accelerated by an electric field is injected into the bond substrate, and the surface of the bond substrate is The crystal structure is disrupted and a locally weakened embrittlement layer is formed in a region at a certain depth from the surface. The depth of the region where the embrittlement layer is formed depends on the acceleration energy of the ion beam and the The incident angle can be adjusted by the angle of incidence. The insulating film 701 is sandwiched between the substrate 700 and the insulating film 701. After the bond substrate and the substrate 700 are superposed, a 1N / cm 2 More than 500N / cm 2 Less than 11N / cm, preferably 2 More than 20N / cm 2 below When pressure is applied to a part, the bond substrate and the insulating film 701 are separated from that part. The bonding begins at the beginning of the bonding process, and eventually the bonding spreads over the entire surface. As a result, the microvoids in the embrittlement layer expand and join together. At the embrittlement layer, the single crystal semiconductor film, which is a part of the bond substrate, is separated from the bond substrate. The temperature of the heat treatment is set to a temperature that does not exceed the strain point of the substrate 700. The semiconductor film is processed into a desired shape by etching or the like to form an island-shaped semiconductor film 702. It can be achieved.

[0121] The semiconductor film 702 is doped with boron, aluminum, gallium, or the like to control the threshold voltage. Impurity elements that impart p-type conductivity, or impart n-type conductivity such as phosphorus or arsenic An impurity element may be added. The addition of an impurity element for controlling the threshold voltage is performed by patterning. It may be performed on the semiconductor film before patterning, or on the semiconductor film 7 formed after patterning. The addition of impurity elements to control the threshold voltage may be performed on the BN layer. Alternatively, the addition of impurity elements may be performed on the substrate to roughly adjust the threshold voltage. To fine-tune the threshold voltage, the device is patterned on a bond substrate. This can be performed on the previous semiconductor film or on the semiconductor film 702 formed by patterning. That's fine.

[0122] In this embodiment mode, an example in which a single crystal semiconductor film is used is described. For example, a multilayer film formed on the insulating film 701 by vapor deposition may be used. A crystalline, microcrystalline, or amorphous semiconductor film may be used, and the semiconductor film may be sintered by a known technique. Known crystallization methods include laser crystallization using laser light, catalytic element crystallization, and the like. Alternatively, a crystallization method using a catalytic element and a laser crystallization method may be combined. In addition, when a substrate with excellent heat resistance such as quartz is used, In this case, thermal crystallization method using an electric furnace, lamp annealing crystallization method using infrared light, catalytic element Alternatively, a crystallization method using a high-temperature annealing method at about 950°C may be used. stomach.

[0123] Next, as shown in FIG. 9(B), after forming a gate insulating film 703 on the semiconductor film 702, A mask 705 is formed on the gate insulating film 703, and an impurity element that gives conductivity is introduced into the semiconductor film By doping a part of 702, an impurity region 704 is formed.

[0124] The gate insulating film 703 is formed by performing high density plasma treatment, heat treatment, etc. The surface of the silicon dioxide film can be formed by oxidizing or nitriding the silicon dioxide film. For example, rare gases such as He, Ar, Kr, and Xe, and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. In this case, the plasma is excited by introducing microwaves. This allows for the generation of high density plasma at low electron temperatures. Oxygen radicals (which may contain OH radicals) and nitrogen radicals (NH The surface of the semiconductor film is oxidized or nitrided by the reaction (which may contain radicals), An insulating film having a thickness of 1 to 20 nm, preferably 5 to 10 nm, can be formed so as to be in contact with the semiconductor film. For example, nitrous oxide (NO) is diluted 1 to 3 times (flow ratio) with Ar and the pressure is 10 to 30 Pa. The semiconductor film 702 was heated by applying microwave (2.45 GHz) power of 3 to 5 kW at a pressure of The surface is oxidized or nitrided. This treatment reduces the surface thickness by 1 nm to 10 nm (preferably 2 nm to Then, nitrous oxide (N2O) and silane (SiH4) are introduced. , and microwave (2.45 GHz) power of 3 to 5 kW was applied at a pressure of 10 to 30 Pa. A silicon oxynitride film is formed by vapor phase deposition to form a gate insulating film. By combining the reaction by the growth method, the gate insulating film with low interface state density and excellent dielectric strength is obtained. A velum can be formed.

[0125] The oxidation or nitridation of the semiconductor film by the high-density plasma treatment described above proceeds as a solid-phase reaction. The interface state density between the insulating film 703 and the semiconductor film 702 can be made extremely low. The insulating film formed by directly oxidizing or nitriding the semiconductor film 702 by high-density plasma treatment In addition, when the semiconductor film has crystallinity, it is possible to suppress the variation in the thickness of the insulating film. By using a high-temperature plasma treatment to oxidize the surface of the semiconductor film through a solid-phase reaction, This prevents oxidation from progressing too quickly only at the gate electrode, resulting in a gate with good uniformity and low interface state density. The insulating film formed by the high density plasma treatment can be used as a gate insulating film. The transistor formed by including the insulating film in part or all of the insulating film can suppress the variation in characteristics. can be done.

[0126] In addition, silicon oxide, silicon nitride oxide, and oxide are formed by using a plasma CVD method or a sputtering method. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide or tantalum oxide, tantalum oxide Thorium, hafnium silicate (HfSixOy (x>0, y>0)), nitrogen doped Hafnium silicate (HfSixOy(x>0, y>0)), nitrogen-doped hafnium silicate (HfSixOy(x>0, y>0)), Films containing fluorine aluminate (HfAlxOy (x>0, y>0)) etc. can be used as a single layer or The gate insulating film 703 may be formed by stacking.

[0127] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0128] The thickness of the gate insulating film 703 is, for example, 1 nm or more and 100 nm or less, preferably 10 nm. In this embodiment, the thickness can be increased to 50 nm or less by using a plasma CVD method. A single layer insulating film containing silicon oxide is used as the gate insulating film 703 .

[0129] Next, after removing the mask 705, as shown in FIG. 9(C), a portion of the gate insulating film 703 is The portion is removed, and an opening 706 is formed in the region overlapping the impurity region 704 by etching or the like. After that, a gate electrode 707 and a conductive film 708 are formed.

[0130] The gate electrode 707 and the conductive film 708 are formed by forming a conductive film so as to cover the opening 706. The conductive film can be formed by processing (patterning) the conductive film into a predetermined shape. The film 708 is in contact with the impurity region 704 at the opening 706. For the deposition, a CVD method, a sputtering method, a vapor deposition method, a spin coating method, etc. can be used. The conductive film is made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (M o), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), etc. An alloy containing the above metal as a main component may be used, or a compound containing the above metal may be used. Alternatively, a semiconductor film doped with an impurity element such as phosphorus that provides conductivity may be used. Alternatively, the insulating film 12 may be formed using a semiconductor such as polycrystalline silicon.

[0131] In this embodiment mode, the gate electrode 707 and the conductive film 708 are formed using a single-layer conductive film. However, this embodiment is not limited to this structure. It may be formed of a plurality of layered conductive films.

[0132] The combination of two conductive films is tantalum nitride or tantalum for the first layer and tantalum for the second layer. In addition to the above examples, tungsten nitride and tungsten nitride can be used. Examples include molybdenum and molybdenum, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so they can be used in the process after forming the two-layer conductive film. In this process, a heat treatment can be performed for the purpose of thermal activation. As a combination, for example, silicon doped with an impurity element that gives n-type conductivity and nickel silicide, and silicon and nickel silicide doped with impurity elements that give n-type conductivity. Also usable are tungsten silicide and the like.

[0133] In the case of a three-layer structure in which three or more conductive films are stacked, a molybdenum film, an aluminum film, and a molybdenum film are stacked. It is advisable to adopt a laminated structure of a dielectric film.

[0134] The gate electrode 707 and the conductive film 708 are made of indium oxide or a mixture of indium oxide and tin oxide. Indium oxide zinc oxide mixture, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride A light-transmitting conductive oxide film such as aluminum or zinc gallium oxide can also be used. do.

[0135] The gate electrode 707 and the conductive film 70 are selectively formed by a droplet discharge method without using a mask. The droplet ejection method is a method of ejecting or spraying droplets containing a predetermined composition from a fine hole. This refers to a method of forming a predetermined pattern by using a laser, and inkjet methods fall into this category. Included.

[0136] The gate electrode 707 and the conductive film 708 are formed by ICP (Inductively Coupled Plasma) deposition after the conductive film is formed. Inductively Coupled Plasma (Inductively Coupled Plasma) etching method is used. Etching conditions (amount of power applied to the coil-type electrode layer, amount of power applied to the electrode layer on the substrate side) By appropriately adjusting the pressure, the electrode temperature on the substrate side, etc., a desired tapered shape can be obtained. The tapered shape can be etched at different angles depending on the shape of the mask. The etching gas can be controlled using chlorine, boron chloride, silicon chloride, etc. chlorine-based gases such as carbon tetrachloride, carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride Fluorine-based gas or oxygen can be used as appropriate.

[0137] Next, as shown in FIG. 9(D), a conductive film is formed on the gate electrode 707 using the gate electrode 707 and the conductive film 708 as a mask. By adding an impurity element that imparts conductivity to the semiconductor film 702, the semiconductor film 702 overlaps with the gate electrode 707. A channel forming region 710 and a pair of impurity regions 70 sandwiching the channel forming region 710 therebetween. 9 and an impurity region 711 in which an impurity element is further added to a part of the impurity region 704. It is formed on the conductive film 702 .

[0138] In this embodiment, an impurity element (for example, boron) that imparts p-type conductivity is added to the semiconductor film 702. Let us take the following example.

[0139] FIG. 12(A) is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 12(A) corresponds to FIG. 9(D).

[0140] Next, as shown in FIG. 10(A), a gate insulating film 703, a gate electrode 707, a conductive film 7 Insulating films 712 and 713 are formed to cover the insulating film 08. Specifically, the insulating films 712 and 713 are The insulating film 713 is made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. In particular, an inorganic insulating film such as aluminum nitride oxide can be used. By using a low-k material for the insulating film 713, it is possible to reduce the thickness of various electrodes and wiring. This is preferable because it is possible to sufficiently reduce the capacitance caused by the insulator film 71. 2. A porous insulating film made of the above-mentioned materials may be used as the insulating film 713. In the case of a thin film, the dielectric constant is lower than that of a dense insulating film, so the parasitic It is possible to further reduce the capacitance.

[0141] In this embodiment mode, the insulating film 712 is made of silicon oxynitride, and the insulating film 713 is made of silicon nitride oxide. In this embodiment, the gate electrode 707 and the conductive film 70 are used as an example. 7 shows an example in which an insulating film 712 and an insulating film 713 are formed on the gate electrode 8. Only one insulating film layer may be formed over the conductive electrode 707 and the conductive film 708, or three or more insulating films may be formed over the conductive film 708. A plurality of insulating films may be stacked.

[0142] Next, as shown in FIG. 10(B), the insulating film 712 and the insulating film 713 are subjected to CMP (chemical mechanical polishing). By performing mechanical polishing or etching, the gate electrode 707 and the conductive film 708 are The surface is exposed. In order to improve the characteristics of the transistor 101 to be formed later, It is preferable that the surfaces of the insulating films 712 and 713 be as flat as possible.

[0143] Through the above steps, the transistor 103 can be formed.

[0144] Next, a manufacturing method of the transistor 101 will be described. As shown, the gate electrode 714 is formed on the insulating film 712 or the insulating film 713. 14 is formed using the same material and the same stacked structure as the gate electrode 707 and the conductive film 708. It is possible to do this.

[0145] The thickness of the gate electrode 714 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. By patterning, a gate electrode 714 is formed. It is preferable that the end of the pole is tapered, since this improves the coverage of the gate insulating film laminated thereon. The resist mask may be formed by an ink-jet method. When formed by the jet method, no photomask is used, which reduces manufacturing costs.

[0146] Next, as shown in FIG. 10(D), a gate insulating film 715 is formed on the gate electrode 714. Then, an island-shaped oxide film is formed on the gate insulating film 715 at a position overlapping the gate electrode 714. A semiconductor film 716 is formed.

[0147] The gate insulating film 715 is formed using the same material and the same stacked structure as the gate insulating film 703. However, the gate insulating film 715 is preferably formed to prevent impurities such as moisture and hydrogen from being formed as much as possible. When forming a silicon oxide film by sputtering, A silicon target or a quartz target is used as the target, and oxygen or uses a mixture of oxygen and argon gas.

[0148] Highly purified oxide semiconductors are obtained by removing impurities and reducing oxygen vacancies. Since the body is extremely sensitive to interface states and interface charges, highly purified oxide semiconductors The interface characteristics between the film 716 and the gate insulating film 715 are important. The gate insulating film 715 in contact with the semiconductor film 716 is required to have high quality.

[0149] For example, high-density plasma CVD using microwaves (frequency 2.45 GHz) produces dense, high-insulation This is preferable because it allows the formation of high-quality insulating films with high pressure. The close contact with the gate insulating film reduces the interface state and improves the interface characteristics. Because it can be done.

[0150] Of course, if a good insulating film can be formed as the gate insulating film 715, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film may be one whose film quality or interface characteristics with the oxide semiconductor are improved by heat treatment. In any case, it goes without saying that the quality of the gate insulating film is good, and Any material that can reduce the interface state density between the film and the oxide semiconductor and form a good interface is acceptable. .

[0151] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 715 having a structure in which an insulating film such as a silicon dioxide film is stacked may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are used as insulating films with high barrier properties and oxide semiconductors. The insulating film 716 is formed between the insulating film 716 and the gate electrode 718. As an insulating film with high barrier properties, for example, a silicon nitride film or a nitride oxide film is used. Examples of the barrier film include a silicon film, an aluminum nitride film, and an aluminum nitride oxide film. By using an insulating film with high resistance, impurities in the atmosphere such as moisture or hydrogen, or impurities contained in the substrate Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film 716 and the gate insulating film 7 15 or the interface between the oxide semiconductor film 716 and other insulating films and the vicinity thereof. In addition, when an oxide semiconductor film having a low nitrogen content is formed in contact with the oxide semiconductor film 716, By forming an insulating film such as a silicon film or silicon oxynitride film, the insulating film with high barrier properties can be directly oxidized. This can prevent the metal oxide from coming into contact with the nitride semiconductor film 716 .

[0152] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiO x (x>0) The gate insulating film 715 may be formed by layering the gate insulating film 715 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is in the range of 350 nm to 400 nm. It may be on the order of nm.

[0153] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 71 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 5.

[0154] Note that the gate insulating film 715 is in contact with an oxide semiconductor film 716 to be formed later. The gate insulating film 715 is made of a material containing hydrogen, which adversely affects the characteristics of the gate insulating film 716. It is desirable that the gate insulating film 715 does not contain hydrogen, hydroxyl groups, or moisture. In order to minimize the inclusion of moisture, sputtering is used as a pretreatment for film formation. The substrate 700 on which the gate electrode 714 is formed is preheated in a preheating chamber of the apparatus. It is preferable to desorb and exhaust impurities such as moisture or hydrogen adsorbed on the surface of the substrate. The temperature is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the preheating chamber is preferably a cryopump. The logic can be omitted.

[0155] The island-shaped oxide semiconductor film 716 is formed by forming an oxide semiconductor film over the gate insulating film 715. The oxide semiconductor film can be formed by processing it into a shape of 2 nm. or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 3 nm or more and 200 nm or less. The oxide semiconductor film is formed by sputtering using an oxide semiconductor as a target. The oxide semiconductor film is formed by a method in a rare gas (for example, argon) atmosphere. by sputtering in a mixed atmosphere of rare gas (e.g., argon) and oxygen. It can be formed as follows.

[0156] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 715 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing argon to which chlorine, carbon tetrafluoride, etc. have been added.

[0157] The oxide semiconductor film may be formed of any of the above-mentioned indium oxide, tin oxide, zinc oxide, and binary metal oxide. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn -Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, ternary In-Ga-Zn oxide (also called IGZO), which is an oxide of In-Al -Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga- Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Z n-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides Oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide Compounds can be used.

[0158] In this embodiment, a tantalum containing In (indium), Ga (gallium), and Zn (zinc) is used. In-Ga-Zn oxide semiconductor with a thickness of 30 nm obtained by sputtering using a Zn target The conductive thin film is used as an oxide semiconductor film. When forming the film by the quartz crystal deposition method, the atomic ratio of In:Ga:Zn is preferably 1:1:1, In-, denoted as 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 A Ga-Zn oxide target is used. In-Ga-Zn oxide with the above atomic ratio is used. By depositing an oxide semiconductor film using an oxide target, polycrystalline or CAAC can be obtained. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. The filling rate is preferably 95% or more and less than 100%. By using the above, the formed oxide semiconductor film becomes a dense film.

[0159] When an In-Zn oxide material is used as the oxide semiconductor, the target to be used is The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (InO In:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn= 1.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO = 3:4 to 15:2) For example, the target used to form an oxide semiconductor film made of In-Zn oxide is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn By keeping it within the above range, it is possible to realize an improvement in mobility.

[0160] In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and the remaining moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. During the deposition, the substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably The temperature may be 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump. As an exhaust means, a turbo pump with a A cryopump may be used to evacuate the processing chamber. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since the exhaust gas contains the oxide semiconductor film formed in the treatment chamber, The concentration of impurities can be reduced.

[0161] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film This is preferable because the thickness distribution is uniform.

[0162] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, up to the gate insulating film 715 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A pump is preferable. However, this preheating process can be omitted. Heating is performed to form the conductive films 719 and 720 before forming the gate insulating film 721, which is performed later. The same process may be carried out on the formed substrate 700 .

[0163] Note that the etching for forming the island-shaped oxide semiconductor film 716 is dry etching. Dry etching can be performed by wet etching, or both can be used. The gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride ( Preferred are silicon tetrachloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (SF 6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HB r), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing , etc. can be used.

[0164] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0165] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Organic acids such as phosphoric acid and oxalic acid can be used. (manufactured by Kanto Chemical Co., Ltd.) is used.

[0166] A resist mask for forming the island-shaped oxide semiconductor film 716 is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0167] Note that reverse sputtering is performed before forming a conductive film in the next step, and the island-shaped oxide semiconductor film 716 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 715. .

[0168] Note that the oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen (water) as impurities. It may contain a large amount of water or hydrogen, which easily forms donor levels. Therefore, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the conductive film (dehydration or dehydrogenation), The oxide semiconductor film 716 is heated under a reduced pressure atmosphere with an inert gas atmosphere such as nitrogen or a rare gas. under an oxygen gas atmosphere or ultra-dry air (CRDS (cavity ring down laser separation) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). In an atmosphere of air, preferably 1 ppm or less, preferably 10 ppb or less, The oxide semiconductor film 716 is subjected to heat treatment.

[0169] By performing heat treatment on the island-shaped oxide semiconductor film 716, Specifically, the temperature is preferably 250°C or higher and 750°C or lower. Alternatively, the heat treatment may be performed at a temperature of 400°C or higher but lower than the distortion point of the substrate. If the RTA method is used for the heat treatment, the delamination can be completed in a short time. Since hydration or dehydrogenation can be performed, processing can be performed at temperatures exceeding the strain point of the glass substrate. do.

[0170] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0171] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heat source such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Annealing) equipment, LRTA (Lamp Rap) Rapid Thermal Annealing (RTA) equipment The LRTA device can be used with a halogen lamp. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure natri The treated object is irradiated with light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps. The GRTA device is a device that uses high-temperature gas to perform heat treatment. The gas may be a rare gas such as argon or nitrogen, which is capable of reacting with the object to be treated by heat treatment. A non-reactive inert gas is used.

[0172] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is mixed with water or water. It is preferable that the nitrogen or helium introduced into the heat treatment device is not contained. The purity of rare gases such as neon and argon is 6N (99.9999%) or more, preferably 7N (99.9999%) or more. N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm) pm or less).

[0173] Note that oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem even if it is used in a low-cost sodalite, which contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current Status of Physical Properties and Device Development," Solid State Physics, September 2009, Vol. 44, pp. 62 1-633.) However, this is not an appropriate indication. Alkali metals do not form oxide semiconductors. Alkaline earth metals are not constituent elements of oxide semiconductors, so they are considered impurities. In particular, Na, among alkali metals, is an impurity when it is not an element that is present in the alloy. When the insulating film in contact with the semiconductor film is an oxide, Na diffuses into the insulating film. + It becomes. In addition, Na breaks the bond between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may change in the negative direction. This shift leads to deterioration of transistor characteristics, such as normally-on and reduced mobility. This impurity causes transistor characteristics to vary. The deterioration and variation of the characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor film is 5×10 19 cm -3 Below Below, especially 5x10 18 cm -3 If the concentration of the impurities is less than or equal to Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5 × 10 16 / cm 3 Less than 1 × 10 16 / cm 3 or less, more preferably 1 × 10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 The following is preferred: 1×10 15 / cm 3Similarly, the measured value of the K concentration should be 5 x 10 15 / cm 3 Less than 1 × 10 15 / cm 3 The following would be appropriate.

[0174] Through the above steps, the concentration of hydrogen in the island-shaped oxide semiconductor film 716 can be reduced. In addition, the carrier density caused by hydrogen is low when the heat treatment is performed below the glass transition temperature, and the bumps Therefore, it is possible to form an oxide semiconductor film having a wide band gap. The above heat treatment can be carried out by: The thermal treatment can be performed at any time after the formation of the oxide semiconductor film.

[0175] When the oxide semiconductor film is heated, the temperature may vary depending on the material of the oxide semiconductor film and heating conditions. Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially perpendicularly. It is preferable that the crystals are polycrystalline with the c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. In addition to the c-axis orientation of the polycrystalline body, the ab planes of the crystals are aligned. It is preferable that the a-axis or the b-axis of the oxide semiconductor film coincide with each other. If the surface is uneven, the plate crystal will become polycrystalline. Therefore, the substrate surface should be as flat as possible. It is hoped that there will be.

[0176] Next, as shown in FIG. 11(A), a part of the gate insulating film 715 is removed to form an opening 717. By forming the opening 718, a part of the gate electrode 707 and a part of the conductive film 708 are Then, the oxide film 714 is exposed. A conductive film 719 which is also in contact with the semiconductor film 716 and is in contact with the conductive film 708 in the opening 718, The conductive film 720 is formed so as to be in contact with the oxide semiconductor film 716. The conductive film 720 functions as a source electrode or a drain electrode.

[0177] Specifically, the conductive films 719 and 720 are formed so as to cover the openings 717 and 718. After forming a conductive film on the gate insulating film 715 by sputtering or vacuum deposition, the conductive film is It can be formed by processing (patterning) it into a predetermined shape.

[0178] The conductive films to be the conductive films 719 and 720 can be formed using aluminum, chromium, copper, tantalum, An element selected from titanium, molybdenum, and tungsten, or a composite containing the above elements Examples of the metal include gold and alloy films made of the above elements. chromium, tantalum, titanium, molybdenum, tungsten, etc. on the underside or on the top of the metal film Any high melting point metal film may be laminated. Aluminum or copper has a heat resistance. To avoid problems with corrosion, it is recommended to use it in combination with high melting point metal materials. Metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Scandium, yttrium, etc. can be used.

[0179] The conductive films to be the conductive films 719 and 720 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, A two-layer structure in which a titanium film is laminated on top of the titanium film, and an aluminum film is laminated on top of the titanium film. Examples include a three-layer structure in which a titanium film is formed on top of the laminated film.

[0180] The conductive films 719 and 720 are formed using a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium oxide. Indium tin oxide mixture, indium oxide zinc oxide mixture or the above metal oxide material with silicon A material containing silicon or silicon oxide can be used.

[0181] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0182] Note that the conductive film is etched so as not to remove the oxide semiconductor film 716 as much as possible. The materials and etching conditions are adjusted appropriately. Depending on the etching conditions, island-like The exposed portion of the oxide semiconductor film 716 is partly etched, whereby a groove (a depression) is formed. It may also be achieved.

[0183] In this embodiment mode, a titanium film is used as the conductive film. The conductive film can be selectively wet-etched using a solution containing ammonium peroxide. However, the oxide semiconductor film 716 may also be partly etched. Specifically, the solution contains 31% by weight of hydrogen peroxide, 28% by weight of ammonia water, and water. A solution of chlorine (Cl2), boron chloride, and chlorine (Cl2) in a volume ratio of 5:2:2 is used. The conductive film may be dry-etched using a gas containing (BCl3) or the like.

[0184] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A resist that corresponds to at least two different patterns using a single multi-tone mask Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0185] In addition, the oxide semiconductor film 716 and the conductive film 71 functioning as a source electrode or a drain electrode Between the conductive film 720 and the conductive film 9, an oxide conductive film serving as a source region and a drain region is formed. The material of the oxide conductive film may contain zinc oxide as a component. It is preferable that the oxide does not contain indium oxide. As conductive films, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gas oxide Sodium, etc. can be applied.

[0186] For example, in the case of forming an oxide conductive film, patterning for forming the oxide conductive film, The conductive film 719 and the conductive film 720 are patterned together. is also good.

[0187] By providing an oxide conductive film that functions as a source region and a drain region, Since the resistance between the film 716 and the conductive film 719 and the conductive film 720 can be reduced, In addition, the source and drain regions can be formed by the same material. By providing a functional oxide conductive film, the withstand voltage of the transistor can be increased.

[0188] Next, a plasma treatment using a gas such as N2O, N2, or Ar may be performed. This plasma treatment removes water and the like attached to the exposed surface of the oxide semiconductor film. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0189] FIG. 12(B) is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 12(B) corresponds to FIG. 11(A).

[0190] After the plasma treatment, the conductive film 719 and the conductive film 7 A gate insulating film 721 is formed to cover the oxide semiconductor film 716 and the gate insulating film 721. The gate electrode 72 is formed over the gate insulating film 721 at a position overlapping with the oxide semiconductor film 716. 2 is formed, and a conductive film 723 is formed in a position overlapping with the conductive film 719.

[0191] The gate insulating film 721 is formed using the same material and the same stacked structure as the gate insulating film 703. Note that the gate insulating film 721 is formed to prevent impurities such as moisture and hydrogen as much as possible. It is preferable that the insulating film does not contain any insulating film, and it may be a single layer insulating film or may be composed of a plurality of laminated insulating films. When hydrogen is contained in the gate insulating film 721, the hydrogen is absorbed into the oxide semiconductor. The hydrogen penetrates into the oxide semiconductor film 716 or extracts oxygen from the oxide semiconductor film 716. The film 716 may become low-resistance (n-type), which may result in the formation of a parasitic channel. Therefore, the hydrogen content of the gate insulating film 721 is reduced to a minimum by the film formation method. It is important not to use a material with high barrier properties for the gate insulating film 721. For example, as an insulating film with high barrier properties, a silicon nitride film, a silicon nitride oxide film, An aluminum nitride film, an aluminum nitride oxide film, or the like can be used. When a layered insulating film is used, a silicon oxide film or a silicon oxynitride film having a low nitrogen content is used. The insulating film is formed closer to the oxide semiconductor film 716 than the insulating film with high barrier properties. Then, the conductive films 719, 720, and An insulating film with high barrier properties is formed so as to overlap with the oxide semiconductor film 716. By using a thick insulating film, the oxide semiconductor film 716, the gate insulating film 721, or Impurities such as moisture or hydrogen enter the interface between the oxide semiconductor film 716 and another insulating film and the vicinity thereof. In addition, when the ratio of nitrogen is set to 0.01, the oxide semiconductor film 716 is in contact with the oxide semiconductor film 716. By forming insulating films such as low-resistance silicon oxide films and silicon oxynitride films, materials with high barrier properties can be used. This can prevent the insulating film from being in direct contact with the oxide semiconductor film 716.

[0192] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. Gate insulating film 7 has a structure in which a silicon nitride film having a thickness of 100 nm is laminated by the method. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. In this state, the temperature is 100°C.

[0193] Note that heat treatment may be performed after the gate insulating film 721 is formed. , ultra-dry air or rare gas (argon, helium, etc.) atmosphere, preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. The content is 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less. In this embodiment, for example, heating is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before the conductive films 719 and 720 are formed, moisture or hydrogen may be reduced. Similar to the previous heat treatment performed on the oxide semiconductor film to reduce the After the gate insulating film 721 containing oxygen is provided, heat treatment is performed. By this, the oxide semiconductor film 716 is free from the oxide semiconductor film 718 by the heat treatment. Even if oxygen vacancies occur in the semiconductor film 716, the oxide semiconductor Oxygen is supplied to the oxide semiconductor film 716. In the oxide semiconductor film 716, oxygen vacancies serving as donors are reduced and the stoichiometric composition ratio is As a result, the oxide semiconductor film 716 can be highly purified and become closer to i-type. This reduces variations in the electrical characteristics of transistors due to oxygen deficiency, and improves the electrical characteristics. The timing of this heat treatment is determined by the temperature of the gate insulating film 721. There are no particular limitations on the process as long as it is after the formation of the transparent conductive film. This process also serves as a heat treatment to reduce the resistance of the conductive film, and the oxide can be removed without increasing the number of processes. The semiconductor film 716 can be made closer to i-type.

[0194] Further, by performing heat treatment on the oxide semiconductor film 716 in an oxygen atmosphere, the oxide semiconductor By adding oxygen, oxygen vacancies that serve as donors in the oxide semiconductor film 716 may be reduced. The temperature of the heat treatment is, for example, 100°C or higher and lower than 350°C, preferably 150°C or higher and lower than 250°C. The oxygen gas used in the heat treatment in the oxygen atmosphere contains water, hydrogen, etc. It is preferable that the purity of the oxygen gas introduced into the heat treatment device is not more than 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities in oxygen It is preferable to keep the concentration of impurities at 1 ppm or less, preferably 0.1 ppm or less.

[0195] Alternatively, an oxide semiconductor film 716 may be formed by adding an oxide thereto by an ion implantation method, an ion doping method, or the like. The oxygen vacancies that act as donors may be reduced by adding a 2.45GH Oxygen plasma generated by microwaves at 2000 kJ / s may be added to the oxide semiconductor film 716.

[0196] The gate electrode 722 and the conductive film 723 are formed by forming a conductive film over the gate insulating film 721. Then, the conductive film is patterned to form the gate electrode 722 and the conductive film. The conductive film 723 is made of the same material as the gate electrode 714, or the conductive films 719 and 720. It can be formed using a similar structure.

[0197] The thickness of the gate electrode 722 and the conductive film 723 is 10 nm to 400 nm, preferably 100 For example, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. After forming a conductive film having a structure, a resist mask is formed by photolithography or the like. Then, unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning). The gate electrode 722 and the conductive film 723 may be formed by performing a photolithography process.

[0198] Through the above steps, the transistor 101 is formed.

[0199] Note that the portion where the conductive film 719 and the conductive film 723 overlap with each other with the gate insulating film 721 therebetween is It corresponds to the capacitance element 102 .

[0200] FIG. 12(C) is a top view of the memory cell after the above steps are completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 11C corresponds to FIG. 11B.

[0201] Although the transistor 101 has been described as a single-gate transistor, Optionally, a plurality of electrically connected gate electrodes 714 may be provided to facilitate channel formation. A transistor having a multi-gate structure having multiple regions can also be formed.

[0202] Note that the insulating film in contact with the oxide semiconductor film 716 (in this embodiment, the gate insulating film 7 15, the gate insulating film 721 corresponds to this.) is made of an insulating material containing a group 13 element and oxygen. Many oxide semiconductor materials contain Group 13 elements. The insulating material containing the element is compatible with the oxide semiconductor, and it is used as an insulating material in contact with the oxide semiconductor film. By using the oxide semiconductor film as a film, the state of the interface with the oxide semiconductor film can be kept favorable.

[0203] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). %), and gallium aluminum oxide is a material with a high gallium content (atomic %). Indicates an aluminum content (atomic %) of 100 or more.

[0204] For example, when an insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor film and the insulating film can be maintained good. For example, an oxide semiconductor film and an insulating film containing gallium oxide can be provided in contact with each other. This can reduce the pileup of hydrogen at the interface between the oxide semiconductor film and the insulating film. In addition, when an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same For example, it is possible to form an insulating film using a material containing aluminum oxide. It is also effective to form a thin film of aluminum oxide, which has the property of being difficult for water to pass through. Therefore, the use of this material is advantageous in terms of preventing water from entering the oxide semiconductor film. It is also preferred in

[0205] The insulating film in contact with the oxide semiconductor film 716 is subjected to heat treatment in an oxygen atmosphere or oxygen doping. It is preferable to make the insulating material have more oxygen than the stoichiometric composition ratio by using a filter or the like. Oxygen doping refers to adding oxygen to the bulk. The term "acid" is used to clarify that the acid is added not only to the surface of the thin film but also to the inside of the thin film. The elemental doping includes oxygen plasma doping in which oxygen in plasma form is added to the bulk. The oxygen doping may be performed by ion implantation or ion doping.

[0206] For example, when gallium oxide is used as an insulating film in contact with the oxide semiconductor film 716, By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO X (X=3+α, 0<α<1).

[0207] When aluminum oxide is used as the insulating film in contact with the oxide semiconductor film 716, oxygen By performing heat treatment under atmospheric conditions or oxygen doping, the composition of aluminum oxide is changed to Al 2O X (X=3+α, 0<α<1).

[0208] Further, an insulating film in contact with the oxide semiconductor film 716 is formed by gallium aluminum oxide (AlO). When using aluminum gallium, heat treatment in an oxygen atmosphere or oxygen doping is required. The composition of gallium aluminum oxide (aluminum gallium oxide) is Ga X Al2 -X O 3+α (0 <X<2、0<α<1)とすることができる。

[0209] By performing oxygen doping treatment, an insulating film having a region in which oxygen is present in a larger amount than the stoichiometric composition ratio is formed. When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and the oxide semiconductor film or the oxide The oxygen defects at the interface between the oxide semiconductor film and the insulating film are reduced, and the oxide semiconductor film is made i-type or i-type. It is possible to make it as close to the mold as possible.

[0210] Note that the insulating film having a region with more oxygen than the stoichiometric composition is Of the insulating films in contact with each other, either the insulating film located in the upper layer or the insulating film located in the lower layer Although it may be used in only one of the insulating films, it is preferable to use it in both insulating films. An insulating film having an oxygen-rich region is used for the insulating films located in the upper layer and the lower layer of the insulating film in contact with the oxide semiconductor film 716, and by adopting a configuration in which the oxide semiconductor film 716 is sandwiched, the above-described effect can be enhanced.

[0211] Also, the insulating film used for the upper layer or the lower layer of the oxide semiconductor film 716 may be an insulating film having the same constituent elements in the upper layer and the lower layer, or may be an insulating film having different constituent elements. For example, both the upper layer and the lower layer may be gallium oxide having a composition of Ga2O (X = 3 + α, 0 < α < 1), or one of the upper layer and the lower layer may be gallium oxide having a composition of Ga2O X (X = 3 + α, 0 < α < 1), and the other may be aluminum oxide having a composition of Al2O (X = 3 + α, 0 < α < 1). X (X = 3 + α, 0 < α < 1). X (X = 3 + α, 0 < α < 1).

[0212] Also, the insulating film in contact with the oxide semiconductor film 716 may be a laminate of insulating films having an oxygen-rich region compared to the stoichiometric composition ratio. For example, gallium oxide having a composition of Ga2 O X (X = 3 + α, 0 < α < 1) is formed on the upper layer of the oxide semiconductor film 716, and gallium aluminum oxide (aluminum gallium oxide) having a composition of Ga X Al2 -X O 3+α (0 < X < 2, 0 < α < 1) may be formed thereon. Note that the lower layer of the oxide semiconductor film 716 may be a laminate of insulating films having an oxygen-rich region compared to the stoichiometric composition ratio, or both the upper layer and the lower layer of the oxide semiconductor film 716 may be a laminate of insulating films having an oxygen-rich region compared to the stoichiometric composition ratio.

[0213] Next, as shown in FIG. 11(C), a gate insulating film 721, a conductive film 723, a gate electrode 72 The insulating film 724 is formed so as to cover the insulating film 2. The insulating film 724 is formed by a method such as PVD or CVD. It can be formed using silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, etc. It is formed using a material containing an inorganic insulating material such as silicon dioxide, gallium oxide, or aluminum oxide. The insulating film 724 may be made of a material with a low dielectric constant or a structure with a low dielectric constant (porous By lowering the dielectric constant of the insulating film 724, it is possible to This is because it reduces the parasitic capacitance that occurs between the electrodes and other elements, thereby enabling faster operation. Note that in this embodiment, the insulating film 724 has a single-layer structure. The shape is not limited to this, and a laminated structure of two or more layers may also be used.

[0214] Next, an opening 725 is formed in the gate insulating film 721 and the insulating film 724, and a part of the conductive film 720 is Then, a conductive film 720 is formed on the insulating film 724 in the opening 725. A wiring 726 is formed.

[0215] The wiring 726 is formed by forming a conductive film using a PVD method or a CVD method, and then patterning the conductive film. The conductive film is formed by etching. The material of the conductive film is aluminum, chromium, An element selected from aluminum, copper, tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above Alloys containing manganese, magnesium, zirconium, Beryllium, neodymium, scandium, or a combination of these materials It may be used.

[0216] More specifically, for example, a titanium film is thinly formed by PVD in the region including the opening of the insulating film 724. After forming a thin titanium film (about 5 nm) by the PVD method, A method of forming an aluminum film so as to fill the gap can be applied. The titanium film formed by this method reduces the oxide film (such as a natural oxide film) on the surface on which it is formed, It has the function of reducing the contact resistance with the electrode (here, the conductive film 720). In addition, it is possible to prevent the formation of burrs on the titanium film. After the aluminum film is formed, a copper film may be formed by plating.

[0217] The opening 725 formed in the insulating film 724 can be formed in a region overlapping with the conductive film 708. By forming the opening 725 in such a region, it is possible to prevent the formation of a contact region. This makes it possible to suppress an increase in the element area.

[0218] Here, the conductive film 708 is not used, and the impurity region 704 and the conductive film 720 are connected. The case where the connection between the impurity region 720 and the wiring 726 is overlapped will be described. An opening (called a lower opening) is formed in the insulating film 712 and the insulating film 713 formed on the region 704. After forming a conductive film 720 so as to cover the lower opening, a gate insulating film 721 and In the insulating film 724, an opening (referred to as an upper opening) is formed in a region overlapping with the lower opening. The upper opening is formed in the region overlapping with the lower opening, forming a wiring 726. When forming the conductive film 720, the conductive film 720 formed in the lower opening is broken by etching. To avoid this, make sure that the lower opening and the upper opening do not overlap. However, forming the element in this manner increases the element area.

[0219] As shown in this embodiment, the conductive film 708 is used to prevent the conductive film 720 from being broken. This allows the upper opening to be formed without forming the lower opening and the upper opening. Since the portions can be provided overlapping each other, an increase in the element area due to the opening can be suppressed. In other words, the degree of integration of the semiconductor device can be increased.

[0220] Next, an insulating film 727 is formed so as to cover the wiring 726. It is possible to create a storage device.

[0221] In the above manufacturing method, the conductive films 719 and 720 functioning as a source electrode and a drain electrode are The conductive film 720 is formed after the oxide semiconductor film 716. As shown in the figure, the transistor 101 obtained by the above manufacturing method has a conductive film 719 and a conductive film 720. The oxide semiconductor film 716 is formed on the oxide semiconductor film 720. 1, a conductive film functioning as a source electrode and a drain electrode is formed under an oxide semiconductor film 716. That is, the insulating film 714 may be provided between the oxide semiconductor film 716 and the gate insulating film 715.

[0222] 13, a conductive film 719 and a conductive film 720 which function as a source electrode and a drain electrode are formed. , the memory cell when the gate insulating film 715 is provided between the oxide semiconductor film 716 and the gate insulating film 715. 13 is a cross-sectional view of the transistor 101 after forming a gate insulating film 715. Then, the conductive films 719 and 720 are formed, and then the oxide semiconductor film 716 is formed. This can be obtained by doing so.

[0223] This embodiment mode can be implemented in combination with the above embodiment modes.

[0224] (Embodiment 3) An example of a specific configuration of a driver circuit in a memory device according to one embodiment of the present invention will be described.

[0225] FIG. 14 is a block diagram illustrating a specific configuration example of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 14, the circuits in the memory device are classified by function and are mutually Although it is shown as an independent block, the actual circuit can be completely separated by function. It is difficult, and one circuit may be involved in multiple functions.

[0226] A memory device 800 shown in FIG. 14 includes a cell array 801 and a driver circuit 802. The drive circuit 802 is a read circuit that generates a signal including data read from the cell array 801. a first word line drive circuit 804 for controlling the potential of the first word line; A second word line driver circuit 820 controls the potential of the word line, and a selector circuit 822 is provided in the cell array 801. and a bit line driver circuit 805 that controls writing of data in the selected memory cell. Furthermore, the driving circuit 802 includes a read circuit 803, a first word line driving circuit 804, A control circuit 806 that controls the operations of the second word line driving circuit 820 and the bit line driving circuit 805 It has the following characteristics.

[0227] In the memory device 800 shown in FIG. 14, the first word line driving circuit 804 is connected to the decoder 80. 7, a level shifter 808, and a buffer 809. has a decoder 810 , a level shifter 811 , and a selector 812 .

[0228] The memory device 800 according to one embodiment of the present invention includes at least a cell array 801 as its configuration. Furthermore, the memory device 800 according to one embodiment of the present invention may include a cell array 801. The memory module in which a part or all of the drive circuit 802 is connected to the The memory module is provided with connection terminals that can be mounted on a printed wiring board, etc. The semiconductor device may be in a so-called packaged state, in which the semiconductor device is protected by a resin or the like.

[0229] Also, a cell array 801, a read circuit 803, a first word line driving circuit 804, a second word line driving circuit 805, a The bit line driver circuit 820, the bit line driver circuit 805, and the control circuit 806 are all mounted on a single substrate. Alternatively, one or all of the layers may be formed using different substrates. It's okay to have it.

[0230] If a different substrate is used, FPC (Flexible Printed Circuit) In this case, the electrical connection can be ensured through the driver circuit 802. A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0231] A signal A containing the address (Ax, Ay) of the cell array 801 as information is sent to the memory device 800. When D is input, the control circuit 806 outputs information Ax relating to the column direction of the address to the bit line driver. and sends address row direction information Ay to the first word line driving circuit 804. The control circuit 806 also sends a signal DAT containing the data input to the storage device 800. A is sent to the bit line driver circuit 805 .

[0232] The selection of the data write operation or read operation in the cell array 801 is performed by the control circuit 80 6, the signal RE (Read enable) and the signal WE (Write enable) Furthermore, when there are multiple cell arrays 801, the control circuit A signal CE (Chip enable) for selecting the cell array 801 is input to 806. In this case, the operation selected by the signal RE and the signal WE may be input to the is executed in the cell array 801 selected by

[0233] In the cell array 801, when a write operation is selected by the signal WE, the control circuit 806 In accordance with the instruction from the decoder 807 of the first word line driving circuit 804, A signal is generated to select the memory cell corresponding to the address Ay. After the amplitude is adjusted by the shifter 808, the waveform is processed in the buffer 809. On the other hand, in the bit line driver circuit 805, the control circuit 806 In accordance with the instruction from the address Ax A signal for selecting a memory cell corresponding to the level shifter 8 is generated. After the amplitude is adjusted by the amplifier 11, the signal is input to the selector 812. The selector 812 The signal data is sampled according to the input signal and corresponds to the address (Ax, Ay). The sampled signal is input to the corresponding memory cell.

[0234] In addition, in the cell array 801, when a read operation is selected by the signal RE, the control circuit In accordance with the instruction from 806, a decoder 807 included in the first word line driving circuit 804 A signal for selecting a memory cell corresponding to the address Ay is generated. After the amplitude is adjusted by the level shifter 808, the waveform is processed in the buffer 809. The read circuit 803 receives the data from the control circuit 806 and inputs it to the cell array 801. In accordance with the instruction from the decoder 807, among the memory cells selected by the decoder 807, the address Ax Then, select the memory cell corresponding to the address (Ax, Ay). The data stored in the buffer is read and a signal containing the data is generated.

[0235] The second word line driving circuit 820 supplies the potential of the second word line to the cell array 801 .

[0236] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0237] (Fourth embodiment) In this embodiment, an example of a specific configuration of the readout circuit will be described.

[0238] The potential read from the cell array is determined according to the data written in the memory cell. Therefore, ideally, data of the same digital value is stored in multiple memory cells. If so, the potentials read from multiple memory cells will all be at the same level. However, in reality, a transistor, a capacitor, or a read element that functions as a memory element The characteristics of the transistor that functions as a switching element when data is read out are In this case, the data to be read may not all be the same digital data. Even if the value is the same, the actual read potential varies, so the distribution has a certain width. Therefore, even if there is some variation in the potential read from the cell array, It creates a signal that contains the necessary data and has its amplitude and waveform processed to meet the desired specifications. It is preferable to provide the readout circuitry in the drive circuitry.

[0239] An example of a readout circuit is shown in a circuit diagram in FIG. 15. The readout circuit shown in FIG. A switch for controlling the input of the potential Vdata read from the The transistor 260 functions as a switching element, and the transistor 261 functions as a resistor. 15 also includes an operational amplifier 262.

[0240] Specifically, the transistor 261 has its gate electrode and drain electrode (or drain region) is connected, and a high level is applied to the gate electrode and the drain electrode. The source electrode of the transistor 261 is connected to the power supply potential Vdd. The transistor 261 is connected to the non-inverting input terminal (+) of the amplifier 262. , the node to which the power supply potential Vdd is applied and the non-inverting input terminal (+) of the operational amplifier 262 In FIG. 15, the gate electrode and the drain electrode are connected to each other. However, the present invention is not limited to this, and a resistor and a transistor with connected poles are used as resistors. Any element that functions as such can be substituted.

[0241] The transistor 260, which functions as a switching element, has a gate electrode connected to the The potential Vda of the source electrode of the transistor 260 is applied according to the potential of the signal Sig. Control the supply of ta.

[0242] For example, when the transistor 260 is turned on, the potential Vdata and the power supply potential Vdd are connected to the transistor 260. The potential obtained by dividing the resistors by the transistor 260 and the transistor 261 is The voltage is applied to the non-inverting input terminal (+) of the amplifier 262. The level of the power supply potential Vdd is Since the voltage level obtained by the resistor division is fixed, the voltage level of the Vdata The digital value of the read data is reflected.

[0243] On the other hand, the inverting input terminal (-) of the operational amplifier 262 is supplied with a reference potential Vref. And, the potential applied to the non-inverting input terminal (+) is higher than the reference potential Vref. Depending on whether the voltage Vout is low or high, the level of the potential Vout at the output terminal can be varied. A signal containing data can be obtained indirectly.

[0244] Even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. The variation in the voltage Vdata also causes variations in the level of the read potential Vdata, and the distribution of the voltage Vdata varies widely. Therefore, the level of the reference potential Vref is Therefore, it is determined taking into consideration the variations in the node potential Vdata.

[0245] Also, since FIG. 15 shows an example of a readout circuit for handling binary digital values, The operational amplifiers used to read the data are connected to the nodes to which the potential Vdata is applied. However, the number of operational amplifiers is not limited to this. When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is applied is n- Let's say it's 1.

[0246] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0247] (Embodiment 5) In this embodiment mode, an example of the structure of an RF tag, which is one of the semiconductor devices of the present invention, will be described. Reveal.

[0248] FIG. 16 is a block diagram showing one embodiment of the RF tag of the present invention. The antenna circuit 550 includes an antenna circuit 551 and an integrated circuit 552. The integrated circuit 552 is source circuit 553, demodulation circuit 554, modulation circuit 555, regulator 556, arithmetic circuit 557 , a memory device 558, and a booster circuit 559.

[0249] Next, an example of the operation of the RF tag 550 will be described. The radio wave is converted into an AC voltage in the antenna circuit 551. The AC voltage from the antenna circuit 551 is rectified to generate a power supply voltage. The power supply voltage generated by the power supply circuit 551 is supplied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes the power supply voltage from the power supply circuit 553 or adjusts its level. Then, the integrated circuit 552 includes a demodulation circuit 554, a modulation circuit 555, an arithmetic circuit 557, and a memory device. The output voltage is supplied to various circuits such as a voltage regulator 558 or a booster circuit 559.

[0250] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the subsequent calculation circuit The calculation circuit 557 performs calculation processing according to the signal input from the demodulation circuit 554. When the above-mentioned calculation process is performed, the storage device 558 stores the primary cache. The arithmetic circuit 557 can be used as a flash memory or a secondary cache memory. The signal input from the demodulation circuit 554 is analyzed, and the signal is output in accordance with the command sent from the interrogator. Thus, the output of information in the memory device 558 or the execution of the contents of the instructions in the memory device 558 The signal output from the arithmetic circuit 557 is coded and sent to the modulation circuit 555. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 in accordance with the signal. The radio waves modulated by the antenna circuit 551 are received by the interrogator.

[0251] In this way, the communication between the RF tag 550 and the interrogator uses radio waves as a carrier. This is done by modulating the carrier. The modulation method also varies depending on the standard, and can be amplitude modulation, frequency modulation, phase modulation, etc. There are various modulation methods, such as modulation with a standard, but any modulation method can be used as long as it conforms to the standard. .

[0252] The signal transmission method is classified into electromagnetic coupling method, electromagnetic induction method, and microwave method depending on the carrier wavelength. They can be classified into various types, such as:

[0253] The boost circuit 559 boosts the voltage output from the regulator 556 and outputs it to the storage device 558. We are supplying it.

[0254] When the RF tag 550 is a passive type, a direct current is supplied to the RF tag 550 from an external power source. Therefore, the second word line driving circuit 150 shown in FIG. When the RF tag 550 is provided with the potential VSS, the potential VSS is supplied to the terminal A from the outside. Therefore, in one aspect of the present invention, when the RF tag 550 is a passive type, the charge A circuit for generating a negative potential, such as a pump circuit, is provided in the power supply circuit 553. The potential VSS is supplied from the power supply circuit 553 to the terminal A of the second word line driving circuit 150 shown in FIG. This can improve the retention characteristics of the storage device.

[0255] In one embodiment of the present invention, the memory device 558 has the structure described in the above embodiment. It is possible to retain data for a long period of time and increase the number of times data can be rewritten. Therefore, the RF tag 550 according to one aspect of the present invention can store the data using the storage device 558. This will increase the reliability of the data.

[0256] In one embodiment of the present invention, the memory device 558 has the structure described in any of the above embodiments. Therefore, the power consumption can be reduced. Since the power consumed inside the RF tag 550 can be kept low, The communication distance between the interrogator and the RF tag 550 can be increased accordingly.

[0257] In this embodiment, the configuration of an RF tag 550 having an antenna circuit 551 will be described. However, the RF tag according to one aspect of the present invention does not necessarily include an antenna circuit as a component. It is also possible to provide an oscillator circuit or a secondary battery in the RF tag shown in FIG.

[0258] This embodiment mode can be implemented in appropriate combination with the above embodiment modes or embodiments. is.

[0259] (Embodiment 6) In this embodiment, a semiconductor device using a memory device according to one embodiment of the present invention will be described. An example of a strip-type storage medium will be described.

[0260] FIG. 17A illustrates an example of the structure of a storage medium according to one embodiment of the present invention. The storage medium shown in A) is a storage device 751 according to one embodiment of the present invention, a drive device, and a storage medium. A connector 752 for electrical connection and a connector for various signals input and output via the connector 752 , an interface 753 that processes signals according to specifications, and an interface 754 that processes signals according to specifications, such as the operating state of the storage medium. Therefore, the light emitting diode 754 is turned on, and the memory device 751, the interface 753, the light emitting diode 754 are turned on. A controller that controls the operation of various circuits and semiconductor elements in the storage medium, such as a photodiode 754. A roller 755 is mounted on a printed wiring board 756. In addition, a controller A quartz crystal used to generate a clock signal to control the operation of the 755, memory A regulator or the like may be provided to control the level of the power supply potential in the medium. stomach.

[0261] The printed wiring board 756 shown in FIG. 17(A) is connected to the connector 7 as shown in FIG. 17(B). 52 and the light emitting diode 754 are covered with a cover material 757 made of resin or the like so that they are partially exposed. It is also possible to protect it by doing so.

[0262] The memory device 751 according to one embodiment of the present invention can reduce power consumption during operation. This allows for lower power consumption of the storage medium using the storage device 751, and ultimately reduces the power consumption of the storage medium. A driving device connected to the driving circuit can be reduced in power consumption. The storage device 751 can store data for a long period of time and can also write data. Since the number of times of replacement can be increased, the reliability of the storage medium can be improved.

[0263] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0264] By using a semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and low power consumption devices can be realized. It is possible to provide electronic devices with low power consumption and high-speed operation. In the case of portable electronic devices that are difficult to install, the low-power semiconductor device according to one embodiment of the present invention By adding the device to the components, the benefit of continuous use time can be extended. Obtained.

[0265] The semiconductor device according to one embodiment of the present invention can be used in a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in an electric device. Sub-devices include mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) navigation systems, audio playback devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, multi-function printers, automated teller machines Examples of such electronic devices include ATMs and vending machines. show.

[0266] FIG. 18A shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. It can be used in an integrated circuit for controlling the operation of a portable game console. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, a highly reliable portable game device can be realized. It is possible to provide a portable game machine with high functionality. The portable game machine has two display units 7033 and 7034. The number of display units that the game machine has is not limited to this.

[0267] FIG. 18B shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the driving of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this device, we can provide highly reliable mobile phones with advanced functions. Cut.

[0268] FIG. 18C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 18C has a modem built in a housing 7051. A semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a highly reliable portable information terminal, a highly functional portable information terminal, A portable information terminal can be provided.

[0269] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0270] 100 memory cells 101 Transistor 102 Capacitor element 103 Transistor 104 transistors 110 Substrate 111 Gate electrode 112 insulating film 113 Oxide semiconductor film 114 Source electrode 115 Drain electrode 116 Insulating film 117 Gate electrode 118 insulating film 120 lines 121 line 150 Second word line driving circuit 151 transistors 152 Capacitor element 200 cell array 260 transistors 261 Transistor 262 Operational Amplifier 300 cell array 550 RF tags 551 Antenna Circuit 552 Integrated Circuits 553 Power supply circuit 554 Demodulation Circuit 555 Modulation Circuit 556 Regulator 557 Arithmetic circuit 558 Storage device 559 Boost Circuit 700 boards 701 Insulating film 702 Semiconductor film 703 Gate insulating film 704 Impurity region 705 Mask 706 Opening 707 Gate electrode 708 Conductive film 709 Impurity region 710 Channel formation region 711 Impurity region 712 insulating film 713 Insulating Film 714 Gate electrode 715 Gate insulating film 716 Oxide semiconductor film 717 Opening 718 Opening 719 Conductive Film 720 Conductive film 721 Gate insulating film 722 gate electrode 723 Conductive Film 724 insulating film 725 Opening 726 Wiring 727 Insulating Film 751 Storage device 752 Connector 753 Interface 754 Light Emitting Diode 755 Controller 756 Printed Wiring Board 757 Cover material 800 storage device 801 Cell Array 802 drive circuit 803 Circuit 804 First word line driving circuit 805 Bit line driver circuit 806 Control circuit 807 decoder 808 Level Shifter 809 buffer 810 decoder 811 Level Shifter 812 Selector 820 second word line driving circuit 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key

Claims

1. a first circuit and a second circuit; The first circuit and the second circuit are semiconductor devices each having a first transistor, a second transistor, and a capacitor, a silicon layer having a channel formation region of the first transistor; a first conductive layer having a region located above the silicon layer and functioning as a gate electrode of the first transistor; a second conductive layer disposed in the same layer as the first conductive layer; a first insulating layer having a region in contact with a side surface of the first conductive layer and a region in contact with a side surface of the second conductive layer; a second insulating layer having a region located above the first insulating layer; a third conductive layer having a region located above the second insulating layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer disposed in the same layer as the third conductive layer and functioning as the other of the source electrode and drain electrode of the second transistor; an oxide semiconductor layer including a channel formation region of the second transistor; a fifth conductive layer that functions as a gate electrode of the second transistor; a sixth conductive layer disposed in the same layer as the fifth conductive layer; a third insulating layer having a region located above the fifth conductive layer; a seventh conductive layer having a region located above the third insulating layer; the first conductive layer is electrically connected to the third conductive layer; the second conductive layer is disposed so as to overlap the seventh conductive layer with the fourth conductive layer interposed therebetween; the sixth conductive layer overlaps the third conductive layer and functions as an electrode of the capacitor; the seventh conductive layer has a function of electrically connecting a source or a drain of the first transistor in the first circuit to a source or a drain of the first transistor in the second circuit.

2. a first circuit and a second circuit; The first circuit and the second circuit are semiconductor devices each having a first transistor, a second transistor, and a capacitor, a silicon layer having a channel formation region of the first transistor; a first conductive layer having a region located above the silicon layer and functioning as a gate electrode of the first transistor; a second conductive layer disposed in the same layer as the first conductive layer; a first insulating layer having a region in contact with a side surface of the first conductive layer and a region in contact with a side surface of the second conductive layer; a second insulating layer having a region located above the first insulating layer; a third conductive layer having a region located above the second insulating layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive layer disposed in the same layer as the third conductive layer and functioning as the other of the source electrode and drain electrode of the second transistor; an oxide semiconductor layer including a channel formation region of the second transistor; a fifth conductive layer that functions as a gate electrode of the second transistor; a sixth conductive layer disposed in the same layer as the fifth conductive layer; a third insulating layer having a region located above the fifth conductive layer; a seventh conductive layer having a region located above the third insulating layer; the first conductive layer is electrically connected to the third conductive layer; the second conductive layer is disposed so as to overlap the seventh conductive layer with the fourth conductive layer interposed therebetween; the sixth conductive layer overlaps the third conductive layer and functions as an electrode of the capacitor; the seventh conductive layer has a function of electrically connecting a source or a drain of the first transistor in the first circuit to a source or a drain of the first transistor in the second circuit; a direction connecting a source region and a drain region of the first transistor in a plan view is a first direction; In a plan view, the width of the second conductive layer in the first direction is larger than the width of the first conductive layer in the first direction.

3. In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer contains In.

4. In claim 1 or claim 2, The semiconductor device, wherein the oxide semiconductor layer contains In, Ga, and Zn.

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