Semiconductor module and electronic device

Abstract

SOLUTION: In a method of manufacturing a semiconductor module, after a first die having a first die electrode, a second die having a second die electrode, a first connection part connected to the first die electrode, and a second connection part connected to the second die electrode are sealed with a sealing body, a bridge having a first bridge electrode and a second bridge electrode is mounted on a structure sealed with the sealing body. The first die and the second die 42 are electrically connected via a bridge.SELECTED DRAWING: Figure 21

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and an electronic device. [Background technology]

[0002] There are technologies for connecting multiple IC (Integrated Circuit) chips. For example, Patent Document 1 describes a semiconductor package in which two IC chips are connected by a bridge (nested component) molded together with an interposer. Patent Document 2 describes a semiconductor package in which two IC chips are electrically connected via a bridge formed integrally with the interposer via an underfill material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0005542 [Patent Document 2] US Patent Application Publication No. 2020 / 0395313 Summary of the Invention [Problem to be solved by the invention]

[0004] The inventors of the present application have studied semiconductor packages having multiple IC chips connected via bridges and semiconductor modules using such packages, and have found that there is room for improvement in the semiconductor packages and semiconductor modules described above. For example, when electrically connecting two IC chips via a bridge integrated with an interposer, it is difficult to align the terminals of the two IC chips with the terminals of the bridge with high precision. This limits the density of the terminals electrically connecting the IC chips and the bridge.

[0005] The present invention has been made in light of such a situation, and one exemplary purpose of an embodiment of the present invention is to provide a technique that enables higher density bonding between IC chips and bridges. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor module according to one embodiment includes the steps of: (a) forming, on a first surface of a first support, a first connection portion including a first columnar connection portion extending in an out-of-plane direction of the first surface; and a second connection portion including a second columnar connection portion extending in an out-of-plane direction of the first surface; (b) preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, and mounting the first semiconductor die and the second semiconductor die on the first support such that the first die electrode is disposed on the first connection portion and the second die electrode is disposed on the second connection portion; (d) after step (c), encapsulating the first semiconductor die, the second semiconductor die, the first connecting portion, and the second connecting portion with a first sealing body; (d) after step (c), removing the first support and exposing a portion of the first columnar connecting portion and a portion of the second columnar connecting portion from the first sealing body; (e) preparing a bridge including a first bridge electrode connected to the first connecting portion and a second bridge electrode connected to the second connecting portion, and after step (d), mounting the bridge on the structure encapsulated with the first sealing body so that the first bridge electrode is disposed on the first columnar connecting portion and the second bridge electrode is disposed on the second columnar connecting portion.

[0007] Another embodiment of a method for manufacturing a semiconductor module includes: (a) forming a first insulating layer on a first surface of a first support, and then forming a first opening and a second opening in the first insulating layer; (b) forming a first connecting portion including a first columnar connecting portion formed in the first opening and a second connecting portion including a second columnar connecting portion formed in the second opening; and (c) preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode, such that the first die electrode is disposed on the first connecting portion and the second die electrode is disposed on the second connecting portion. (d) after step (c), mounting the first semiconductor die and the second semiconductor die on the first support, (d) after step (c), encapsulating the first semiconductor die and the second semiconductor die with a first encapsulant, (e) after step (d), removing the first support and exposing a portion of the first columnar connecting portion and a portion of the second columnar connecting portion from the first insulating layer, (f) preparing a bridge including a first bridge electrode connected to the first connecting portion and a second bridge electrode connected to the second connecting portion, and after step (e), mounting the bridge on the structure encapsulated with the first encapsulant so that the first bridge electrode is disposed on the first columnar connecting portion and the second bridge electrode is disposed on the second columnar connecting portion. In step (c), the first insulating layer and the second insulating layer are bonded to each other, and the first die electrode is encapsulated by the first insulating layer and the second insulating layer. In the step (c), the first insulating layer and the third insulating layer are bonded to each other, and the second die electrode is sealed by the first insulating layer and the third insulating layer.

[0008] Another embodiment of a semiconductor module includes a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, a bridge having a first bridge electrode electrically connected to the first die electrode, a second bridge electrode electrically connected to the second die electrode, and a wiring layer, an encapsulant encapsulating at least a portion of the bridge and having a first surface facing the first IC chip and the second IC chip and a second surface opposite the first surface, and an external electrode formed on the second surface of the encapsulant. The wiring layer of the bridge includes a first wiring electrically connected to the first bridge electrode or the second bridge electrode and multiple insulating layers encapsulating the first wiring. A portion of the first bridge electrode and a portion of the second bridge electrode are each exposed from the first surface of the encapsulant. The wiring layer has a third surface to which the first bridge electrode and the second bridge electrode are connected and a fourth surface opposite the third surface. The first wiring and the external electrode are electrically connected through a via formed on the fourth surface of the wiring layer.

[0009] Another aspect of the present invention relates to an electronic device comprising: a first die having a first electrode, a second die having a second electrode, a first connection electrically connected to the first electrode, a second connection electrically connected to the second electrode, and a bridge electrically connected to the first and second connection portions, wherein the first connection portion has a columnar connection portion facing from the bridge toward the first die.

[0010] Another aspect of the present invention relates to an electronic module, which includes the electronic device described above, a wiring layer having wiring provided therein, and a columnar connection portion that electrically connects the wiring and the electronic device.

[0011] Another aspect of the present invention relates to a method for manufacturing an electronic device, the method including: a forming step of forming, on a support, a first connection portion including a columnar connection portion protruding from the support, and a second connection portion, a die bonding step of bonding a first electrode of a first die to the first connection portion and a second electrode of a second die to the second connection portion, a sealing step of sealing the first die, the second die, and the first connection portion with a resin, and a bridge bonding step of bonding a bridge between a lower portion of the first connection portion and a lower portion of the second connection portion.

[0012] Any combination of the above components, and any transformation of the present invention into a method, device, system, recording medium, computer program, etc., are also valid aspects of the present invention. be. [Effects of the Invention]

[0013] According to the above-described embodiment, the IC chip and the bridge can be bonded with higher density. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic diagram of a chip integration system according to an embodiment; [Figure 2] 2 is a perspective view showing a configuration example of the chip-integrated body shown in FIG. 1. FIG. [Figure 3] 3 is an explanatory diagram showing a configuration example of the chip-integrated body shown in FIG. 2. FIG. [Figure 4] 4 is an enlarged cross-sectional view showing a configuration example of a portion of the chip integrated module shown in FIG. 3. FIG. [Figure 5] FIG. 4 is an explanatory diagram schematically illustrating an example of the configuration of the optical module shown in FIG. 3. [Figure 6] 1A to 1C are explanatory diagrams showing an outline of a method for manufacturing a chip integrated module, which is an example considered in relation to an embodiment; [Figure 7] 5 is an explanatory diagram showing an outline of a manufacturing process for the chip integrated module shown in FIG. 4. [Figure 8] FIG. 8 is an enlarged cross-sectional view showing details of the connecting portion forming step shown in FIG. 7. [Figure 9] FIG. 9 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. 8. [Figure 10] FIG. 10 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. 9. [Figure 11] FIG. 11 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. [Figure 12] FIG. 12 is an enlarged cross-sectional view showing the details of the connecting portion forming step following FIG. [Figure 13] 8 is an enlarged cross-sectional view showing details of the semiconductor die mounting step shown in FIG. 7. [Figure 14] FIG. 14 is an enlarged cross-sectional view showing details of the semiconductor die mounting step following FIG. 13. [Figure 15] FIG. 15 is an enlarged cross-sectional view showing details of the semiconductor die mounting step following FIG. 14. [Figure 16] FIG. 8 is an enlarged cross-sectional view showing details of the first sealing step shown in FIG. 7. [Figure 17] FIG. 8 is an enlarged cross-sectional view showing details of the support removal step shown in FIG. 7. [Figure 18] 8 is an enlarged cross-sectional view showing details of the connection portion exposing step shown in FIG. 7. FIG. [Figure 19] FIG. 19 is an enlarged cross-sectional view showing the details of the connection portion exposing step following FIG. 18. [Figure 20] FIG. 8 is an enlarged cross-sectional view showing details of the bridge mounting step shown in FIG. 7. [Figure 21] FIG. 21 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 20. [Figure 22] FIG. 22 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 21. [Figure 23] FIG. 8 is an enlarged cross-sectional view showing details of the second sealing step shown in FIG. 7. [Figure 24] FIG. 24 is an enlarged cross-sectional view showing a modification of FIG. 23. [Figure 25] 5 is an enlarged cross-sectional view showing a modification of the sealing body shown in FIG. [Figure 26] 5 is an enlarged cross-sectional view showing another modified example of the sealing body shown in FIG. [Figure 27]5 is an enlarged cross-sectional view showing another modified example of the sealing body shown in FIG. [Figure 28] FIG. 5 is an enlarged cross-sectional view of a chip-integrated module which is a modified example of the module shown in FIG. 4. [Figure 29] 29 is an explanatory diagram showing an outline of a manufacturing process for the chip integrated module shown in FIG. 28. [Figure 30] FIG. 30 is an enlarged cross-sectional view showing details of the insulating layer forming step shown in FIG. 29. [Figure 31] FIG. 31 is an enlarged cross-sectional view showing details of the insulating layer forming step following FIG. 30. [Figure 32] FIG. 30 is an enlarged cross-sectional view showing details of the connecting portion forming step shown in FIG. 29. [Figure 33] 30 is an enlarged cross-sectional view showing details of the semiconductor die mounting step shown in FIG. 29. [Figure 34] FIG. 34 is an enlarged cross-sectional view showing details of the semiconductor die mounting step following FIG. 33. [Figure 35] FIG. 35 is an enlarged cross-sectional view showing details of the semiconductor die mounting step following FIG. 34. [Figure 36] FIG. 30 is an enlarged cross-sectional view showing details of the sealing step shown in FIG. 29. [Figure 37] FIG. 30 is an enlarged cross-sectional view showing details of the connection portion exposing step shown in FIG. 29. [Figure 38] FIG. 38 is an enlarged cross-sectional view showing details of the connecting portion exposing step following FIG. 37. [Figure 39] FIG. 30 is an enlarged cross-sectional view showing details of the bridge mounting step shown in FIG. 29. [Figure 40] FIG. 40 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 39. [Figure 41] FIG. 41 is an enlarged cross-sectional view showing the details of the bridge mounting step following FIG. 40. [Figure 42] 4 is an explanatory diagram showing a modified example of the chip-integrated body shown in FIG. 3. FIG. [Figure 43] 4 is an explanatory diagram showing another modified example of the chip-integrated body shown in FIG. 3. FIG. [Figure 44] 5 is a cross-sectional view showing a modification of the bridge shown in FIG. 4. FIG. [Figure 45]FIG. 45 is a cross-sectional view showing an outline of a wiring layer forming step in the bridge manufacturing process shown in FIG. 44. [Figure 46] FIG. 45 is a cross-sectional view showing an outline of a wiring layer transfer step in the bridge manufacturing process shown in FIG. 44. [Figure 47] FIG. 45 is a cross-sectional view showing an outline of a support member removing step in the bridge manufacturing process shown in FIG. 44. [Figure 48] 5 is an explanatory diagram showing another modified example of the bridge shown in FIG. 4. FIG. [Figure 49] 5 is a diagram showing a partial configuration of a chip integrated module which is a modified example of the module shown in FIG. 4. FIG. [Figure 50] 50 is a diagram showing the configuration of a chip-integrated module according to a first modified example of the chip-integrated module shown in FIG. 49. FIG. [Figure 51] 50 is a diagram showing the configuration of a chip-integrated module according to a second modified example of the chip-integrated module shown in FIG. 49. FIG. [Figure 52] FIG. 50 is a diagram showing the configuration of a chip-integrated module according to a third modified example of the chip-integrated module shown in FIG. 49. [Figure 53] FIG. 50 is a diagram showing the configuration of a chip-integrated module according to a fourth modified example of the chip-integrated module shown in FIG. 49. [Figure 54] FIG. 50 is a diagram showing the configuration of a chip-integrated module according to a fifth modified example of the chip-integrated module shown in FIG. 49. [Figure 55] 10A to 10C are diagrams illustrating a method for manufacturing a chip-integrated module according to another embodiment. [Figure 56] 10A to 10C are diagrams for explaining a method for manufacturing the chip-integrated module according to the embodiment. [Figure 57] 10A to 10C are diagrams for explaining a method for manufacturing the chip-integrated module according to the embodiment. [Figure 58] 10A to 10C are diagrams for explaining a method for manufacturing the chip-integrated module according to the embodiment. [Figure 59] 10A to 10C are diagrams for explaining a method for manufacturing the chip-integrated module according to the embodiment. [Figure 60] 10A to 10C are diagrams for explaining a method for manufacturing the chip-integrated module according to the embodiment. [Figure 61] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a sixth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 62] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a sixth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 63] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a sixth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 64] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a sixth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 65] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a seventh modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 66] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to a seventh modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 67] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to an eighth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 68] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to an eighth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 69] 61 is a diagram for explaining a method for manufacturing a chip-integrated module according to an eighth modified example of the method for manufacturing the chip-integrated module shown in FIGS. 55 to 60. FIG. [Figure 70] 10A to 10C are diagrams for explaining a method for manufacturing an optical module according to an embodiment. [Figure 71] 10A to 10C are diagrams for explaining a method for manufacturing an optical module according to the embodiment. [Figure 72] 10A to 10C are diagrams for explaining a method for manufacturing an optical module according to the embodiment. [Figure 73] 10A to 10C are diagrams for explaining a method for manufacturing an optical module according to the embodiment. [Figure 74] 10A to 10C are diagrams for explaining a method for manufacturing an optical module according to the embodiment. [Figure 75] 10A to 10C are diagrams for explaining a method for manufacturing a chip-integrated body according to another embodiment. [Figure 76] 10A to 10C are diagrams for explaining a method for manufacturing a chip-integrated body according to the same embodiment. [Figure 77] 10A to 10C are diagrams for explaining a method for manufacturing a chip-integrated body according to the same embodiment. [Figure 78] 10A to 10C are diagrams for explaining a method for manufacturing a chip-integrated body according to the same embodiment. [Figure 79] 10A to 10C are diagrams for explaining a method for manufacturing a chip-integrated body according to the same embodiment. [Figure 80] 1 is a diagram illustrating an example of the configuration of an integrated circuit chip according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiments of the present invention will be described below with reference to the drawings. In the following description, a structure in which circuit elements such as transistors and wiring are formed on a semiconductor substrate is referred to as an IC chip. IC chips include superconducting integrated circuits (quantum computers), etc. A structure with a wiring layer stacked on the main surface of an IC chip is referred to as a semiconductor die. A rewiring layer may also be formed on the IC chip, in which case the rewiring layer is included in the wiring layer. A structure in which multiple semiconductor dies are encapsulated and integrated with an encapsulant is referred to as a chip-integrated module. A chip-integrated module also includes bridges that electrically connect the multiple semiconductor dies to each other. A structure in which multiple modules, including a chip-integrated module, are integrated is referred to as a chip-integrated module. A chip-integrated module may include modules such as optical modules in addition to chip-integrated modules. A chip-integrated module may include multiple chip-integrated modules. A chip-integrated module may also include a global wiring layer that electrically connects the multiple modules, and a heat dissipation mechanism or heat dissipation member that dissipates heat generated in each module to the outside. The portion of a chip-integrated module excluding heat-dissipating components is referred to as an integrated layer. In the following description, a chip-integrated module is used as an example of a semiconductor module. Also, an integrated layer is taken as an example of a semiconductor package.

[0016] However, the scope of a semiconductor module and a semiconductor package are not limited to the above definitions. For example, as shown in FIG. 1, which will be described later, a chip integration 10 is an electronic component (module) incorporated into a chip-integrated system 1. In this case, the chip integration 10 can be considered a semiconductor module incorporated into the chip-integrated system 1. Furthermore, the chip-integrated module, integration layer, and chip integration described below each include an IC chip and may be distributed as a packaged semiconductor package. Therefore, each of the chip-integrated module, integration layer, and chip integration can be considered a semiconductor package.

[0017] <Chip integrated system> FIG. 1 is a schematic diagram of a chip-integrated system according to one embodiment of the present invention. The chip-integrated system 1 according to this embodiment includes multiple chip assemblies 10. These chip assemblies 10 are connected to each other by optical wiring 110. Optical wiring may be used to connect different chip assemblies, for example, or may be used to connect different parts within a chip assembly if the chip assembly is large. The chip-integrated system 1 may be used, for example, in an artificial intelligence system that highly integrates various processors and memories. Note that while FIG. 1 shows two chip assemblies 10a and 10b, the chip-integrated system 1 may include three or more chip assemblies 10, or may consist of only one chip assembly 10.

[0018] Chip-integrated structure 10 is an assembly that includes multiple chip-integrated modules. The size of the chip-integrated module is not particularly limited, but examples include sizes ranging from approximately 50 mm square to as large as approximately 300 mm square. Here, the chip-integrated module is a semiconductor module that includes multiple IC chips. In FIG. 1, the area in chip-integrated structure 10 where the chip-integrated modules are arranged is indicated by a dashed line. In the example shown in FIG. 1, eight chip-integrated modules are arranged vertically and eight chip-integrated modules horizontally, for a total of 64 chip-integrated modules. However, the number of chip modules included in chip-integrated structure 10 is not limited to this and may be 63 or less, or 65 or more.

[0019] The chip integrated unit 10 according to this embodiment also includes an optical transceiver module (hereinafter referred to as an "optical module"). The chip integrated unit 10 according to this embodiment includes, for example, six optical modules. In the example shown in FIG. 1, the chip integrated unit 10a includes optical modules 11a, 12a, 13a, 14a, 15a, and 16a. The chip integrated unit 10b includes optical modules 11b, 12b, 13b, 14b, 15b, and 16b. The optical modules 11a to 16a and the optical modules 11b to 16b shown in FIG. 1 correspond to the optical modules 11 to 16 shown in FIG. 2, which will be described later. These optical modules are connected to optical modules provided in the same chip integrated unit 10 or optical modules provided in other chip integrated units 10 by optical wiring 110. A typical example of optical wiring is optical fiber, but is not limited thereto. For example, optical wiring using a planar panel or sheet with optical waveguides or free space can also be used. In the chip-integrated system 1 according to this embodiment, signals in the chip-integrated structure 10 are transmitted by light, and therefore signals are transmitted at a higher speed than when signals are transmitted only by electrical signals.

[0020] <Chip assembly> Fig. 2 is a perspective view showing an example of the configuration of the chip integration shown in Fig. 1. Chip integration 10 according to this embodiment includes an integration layer (also referred to as a semiconductor package or an electronic module) 100, optical modules 11-16 arranged on the upper surface of integration layer 100, a heat dissipation mechanism 20 arranged on the upper surface of integration layer 100, and an external terminal 30 arranged on the lower surface of integration layer 100.

[0021] The integration layer 100 has a stacked structure and is a layer having a plurality of chip-integrated modules (also called semiconductor modules or electronic devices). The detailed configuration of the integration layer 100 will be described later with reference to FIG.

[0022] The heat dissipation mechanism 20 is a mechanism that dissipates heat generated in the chip integration body 10. The heat dissipation mechanism 20 has the function of dissipating heat generated during operation of, for example, the IC chips included in the plurality of IC chips built into the integration layer 100 and the optical modules 11-16. In other words, the heat dissipation mechanism 20 can dissipate heat generated during operation of, for example, the integrated circuit chips included in the integration layer 100 and the integrated circuit chips included in the optical modules 11-16 (see FIG. 2).

[0023] The external terminals 30 are terminals that are electrically connected to any of the optical modules 11 to 16 or the chip-integrated module 40 (see FIG. 3, which will be described later). In the example shown in FIG. 2, the external terminals 30 are solder balls that form part of the transmission path of electrical signals. In this embodiment, the external terminals 30 can be used to supply power to the optical module or the chip-integrated module, or to input and output electrical signals from and to the outside. The shape of the external terminals may be spherical as shown in FIG. 2, or may be various shapes such as pin-shaped or pad-shaped.

[0024] Fig. 3 is an explanatory diagram showing an example of the configuration of the chip-integrated module shown in Fig. 2. Fig. 3 is a diagram showing the cross-sectional structure of the chip-integrated module, but hatching has been omitted for ease of viewing. Fig. 3 also shows two of the 64 chip-integrated modules shown in Fig. 1.

[0025] Each of the optical modules 11 to 16 shown in Fig. 2 includes an optical transceiver, a connector, and a heat dissipation member. For example, the optical module 13 shown in Fig. 3 includes an optical transceiver 130, a connector 132, and a heat dissipation member 136. The heat dissipation member 136 includes a support plate (heat spreader) fixed on the optical transceiver 130, and a plurality of heat dissipation fins fixed on the support plate and protruding in a direction away from the optical transceiver 130.

[0026] The optical transceiver 130 is an optoelectronic conversion component that has the function of converting an optical signal received via the optical wiring 110 (see FIG. 1) into an electrical signal, and the function of converting the electrical signal into an optical signal and transmitting the optical signal to the outside via the optical wiring 110. A connector 132 is connected to the bottom surface of the optical transceiver 130. The connector 132 is also connected via solder 138 to an electrode 140 formed on the surface of the integration layer 100. The optical transceiver 130 can transmit and receive electrical signals to and from the integration layer 100 via the connector 132. The use of a connector allows the optical transceiver to be easily attached and detached, enabling rapid replacement in the event of, for example, a malfunction of the optical transceiver.

[0027] A heat dissipation member 136 is also disposed on the top surface of the optical transceiver 130. The heat dissipation member 136 can dissipate heat from, for example, the optical transceiver 130. The heat dissipation member 136 includes a heat spreader with heat dissipation fins on the top surface that achieve a large surface area in a small volume. The heat dissipation fins can dissipate heat from, for example, the optical transceiver 130.

[0028] The heat dissipation mechanism 20 is supported by a support member 210 disposed on the surface of the integration layer 100. The heat dissipation mechanism 20 includes a support plate fixed to the support member 210 and a plurality of heat dissipation fins fixed to the support plate and protruding in a direction away from the chip-integrated module 40. The heat dissipation mechanism 20 is thermally connected to the chip-integrated module 40 (in other words, each of the plurality of IC chips) disposed inside the integration layer 100 (specifically, within the chip layer 104) via the support member 210. The support member 210 is, for example, a thermal interface material (TIM), and is thermally connected to the IC chips disposed inside the integration layer 100.

[0029] The integrated layer 100 shown in FIG. 3 includes a global wiring layer 102, a chip layer 104, and a connection layer 106.

[0030] The global wiring layer 102 has a laminated structure made up of multiple layers. Each of the multiple layers of the global wiring layer 102 includes a conductor pattern such as wiring and an insulating layer covering the conductor pattern. The insulating layer is made of, for example, insulating resin. The conductor pattern such as wiring is formed on an underlying insulating layer. Two wires provided on adjacent layers in the thickness direction are electrically connected by a conductor via. In the example shown in FIG. 3, the global wiring layer 102 has four layers, and an external terminal 30 is formed on a wire provided on the bottom layer (the layer farthest from the chip layer 104). In addition, a wire provided on the top layer (the layer closest to the chip layer 104) of the global wiring layer 102 is electrically connected to an electrode provided on the chip layer 104.

[0031] The chip layer 104 is a layer including an insulating encapsulant 105 and various conductors and functional devices embedded in the encapsulant 105. For example, conductor posts 146 and a plurality of chip integrated modules 40 are embedded in the encapsulant 105. In the example shown in Fig. 3, electrodes 148 are provided on the lower surfaces of the conductor posts 146, and the conductor posts 146 are electrically connected via the electrodes 148 to wiring arranged on the top layer of the global wiring layer 102.

[0032] 3, the chip-integrated module 40 is electrically connected to wiring arranged on the top layer of the global wiring layer 102 via conductive toll pillars 401 and electrodes 403. The configuration of the chip-integrated module 40 will be described in detail later with reference to FIG.

[0033] The connection layer 106 is a layer that connects components arranged on the surface of the integration layer 100 to the chip layer 104. For example, the connection layer 106 has a conductor via 142 and an electrode 144 that connect a conductor post 146 of the chip layer 104 to an electrode 140 that is electrically connected to the optical transceiver 130.

[0034] The connection layer 106 also has metal contact portions 222 thermally connected to each of the plurality of chip-integrated modules 40, and the contact portions 222 are connected to coupling portions 220 provided inside the support member 210 of the heat dissipation mechanism 20. In this manner, the chip-integrated module 40 according to this embodiment is thermally connected to the heat dissipation mechanism 20 via the contact portions 222 and the coupling portions 220.

[0035] <Chip integrated module> FIG. 4 is an enlarged cross-sectional view showing an example of the configuration of a portion of the chip-integrated module shown in FIG. 3. As shown in FIG. 4, a chip-integrated module 40 according to this embodiment includes a semiconductor die 41, a semiconductor die 42, and a sealing body 45 that seals the semiconductor die 41 and the semiconductor die 42. The chip-integrated module 40 also includes a bridge 43 that electrically connects the semiconductor die 41 and the semiconductor die 42. The chip-integrated module 40 also includes a connection portion 47 that electrically connects the semiconductor die 41 and the bridge 43, and a connection portion 48 that electrically connects the semiconductor die 42 and the bridge 43. The connection portion 47 and the connection portion 48 are each sealed in the sealing body 45. The semiconductor die 41 is also electrically connected to the outside of the chip-integrated module 40 (for example, the external terminal 30 shown in FIG. 3) via the connection portion 49.

[0036] The semiconductor die 41 has an IC chip 411 having a main surface 411t, and insulating layers 412 and 413 stacked on the main surface 411t of the IC chip 411. The semiconductor die 41 has wiring 414 and wiring 415 electrically connected to the IC chip 411. The semiconductor die 41 also has a die electrode 416 connected to the wiring 414 and a die electrode 417 connected to the wiring 415. In the example shown in FIG. 4 , the semiconductor die 41 has two insulating layers 412 and 413. However, the total number of insulating layers included in the semiconductor die 41 is not limited to two, and the semiconductor die 41 may have, for example, three or more insulating layers.

[0037] The IC chip 411 includes a semiconductor substrate such as silicon, and circuit elements such as transistors and diodes. The circuit elements within the IC chip 411 can be integrated in a variety of ways, including two-dimensional or three-dimensional circuit elements formed on the main surface 411t of the IC chip, or circuit elements formed on each layer of a multi-layered semiconductor substrate, connected by vias (TSV: Through Silicon Via) that penetrate the semiconductor substrate.

[0038] The semiconductor die 42 has an IC chip 421 having a main surface 421t, and insulating layers 422 and 423 stacked on the main surface 421t of the IC chip 421. The semiconductor die 42 has wiring 425 electrically connected to the IC chip 421. The semiconductor die 42 also has a die electrode 427 connected to the wiring 425. In the example shown in FIG. 4, the semiconductor die 42 has two insulating layers 422 and 423. However, the total number of insulating layers included in the semiconductor die 42 is not limited to two, and the semiconductor die 42 may have, for example, three or more insulating layers and two or more wiring layers. The structure of the semiconductor die 42 is similar to, for example, the structure of the semiconductor die 41 described above.

[0039] The bridge 43 includes a chip 431 having a main surface 431t and insulating layers 432 and 433 stacked on the main surface 431t of the chip 431. The bridge 43 includes wiring 434 formed on the insulating layer 432. The chip 431 is formed of a semiconductor substrate such as a silicon wafer, but may also be formed of an inorganic material such as glass. However, the total number of insulating layers included in the bridge 43 is not limited to two, and may include, for example, three or more insulating layers and two or more wiring layers. Furthermore, if the chip 431 includes a circuit, it may be electrically connected to the wiring 434. The bridge 43 includes a bridge electrode 436 connected to the connection portion 47 and a bridge electrode 437 connected to the connection portion 48. The bridge electrode 436 and the bridge electrode 437 are electrically connected to each other via the wiring 434.

[0040] The bridge 43 according to this embodiment is a pillar-suspended bridge. The wiring 434 according to this embodiment is electrically connected to the chip 431, and the wiring 434 and the chip 431 function together as a bridge. However, as will be described later, the bridge 43 can function as a bridge circuit as long as it has the function of electrically connecting the semiconductor die 41 and the semiconductor die 42. Therefore, as a modified example, the bridge 43 may not have the chip 431, or the chip 431 may not be electrically connected to the wiring 434. In addition, in the example shown in FIG. 4, the bridge 43 has two insulating layers 432 and 433. However, the total number of insulating layers in the bridge 43 is not limited to two, and may have, for example, three or more insulating layers.

[0041] 4, the connection portion 47 includes a columnar connection portion 472. In the example shown in FIG. 4, the connection portion 47 has the columnar connection portion 472, a solder layer 473 that connects the columnar connection portion 472 and the die electrode 417, and a solder layer 474 that connects the columnar connection portion 472 and the bridge electrode 436.

[0042] 4, the connection portion 48 includes a columnar connection portion 482. In the example shown in FIG. 4, the connection portion 48 has the columnar connection portion 482, a solder layer 483 that connects the columnar connection portion 482 and the die electrode 427, and a solder layer 484 that connects the columnar connection portion 482 and the bridge electrode 437.

[0043] In this embodiment, each of the columnar connecting portions 472 and 482 is a columnar conductor (also referred to as a "micropillar") of μm size. The main body of each of the columnar connecting portions 472 and 482 is made of a metal material mainly composed of, for example, copper. At the bonding interface between the columnar connecting portion 472 and the solder layer 473 and at the bonding interface between the columnar connecting portion 472 and the solder layer 474, an alloy layer is formed. The alloy layer is made of a metal material, such as gold, which has higher oxidation resistance than the main body portion, in other words, a higher free energy for forming metal oxide, and a solder mainly composed of, for example, tin. The alloy layer is formed by a eutectic reaction between the solder layer and a metal film formed at the bonding interface between the columnar connecting portion and the solder layer when the columnar connecting portion 472 is bonded to the solder layers 473 and 474. The alloy layer will be described in detail later.

[0044] Similarly, a bonding film made of a metal material such as gold, which has higher oxidation resistance than the main body, is formed at each of the bonding interfaces between the columnar connecting portion 482 and the solder layer 483 and between the columnar connecting portion 482 and the solder layer 484. However, when the columnar connecting portion 482 is bonded to the solder layers 483 and 484, an alloy layer with the solder layers 483 and 484 is formed near the bonding film, and the original constituent components of the bonding film may be diffused into the solder layer.

[0045] 4, the connection portion 49 includes an electrode 492 connected to the tor pillar 401 and a solder layer 493 connecting the electrode 492 and the die electrode 426. In the example shown in FIG. 4, the tor pillar 401 connected to the electrode 492 is not included in the chip-integrated module 40, and is therefore indicated by a dotted line. However, as a variant, the tor pillar 401 can also be considered as part of the chip-integrated module 40.

[0046] In the example shown in FIG. 4, in this embodiment, the bridge electrodes 436 and 437 are each sealed in a sealing body 44 formed separately from the sealing body 45. The sealing body 44 is, for example, an underfill resin. However, as a modified example, a sealing body that seals the chip 431 and the bridge electrodes 436 and 437 together can also be used. Alternatively, as another modified example, the sealing body 44 may be replaced with the sealing body 105 shown in FIG. 3. As shown in FIG. 4, the structure in which the connecting portions 47 and 48 are sealed in the sealing body 45 and the bridge 43 is exposed from the sealing body 45 is obtained by the manufacturing method of the chip-integrated module 40 described below. The reason why the structure shown in FIG. 4 is obtained will be described in detail later.

[0047] In the present embodiment, an example has been described in which the bridge 43 is a semiconductor die including the chip 431, but there is also a case in which the bridge does not include the chip 431 and is mainly composed of the wiring 434, the insulating layers 432 and 433 in which the wiring is embedded, and the bridge electrodes 436 and 437. Also, in the present embodiment, the connection portion 47 and the connection portion 48 each have one columnar connection portion 472, 482. However, depending on the separation distance between the semiconductor die 41 and the bridge 43, the connection portion 47 and the connection portion 48 may each have two or more stacked columnar connection portions. The stacked columnar connection portions may have different cross-sectional shapes and cross-sectional areas.

[0048] <Optical module> FIG. 5 is an explanatory diagram schematically illustrating an example of the configuration of the optical module shown in FIG. 3. The optical module 13 according to this embodiment mainly includes an optical system mechanism 131, an optical transceiver 130, and a connector 132. The optical module 13 also includes a mechanism for transmitting an optical signal to the outside (hereinafter also referred to as a "transmitting mechanism 13T") and a mechanism for receiving an optical signal from the outside (hereinafter also referred to as a "receiving mechanism 13R"). In FIG. 5, the transmitting mechanism 13T is shown on the left side of the page, and the receiving mechanism 13R is shown on the right side. However, the positional relationship between the transmitting mechanism 13T and the receiving mechanism 13R can be modified in various ways other than the manner shown in FIG. 5. In the following, the structure of the transmitting mechanism 13T will be described, and a description of parts of the receiving mechanism 13R that are common to the structure of the transmitting mechanism 13T may be omitted.

[0049] The optical system mechanism 131 of the transmission mechanism 13T includes an optical fiber 600, a lens 601, a reflecting mechanism (a reflecting mirror in FIG. 5) 602, and a lens 603. Light incident on the lens 603 from the optical transceiver 130 passes through the lens 603 and is reflected by the reflecting mechanism 602. The reflected light passes through the lens 601 and enters the optical fiber 600. As a result, an optical signal is transmitted to the outside via the optical fiber 600.

[0050] The optical system mechanism 131 of the receiving mechanism 13R includes an optical fiber 610, a lens 611, a reflecting mechanism (a reflecting mirror in FIG. 5) 612, and a lens 613. Light emitted from the optical fiber 610 passes through the lens 611 and is reflected by the reflecting mechanism 612. The reflected light passes through the lens 613 and enters the optical transceiver 130. As a result, the optical signal received by the optical fiber 610 is converted into an electrical signal, and various processes are performed. The lenses and reflecting mechanisms that make up the optical system mechanism 131 can be added or deleted as appropriate based on design requirements. For example, a configuration is possible in which the optical fiber is directly coupled to the optical element chip of the optical transceiver, or in some cases, to the light-emitting element or light-receiving element, without passing through the lens or reflecting mechanism.

[0051] The optical transceiver 130 mainly includes a chip layer 620, a wiring layer 630, two optical element chips 605 and 615, a light emitting element 606, and a light receiving element 616 arranged on the wiring layer 630. In this embodiment, the two optical element chips 605 and 615, the light emitting element 606, and the light receiving element 616 are electrically connected to the wiring layer 630, and the connection portions are sealed with an underfill resin 607 or the like. In other words, in this embodiment, the two optical element chips 605 and 615, the light emitting element 606, and the light receiving element 616 are fixed by a fixing member (underfill resin 607) made of resin or the like.

[0052] The wiring layer 630 according to this embodiment has, for example, a two-layer structure. Conductor patterns such as wiring and electrodes are formed on each layer of the wiring layer 630. The chip layer 620 also includes an optical element driver chip 621 and an optical element driver chip 622. The optical element driver chips 621 and 622 are chips that control the driving of the optical element chips 605 and 615, respectively. The optical element driver chips 621 and 622 may also include a function for converting the electrical signal levels (voltage, current) required for the optical elements to perform appropriate optical / electrical conversion and the electrical signal levels input and output from outside the optical transceiver.

[0053] The light emitting element 606 of the transmission mechanism is provided on the surface of the optical element chip 605, and is an element that emits an optical signal in response to an electrical signal transmitted from the optical element chip 605. The optical signal emitted by the light emitting element 606 is incident on the lens 603 of the optical system mechanism 131.

[0054] The optical element chip 605 is connected to electrodes 631 formed on the upper layer of the wiring layer 630 via electrode terminals 608 and solder layer 609, and the optical element driver chip 621 is connected to electrodes 633 formed on the lower layer of the wiring layer 630 via electrode terminals 623 and solder layer 634. Thus, the optical element chip 605 and the optical driver chip 621 are electrically connected via the wiring layer 630. This structure realizes multi-parallel, short-distance connections between the optical element chips and the optical driver chips through the nearly vertical electrical connections within the wiring layer 630. This enables wideband signal transmission between the optical element groups arranged in a two-dimensional array and the optical driver chip. Note that, depending on the manufacturing method of the optical transceiver, the solder layer 634 may not be necessary. Furthermore, by arranging the electrode terminals 608, conductive vias 632, and electrode terminals 623 in a nearly straight line, the electrical connection path length between the optical element chips and the optical driver chips can be minimized, resulting in an excellent electrical connection with low parasitic impedance.

[0055] A metal layer 629 made of metal is formed on the lower surface of the optical element driver chip 621. The metal layer 629 is thermally connected to a conductive via 641 provided in the connector 132 via a coupling member 640. As a result, heat generated by the optical element driver chip 621 when it is driven is dissipated via the coupling member 640 in the direction of the arrow shown schematically in Fig. 5 (the direction from the metal layer 629 toward the connector 132). Note that although the presence of the metal layer 629 is desirable for heat dissipation, the effect can still be obtained even if it is not necessarily present.

[0056] Conductive via 641 of connector 132 is connected to electrode 140 formed on the surface of connection layer 106 via solder layer 642. Furthermore, as shown in Fig. 3, electrode 140 is connected to electrode 148 connected to conductor post 146 formed on chip layer 104 via conductor via 142. Therefore, heat dissipated to connector 132 is dissipated through conductor post 146.

[0057] An electrode terminal 624 is formed on the upper surface of the light element driving chip 621, and this electrode terminal 624 is connected to an electrode 626 formed on the underside of the wiring layer 630 via a solder layer or a conductor connection portion 625. In addition, a wire 635 is formed on the wiring layer 630. The wire 635 is connected to the electrode 626 electrically connected to the light element driving chip 621 via a conductor via 636. In addition, the wire 635 is connected to an electrode 627 coupled to a conductor post 628 formed on the chip layer 620 via a conductor via 637.

[0058] The conductor post 628 is electrically connected to a conductor via 644 of the connector 132 via a coupling member 643. In the example shown in FIG. 5 , the coupling member 643 allows, for example, electrical signals to be transmitted between the optical transceiver 130 and the connector 132. However, as a modified example, the transmission direction of the electrical signal between the optical transceiver 130 and the connector 132 may be unidirectional. That is, in the case of the transmitting mechanism 13T, the electrical signal is transmitted from the connector 132 to the optical transceiver 130, and in the case of the receiving mechanism 13R, the electrical signal is transmitted from the optical transceiver 130 to the connector 132.

[0059] <Method of manufacturing chip integrated module> Next, a method for manufacturing the chip-integrated module 40 shown in Figures 3 and 4 will be described. Before describing the method for manufacturing the chip-integrated module according to this embodiment, a brief outline of the manufacturing method studied by the inventors of the present application will be given. Figure 6 is an explanatory diagram showing an outline of the method for manufacturing the chip-integrated module, which is an example of the method studied for this embodiment.

[0060] In the method for manufacturing the chip integrated module shown in Fig. 6, first, as shown in the upper part of Fig. 6, a plurality of semiconductor dies 51 and a bridge structure 52 are prepared. The bridge structure 52 is a structure in which a plurality of bridges 520 and a plurality of connection portions 521 are each sealed with a sealing body 523, thereby integrating the plurality of bridges 520 and the plurality of connection portions 521. In the example shown in Fig. 6, a plurality of tow pillars 401 are sealed in the sealing body 523 together with a plurality of bridges 520.

[0061] 6, the plurality of semiconductor dies 51 are mounted on the bridge structure 52. At this time, the plurality of die electrodes 511 of the semiconductor die 51 and the plurality of connection portions 521 of the bridge structure 52 are bonded to each other.

[0062] Next, as shown in the lower part of FIG. 6, the semiconductor dies 51 are sealed with a sealing body 512, thereby integrating the semiconductor dies 51 and the bridge structure 52, and a chip-integrated module 50 is obtained.

[0063] In the case of the study example shown in FIG. 6, by integrating a plurality of bridge structures 52 in advance, the work of electrically connecting a plurality of semiconductor dies 51 and a plurality of bridges 520 can be made more efficient.

[0064] However, it was found that the manufacturing method shown in FIG. 6 has the following concerns. Specifically, it was found that it is difficult to improve the positional accuracy of each of the multiple connection portions 521 due to contraction or expansion of the sealing body 523 that constitutes the bridge structure 52. A possible solution to this problem is to increase the area of ​​the bonding interface of each of the multiple connection portions 521 to increase the allowable margin for misalignment. However, in this case, the arrangement pitch of adjacent connection portions 521 must also be increased, which hinders the density of the connection portions 521. In other words, this restricts the density of the terminal portion that electrically connects the semiconductor die 51 and the bridge 520.

[0065] As described above, it is believed that the reason why it is difficult to improve the positional accuracy of each of the multiple connection portions 521 is due to the large volume of the sealant 523. One possible measure is to reduce the linear expansion coefficient of the sealant 523 by mixing inorganic filler particles, as described below, into the sealant 523, but this measure also has its limitations.

[0066] Based on the above findings, the present inventors have devised a method for manufacturing a chip-integrated module according to the present embodiment. While the details of the manufacturing method will be described later, the method for manufacturing a chip-integrated module according to the present embodiment involves preparing a structure in which multiple semiconductor dies and multiple connectors are integrated with a sealing body, and then mounting multiple bridges on the structure. The volume of the sealing body in the structure in which multiple semiconductor dies and multiple connectors are integrated can be made smaller than the volume of sealing body 523 in bridge structure 52 shown in FIG. 6. In particular, by reducing the gap between adjacent IC chips, the effects of thermal contraction and thermal expansion can be reduced. As a result, the manufacturing method for a chip-integrated module according to the present embodiment can improve the positional accuracy of each of the multiple connectors, thereby enabling high-density terminals that electrically connect the semiconductor dies and bridges.

[0067] The method for manufacturing the chip-integrated module according to this embodiment will be described in detail below. Fig. 7 is an explanatory diagram showing an overview of the manufacturing process for the chip-integrated module shown in Fig. 4. As shown in Fig. 7, the method for manufacturing the chip-integrated module according to this embodiment includes a connection portion forming step, a semiconductor die mounting step, a first sealing step, a support member removing step, a connection portion exposing step, a bridge mounting step, and a second sealing step.

[0068] The connection portion forming step shown in Fig. 7 includes the steps shown in Fig. 8 to Fig. 12. Each of Fig. 8 to Fig. 12 is an enlarged cross-sectional view showing details of the connection portion forming step shown in Fig. 7. In the connection portion forming step, as shown in Fig. 11, connection portions 47 including columnar connection portions 472 extending in an out-of-plane direction of the upper surface 70t and connection portions 48 including columnar connection portions 482 extending in an out-of-plane direction of the upper surface 70t are formed on the upper surface 70t of the support body 70.

[0069] Specifically, first, a support 70 having an upper surface 70t is prepared as shown in FIG. 8. A release layer 71 and a seed layer 72 are formed in advance on the upper surface 70t of the support 70. The material of the support 70 is not particularly limited as long as it is a plate with sufficient rigidity to ensure ease of operation in each step up to the support removal step shown in FIG. 7. Examples of the material include a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, and a resin plate. However, taking into account expansion due to heating during connection, it is desirable for the linear expansion coefficient of the support to be close to that of the semiconductor die.

[0070] The release layer 71 is a functional layer that has the function of enabling the support 70 to be peeled off in the support removal step shown in Fig. 7, and various materials are selected depending on various techniques, such as a method of peeling off using an energy beam such as a laser or a method of mechanical peeling. The seed layer 72 is a seed film that serves as a base for forming conductive members such as the connection portions 47, 48, and 49 by a plating method. The seed layer 72 can be formed, for example, by depositing a copper film on the release layer 71 by a sputtering method.

[0071] 9, a resist mask 73 is formed on the upper surface 70t of the support 70, more specifically, on the seed layer 72. A plurality of openings 73H are formed in the resist mask 73 using, for example, photolithography technology.

[0072] Next, as shown in FIG. 10 , a metal film is deposited in the openings 73H of the resist mask 73 by plating or the like to form the connection portions 47, 48, and 49. Because the seed layer 72 has been formed in advance on the upper surface 70t of the support 70, the columnar connection portion 472, which is a part of the connection portion 47, the columnar connection portion 482, which is a part of the connection portion 48, and the electrode 492, which is a part of the connection portion 49, can be formed by plating, for example. In the example shown in FIG. 10 , the columnar connection portion 472 includes a main body portion 472A and a metal film 472B. The columnar connection portion 482 includes a main body portion 482A and a metal film 482B. The electrode 492 includes a main body portion 492A and a metal film 492B. Each of the main bodies 472A, 482A, and 492A is made of, for example, copper, and each of the metal films 472B, 482B, and 492B is made of a metal material that is more resistant to oxidation than copper, such as gold. The metal films 472B, 482B, and 492B each have the function of preventing oxidation of the bonding surfaces of the copper main body portions 472A, 482A, and 492A, respectively, and enabling fluxless solder bonding in the semiconductor die mounting process described below.

[0073] Next, as shown in FIG. 11 , the resist mask 73 (see FIG. 10 ) is removed. Removing the resist mask 73 exposes the side surfaces of the connection portions 47, 48, and 49 and a portion of the upper surface of the seed layer 72. While the semiconductor die mounting process shown in FIG. 7 can be performed in the state shown in FIG. 11 , it is preferable to include a step of forming an oxide film 72A on the side surfaces of the connection portions 47, 48, and 49 and on the exposed surface of the seed layer 72, as shown in FIG. 12 . Forming the oxide film 72A before the semiconductor die mounting process prevents the solder from spreading over the side surfaces of the connection portions during the semiconductor die mounting process, resulting in an unstable bond. If the step of forming the oxide film 72A on the side surfaces of the connection portions 47, 48, and 49 and on the exposed surface of the seed layer 72 is included, the side surfaces of the connection portions 47, 48, and 49 are covered with the oxide film 72A, as shown in FIG. 4 . If the oxide film 72A is not formed in this process, the oxide film 72A shown in FIG. 4 may not be formed, as shown in FIG. 24 (described later).

[0074] The oxide film 72A can be formed, for example, by the following methods. For example, after removing the resist mask 73 shown in FIG. 10, the oxide film 72A shown in FIG. 12 is exposed to an oxygen-containing atmosphere until it is formed. Another method for forming the oxide film 72A in a shorter time is to heat the side surfaces of the connection portions 47, 48, and 49 and the exposed surface of the seed layer 72 in an oxygen-containing atmosphere. Note that, for ease of viewing, the oxide film 72A is shown thick in FIG. 12; however, it is sufficient for the oxide film 72A to be thin on the side surfaces of the connection portions 47, 48, and 49 and the exposed surface of the seed layer 72.

[0075] The semiconductor die mounting step shown in Fig. 7 includes the steps shown in Fig. 13 to Fig. 15. Each of Fig. 13 to Fig. 15 is an enlarged cross-sectional view showing details of the semiconductor die mounting step shown in Fig. 7. In the semiconductor die mounting step, as shown in Fig. 15, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. In addition, in the semiconductor die mounting step, each of the semiconductor die 41 and the semiconductor die 42 is mounted on the support 70 so that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48.

[0076] More specifically, first, semiconductor die 41 and semiconductor die 42 are prepared as shown in FIG. 13. The detailed structures of semiconductor die 41 and semiconductor die 42 have already been described using FIG. 4, so a duplicated description will be omitted. Next, as shown in FIG. 13, semiconductor die 41 and semiconductor die 42 are aligned with support 70 so that die electrode 417 is disposed on connecting portion 47 and die electrode 427 is disposed on connecting portion 48. A solder layer 473 is formed on die electrode 417 of semiconductor die 41. A solder layer 493 is formed on die electrode 416 of semiconductor die 41. A solder layer 483 is formed on die electrode 427 of semiconductor die 42.

[0077] 14 , the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed against the connection portion 49 via the solder layer 493. Similarly, the die electrode 427 of the semiconductor die 42 is pressed against the connection portion 48 via the solder layer 483. In this step, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid-state diffusion bonding.

[0078] Next, the bonding interface between the solder layer 473 and the metal film 472B of the columnar connection portion 472, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface between the solder layer 483 and the metal film 482B of the columnar connection portion 482 shown in FIG. 14 are each heated to the melting temperature of solder and maintained at this temperature. This allows a liquid phase to be generated at each bonding interface. As shown in FIG. 15, alloy layers 472D, 482D, and 492D are formed at each bonding interface. By maintaining the temperature at which the liquid phase is generated, the elements in the liquid phase diffuse toward the alloy layer, raising the melting point of the liquid phase. As a result, the liquid phase solidifies. This type of bonding method is called liquid phase diffusion bonding. When temporary bonding by solid phase diffusion bonding and bonding by liquid phase diffusion bonding are combined as in this embodiment, a strong and thermally stable bond can be achieved in the bonding process using solder without using flux. In the case of a reflow bonding method using flux, there is a high possibility that flux residue will remain around the joint when bonding fine parts such as those in this embodiment. On the other hand, in the case of this embodiment, no flux residue remains, so the cleaning process can be omitted. Furthermore, the process of cleaning and removing flux residue becomes difficult as the joints become finer and denser. In the case of this embodiment, since there is no need to clean the flux residue, finer and denser joints can be achieved. Note that, depending on the size and arrangement of the joints, other bonding process options besides those mentioned above may also include regular solder bonding (brazing), solder bonding using flux, and solid-state diffusion bonding between metals.

[0079] When performing solder bonding, it is preferable to prevent the solder components of each solder layer from spreading onto the side surfaces of the columnar connection parts. This is because if the solder components spread onto the side surfaces of the columnar connection parts or the top surface of the seed layer 72, the shape of the joint will become unstable or the solder is likely to adversely affect the seed layer or the release layer. In this embodiment, as described above, an oxide film 72A is formed on the side surfaces of the columnar connection parts and the exposed surface of the seed layer 72. In this case, the spreading of the solder components can be prevented, allowing the die electrode and the connection parts to be bonded with a small amount of solder.

[0080] In the first encapsulation step shown in FIG. 7, after the semiconductor die mounting step, the semiconductor die 41, the semiconductor die 42, the connection portion 47, and the connection portion 48 are encapsulated with an encapsulant 45, as shown in FIG. 16. FIG. 16 is an enlarged cross-sectional view showing details of the first encapsulation step shown in FIG. 7. In this step, the semiconductor die 41, the semiconductor die 42, the connection portion 47, and the connection portion 48 are integrated with the encapsulant 45. In the example shown in FIG. 16, the connection portion 49 is also encapsulated with the encapsulant 45. The encapsulant 45 can be, for example, a resin material containing a thermosetting resin. As a variation of the encapsulant 45, a large number of inorganic filler particles may be contained in the resin, as described below.

[0081] In the chip-integrated module 40 shown in FIG. 4, the distance between the semiconductor die 41 and the semiconductor die 42 is narrow. For example, in the example shown in FIG. 16, the distance G1 between the semiconductor die 41 and the semiconductor die 42 is shorter than the shortest distance G2 from the top surface 70t of the support 70 to the portion of the semiconductor die 41 excluding the die electrodes 416 and 417. Furthermore, the IC chips that occupy most of the semiconductor die 41 and the semiconductor die 42 are made of a semiconductor material with a very low linear expansion coefficient compared to the encapsulant 45. Therefore, even if the encapsulant 45 undergoes thermal expansion or contraction, the positions of the die electrodes 416, 417, and 427 are less likely to be affected. Furthermore, the connecting portions 47, 48, and 49 are already fixed to the semiconductor die 41 or the semiconductor die 42 before the first encapsulation step. Therefore, the connecting portions 47, 48, and 49 can maintain high positional accuracy even when encapsulated by the encapsulant 45. Therefore, the problem of difficulty in improving the positional accuracy of each of the plurality of connecting portions 521 of the bridge structure 52, which was described with reference to FIG. 6, is unlikely to arise in this embodiment.

[0082] In the support removal step shown in FIG. 7, after the first sealing step, the support 70 (see FIG. 16) is removed as shown in FIG. 17. FIG. 17 is an enlarged cross-sectional view showing the details of the support removal step shown in FIG. 7. In this step, energy is applied to the peeling layer 71 using a laser or the like to decompose (ablate) the peeling layer 71, thereby significantly reducing the adhesion of the peeling layer 71 to the support, making it possible to easily peel off the support 70. In the support removal step, peeling can also be performed at the peeling layer by mechanical stress.

[0083] In the connection portion exposing step shown in FIG. 7, after the support removing step, a portion (lower surface) of the columnar connection portion 472 and a portion (lower surface) of the columnar connection portion 482 are exposed from the sealing body 45 as shown in FIG. 18. FIG. 18 is an enlarged cross-sectional view showing details of the connection portion exposing step shown in FIG. 7. In this step, the peeling layer 71 and the seed layer 72 shown in FIG. 17 are removed by, for example, etching. In addition, in this step, the portion of the oxide film 72A shown in FIG. 17 formed on the upper surface of the seed layer 72 is removed. In the example shown in FIG. 18, in this step, a portion (lower surface) of the electrode 492 is also exposed from the sealing body 45.

[0084] In this step, as shown in FIG. 19, after exposing the connection portions from the sealing body 45, it is preferable to form metal films 472C, 482C, and 492C on the exposed surfaces of the connection portions. FIG. 19 is an enlarged cross-sectional view showing details of the connection portion exposing step subsequent to FIG. 18. As shown in FIG. 19, in this step, a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45. Similarly, a metal film 482C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45. A metal film 492C is formed on the surface of the electrode 492 exposed from the sealing body 45. Each of the metal films 472C, 482C, and 492C has a function of preventing oxidation of the bonding surfaces of the copper main bodies 472A, 482A, and 492A, respectively, and a function of enabling bonding in a low-temperature process by undergoing a eutectic reaction with a solder mainly composed of tin in a semiconductor die mounting step described later. For example, like the metal films 472B, 482B, and 492B, the metal films 472C, 482C, and 492C are made of a metal material (such as gold) that is more resistant to oxidation than the material of the main body portions 472A, 482A, and 492A. Gold is an example of a metal material that has the above-mentioned function. By providing the metal films 472C, 482C, and 492C, the above-mentioned solder bonding can be performed in the bridge mounting process shown in FIG. 7.

[0085] The bridge mounting step shown in Fig. 7 includes the steps shown in Fig. 20 to Fig. 22. Each of Fig. 20 to Fig. 22 is an enlarged cross-sectional view showing the details of the bridge mounting step shown in Fig. 7. In the bridge mounting step, as shown in Fig. 22, a bridge 43 is prepared, which includes a bridge electrode 436 connected to the connection portion 47 and a bridge electrode 437 connected to the connection portion 48. Furthermore, in the bridge mounting step, after the connection portion exposing step, the bridge 43 is mounted on a structure sealed with a sealant 45 so that the bridge electrode 436 is arranged on the columnar connection portion 472 and the bridge electrode 437 is arranged on the columnar connection portion 482.

[0086] More specifically, first, a bridge 43 is prepared as shown in Fig. 20. The detailed structure of the bridge 43 has already been explained using Fig. 4, so a duplicated explanation will be omitted. Next, as shown in Fig. 20, the bridge 43 is aligned with the structure sealed with the sealing body 45 so that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0087] 21 , the bridge electrodes 436 of the bridge 43 are pressed against the columnar connection portions 472 of the connection portions 47 via the solder layers 474. At this time, the bridge electrodes 437 of the bridge 43 are pressed against the columnar connection portions 482 of the connection portions 48 via the solder layers 484. In this step, the solder layers 474 and the columnar connection portions 472 of the connection portions 47 (more specifically, the metal films 472C of the columnar connection portions 472) are temporarily joined by solid-state diffusion bonding. Similarly, the solder layers 484 and the columnar connection portions 482 of the connection portions 48 (more specifically, the metal films 482C of the columnar connection portions 482) are temporarily joined by solid-state diffusion bonding.

[0088] Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connecting portion 472, and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connecting portion 482 shown in FIG. 21 are bonded by liquid phase diffusion bonding. The liquid phase diffusion bonding method is as described above, so a repeated explanation will be omitted. By performing liquid phase diffusion bonding, the metal films 472C and 482C shown in FIG. 21 become alloy layers 472E and 482E formed by a eutectic reaction between tin, the main component of the solder layer, and the material of the metal film (e.g., gold), as shown in FIG. 22. Note that if it is possible to clean the flux residue, including during the semiconductor die mounting process described above, a solder reflow process using flux may be performed instead of the combination of solid phase diffusion bonding and liquid phase diffusion bonding described above.

[0089] However, as in the present embodiment, when the solder layers 473, 483 joining the columnar connecting portions 472, 782 and the die electrodes 417, 427 are already sealed with the sealing body 45 in the bridge mounting step, it is particularly preferable to apply liquid phase diffusion bonding from the viewpoint of preventing melting of the sealed solder layers 473, 483. With liquid phase diffusion bonding, the interface between the solder layer 474 and the columnar connecting portion 472 and the interface between the solder layer 484 and the columnar connecting portion 482 can be joined at a temperature lower than the melting points of the solder layers 473, 483.

[0090] 7, after the bridge mounting step, the bridge electrodes 436 and 437 are sealed with the sealing body 44 as shown in FIG. 23. FIG. 23 is an enlarged cross-sectional view showing details of the second sealing step shown in FIG. 7. In the example shown in FIG. 23, the sealing body 44 is an underfill resin embedded between the bridge 43 and the sealing body 45. By sealing the bridge electrodes 436 and 437 with the sealing body 44, it is possible to protect parts of the columnar connectors 472 and 482 exposed from the sealing body 45.

[0091] However, there are various modifications of the embodiment shown in FIG. 23 . For example, the second sealing step shown in FIG. 7 may be omitted, and the semiconductor module in the state shown in FIG. 22 may be shipped as a product. Alternatively, as shown in a modification in FIG. 24 , the bridge electrodes 436 and 437 may be sealed with the sealing body 105 together with the conductive tor pillars 401. This sealing step is generally called mold underfill (MUF). In this modification, a step of forming the tor pillars 401 is required before the second sealing step. For example, the step of forming the tor pillars is preferably performed after the connection portion exposing step and before the bridge mounting step. The tor pillars 401 can be formed in the same manner as the connection portion forming step described with reference to FIGS. 8 to 12 . That is, a resist mask is formed on the lower surface 45b of the sealing body 45 shown in FIG. 24 . An opening is formed in the resist mask at a position overlapping a portion of the connection portion 49. The tor pillars 401 are formed by depositing a metal film in the opening of the mask by plating or the like. In this case, the tor pillars 401 are formed directly on the electrodes 492 .

[0092] In the case of the modification shown in FIG. 24, the entire chip layer 104, the entire integrated layer 100, or the entire chip integrated body 10 shown in FIG. 3 can also be regarded as a semiconductor module.

[0093] 7, in the case of a manufacturing method in which a bridge mounting step is performed after integrating multiple semiconductor dies through a first sealing step, multiple die electrodes and multiple connecting portions can be positioned with high positional accuracy, thereby enabling higher density bonding of the IC chip and the bridge. Also, as explained using FIG. 4, the structure in which connecting portion 47, connecting portion 48, semiconductor die 41, and semiconductor die 42 are each sealed with one sealing body 45 is a structure obtained by manufacturing using the manufacturing method explained using FIGS.

[0094] <Modifications of the sealing body> Next, a description will be given of modifications of the sealing body 45 and the sealing body 44 shown in Fig. 4. Each of Figs. 25 to 27 is an enlarged cross-sectional view showing a modification of the sealing body shown in Fig. 4.

[0095] The chip-integrated module 40A shown in FIG. 25 differs from the chip-integrated module 40 shown in FIG. 4 in the sealing body 45A and sealing body 44A. The sealing body 45A includes a plurality of filler particles 451, and the sealing body 44A includes a plurality of filler particles 441. The average particle size of the plurality of filler particles 451 is larger than the average particle size of the plurality of filler particles 441. By including a plurality of filler particles 451 with a large average particle size in the sealing body 45A as in this modification, the linear expansion coefficient of the sealing body 45A as a whole can be reduced. As a result, the positional accuracy of the connecting portions 47 and 48 can be further improved in the bridge mounting process described with reference to FIGS. 7 and 20 to 22. The plurality of filler particles 451 are premixed in the sealing resin used in the first sealing process shown in FIG. 7. Similarly, the plurality of filler particles 441 are premixed in the sealing resin used in the second sealing process shown in FIG. 7.

[0096] The chip-integrated module 40B shown in FIG. 26 differs from the chip-integrated module 40 shown in FIG. 4 in terms of the encapsulant 45B and the encapsulant 44B. The encapsulant 45B includes a plurality of filler particles 452, and the encapsulant 44B includes a plurality of filler particles 442. The filling rate of the encapsulant 45B with the plurality of filler particles 452 is greater than the filling rate of the encapsulant 44B with the plurality of filler particles 442. The "filling rate of the filler particles 452" is defined as the sum of the volumes of the plurality of filler particles 452 contained in the entire volume of the encapsulant 45B, including the resin 453 and the plurality of filler particles 452. The "filling rate of the filler particles 442" is defined as the sum of the volumes of the plurality of filler particles 442 contained in the entire volume of the encapsulant 44B, including the insulating resin 443 and the plurality of filler particles 442.

[0097] However, when calculating the filling rate, for example, images of the cross sections of two or more randomly selected regions of the encapsulant 45A are captured, and the ratio of the cross-sectional area of ​​the filler particles 452 to the cross-sectional area of ​​the encapsulant 45A is measured in each captured region. The average value of the captured regions can be regarded as the "filling rate of the filler particles 452." The same applies to the "filling rate of the filler particles 442." Increasing the filling rate of the filler particles 452 in the encapsulant 45B, as in this modification, can reduce the linear expansion coefficient of the encapsulant 45B as a whole. As a result, the positional accuracy of the connecting portions 47 and 48 can be further improved in the bridge mounting process described with reference to FIGS. 7 and 20 to 22. The filler particles 452 are premixed in the encapsulating resin used in the first encapsulating process shown in FIG. 7. Similarly, the filler particles 442 are premixed in the encapsulating resin used in the second encapsulating process shown in FIG. 7.

[0098] A chip-integrated module 40C shown in FIG. 27 differs from the chip-integrated module 40 shown in FIG. 4 in that the sealing body 45B includes a plurality of filler particles 452, while the sealing body 44 is made of insulating resin 443 that does not include filler particles. As in this modification, regardless of whether or not the sealing body 44 includes filler particles, the linear expansion coefficient of the sealing body 45B as a whole can be reduced if the sealing body 45B includes filler particles. As a result, the positional accuracy of the connecting portions 47 and 48 can be further improved in the bridge mounting process described with reference to FIGS. 7 and 20 to 22.

[0099] <Modification of manufacturing method> Next, modifications of the manufacturing method of chip-integrated module 40 described with reference to FIGS. 7 to 23 will be described. FIG. 28 is an enlarged cross-sectional view of a chip-integrated module that is another modification of the chip-integrated module shown in FIG. 4. Chip-integrated module 40D shown in FIG. 28 differs from chip-integrated module 40 shown in FIG. 4 in that connecting portions 47 and 48 are sealed in insulating layer 81, and die electrodes 416 and 417 of semiconductor die 41 and die electrode 427 of semiconductor die 42 are each sealed in insulating layer 82 that is in close contact with insulating layer 81. Chip-integrated module 40D also differs from chip-integrated module 40 shown in FIG. 4 in that bridge electrodes 436 and 437 of bridge 43 are each sealed in insulating layer 84 that is in close contact with insulating layer 81.

[0100] The following describes a manufacturing method for chip-integrated module 40D shown in Fig. 28. In the following description, differences from the manufacturing method for chip-integrated module 40 described using Figs. 7 to 23 will be mainly described, and common steps may be omitted. Fig. 29 is an explanatory diagram showing an overview of the manufacturing process for the chip-integrated module shown in Fig. 28. As shown in Fig. 29, the manufacturing method for the chip-integrated module of this variation includes an insulating layer forming step, a connecting portion forming step, a semiconductor die mounting step, a sealing step, a support removing step, a connecting portion exposing step, and a bridge mounting step.

[0101] The insulating layer formation step shown in FIG. 29 includes the steps shown in FIGS. 30 and 31. FIGS. 30 and 31 are enlarged cross-sectional views each showing the details of the insulating layer formation step shown in FIG. 29. In the insulating layer formation step, as shown in FIG. 30, an insulating layer 81 is formed on the upper surface 70t of the support 70. Then, as shown in FIG. 31, an opening 81H1 and an opening 81H2 are formed in the insulating layer 81. In the example shown in FIG. 31, an opening 81H3 for forming the connection portion 49 shown in FIG. 28 is also formed. The insulating layer 81 is bonded to the insulating layer 82 shown in FIG. 28 in the semiconductor die mounting step described below. For this reason, it is preferable to use an insulating material for the insulating layer 82 that has high heat resistance in addition to electrical insulation properties. Examples of such materials include organic insulating materials such as polyimide and PBO (polybenzoxazole). The support 70, release layer 71, and seed layer 72 shown in FIGS. 30 and 31 have already been described using FIG. 8, so repeated description will be omitted.

[0102] In the connecting portion forming step shown in FIG. 29, as shown in FIG. 32, a connecting portion 47 including a columnar connecting portion 472 formed in the opening 81H1 and a connecting portion 48 including a columnar connecting portion 482 formed in the opening 81H2 are formed. FIG. 32 is an enlarged cross-sectional view showing details of the connecting portion forming step shown in FIG. 29. In the example shown in FIG. 32, an electrode 492 constituting the connecting portion 49 is formed in the opening 81H3. This modified example differs from the manufacturing method described with reference to FIG. 10 in that an insulating layer 81 is used as a mask instead of the resist mask 73 described with reference to FIG. 10. The structures of the columnar connecting portions 472, 482 and the electrode 492 are the same as those described with reference to FIG. 10, and therefore, redundant description will be omitted.

[0103] As described above, in this modification, the insulating layer 81 is used as a mask to form the connection portions 47, 48, and 49. Therefore, the step of removing the resist mask 73 described with reference to FIG. 11 and the step of forming the oxide film 72A described with reference to FIG. 12 are not applied to this modification.

[0104] The semiconductor die mounting step shown in Fig. 29 includes the steps shown in Fig. 33 to Fig. 35. Each of Fig. 33 to Fig. 35 is an enlarged cross-sectional view showing details of the semiconductor die mounting step shown in Fig. 29. In the semiconductor die mounting step, as shown in Fig. 35, a semiconductor die 41 having an IC chip 411 and a die electrode 417 connected to the IC chip 411, and a semiconductor die 42 having an IC chip 421 and a die electrode 427 connected to the IC chip 421 are prepared. Furthermore, in the semiconductor die mounting step, each of the semiconductor die 41 and the semiconductor die 42 is mounted on the support 70 so that the die electrode 417 is arranged on the connecting portion 47 and the die electrode 427 is arranged on the connecting portion 48.

[0105] More specifically, first, semiconductor die 41 and semiconductor die 42 are prepared as shown in FIG. 33. This modification differs from the semiconductor die mounting process described with reference to FIGS. 13 to 15 in that an insulating layer 82 is formed on the top surface (die electrode formation surface) of semiconductor die 41, and an insulating layer 83 is formed on the top surface (die electrode formation surface) of semiconductor die 42. Insulating layer 82 is an insulating layer that is bonded to insulating layer 81 in this process. In consideration of the bondability with insulating layer 81, it is particularly preferable that insulating layers 82 and 83 be made of the same material as insulating layer 81. The detailed structures of semiconductor die 41 and semiconductor die 42 other than the above differences have already been described with reference to FIG. 4, so a repeated description will be omitted.

[0106] Next, as shown in FIG. 33 , the semiconductor die 41 and the semiconductor die 42 are aligned with the support 70 so that the die electrode 417 is positioned on the connection portion 47 and the die electrode 427 is positioned on the connection portion 48. A solder layer 473 is formed on the die electrode 417 of the semiconductor die 41. A solder layer 483 is formed on the die electrode 427 of the semiconductor die 42. In this modification, in the sealing process shown in FIG. 29 , the sealing body 45 does not come into contact with the connection portions 47, 48, and 49. For this reason, it is preferable that the solder layer 493 be formed on the bonding surface of the electrode 492, which has a relatively larger area than the die electrode 416. This reduces the volume of the gap around the solder layer 493 after the semiconductor die mounting process. Meanwhile, from the viewpoint of preventing oxidation of the bonding surface of the die electrode 416, it is preferable that the die electrode 416 also has a solder layer formed thereon.

[0107] Next, as shown in FIG. 34 , the die electrode 417 of the semiconductor die 41 is pressed against the connection portion 47 via the solder layer 473. At this time, the die electrode 416 of the semiconductor die 41 is pressed against the solder layer 493. Similarly, the die electrode 427 of the semiconductor die 42 is pressed against the connection portion 48 via the solder layer 483. In this process, the solder layer 473 and the columnar connection portion 472 of the connection portion 47 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 493 and the electrode 492 of the connection portion 49 are temporarily bonded by solid-state diffusion bonding. Similarly, the solder layer 483 and the columnar connection portion 482 of the connection portion 48 are temporarily bonded by solid-state diffusion bonding. At this point, the insulating layer 81 contacts the insulating layer 82 and the insulating layer 83, respectively, but is not yet bonded.

[0108] Next, the bonding interface between the solder layer 473 and the metal film 472B of the columnar connecting portion 472 shown in Fig. 34, the bonding interface between the solder layer 493 and the metal film 492B of the electrode 492, and the bonding interface between the solder layer 483 and the metal film 482B of the columnar connecting portion 482 are bonded by the liquid phase diffusion bonding described above. In this case, as shown in Fig. 35, alloy layers 472D, 482D, and 492D are formed by a eutectic reaction at each bonding interface. The details of liquid phase diffusion bonding have already been explained, so a duplicated explanation will be omitted.

[0109] In this modification, the insulating layers 81 and 82 are bonded to each other during the semiconductor die mounting process, and the die electrode 417 is sealed by the insulating layers 81 and 82. The insulating layers 81 and 83 are bonded to each other during the semiconductor die mounting process, and the die electrode 427 is sealed by the insulating layers 81 and 83. The timing at which the insulating layers 81 and 82 are bonded to each other can be approximately the same as the timing at which liquid-phase diffusion bonding is performed. That is, when the solder layer 473 and the metal film 472B shown in FIG. 34 are heated to a temperature at which a eutectic reaction occurs, the insulating layers 81, 82, and 83 are also heated. This softens the materials constituting the insulating layers 81, 82, and 83, and their contact interfaces are bonded. The insulating layers can be bonded together using a method such as fusion bonding, which involves dehydration polymerization of hydroxyl groups on the surfaces of the insulating layers. Depending on the material, softening and melting can also be used for bonding. When using the fusion bonding method, it is desirable to activate the surface of the insulating layer with plasma before bonding the insulating layers together.

[0110] In this modification, the connection portions 47, 48, and 49 are surrounded by an insulating layer 81. This prevents the solder component from spreading during liquid phase diffusion bonding. Therefore, in this modification, the die electrode and the connection portions can be bonded with a small amount of solder.

[0111] In the encapsulation step shown in Fig. 29, after the semiconductor die mounting step, the semiconductor die 41 and the semiconductor die 42 are encapsulated with the encapsulant 45 as shown in Fig. 36. Fig. 36 is an enlarged cross-sectional view showing details of the encapsulation step shown in Fig. 29. In this step, the semiconductor die 41 and the semiconductor die 42 are integrated with the encapsulant 45. In the case of this modification, the connection portions 47, 48, and 49 are already encapsulated, so strictly speaking, the semiconductor die 41 and the semiconductor die 42 are integrated with each other via the insulating layer 81. In this step, encapsulation with the encapsulant 45 improves the rigidity of the integrated structure of the semiconductor die 41 and the semiconductor die 42.

[0112] In this modification, the volume of the sealing body 45 is even smaller than the volume of the sealing body 45 shown in Fig. 4. Therefore, even if the sealing body 45 undergoes thermal expansion or thermal contraction, each of the connection portions 47, 48, and 49 can maintain high positional accuracy even when sealed by the sealing body 45.

[0113] In the support removal step shown in Fig. 29, after the sealing step, the support 70 shown in Fig. 36 is removed. The method for removing the support 70 is the same as the support removal step described using Fig. 17, so a duplicated description will be omitted.

[0114] 29, after the support member removing step, as shown in FIG. 37, a portion (lower surface) of the columnar connecting portion 472 and a portion (lower surface) of the columnar connecting portion 482 are exposed from the insulating layer 81. FIG. 37 is an enlarged cross-sectional view showing details of the connecting portion exposing step shown in FIG. 29. In this step, the peeling layer 71 and the seed layer 72 shown in FIG. 36 are removed by, for example, etching. In the example shown in FIG. 37, a portion (lower surface) of the electrode 492 is also exposed from the insulating layer 81 in this step.

[0115] In this step, as shown in FIG. 38, after exposing the connection portions from the insulating layer 81, it is preferable to form metal films 472C, 482C, and 492C on the exposed surfaces of the connection portions. FIG. 38 is an enlarged cross-sectional view showing details of the connection portion exposing step subsequent to FIG. 37. As shown in FIG. 38, in this step, a metal film 472C is formed on the surface of the columnar connection portion 472 exposed from the sealing body 45. Similarly, a metal film 482C is formed on the surface of the columnar connection portion 482 exposed from the sealing body 45. A metal film 492C is formed on the surface of the electrode 492 exposed from the sealing body 45. The details of the metal films 472C, 482C, and 492C have already been described using FIG. 19, and therefore a repeated description will be omitted.

[0116] The bridge mounting step shown in Fig. 29 includes the steps shown in Fig. 39 to Fig. 41. Each of Fig. 39 to Fig. 41 is an enlarged cross-sectional view showing the details of the bridge mounting step shown in Fig. 29. In the bridge mounting step, as shown in Fig. 41, a bridge 43 is prepared, which includes a bridge electrode 436 connected to a connection portion 47 and a bridge electrode 437 connected to a connection portion 48. Furthermore, in the bridge mounting step, after the connection portion exposing step, the bridge 43 is mounted on a structure sealed with a sealant 45 so that the bridge electrode 436 is arranged on the columnar connection portion 472 and the bridge electrode 437 is arranged on the columnar connection portion 482.

[0117] In more detail, first, a bridge 43 is prepared as shown in Fig. 39. This modification differs from the semiconductor die mounting process described using Figs. 13 to 15 in that an insulating layer 84 is formed on the upper surface (bridge electrode forming surface) of the bridge 43, and the bridge electrodes 436 and 437 are each sealed with the insulating layer 84. The detailed structure of the bridge 43, excluding the above differences, has already been described using Fig. 4, so a duplicated description will be omitted.

[0118] 39 , the bridge 43 is aligned with the structure sealed with the sealing body 45 so that the bridge electrode 436 is disposed on the columnar connection portion 472 and the bridge electrode 437 is disposed on the columnar connection portion 482. A solder layer 474 is formed on the bridge electrode 436. A solder layer 484 is formed on the bridge electrode 437.

[0119] 40 , the bridge electrodes 436 of the bridge 43 are pressed against the columnar connection portions 472 of the connection portions 47 via the solder layers 474. At this time, the bridge electrodes 437 of the bridge 43 are pressed against the columnar connection portions 482 of the connection portions 48 via the solder layers 484. In this step, the solder layers 474 and the columnar connection portions 472 of the connection portions 47 (more specifically, the metal films 472C of the columnar connection portions 472) are temporarily joined by solid-state diffusion bonding. Similarly, the solder layers 484 and the columnar connection portions 482 of the connection portions 48 (more specifically, the metal films 482C of the columnar connection portions 482) are temporarily joined by solid-state diffusion bonding.

[0120] In this modified example, the insulating layer 81 and the insulating layer 84 are in contact with each other at this time. However, at this point, the insulating layer 81 and the insulating layer 84 are not yet bonded together.

[0121] Next, the bonding interface between the solder layer 474 and the metal film 472C of the columnar connecting portion 472 shown in Fig. 40, and the bonding interface between the solder layer 484 and the metal film 482C of the columnar connecting portion 482 are bonded by liquid phase diffusion bonding. The liquid phase diffusion bonding method is as described above, so a duplicated explanation will be omitted. By performing liquid phase diffusion bonding, the metal films 472C and 482C shown in Fig. 40 become alloy layers 472E and 482E (see Fig. 41) formed by a eutectic reaction between tin, which is the main component of the solder layer, and the material of the metal film (e.g., gold), respectively.

[0122] In this modification, insulating layer 81 and insulating layer 84 are bonded to each other in the bridge mounting process. The timing at which insulating layer 81 and insulating layer 84 are bonded to each other coincides with the timing at which liquid phase diffusion bonding is performed. That is, when solder layer 474 and metal film 472C shown in FIG. 40 are heated to a temperature at which a eutectic reaction occurs, insulating layer 81 and insulating layer 84 are also heated together. This softens the materials that make up insulating layer 81 and insulating layer 84, and their contact interfaces are bonded. The principle of bonding insulating layers to each other can also be the aforementioned bonding by dehydration polymerization of hydroxyl groups on the surfaces of the insulating layers (fusion bonding).

[0123] Although this modified example has been described as an example using insulating layers 81 to 84 shown in Fig. 28, there are cases where the configuration example shown in Fig. 4 or the configuration of the modified example described using Fig. 24 is partially applied. For example, instead of insulating layer 84 shown in Fig. 28, bridge electrode 436 and bridge electrode 437 may each be sealed with sealing body 44 shown in Fig. 4 or sealing body 105 shown in Fig. 24.

[0124] Furthermore, in this modification, an example has been described in which the top surface of bridge 43 is covered with insulating layer 84, but insulating layer 84 may not be formed. For example, if a functional insulating film called an NCF (Non Conductive Film) is used instead of insulating layer 84, the NCF is disposed so as to cover insulating layer 81 and connecting portions 47 and 48 after the step shown in FIG. 38. In this case, in the bridge mounting step, bridge 43 having the structure shown in FIG. 20 is pressed against the NCF, so that bridge electrode 436 and bridge electrode 437 each penetrate the NCF and contact connecting portion 47 or connecting portion 48. In this state, solid-phase diffusion bonding and liquid-phase diffusion bonding described above are performed, thereby obtaining a structure similar to chip-integrated module 40D shown in FIG. 28.

[0125] <Method of manufacturing chip assembly> Next, a method for manufacturing a chip assembly will be described with reference to FIG. 3. First, a global wiring layer 102 is formed on a support (not shown). The method for forming the global wiring layer 102 is not particularly limited, and a build-up method, for example, can be used. Next, a plurality of electrodes 403 and tor pillars 401 are formed on the global wiring layer 102. The method for forming the electrodes 403 and tor pillars 401 can be applied by applying the connection portion formation process described with reference to FIGS. 8 to 12. In this process, the electrodes 148 and conductor posts 146 are also formed. If the electrodes 148 and 403 have the same thickness, they can be formed collectively at the same time. However, since the conductor posts 146 and tor pillars 401 have different thicknesses, they are formed separately.

[0126] Next, the chip-integrated module 40 is mounted on the tor pillar 401. The tor pillar 401 is connected to the connection portion 49 shown in FIG. 4. There are no particular limitations on the method for connecting the tor pillar 401 and the connection portion 49, but they can be connected, for example, via a solder layer (not shown). At this time, it is preferable to use liquid phase diffusion bonding to prevent the solder layer in the chip-integrated module 40 from remelting.

[0127] Next, the various components formed on the chip layer 104 are encapsulated with the encapsulant 105. In the example shown in FIG. 3, the conductor posts 146, electrodes 148, chip-integrated module 40, tor pillars 401, and electrodes 403 are each encapsulated with the encapsulant 105. After that, the support (not shown) is removed from the global wiring layer 102. Furthermore, the upper part of the encapsulant 105 is ground so that the conductor posts 146 and chip-integrated module 40 are exposed.

[0128] Next, the connection layer 106 is formed on the encapsulant 105. More specifically, the connection layer 106 is formed on the encapsulant 105 so that the wiring included in the connection layer 106 is connected to the exposed portion of the conductor post 146 or the exposed portion of the chip integrated module 40. For example, the electrode 140 formed on the connection layer 106 is connected to the conductor post 146 through the conductor via 142.

[0129] Next, the heat dissipation mechanism 20 is mounted on the contact portion 222. Furthermore, an optical module 13 to which an optical fiber 600 (see FIG. 5) or an optical fiber 610 (see FIG. 5) is connected is connected to the electrode 140. The heat dissipation member 136 is connected to the optical module 13 in advance. Next, by mounting a plurality of external terminals 30 on the global wiring layer 102, the chip integration 10 shown in FIG. 3 is obtained.

[0130] <Modification of Chip Assembly> Next, a modified example of the chip integrated structure shown in FIG. 3 will be described. FIGS. 42 and 43 are explanatory diagrams illustrating modifications of the chip integrated structure shown in FIG. 3. The chip integrated structure 10A shown in FIG. 42 differs from the chip integrated structure 10 shown in FIG. 3 in that a portion of the optical module 13 is embedded in the chip layer 104 of the integrated layer 100. Specifically, the connector 132 of the optical module 13 is sealed by the sealing body 105. The connector 132 and the electrode 148 are connected via a conductive via 142. Embedding the connector 132 in the chip layer 104 reduces the overall height of the chip integrated structure 10A and improves signal transmission characteristics by shortening the distance from the chip integrated module to the optical transceiver compared to the case shown in FIG. 3. Furthermore, the optical transceiver 130 is exposed from the chip layer 104 and the connection layer 106, making it easy to attach and detach the optical transceiver 130.

[0131] The chip-integrated structure 10B shown in FIG. 43 differs from the chip-integrated structure 10 shown in FIG. 3 in that the optical module 13 is disposed on the back surface 100b side of the integration layer 100. The integration layer 100 has a front surface 100f on which the heat dissipation mechanism 20 is mounted and a back surface 100b opposite the front surface 100f. The optical module 13 is mounted on the back surface 100b side. By disposing the optical module 13 on the back surface 100b, the distance between the heat dissipation mechanism 20 and the optical module 13 increases, thereby reducing the thermal impact from the heat dissipation mechanism 20. In the example shown in FIG. 43, the optical module 13 is disposed at a position overlapping the chip-integrated module 40 in the thickness direction of the integration layer 100. In this case, the distance between the chip-integrated module 40 and the optical module 13 is shortened, thereby improving the transmission efficiency of electrical signals.

[0132] <Modification of measures to reduce parasitic capacitance occurring in bridges> Signals are transmitted at ultra-high speeds through a signal transmission path via a bridge 43 shown in Fig. 4. In the case of a high-speed signal transmission path, it is preferable to reduce the electrical parasitic capacitance imparted to the transmission path. A technique for reducing the parasitic capacitance occurring between a chip 431 and a wiring 434 shown in Fig. 4 will be described below as a modified example. Fig. 44 is a cross-sectional view showing a modified example of the bridge shown in Fig. 4.

[0133] The bridge 43A shown in FIG. 44 differs from the bridge 43 shown in FIG. 4 in that it further includes an insulating layer 438 between the insulating layer 432 and the chip 431. The bridge 43A is otherwise similar to the bridge 43 shown in FIG. 4. The bridge 43A includes a chip 431, insulating layers 438, 432, and 433 stacked in this order on the chip 431, and wiring 434 sandwiched between the insulating layers 432 and 438 and connected to the bridge electrodes 436 and 437, respectively. The insulating layer 438 is a thick insulating layer. The thickness of the insulating layer 438 is greater than the thicknesses of the insulating layers 432 and 433. The insulating layer 438 has a surface 438t bonded to the insulating layer 432 and a surface 438b bonded to the chip 431. Each of the surfaces 438t and 438b has an adhesive function, and the insulating layer 438 is adhesively fixed to the insulating layer 432 and the chip 431 via the adhesive functions of the surfaces 438t and 438b. The entire insulating layer 438 may be an adhesive layer.

[0134] When an insulating layer 438 is interposed between the insulating layer 432 and the chip 431 as in the bridge 43A, it is possible to increase the distance between the wiring 434 and the chip 431. As a result, it is possible to reduce the parasitic capacitance occurring between the chip 431 and the wiring 434 compared to the bridge 43 shown in FIG.

[0135] In the case of bridge 43A provided with insulating layer 438, warpage of the bridge is more likely to occur than in bridge 43 shown in FIG. 4. Warpage of the bridge occurs due to film formation stress (hardening shrinkage and thermal shrinkage of the resin) that occurs when insulating layer 438 is formed. From the viewpoint of reducing this warpage, it is desirable to use a material with a low elastic modulus for insulating layer 438. From the same viewpoint, it is also desirable to use a resin material with a lower hardening temperature and thermal decomposition temperature than insulating layers 432 and 433. For example, if insulating layers 432 and 433 are made of polyimide resin and insulating layer 438 is made of epoxy resin, insulating layer 438 is made of a resin material with a lower hardening temperature and thermal decomposition temperature than insulating layers 432 and 433, thereby suppressing warpage of bridge 43A.

[0136] The bridge 43A shown in Fig. 44 is manufactured, for example, as follows. Figs. 45 to 47 are cross-sectional views showing an outline of the manufacturing process for the bridge shown in Fig. 44. The manufacturing method for the bridge 43A includes a wiring layer forming step shown in Fig. 45, a wiring layer transferring step shown in Fig. 46, a support removing step shown in Fig. 47, and a bridge electrode forming step shown in Fig. 44.

[0137] First, in the wiring layer formation process, an insulating layer 433, wiring 434, and insulating layer 432 are sequentially stacked on a support 80 shown in FIG. 45 . Specifically, in the wiring layer formation process, a support 80 shown in FIG. 45 is prepared. A release layer 81A and a seed layer 82A are pre-formed on an upper surface 80t of the support 80. The material of the support 80 is not particularly limited as long as it is a plate with sufficient rigidity to ensure ease of operation in each process up to the support removal process described below. Examples of the material include a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as a glass or sapphire substrate, and a resin plate. The release layer 81A is similar to the release layer 71 described with reference to FIG. 8 , and the seed layer 82A is similar to the seed layer 72 described with reference to FIG. 8 , so redundant description will be omitted.

[0138] In the wiring layer formation step, after preparing support 80, insulating layer 433 is deposited on seed layer 82A. Next, openings are formed in parts of insulating layer 433, and wiring 434 is formed in the openings. Although redundant explanations will be omitted, the method of forming the openings and the method of forming wiring 434 in the openings can be formed by the method utilizing the photolithography technology described with reference to FIGS. 9 and 10. Next, insulating layer 432 is formed so as to cover insulating layer 433 and wiring 434, thereby obtaining the structure shown in FIG.

[0139] Next, in the wiring layer transfer process, as shown in FIG. 46, the insulating layer 432 on the support 80 and the chip 431 are bonded together via the insulating layer 438. Note that FIG. 46 illustrates an example in which a singulated chip 431 is bonded. However, as a modified example, a silicon wafer before singulation, a glass substrate before singulation, or a sapphire substrate before singulation may be bonded instead of the chip 431 in this process. When a substrate in a pre-singulated state is bonded in this process, a singulation process is performed after the bridge electrode formation process, in which the substrate is diced to obtain multiple bridges 43A (see FIG. 44). This modified example is preferable from the viewpoint of improving manufacturing efficiency, since a large number of bridges 43A can be manufactured at once. Including these modified examples, this process can be expressed as follows. That is, in the wiring layer transfer process, the insulating layer 432 on the support 80 and the substrate are bonded together via the insulating layer 438. The term "substrate" as used herein includes, in addition to the chip shown in FIG. 46, a semiconductor substrate such as a silicon wafer before singulation, a glass substrate before singulation, or a sapphire substrate before singulation. As described with reference to FIG. 44, each of the surfaces 438t and 438b of the insulating layer 438 has an adhesive function, and therefore the insulating layer 432 on the support 80 and the chip 431 are adhesively fixed via the insulating layer 438. In this modification, the chip 431 and the wiring 434 are not electrically connected. When the chip 431 is not connected to another circuit, the chip 431 shown in FIG. 44 may be replaced with a substrate (e.g., a semiconductor substrate or a glass substrate) on which no integrated circuit is formed. Alternatively, as described below, a bridge may be formed from the chip 431.

[0140] Next, as shown in FIG. 47, the support removal step is performed by, for example, applying energy to the release layer 81A (see FIG. 46) to decompose the release layer 81A. After the support removal step, the conductor portions connected to the bridge electrode 437 and the bridge electrode 436 (the conductor portion 437A connected to the bridge electrode 437 and the conductor portion 436A connected to the bridge electrode 436) are exposed. The conductor portion 436A and the conductor portion 437A each function as a contactor for electrically connecting the wiring substrate and the bridge electrode. In this step, the release layer 81A and the seed layer 82A shown in FIG. 46 are removed by, for example, etching.

[0141] 44, in the bridge electrode formation step, a bridge electrode 437 is formed on a conductor portion 437A connected to the wiring 434, and a bridge electrode 436 is formed on a conductor portion 436A connected to the wiring 434. Also in this step, a solder layer 474 is formed on the tip surface of the bridge electrode 436, and a solder layer 484 is formed on the tip of the bridge electrode 437.

[0142] The above steps are performed on a large-sized wafer or panel, and then the resulting product is divided into bridges of a predetermined size to form the bridge 43A shown in FIG. 44. The bridge 43A can be used, for example, in place of the bridge 43 shown in FIG. 4. Replacing the bridge 43 with the bridge 43A reduces the parasitic capacitance between the chip 431 and the wiring 434, making this particularly suitable for transmitting high-speed signals. In this modification, the bridge 43A shown in FIG. 44 and the bridge 43B shown in FIG. 48 (described later) are described as modifications of the bridge 43 shown in FIG. 4. However, the bridge 43A and the bridge 43B can be replaced with the bridge 43 shown in any of the chip-integrated module 40A shown in FIG. 25, the chip-integrated module 40B shown in FIG. 26, the chip-integrated module 40C shown in FIG. 27, and the chip-integrated module 40D shown in FIG. 28.

[0143] Fig. 48 is a cross-sectional view showing another modified example of the bridge shown in Fig. 4. Bridge 43B shown in Fig. 48 differs from bridge 43 shown in Fig. 4 in that the portion corresponding to chip 431 has been removed. In the case of bridge 43B, chip 431 is not placed near wiring 434, so the effect of parasitic capacitance on wiring 434 can be further reduced.

[0144] However, the bridge 43B has lower rigidity than the bridge 43 shown in FIG. 4 or the bridge 43A shown in FIG. 44. Therefore, in the manufacturing process of the chip-integrated module 40E, it is preferable to perform each step similar to the manufacturing method described with reference to FIGS. 20 to 23 with the insulating layer 433 held on the chip 431 until the semiconductor die 41 and the semiconductor die 42 are bonded to the bridge 43B and the peripheries of the bridge electrodes 436 and 437 are sealed. Thereafter, a manufacturing method in which the chip 431 is removed in the state shown in FIG. 23 is preferable. For example, when the chip 431 is made of silicon, it can be removed by dry etching or the like. When the chip 431 is made of an inorganic material such as glass, a method can be used in which a release layer is interposed between the chip 431 and the insulating layer 433 and the release layer is decomposed (ablated) with an energy beam such as a laser to remove the chip 431. Note that as a variation of the manufacturing method of the bridge 43B, the manufacturing method described with reference to FIGS. 44 to 47 may also be used.

[0145] <Other Modifications of Chip Integrated Module> FIG. 49 is a diagram showing a partial configuration of a chip-integrated module that is a modification of FIG. 4. As shown in FIG. 49, a chip-integrated module 40E according to this embodiment includes a first die 41E, a second die 42E, a bridge 43E, and sealing members 45E and 46E that seal these components. The first die 41E is connected to the bridge 43E via a first connecting portion 47E. The bridge 43E is connected to the second die 42E via a second connecting portion 48E. The first die 41E is connected to the outside of the chip-integrated module 40E via a third connecting portion 49E.

[0146] The first die 41E includes a first integrated circuit chip 402E, die electrodes 408E and 410E, wiring 404E and 406E connected to the first integrated circuit chip 402E, and insulating layers 412E and 414E in which the wiring 404E and 406E are embedded. The wiring 404E and 406E are separate from the wiring layer included in the first integrated circuit chip 402E. More specifically, the wiring 404E and 406E may be thick-film wiring using an insulating film made of organic (or inorganic, in some cases) resin, and are so-called redistribution layers (RDLs). Note that the wiring included in the second die and bridge is also called redistribution. A second integrated circuit chip 420 and a third integrated circuit chip 442E, which will be described later, may have a configuration similar to that of the first integrated circuit chip 402E.

[0147] The second die 42E includes a second integrated circuit chip 420E, die electrodes 424E, wiring 422E connected to the second integrated circuit chip 420E, and insulating layers 426E and 428E in which the wiring 422E is embedded.

[0148] The bridge 43E includes a third integrated circuit chip 442E, bridge electrodes 446E and 448E, a wiring 444E connected to the third integrated circuit chip 442E, and insulating layers 450E and 452E in which the wiring 444E is embedded. In this embodiment, the wiring 444E constitutes part of a bridge electrically connected to the first connecting portion 47E and the second connecting portion 48E. The bridge according to this embodiment is a pillar-suspended bridge. The wiring 444E according to this embodiment is electrically connected to the third integrated circuit chip 442E, and the wiring 444E and the third integrated circuit chip 442E function together as a bridge.

[0149] The first connecting portion 47E includes pillar-shaped connecting portions 474E and 472E. In this embodiment, the pillar-shaped connecting portions are pillar-shaped conductors (also referred to as "micropillars") of μm size. The pillar-shaped connecting portions 472E and 474E are pillar-shaped conductors formed from the bridge 43E toward the first die 41E. In this embodiment, the cross-sectional area of ​​the portion of the pillar-shaped connecting portion 472E connected to the pillar-shaped connecting portion 474E is larger than the cross-sectional area of ​​the portion of the pillar-shaped connecting portion 474E connected to the pillar-shaped connecting portion 472E. In this modification, the pillar-shaped connecting portion 474E is connected to the die electrode 408E via solder 478E. Furthermore, the pillar-shaped connecting portion 472E is connected to the bridge electrode 446E via solder 476E.

[0150] The second connecting portion 48E includes columnar connecting portions 480E and 482E. The columnar connecting portions 480E and 482E are columnar conductors formed from the bridge 43E toward the second die 42E. In this modification, the cross-sectional area of ​​the portion of the columnar connecting portion 480E connected to the columnar connecting portion 482E is larger than the cross-sectional area of ​​the portion of the columnar connecting portion 482E connected to the columnar connecting portion 480E. In this modification, the columnar connecting portion 482E is connected to the die electrode 424E via solder 486E. Furthermore, the columnar connecting portion 480E is connected to the bridge electrode 448E via solder 484E.

[0151] The third connection portion 49E includes a columnar connection portion 492E. The columnar connection portion 492E is a columnar conductor formed so as to extend outward from the first die 41E. The columnar connection portion 492E is connected to the die electrode 410E via solder 490E. The columnar connection portion 492E is also connected to an electrode pad 494E connected to the outside (e.g., the global wiring layer 102). The third connection portion 49E may include various structures in addition to (or instead of) the configuration shown in FIG. 49. For example, the third connection portion 49E may include various structures that can be connected to the global wiring layer 102 (see FIG. 3), such as a deep via, a toll pillar, or a columnar connection portion, provided below the electrode pad 494E.

[0152] In this modified example, an example in which the bridge is a die including an integrated circuit chip has been described, but the bridge may not include an integrated circuit chip and may be mainly composed of wiring and an insulating layer in which the wiring is embedded. Also, in this embodiment, an example in which the die and the bridge are connected by two columnar connecting parts with different diameters has been described. However, the present invention is not limited to this, and the die and the bridge may be connected by one columnar connecting part, or by three or more columnar connecting parts.

[0153] (First Modification) Fig. 50 is a diagram showing the configuration of a chip-integrated module according to a first modified example of the chip-integrated module shown in Fig. 49. Of the components of the chip-integrated module 40F shown in Fig. 50, components that are substantially the same as those of the chip-integrated module 40E shown in Fig. 49 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0154] The chip-integrated module 40F according to the first modification differs from the chip-integrated module 40E (see FIG. 49) described above in the configurations of the first, second, and third connection portions. Specifically, in the first modification, the columnar connection portions or electrode pads are directly connected to other electrodes or wiring without solder. More specifically, in the first connection portion according to the first modification, the columnar connection portion 502F is connected to the die electrode 408E and the bridge electrode 446E. In addition, in the second connection portion, the columnar connection portion 504 is connected to the die electrode 424E and the bridge electrode 448E. Furthermore, in the third connection portion, the die electrode 410E is connected to an electrode pad 494E. Here, the columnar connection portions and the die electrode or the bridge electrode, or the die electrode and the electrode pad, may be connected by various known hybrid bonding techniques.

[0155] In the first modification, various conductors are embedded in an insulator. Specifically, the die electrodes 408E, 410E, and 424E are embedded in an insulating film 510F. The electrode pad 494E and the columnar connecting portions 502F and 504F are embedded in an insulating layer 512F. The bridge electrodes 446E and 448E are embedded in an insulating film 514F. The first die 41E and the second die 42E are sealed with an insulating resin 506F. By selecting appropriate material systems and process conditions in various well-known hybrid bonding techniques, the die electrode 408E and the columnar connecting portion 502F, and the insulating film 510F and the insulating layer 512F can be connected and bonded. Similarly, the bridge electrodes 446E and 448E and the insulating layer 512F, and the insulating film 514F and the insulating layer 512F can be connected and bonded.

[0156] In the first modification, an example in which the bridge includes an integrated circuit chip has been described, but the bridge does not have to include an integrated circuit chip. For example, instead of an integrated circuit chip, the bridge may include a solid chip made of various materials such as silicon and glass.

[0157] (Second Modification) FIG. 51 illustrates the configuration of a chip-integrated module according to a second modification of the chip-integrated module shown in FIG. 49. In a chip-integrated module 40G according to the second modification, a deep via 520G is formed in an insulating resin 524G that seals a bridge 43E. The first die 41E is electrically connected to an external conductor through the deep via 520G. More specifically, the deep via 520G is connected to an electrode pad 494E connected to the bridge 43E, and a solder 522G that connects to an external conductor may be formed at the end of the deep via 520G. The deep via 520G may be formed so that its diameter increases from the electrode pad 494E toward the solder 522G. In addition, in the second modification, the bottom surface of the third integrated circuit chip 442E may be exposed.

[0158] In the second modification, the bridges including bridge 43E are sealed with insulating resin 524G. Therefore, in the second modification, the bridges are protected by insulating resin 524G. Furthermore, it is possible to seal (underfill) the connection portions between the bridges and other components at the same time as sealing the bridges. Furthermore, by flattening the portions where the die terminals are formed, it is possible to further narrow the pitch of the connection portions with the global wiring layer.

[0159] (Third Modification) FIG. 52 is a diagram illustrating a chip-integrated module according to a third modification of the chip-integrated module shown in FIG. 49. FIG. 52 illustrates a deep via 520G and a portion of a third integrated circuit chip 442E in a chip-integrated module H, which is a modification of the chip-integrated module 40G shown in FIG. 51. The third modification will mainly focus on differences from the chip-integrated module 40G according to the second modification. The chip-integrated module according to the third modification may have the same configuration as the chip-integrated module 40G according to the second modification. That is, configurations not shown in FIG. 52 may be substantially the same as the configurations shown in FIG. 51. Unlike the second modification, the chip-integrated module 40H according to the third modification does not expose the lower surface of the third integrated circuit chip 442E. More specifically, the lower side of the third integrated circuit chip 442E is covered with insulating resin 525G.

[0160] (Fourth Modification) Fig. 53 is a diagram showing a chip-integrated module according to a fourth modification of the chip-integrated module shown in Fig. 49. In a chip-integrated module 40K according to the fourth modification, a wiring layer 570 is formed below insulating resin 524 in which a bridge 43E is embedded. A first die 41E and a bridge 43E are connected to wiring formed in this wiring layer 570K.

[0161] The wiring layer 570K according to the fourth modification has various conductors embedded in insulating layers, specifically, wiring 578K and electrodes 576 embedded in insulating layers 572K and 574K. These wiring 578K and electrodes 576K may be electrically connected to external conductors. According to the fourth modification, for example, it is possible to arrange terminals on the bridge. Furthermore, for example, it is possible to supply power directly from the outside to the bridge.

[0162] A third integrated circuit chip 564K according to the fourth modification includes a functional element 566K having various functions in an area surrounded by a dashed line. The functional element 566K is connected to an electrode 576K formed on a wiring layer 570K through a via 568K formed inside the third integrated circuit chip 564K. In addition, in this embodiment, the bridge electrode 446E is connected to the wiring 443K, and the bridge electrode 448E is connected to the wiring 444E. Thus, in the fourth modification, the first die 41E and the second die 42E are connected via the functional element 566K.

[0163] Furthermore, the electrode pad 494E electrically connected to the first die 41E is connected to the wiring 578K of the wiring layer 570K through the tor pillar 560K. Unlike the deep via 520G (see FIG. 51) described in the second modified example, the tor pillar 560K may have a substantially constant cross-sectional area from the electrode pad 494E to the wiring 578K.

[0164] (Fifth Modification) Fig. 54 shows a chip-integrated module according to a fifth modification of the chip-integrated module shown in Fig. 49. In chip-integrated module 40M according to the fifth modification, the bridge mainly includes wiring. Specifically, bridge 580M according to the fifth modification has various wirings and an insulating layer in which the wirings are embedded, but does not have an integrated circuit chip.

[0165] The bridge 580M has a wiring 588M embedded in an insulating layer 582M, and this wiring 588M is connected to the bridge electrodes 446E and 448E. Furthermore, wiring 589M and 590M are embedded in the insulating layers 582M, 584M, and 586M. These wiring 589M and 590M are connected to the electrode 576 of the wiring layer 570K through a contact via 592M.

[0166] <Another Modification of the Manufacturing Method of the Chip Integrated Module> Another modified example of the method for manufacturing the chip integrated module will be described with reference to FIGS.

[0167] First, a flat support 800 having a release film 802 formed on its surface as shown in FIG. 55 is prepared. Various conductors are formed on this release film 802 (forming process). Various materials, including glass, silicon, and metal, can be used as the support. For example, columnar connecting portions 806 and 808 are formed on the release film 802 so as to protrude from the surface of the support 800. Electrode pads 804 and 809 may also be formed on the release film 802.

[0168] 56, multiple dies including a first die 81E and a second die 82E are bonded to various conductors formed on the release film 802. The first die 81E has a first integrated circuit chip 810, a wiring layer 812 formed on its surface, and various electrodes including die electrodes 814 and 816 formed on its surface. The second die 82E has a second integrated circuit chip 820, a wiring layer 822 formed on its surface, and various electrodes including die electrodes 824 and 826 formed on its surface.

[0169] In this embodiment, die electrodes formed on the die are bonded to various conductors (die bonding process). For example, die electrodes 814 and 816 of the first die 81E are bonded to electrode pads 804 and columnar connections 806, respectively. Also, die electrodes 824 and 826 of the second die 82E are bonded to electrode pads 809 and columnar connections 808, respectively. The die electrodes may be connected to the electrode pads or columnar connections via solder, or may be bonded by hybrid bonding without solder.

[0170] 57, the various conductors and the multiple dies formed on the release film 802 are sealed with resin 818 (sealing member) (sealing process). Prior to the sealing process with resin 818, the spaces between the first die 81E and the second die 82E and the release layer may be sealed in advance by injecting and curing a liquid underfill resin using capillary action (Capillary Underfill) or by using an insulating resin such as NCF (Non Conductive Film). Alternatively, the spaces may be sealed simultaneously with the sealing process with resin 818 (Mold Underfill). As a result, the multiple dies are fixed in a state where they are bonded to the columnar connections and metal pads.

[0171] Next, as shown in FIG. 58, the release film 802 and support 800 are removed, and a process is performed to remove the release film remaining on the electrode pads, etc. Various methods can be used to remove the support, such as mechanically peeling the support, irradiating the release film with laser light, or, in some cases, removing the support by grinding or etching. In the case of methods using grinding or etching, the release film may become unnecessary. Furthermore, the resin 818 on the surface side of the die is ground away, thereby exposing the die. Hereinafter, the resin in which various conductors and multiple dies are embedded as shown in FIG. 58 using the method described with reference to FIGS. 55 to 58 and ground away is also referred to as intermediate 84E.

[0172] Next, as shown in Fig. 59, bridges are bonded to the plurality of columnar connection portions (bridge bonding process). In this embodiment, each of the plurality of dies including the bridge 83E is used as a bridge, and the bridge is bonded to the lower part of each of the plurality of columnar connection portions. In this embodiment, the bridge 83E has a third integrated circuit chip 830, a wiring layer 832 formed on its surface, and bridge electrodes (including bridge electrodes 834 and 836) formed thereon.

[0173] A bridge electrode 834 of the bridge 83E is coupled to a columnar connection portion 806 connected to the first die 81E. Furthermore, the bridge electrode 836 of the bridge 83E is joined to a columnar connection portion 808 connected to the second die 82E. As a result, the bridge 83E functions as a bridge electrically connected to the first die 81E and the second die 82E, forming a structure characterized by a suspended bridge using pillars. Note that the bridge electrode may be coupled to the columnar connection portion via solder or by hybrid bonding without using solder.

[0174] 60, the resin 818 is cut so as to separate each chip-integrated module 80. As a result, each chip-integrated module is formed individually.

[0175] According to the method for manufacturing a chip-integrated module of this embodiment, as described with reference to FIG. 57 , the first die, the second die, and the columnar connection portions are fixed with resin before the subsequent processes are performed. Therefore, in the subsequent processes, the positional relationship between the multiple dies is not misaligned, enabling the integrated circuit chips to be connected with higher accuracy. This also simplifies the process and handling. Furthermore, it also becomes possible to form external terminals directly below the integrated circuit chips, which is expected to achieve excellent characteristics in terms of power integrity (PI) and signal integrity (SI). Furthermore, because stable relative positional accuracy of the dies can be ensured regardless of the module size, this embodiment facilitates the application to panel-scale large-scale chip integration.

[0176] (Sixth Modification) 61 to 64 are diagrams illustrating a method for manufacturing a chip-integrated module according to a sixth modified example of the method for manufacturing a chip-integrated module shown in Figures 55 to 60. In the sixth modified example, a method for manufacturing a chip-integrated module having a configuration similar to that of chip-integrated module 40F according to the second modified example described with reference to Figure 50 is described.

[0177] First, a plurality of intermediate bodies 84E embedded in resin 818 are prepared in the same manner as described above with reference to FIGS.

[0178] The next step will be described with reference to FIG. 61. First, a bridge is connected to the columnar connection portion. The bridge according to the sixth modified example has a wiring layer 946 and an integrated circuit chip 948. The wiring layer 946 has wiring (not shown in FIG. 61), which is connected to a plurality of bridge electrodes. The bridge electrodes are connected to the columnar connection portion. For example, the bridge electrode 942 is connected to the columnar connection portion 806, and the bridge electrode 944 is connected to the columnar connection portion 808. As a result, the bridge electrodes 942 and 944, the wiring layer 946, and the integrated circuit chip function as a bridge.

[0179] Furthermore, resin sealing is performed to cover the die electrode, wiring layer, and integrated circuit chip (Fig. 61), and the integrated circuit chip is exposed by grinding or the like (Fig. 62).

[0180] The next step will be described with reference to Fig. 62. In Fig. 61, the underside of the integrated circuit chip is covered with resin 940. The underside of the integrated circuit chip and the resin 940 on the underside are ground away. As a result, the underside of the integrated circuit chip is exposed, as shown in Fig. 62.

[0181] The next step will be described with reference to Figure 63. In this step, a via opening 950 is formed in the resin 940 in which the integrated circuit chip is embedded. For example, the opening 950 may be formed in the resin by irradiating the resin 940 with a laser. The opening 950 may be formed so as to expose the electrode pad 809 connected to the integrated circuit chip. Furthermore, the via opening 950 may be formed so that its diameter increases downward from the electrode pad 809.

[0182] The next step will be described with reference to Figure 64. In this step, metal is formed in the openings formed in resin 940 by, for example, plating, and solder is provided at the ends of the metal. As a result, deep vias 952 with solder 954 provided at the ends are formed in resin 940, as shown in Figure 64. Furthermore, resins 818 and 940 can be cut to separate chip-integrated modules of desired sizes.

[0183] In the sixth modification, an example in which the underside of the integrated circuit chip and the resin 940 on the underside are ground has been described, but the present invention is not limited to this. Openings 950 may be formed without grinding resin 940, and deep vias with solder provided at their ends may be formed therein. This may result in the fabrication of the chip-integrated module described in the third modification.

[0184] (Seventh Modification) A method for manufacturing a chip integrated module according to the seventh modified example will be described with reference to Figures 65 and 66. In the seventh modified example, first, as described with reference to Figures 55 to 58, a preform 84E is fabricated.

[0185] The next step will be described with reference to Figure 65. In this step, tor pillars 962 are formed on electrode pads 809 embedded in resin 818, and a bridge is bonded to the connection portion. The bridge according to the seventh modification has a wiring layer 964 and an integrated circuit chip 966. The wiring layer 964 has wiring, and bridge electrodes provided on the surface of this wiring are connected to, for example, pillar-shaped connection portions 806, 808, thereby functioning as a bridge.

[0186] Furthermore, the formed tor pillars and the bridges connected to the columnar connections are covered with resin encapsulation (Figure 64).The tor pillars and bridges are then exposed by grinding or other methods (Figure 65).

[0187] The next step will be described with reference to Figure 66. In this step, the resin 960 that seals the tor pillars and bridges, the tor pillars, and the integrated circuit chip are ground away. As a result, the surfaces of the tor pillars and the integrated circuit chip are exposed on the surface of the resin 960, as shown in Figure 66. Furthermore, by cutting the resins 818 and 960, a chip-integrated module of the desired size can be fabricated.

[0188] (Eighth Modification) A method for manufacturing a chip integrated module according to the eighth modified example will be described with reference to Figures 67 to 69. In the eighth modified example, first, as described with reference to Figures 55 to 58, an intermediate body 84E is prepared.

[0189] The next step will be described with reference to Fig. 67. In this step, a bridge is bonded to the connection portion embedded in resin 818. The bridge according to the eighth modification has a wiring layer 986 and an integrated circuit chip 988. The wiring layer 986 has wiring. A bridge electrode provided on the surface of this wiring is connected to the columnar connection portions 806, 808, so that the bridge electrode and the wiring layer 986 function as a bridge.

[0190] Furthermore, resin sealing is applied to cover the wiring layer 986 and the bridge electrodes formed on the wiring layer 986. As a result, as shown in FIG. The bridge is connected to the post-shaped connection part while being fixed by the

[0191] The next step will be described with reference to Figure 68. In this step, integrated circuit chip 988 is removed from wiring layer 986. Furthermore, by cutting resin 818, a chip integrated module of a desired size can be fabricated.

[0192] With reference to FIG. 69 , the step of removing the integrated circuit chip 988 from the wiring layer 986 will be described in detail. In the eighth modification, a peeling layer 996 is provided between the integrated circuit chip 988 and the insulating layer 994 of the wiring layer. By irradiating this peeling layer 996 with energetic particles 981 (such as laser light), it is possible to decompose (transform) at least a portion of the peeling layer 996. By moving the area to be irradiated with the energetic particles in the scanning direction indicated by the arrow, it is possible to decompose the peeling layer 996 entirely. This allows the integrated circuit chip 988 to be removed from the insulating layer 994.

[0193] Here, an example has been described in which the peeling layer 996 is decomposed by scanning the area to be irradiated with energetic particles, but this is not limited to this, and the entire peeling layer 996 may be irradiated with energetic particles at once without scanning.

[0194] <Optical module manufacturing method> A method for manufacturing an optical module according to one embodiment of the present invention will be described with reference to FIGS.

[0195] First, a support 850 having a release layer 852 formed on its surface is prepared. Next, as shown in FIG. 70 , a wiring layer 860 is formed on the surface of the release layer 852. This wiring layer 860 may have a two-layer structure, and more specifically, may have substantially the same configuration as the wiring layer 630 described with reference to FIG. 5 . In this embodiment, a plurality of conductor vias are formed in the upper layer of the wiring layer 630, and an electrode is coupled to each conductor via. For example, an electrode 862 to which a conductor post is connected is coupled to the conductor via 861, and an electrode 864 to which a light element driver chip is connected is coupled to the conductor via 863.

[0196] 71 , the conductor post 870 and the light element driving chip 880 are bonded to the electrodes. For example, the conductor post 870 is bonded to the electrode 862. The light element driving chip 880 also has a plurality of electrode terminals 874. The electrode terminals 874 are connected to the electrodes 872 formed on the surface of the wiring layer 860 via solder 782.

[0197] 72, the plurality of conductor posts 870 and the optical element driving chip 880 are sealed with resin 882. In this way, the plurality of conductor posts 870 and the optical element driving chip 880 are fixed in place.

[0198] Next, the release layer 852 and the support 850 are removed, and a process is performed to remove the release layer 852 remaining on the lower surface of the wiring layer 860. Furthermore, the upper surface of the resin 882 is ground, and a metal layer 884 is formed on the upper surface of the optical element driving chip 880, as shown in FIG.

[0199] 74 , the entire structure is turned upside down so that the metal layer 884 faces downward, and an optical element chip 890 is bonded to the upper surface of the wiring layer 860. The optical element chip 890 is provided with a light emitting element 892, a light receiving element 894, and a plurality of electrode terminals 896. The optical element chip 890 is bonded to the wiring layer 860 by bonding each of the plurality of electrode terminals 896 to the electrodes 866 of the wiring layer 860 via solder 868. Furthermore, the underside of the optical element chip 890, the light emitting element 892, the light receiving element 894, and the plurality of electrode terminals 896 are sealed with resin 898. In this way, an optical module 89 is produced.

[0200] <Modification of the manufacturing method of the chip-integrated body> A method for manufacturing a chip-integrated structure according to another embodiment will be described with reference to FIGS.

[0201] 75, a support 900 is prepared, on the surface of which a release layer 902 is formed, and various conductors are formed on the surface of the release layer 902. Specifically, electrodes 906 to which conductor posts are connected and columnar connection parts 908 (tall pillars) to which chip integrated modules are connected are formed.

[0202] Next, as shown in Fig. 76, various components are formed on the various conductors formed on the release layer 902. For example, conductor posts 907 may be formed on the electrodes 906, or a chip-integrated module 909 may be connected to the columnar connecting portions 908. The chip-integrated module 909 may be connected to the columnar connecting portions 908 by solder provided on the columnar connecting portions 908. If the bridge thickness of the chip-integrated module is sufficiently thin, the columnar connecting portions 908 may be replaced by solder bumps, which have a lower height.

[0203] 77, the various formed components are sealed with resin. Specifically, the conductor posts 907, the columnar connectors 908, and the chip-integrated module 909 may be sealed with resin 914. Thereafter, the support 900 is removed from the wiring layer 904 together with the release layer 902. Furthermore, the resin 914 is ground so that the conductor posts 907 and the chip-integrated module 909 are exposed.

[0204] 78, a wiring layer 912 is formed on the resin 914. More specifically, the wiring layer 912 is formed on the resin 914 so that the wiring included in the wiring layer 912 is connected to the exposed portion of the conductor post 907 or the exposed portion of the chip integrated module 909. For example, the electrode 916 formed on the wiring layer 912 may be connected to the conductor post 907 through a conductor via. Furthermore, the contact metal 918 may be connected to the chip integrated module 909 through a conductor via.

[0205] 79, a heat dissipation mechanism 922 is mounted on the contact metal 918. Furthermore, an optical module 917, to which optical wiring 920 is connected, is connected to the electrode 916. In this way, a chip-integrated structure according to this embodiment is fabricated.

[0206] Integrated circuit chip 80 is a diagram showing an example of the configuration of an integrated circuit chip according to one embodiment. The integrated circuit chip 35 includes a wiring layer 350, a transistor 370, and a connection layer 390 that connects the wiring layer 350 and the transistor 370.

[0207] The wiring layer 350 has a five-layer stacked structure, and each layer has a film that insulates the layers, wiring embedded in the film, and vias that connect the wiring of adjacent layers above and below. For example, wiring 352 of the second layer and wiring 354 of the third layer are connected through via 353, and wiring 354 is embedded in an insulating film 356. The films of each layer may be made of, for example, boron-phosphorous silicate glass (BPSG). The wiring of each layer may be made of, for example, a metal such as copper. Note that the wiring of the upper layers (for example, the fifth and fourth layers) serves as a power source or ground, so it does not need to be finer than the wiring of the other layers.

[0208] Although several representative embodiments have been described above using the drawings, there are various other variations of the above-described embodiments and variations. Parts of the embodiments can be modified as appropriate within the scope of the above-described explanation. Furthermore, for example, parts of the above-described embodiments and variations can be combined with parts of other embodiments.

[0209] In the above-described embodiments, examples in which the various columnar connection portions extend in a direction substantially perpendicular to the surface of the die have been described. However, the various columnar connection portions may be formed to extend in any direction as long as they extend in a direction toward other dies. Furthermore, the various dimensions, cross-sectional shape, aspect ratio (the ratio of the dimension in the cross-sectional direction to the dimension perpendicular thereto), etc. of the columnar connection portions can be appropriately set depending on requirements such as performance and reliability, available manufacturing processes, etc.

[0210] In the above embodiment, when the bridge includes a chip, the bridge mainly includes wiring, and the chip is connected to the bridge electrode via this wiring. However, the bridge does not have to include wiring, and the chip may be directly connected to the bridge electrode. In the above embodiments, examples have been described in which various dies (for example, the first die and the second die) include wiring. However, this is not limiting, and the die may not include wiring. In this case, the integrated circuit chip included in the die may be directly connected to the die electrode.

[0211] In the above embodiment, a thin film wiring layer formed on the support 900 is used as the wiring 904, but the wiring 904 is not limited to this, and various known interposers and wiring substrates can also be used. [Industrial Applicability]

[0212] The present invention is widely applicable to semiconductor modules and the like.

Claims

1. a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip; a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip; a bridge having a first bridge electrode electrically connected to the first die electrode, a second bridge electrode electrically connected to the second die electrode, and a wiring layer; an encapsulant that encapsulates at least a portion of the bridge and has a first surface facing the first IC chip and the second IC chip and a second surface opposite to the first surface; an external electrode formed on the second surface of the sealing body; Equipped with the wiring layer of the bridge includes a first wiring electrically connected to the first bridge electrode or the second bridge electrode, and a plurality of insulating layers sealing the first wiring; a portion of the first bridge electrode and a portion of the second bridge electrode are exposed from the first surface of the sealing body; the wiring layer has a third surface to which the first bridge electrode and the second bridge electrode are connected, and a fourth surface opposite to the third surface; the first wiring and the external electrode are electrically connected through a via formed on the fourth surface of the wiring layer.

2. In claim 1, the wiring layer of the bridge further includes a second wiring that electrically connects the first bridge electrode and the second bridge electrode; The second wiring is sealed in the plurality of insulating layers.

Images