Uniformity control circuit for an impedance matching network

Abstract

To correct uniformity in a processing speed of a substrate when the substrate is processed in a plasma chamber.SOLUTION: An impedance matching box housing is described. The impedance matching box housing includes an impedance matching circuit having an input coupled to a radio frequency (RF) generator. The impedance matching circuit has an output coupled to the first RF strap. The match network housing includes a uniformity control circuit coupled in parallel with a portion of the first RF strap to modify uniformity in a processing rate of the substrate when the substrate is processed in the plasma chamber.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present embodiment relates to a system and method for using a uniformity control circuit at the output of an impedance matching box. [Background technology]

[0002] Plasma tools are used to process multiple wafers. Each wafer is placed in a plasma chamber. A radio frequency (RF) signal is applied to the plasma chamber to generate a plasma within the plasma chamber. The plasma is then used to process the wafers.

[0003] During wafer processing, some features etch more than others, i.e., some features etch faster than others. Without precise etching across the entire top surface of each wafer, the surface topography of each wafer will vary significantly, making fabrication of additional layers substantially more difficult.

[0004] It is within this context that the embodiments described in this disclosure arise.

[0005] The background discussion provided herein is intended to provide a general background to the present disclosure. Work by the inventors named herein, to the extent described in this Background section, as well as aspects of the description that may not be considered prior art at the time of filing, are not admitted expressly or implicitly as prior art against the present disclosure. Summary of the Invention

[0006]

[0010] Embodiments of the present disclosure provide a system, an apparatus, a method, and a computer program for using a uniformity control circuit at the output of an impedance matching box. It should be understood that the embodiments can be implemented in numerous ways, such as a process on a computer-readable medium, an apparatus, a system, a device, or a method. Some embodiments are described below.

[0007] In one embodiment, an impedance matcher housing is described. The impedance matcher housing includes an impedance matching circuit having an input coupled to a radio frequency (RF) generator. The impedance matching circuit has an output coupled to a first RF strap. The impedance matcher housing includes a uniformity control circuit coupled in parallel with a portion of the first RF strap to modify uniformity in processing rates of substrates when the substrates are processed in a plasma chamber.

[0008] In one embodiment, a uniformity control circuit is described. The uniformity control circuit includes a first RF strap, a second RF strap coupled to the first RF strap, and a capacitor coupled to the second RF strap. The uniformity control circuit also includes a third RF strap coupled to the capacitor and the first RF strap. The first RF strap is coupled between an output of an impedance matching circuit and an RF transmission line coupled to a plasma chamber.

[0009] Some advantages of the systems and methods described herein that use a uniformity control circuit on the output of the impedance matching circuit include achieving uniformity across the entire top surface of the substrate. The uniformity control circuit is coupled to the output of the impedance matching circuit. The uniformity is achieved by modifying the capacitance of the uniformity control circuit. For example, the uniformity control circuit includes a variable capacitor, and the capacitance of the variable capacitor is changed. As another example, the uniformity control circuit includes a fixed capacitor, and the fixed capacitor is replaced with another fixed capacitor to achieve uniformity. Achieving uniformity results in a uniform topography across the entire top surface of the substrate. As a result, additional layers fabricated on the top surface can also be uniform.

[0010] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] The embodiments may be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0012] [Figure 1A] FIG. 1A is a diagram of one embodiment of a top view of a system illustrating multiple plasma tools consuming a greater amount of floor space than is consumed by other plasma tools described herein with reference to FIG. 1B.

[0013] [Figure 1B] FIG. 1B is a diagram of one embodiment of a system to illustrate multiple plasma tools that consumes a smaller amount of floor space than the plasma tool of FIG. 1A.

[0014] [Figure 2] FIG. 2 is a diagram of one embodiment of a system to illustrate stackable arrangements of components of a plasma tool (such as any of the plasma tools of FIG. 1B).

[0015] [Figure 3] FIG. 3 is a diagram of one embodiment of a system to illustrate the use of a uniformity control circuit.

[0016] [Figure 4A] FIG. 4A is a diagram of one embodiment of a system illustrating a uniformity control circuit located within the housing of the impedance matching circuit.

[0017] [Figure 4B] FIG. 4B is one embodiment of a system for illustrating the operation of the uniformity control circuit of FIG. 4A.

[0018] [Figure 4C] FIG. 4C is a diagram of one embodiment of a system illustrating a uniformity control circuit coupled to an RF transmission line and located external to the housing.

[0019] [Figure 5A]FIG. 5A is a diagram of one embodiment of a system to explain details of the uniformity control circuit of FIG. 4A.

[0020] [Figure 5B] FIG. 5B is a diagram of one embodiment of a system to illustrate the control of the variable capacitor of the uniformity control circuit.

[0021] [Figure 5C] FIG. 5C is a diagram of one embodiment of a system used to control a variable capacitor to illustrate an in-situ method for achieving a predetermined uniformity in processing rate across the top surface of a substrate.

[0022] [Figure 5D] FIG. 5D is a diagram of one embodiment of a system used to control a variable capacitor to illustrate an ex situ method for achieving a predetermined uniformity in processing rate across the top surface of a substrate.

[0023] [Figure 6] FIG. 6 is a diagram of one embodiment of an impedance matching circuit to illustrate the coupling of the uniformity control circuit and the impedance matching circuit of FIG. 4A.

[0024] [Figure 7] FIG. 7 is one embodiment of a graph illustrating the change in uniformity in etch rate with a change in capacitance of a variable capacitor or a change in capacitance of a fixed capacitor.

[0025] [Figure 8] FIG. 8 is one embodiment of a graph illustrating the change in uniformity in etch rate with a change in capacitance of a variable capacitor or a change in capacitance of a fixed capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0026] The following embodiments describe systems and methods for using a uniformity control circuit at the output of an impedance matching box. It will be understood that the embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0027] 1A is a diagram of one embodiment of a top view of a system 100 to illustrate multiple plasma tools that consume a greater amount of floor space than is consumed by other plasma tools described herein with reference to FIG. 1B. System 100 includes multiple plasma tools 102A, 102B, 102C, 102D, 102E, 102F, 102G, and 102H.

[0028] Each plasma tool described herein has a length, width, and depth. For example, plasma tool 102A has width 105A, and plasma tool 102B has width 105B. Width 105A is measured along the x-axis. Plasma tool 102A has depth 107A measured along the z-axis. Plasma tools 102A-102H are positioned on floor 104 of the manufacturing facility and form an octagonal arrangement that occupies more of the floor 104 area than the plasma tools described below with reference to FIG. 1B. Each plasma tool 102A-102H has the same dimensions (e.g., width, depth, and height) as any other of plasma tools 102A-102H.

[0029] Note that there is a space between any two adjacent ones of plasma tools 102A-102H. For example, side 103A of plasma tool 102A and side 103B of plasma tool 102B are not adjacent, and there is a space between the two sides 103A and 103B, forming an acute angle between the sides 103A and 103B. The space is large enough for a person to enter the space to open plasma tool 102A or 102B.

[0030] In embodiments, the terms floor area and footprint are used interchangeably herein.

[0031] 1B is a diagram of one embodiment of a system 110 illustrating multiple plasma tools that consume a smaller amount of floor space than that consumed by plasma tools 102A-102H (FIG. 1A). System 110 includes multiple plasma tools 110A, 110B, 110C, 110D, 110E, 110F, 110G, and 110H. Each of plasma tools 110A-110H has the same dimensions (e.g., width, depth, and height).

[0032] Plasma tool 110A has a width 113A, and plasma tool 110B has a width 113B. Width 113A is measured along the z-axis. Plasma tool 110A also has a depth 115A. Depth 115A is smaller than depth 107A of plasma tool 102A (FIG. 1A). Depth 115A is measured along the x-axis.

[0033] Plasma tools 110A-110H are positioned on floor 104 to form a rectangular arrangement that occupies less area than the area occupied by the octagonal arrangement described above with reference to FIG. 1A. For example, the space between any two adjacent plasma tools 110A-110H is inaccessible. As another example, side 111A of plasma tool 110A is adjacent to side 111B of plasma tool 110B such that there is negligible or no space between sides 111A and 111B. As yet another example, depth 115A is less than depth 107A, and width 113A is less than width 105A.

[0034] In an embodiment, instead of eight plasma tools, any other number of tools can be placed on floor 104, such as four, five, or six.

[0035] In one embodiment, the depth of the plasma tool 110A is greater than the depth of the plasma tool 102A. In one embodiment, the width of the plasma tool 110A is greater than the width of the plasma tool 102A.

[0036] 2 is a diagram of one embodiment of a system 200 to illustrate a stackable arrangement of components of a plasma tool (such as any of plasma tools 110A-110H of FIG. 1B). System 200 includes a system 202 and an impedance matching circuit system (IMCS) 203. System 200 is an example of any of plasma tools 110A-110H (FIG. 1B).

[0037] The IMCS 203 is a housing structure including a housing 211. Examples of the housing or housing structure used herein include a compartment, enclosure, box, container, etc. For example, the housing 211 is made of a metal such as aluminum, an aluminum alloy, steel, a steel alloy, or an aluminum-steel alloy. The housing 211 encloses an impedance matching circuit (IMC) 204. The IMCS 203 further includes a tunable edge sheath (TES) matcher housing 205, a chuck power supply (PS) and filter housing 207, and a set of electrostatic chuck gas supply components 209. Examples of the housing used herein include a compartment, housing, box, container, etc. The chuck PS and filter housing 207 includes a chuck power supply that provides direct current (DC) power to the chuck. The chuck PS and filter housing 207 further includes a filter that filters radio frequency (RF) power from coupling to the DC power to reduce the chance of RF power interfering with the DC power. The TES matcher housing 205 includes a TES matcher coupled to a tunable edge ring surrounding the chuck. The TES matcher includes electrical components, such as one or more inductors, one or more resistors, or one or more capacitors, or a combination thereof, that are coupled to one another. The electrical components of the TES matcher have an impedance that provides a match between the impedance of a load, such as a tunable edge ring, coupled to the output of the TES matcher and a source coupled to the input of the TES matcher. An example of a source coupled to the input of the TES matcher is an RF generator and an RF cable that couples the RF generator to the input of the TES matcher.

[0038] The housing 211 has a top 211A and a bottom 211B. The top 211A has an elongated shape. For example, the top 211A is substantially narrower than the bottom 211B to facilitate fitting the TES matcher housing 205 into the IMCS 203. Furthermore, the elongated shape of the top 211A allows the chuck PS / filter housing 207 and the TES matcher housing 205 to fit into the IMCS 203. The TES matcher housing 205 is located above the bottom 211B, and the chuck PS / filter housing 207 is located above the TES matcher housing 205. The set 209 is located next to the housing 211 of the IMC 204, opposite the side where the TES matcher housing 205 is located.

[0039] The set 209 includes a plurality of conduits, such as helium channels, for passing a cooling gas to control the temperature of a chuck of the plasma chamber. The conduits extend to the chuck to cool different areas within the gap between the upper electrode of the plasma chamber and the chuck. The temperature is controlled by increasing or decreasing the flow rate of the cooling gas to the chuck. For example, increasing the flow rate of the cooling gas to the chuck increases the temperature, and decreasing the flow rate of the cooling gas to the chuck decreases the temperature. An example of a cooling gas is helium, and an example of a chuck is an electrostatic chuck (ESC).

[0040] Additionally, the area adjacent to set 209 includes a gap driver including a set of motors and electronic boards to control (e.g., increase or decrease) the gap amount between the chuck and the upper electrode of the plasma chamber. The area adjacent to set 209 is within and forms part of IMCS 203. Set 209 further includes sensors, such as complex current and voltage sensors, voltage sensors, and power sensors, for sensing variables at the output of IMC 204 or the input of IMC 204. Examples of variables include complex voltage and current, impedance, voltage, power, voltage, current, reflected power, supplied power, etc.

[0041] In one embodiment, a dielectric ring is located between the chuck and the tunable edge ring.

[0042] System 202 includes a low-frequency (LF) RF generator and a high-frequency RF generator and is located above IMCS 203. An example of a low-frequency RF generator is an RF generator having a low frequency of operation of 400 kilohertz (kHz), and examples of high-frequency RF generators are RF generators having high frequencies of operation of 13.56 megahertz (MHz), 27 MHz, or 60 MHz. Another example of a low-frequency RF generator is an RF generator having a low frequency of operation of 2 MHz. Yet another example of a low-frequency RF generator is an RF generator having a low frequency of operation of 100 kHz. System 202 is located on top of IMCS 203 to conserve area on floor 104 (FIGS. 1A and 1B).

[0043] The housing 211 of the IMC 204 has a bottom wall 206B. A low-frequency RF generator of the system 202 is connected to the circuit components of the impedance matching circuit 204 through an opening in the bottom wall 206B. For example, the low-frequency RF generator is coupled to the circuit components of the impedance matching circuit 204 via an RF cable 208A that passes through the opening in the bottom wall 206B. Similarly, a high-frequency RF generator of the system 202 is connected to the circuit components of the impedance matching circuit 204 through an opening in the bottom wall 206B. For example, the low-frequency RF generator is coupled to the circuit components of the impedance matching circuit 204 via an RF cable 208B that passes through the opening in the bottom wall 206B.

[0044] In embodiments, the terms impedance matching circuit, impedance matching network, matcher, impedance matcher, matching network, matcher circuit, and matcher network are used interchangeably herein.

[0045] In one embodiment, system 202 is placed above IMCS 203 rather than on top of IMCS 203. For example, a carrier, such as a network of support rods, is provided above IMCS 203 and system 202 is supported by the carrier.

[0046] In one embodiment, the system 202 is located within the IMCS 203 .

[0047] In one embodiment, the terms substrate support, chuck, and powered electrode as used herein are interchangeable.

[0048] 3 is a diagram of one embodiment of a system 300 to illustrate the use of a uniformity control circuit 338. The system 300 includes a host computer 318, a low frequency RF generator (LF RFG), a high frequency RF generator (HF RFG), RF cables 208A and 208B, a housing 211, an RF transmission line 302, a plasma chamber 304, and a uniformity control circuit 338. The system 300 further includes another RF generator, such as a TES RF generator. The system 300 also includes an RF cable 311, a TES matcher housing 205, and an RF transmission line 317.

[0049] One example of the uniformity control circuit 338 includes a capacitor, such as a fixed capacitor or a variable capacitor. Another example of the uniformity control circuit 338 includes a plurality of capacitors. For example, the uniformity control circuit 338 includes two or more capacitors coupled in series. For another example, the uniformity control circuit 338 includes two or more capacitors coupled in parallel. For yet another example, the uniformity control circuit 338 includes a first group of capacitors coupled in series and a second group of capacitors coupled in parallel, with the first group coupled in series with the second group.

[0050] The TES RF generator can be a low frequency or high frequency RF generator. For example, the TES RF generator can have a low frequency or a high frequency, examples of which are described above. The TES matcher is located within the TES matcher housing 205.

[0051] RF transmission line 302 includes an RF rod and an RF tunnel. The RF rod is surrounded by the insulator material of RF transmission line 302, and the insulator material is surrounded by the RF tunnel of RF transmission line 302. Similarly, RF transmission line 317 includes an RF rod and an RF tunnel surrounding the RF rod. Also, the insulator material of RF transmission line 317 surrounds the RF rod of RF transmission line 317, and the RF tunnel of RF transmission line 317 surrounds the insulator material of RF transmission line 317.

[0052] The plasma chamber 304 includes a substrate support 306 and an upper electrode 308. An example of the substrate support 306 is a chuck, which includes a lower electrode. The lower electrode is made of a metal, such as aluminum or an aluminum alloy. The substrate support 306 is made of a metal and a ceramic, such as aluminum oxide (Al2O3). The upper electrode 308 is fabricated from silicon and is coupled to a ground connection. The plasma chamber 304 further includes a TES ring 307 surrounding the substrate support 306. The TES ring 307 is made of one or more materials, such as crystalline silicon, polycrystalline silicon, silicon carbide, quartz, aluminum oxide, aluminum nitride, silicon nitride, etc. The TES ring 307 performs many functions, such as positioning the substrate S on the substrate support 306 and shielding underlying components of the plasma chamber 304, such as the coupling ring, that are not shielded by the substrate S from being damaged by ions from the plasma formed in the plasma chamber 304. The TES ring 307 also confines the plasma to the region above the substrate S and protects the substrate support 306 from erosion by the plasma.

[0053] The host computer 318 includes a processor 320 and a memory device 322. The processor 320 is coupled to the memory device 322. By way of example, the processor may be a controller, or an application specific integrated circuit (ASIC), or a programmable logic device (PLD), or a central processing unit (CPU), or a microcontroller, or a microprocessor, and these terms are used interchangeably herein. Examples of memory devices used herein include random access memory (RAM), read-only memory (ROM), and combinations thereof.

[0054] Processor 320 is coupled to the LF RF generator via transfer cable 324, to the HF RF generator via transfer cable 326, and to the TES RF generator via another transfer cable 328. Examples of transfer cables as used herein include cables that transfer data in a serial manner, or cables that transfer data in a parallel manner, or cables that transfer data using the Universal Serial Bus (USB) protocol.

[0055] An output O1 of the LF RF generator is coupled to a first branch circuit of the impedance matching circuit 204 in the housing 211 via an input I1 of the RF cable 208A and the housing 211, and an output O2 of the HF RF generator is coupled to a second branch circuit of the impedance matching circuit 204 via an input I2 of the RF cable 208B and the housing 211. An example of the input I1 is a connection, such as a soldered or welded connection, between the RF cable 208A and the first branch circuit. An example of the input I2 is a connection, such as a soldered or welded connection, between the RF cable 208B and the second branch circuit. The input I1 of the housing 211 is also an input to the first branch circuit of the impedance matching circuit 204. The input I2 of the housing 211 is also an input to the second branch circuit of the impedance matching circuit 204.

[0056] The first and second branches of the impedance matching circuit 204 are coupled to an output O4 of the impedance matching circuit 204. The output O4 of the impedance matching circuit 204 is coupled to an input 13 of the uniformity control circuit 338. An example of the output O4 is a connection, such as a weld, between the first branch and the second branch. The housing 211 and the output O3 of the uniformity control circuit 338 are coupled to the lower electrode of the substrate support 306 via an RF rod of the RF transmission line 302. For example, the output O3 of the uniformity control circuit 338 is coupled to an RF rod of the RF transmission line 302 via a connector. Examples of connectors are provided herein.

[0057] The TES RF generator is coupled to the input of the TES matcher enclosure 205 via RF cable 311. The output of the TES matcher enclosure 205 is coupled to the TES ring 307 via RF transmission line 317.

[0058] The processor 320 generates a recipe signal 330 and transmits the recipe signal 330 to the LF RF generator via the transfer cable 324. As an example, the recipe signal transmitted to the RF generator includes recipe information regarding one or more power levels of the RF signal generated by the RF generator and one or more frequency levels of the RF signal. The recipe information further includes a duty cycle for each power level and each frequency level. As an example, the power level includes one or more power values, one or more power values ​​at a power level, or one or more power values ​​at another power level, exclusively. For example, the minimum value of the multiple values ​​of the first power level is greater than the maximum value of the multiple values ​​of the second power level. The first power level is greater than the second power level. Upon receiving the recipe signal 330, the LF RF generator stores the recipe information received in the recipe signal 330 in one or more memory devices of the LF RF generator.

[0059] Similarly, processor 320 generates recipe signal 332 and sends recipe signal 332 to the HF RF generator via transfer cable 326. Upon receiving recipe signal 332, the HF RF generator stores the recipe information received in recipe signal 332 in one or more memory devices of the HF RF generator.

[0060] Processor 320 also generates recipe signal 334 and transmits recipe signal 334 to the TES RF generator via transfer cable 328. Upon receiving recipe signal 334, the TES RF generator stores the recipe information received in recipe signal 334 in one or more memory devices of the TES RF generator.

[0061] Additionally, processor 320 generates trigger signal 336 and sends trigger signal 336 to the LF RF generator via transmission cable 324. Processor 320 also sends trigger signal 336 to the HF RF generator via transmission cable 326 and to the TES RF generator via transmission cable 328.

[0062] Upon receiving trigger signal 336, the LF RF generator generates a low frequency RF signal 304A based on the recipe information received in recipe signal 330 and sends the low frequency RF signal 304A via RF cable 208A to input I1 of impedance matching circuit 204. Similarly, in response to receiving trigger signal 336, the HF RF generator generates a high frequency RF signal 304B based on the recipe information received in recipe signal 332 and sends the high frequency RF signal 304B via RF cable 208B to input I2 of impedance matching circuit 204.

[0063] A first branch of the impedance matching circuit 204 receives a low frequency RF signal 304A from the input I1, modifies the impedance of the low frequency RF signal 304A to match the impedance of a load coupled to the output O4 with the impedance of a source coupled to the input I1, and outputs a first modified RF signal. Examples of loads coupled to the output O4 include the plasma chamber 304, the RF transmission line 302, and the uniformity control circuit 338. Examples of sources coupled to the input I1 include an LF RF generator and an RF cable 208A.

[0064] Similarly, a second branch of impedance matching circuit 204 receives high frequency RF signal 304B from input 12, modifies the impedance of high frequency RF signal 304B to match the impedance of a load coupled to output 04 with the impedance of a source coupled to input 12, and outputs a second modified RF signal. The first and second modified RF signals are combined, such as by being added at output 04, by impedance matching circuit 204 to output combined RF signal 312 at output 04. Examples of sources coupled to input 12 include an HF RF generator and RF cable 208B.

[0065] The composite RF signal 312 is provided from output O4 to input I3 of a uniformity control circuit 338. The uniformity control circuit 338 modifies the impedance of the composite RF signal 312 to achieve uniformity in the processing rate of the substrate S and outputs a modified RF signal 340 at output O3. For example, the uniformity control circuit 338 is a resonant circuit provided at output O4. Illustratively, the reactance of the uniformity control circuit 338 is adjusted to achieve uniformity in the processing rate of the substrate S. The modified RF signal 340 is provided from output O3 through RF transmission line 302 to a lower electrode of the plasma chamber 304 to strike or maintain a plasma in the plasma chamber. For example, in conjunction with the provision of the modified RF signal 340, a plasma is struck or maintained in the plasma chamber 304 when one or more process gases, such as an oxygen-containing gas or a fluorine-containing gas, are provided into a gap between the upper electrode 308 and the substrate support 306.

[0066] Furthermore, upon receiving the trigger signal 336, the TES RFG generates an RF signal 313 based on the recipe information received in the recipe signal 334 and sends the RF signal 313 to the input of the TES matcher housing 205 via the RF cable 311. Upon receiving the RF signal 313, the TES matcher in the TES matcher housing 205 matches the impedance of a load coupled to the output of the TES matcher housing 205 and a source coupled to the input of the TES matcher housing 205, and outputs a modified RF signal 315 to the output of the TES matcher housing 205. Examples of sources coupled to the input of the TES matcher housing 205 include the TES RFG and the RF cable 311, and examples of loads coupled to the output of the TES matcher housing 205 include the TES ring 307 and the RF transmission line 317. The TES ring 307 receives the modified RF signal 315 to process the edge region of the substrate S.

[0067] In one embodiment, the coupling ring is located below the TES ring 307 and surrounds the substrate support 306. The coupling ring is made from an electrical insulator material, such as a dielectric material, ceramic, glass, composite polymer, aluminum oxide, or the like.

[0068] In embodiments, the terms TES ring and tunable edge ring are used interchangeably herein.

[0069] FIG. 4A is a diagram of one embodiment of a system 400 to illustrate a uniformity control circuit 402. The system 400 includes an LF RF generator, an HF RF generator, a housing 211, and a plasma chamber 304. The housing 211 includes a uniformity control circuit 339, which is an example of the uniformity control circuit 338 (FIG. 3). The output O4 is coupled to the output O3 via an RF strap 402. As an example, the RF strap is a flat, elongated metal strap. For example, the RF strap is made of copper or a copper alloy, and the length of the RF strap is greater than its width and depth. As another example, the RF strap is not an RF coil, such as an induction coil having one or more turns.

[0070] The uniformity control circuit 339 includes a capacitor Cx and a portion 443 of the RF strap 402. As an example, the capacitance value of the capacitor Cx is in the range of 3 picofarads (pF) to 200 pF. The capacitor Cx is a fixed capacitor and is coupled in parallel to the portion 403 of the RF strap 402. For example, an end 404 of the capacitor Cx is coupled to a point 422 of the RF strap 402, and an opposite end 406 of the capacitor Cx is coupled to a point 424 of the RF strap 402. For example, the end 404 is coupled to the point 422 via a connector, and the end 406 is coupled to the end 424 via a connector. The end 422 is coupled to the output O4, and the end 424 is coupled to the output O3. Furthermore, neither the ends 404 nor the end 406 of the capacitor Cx are coupled to ground potential. The portion 403 is located between the points 422 and 424.

[0071] In one embodiment, two or more RF straps are used instead of RF strap 402. For example, the two or more RF straps include a first RF strap and a second RF strap. The first RF strap is coupled in series to the second RF strap via a connector, an example of which is described below. In this example, point 422 is located on the first RF strap and point 424 is located on the second RF strap.

[0072] FIG. 4B illustrates one embodiment of a system 420 for explaining the operation of the uniformity control circuit 339. The RF strap 402 extends from an end E1 of the RF strap 402 to an opposite end E2 of the RF strap 402. End E1 is an example of an input I3 (FIG. 3) of the uniformity control circuit 338. End E1 is coupled to an output O4 via a connector. End E2 is also coupled to an output O3 via a connector. An example of a connector includes one or more screws. Another example of a connector includes one or more screws and one or more nuts for fastening two components together.

[0073] The uniformity control circuit 339 also includes another RF strap 432 that extends from an end E3 of the RF strap 432 to an opposite end E4 of the RF strap 432. End E3 is coupled to point 422 via one or more connectors, such as screws. End E4 is coupled to end 404 of the variable capacitor Cx via a connector.

[0074] The uniformity control circuit 339 further includes another RF strap 434 that extends from an end E5 of the RF strap 434 to an opposite end E6 of the RF strap 434. End E6 is coupled via a connector to point 424. End E5 is coupled via a connector to end 406 of the variable capacitor Cx.

[0075] The composite RF signal 312 is split at point 422 into a composite RF signal 426 and another composite RF signal 428. Point 422 on RF strap 402 is coupled to output O4 and end 404 of capacitor Cx. Point 422 is coupled to end 404 of capacitor Cx via RF strap 432. As composite RF signal 426 passes through RF strap 402, RF strap 402 modifies the impedance of composite RF signal 426 to output another composite RF signal 430 at point 424. Point 424 on RF strap 402 is coupled to output O3 and end 406 of capacitor Cx. Point 424 is coupled to end 406 of capacitor Cx via RF strap 434.

[0076] When combined RF signal 428 passes through RF strap 432, RF strap 432 modifies the impedance of combined RF signal 428 to output combined RF signal 436 at terminal E4. When combined RF signal 436 passes through capacitor Cx, capacitor Cx changes the impedance of combined RF signal 436 to output combined RF signal 438 at terminal 406. Combined RF signal 438 passes through RF strap 434. When combined RF signal 438 passes through RF strap 434, RF strap 434 changes the impedance of RF signal 438 to output combined RF signal 440 at terminal E6. Combined RF signal 430 is added to combined RF signal 440 at point 424 to output modified RF signal 340 at output O3.

[0077] In one embodiment, capacitor Cx is coupled in parallel to RF strap 402. For example, capacitor Cx is coupled to RF strap 432, which is coupled via a connector to end E1 of RF strap 402 rather than to point 422 on RF strap 402. Also, capacitor Cx is coupled to RF strap 434, which is coupled via a connector to end E2 of RF strap 402 rather than to point 424 on RF strap 402.

[0078] In one embodiment, end E2 of RF strap 402 is the same as output O3 of uniformity control circuit 338 (FIG. 3), and end E1 is the same as output O4 of impedance matching circuit 204. For example, end E2 is coupled to the RF rod of RF transmission line 302 via a connector.

[0079] 4C is a diagram of an embodiment of a system 450 illustrating a uniformity control circuit 341 coupled to RF transmission line 302 and located external to housing 211. System 450 includes an LF RF generator, an HF RF generator, housing 211, uniformity control circuit 341, and plasma chamber 304. Uniformity control circuit 341 is identical in structure and function to uniformity control circuit 339 (FIG. 4B), except for RF strap 402 (FIG. 4B). Uniformity control circuit 341 includes RF strap 432, capacitor Cx, RF strap 434, and RF rod portion 455 of RF transmission line 302.

[0080] The uniformity control circuit 341 is coupled between the output O3 of the housing 211 and the plasma chamber 304. For example, an end 404 of the capacitor Cx is coupled to an RF strap 432, and an end E3 of the RF strap 432 is coupled to a point 452 on the RF rod of the RF transmission line 302. For example, the end E3 is coupled to the point 452 via a connector. Also, an end 406 of the capacitor Cx is coupled to an RF strap 434, and an end E6 of the RF strap 434 is coupled to another point 454 on the RF rod of the RF transmission line 302. For example, the end E6 is coupled to the point 454 via a connector. The capacitor Cx is coupled in parallel to a portion 455 of the RF rod of the transmission line 302 between points 452 and 454.

[0081] FIG. 5A is a diagram of one embodiment of system 500 to illustrate details of uniformity control circuit 339. RF strap 402 of uniformity control circuit 339 has an internal inductance Lx. RF strap 432 has an internal inductance Ly, and RF strap 434 has an internal inductance Lz. Internal inductance Lx is a small amount. Similarly, internal inductances Ly and Lz are also small amounts. For example, internal inductance Lx is in the range of 5 nanohenries (nH) to 50 nH, internal inductance Ly is in the range of 5 nH to 20 nH, and internal inductance Lz is in the range of 5 nH to 20 nH. For a further example, internal inductances Lx, Ly, and Lz are each the same. As another example, internal inductances Lx, Ly, and Lz are different from one another.

[0082] The small amount of internal inductance Lx provides a small amount of impedance to the high frequencies of the combined RF signal 426. The small amount of internal inductance Ly provides a small amount of impedance to the high frequencies of the combined RF signal 428, and the small amount of internal inductance Lz provides a small amount of impedance to the high frequencies of the combined RF signal 438. Each combined RF signal 426, 428, and 438 has a high frequency that modifies the low frequencies of the combined RF signal. The low frequencies are those of RF signal 304A.

[0083] Similarly, each composite RF signal 312, 436, 430, and 440 has high frequencies that modify the lower frequencies of the composite RF signal, and modified RF signal 340 has high frequencies that modify the lower frequencies of modified RF signal 340.

[0084] Examples of high frequencies include MHz frequencies. By way of example, high frequencies include frequencies of 27 MHz or greater. By way of further example, high frequencies include frequencies in the range of 27 MHz to 100 MHz. As another example, high frequencies include frequencies in the range of 50 MHz to 65 MHz. A first amount of power is delivered to the lower electrode of the substrate support 306 by the modified RF signal 340 due to a small amount of impedance provided by the internal inductances Lx, Ly, and Lz. The first amount of power delivered to the lower electrode of the substrate support 306 is greater than a second amount of power delivered to the lower electrode. The second amount of power is delivered through a larger amount of impedance provided by one or more induction coils having inductances greater than the internal inductances Lx, Ly, and Lz. The high frequency is the RF signal 304B generated by the HF RF generator (FIG. 3). The high frequency is also the frequency of operation of the HF RF generator.

[0085] The capacitance C1a of the capacitor Cx corresponds to a uniformity UNFM1 in the process rate (e.g., etch rate, deposition rate, etc.) across the top surface 502 of the substrate S. The top surface 502 faces the bottom surface 504 of the upper electrode 308. The top surface 502 of the substrate S does not contact the substrate support 306 when the substrate S is placed on the substrate support 306. The top surface 502 is located opposite the bottom surface of the substrate S, which is in contact with the substrate support 306. The capacitor Cx is manually replaced by a user with another capacitor, such as a fixed capacitor, to change the capacitance of the capacitor Cx to a different capacitance C2a. The different capacitance C2a corresponds to a different uniformity in the process rate, for example, UNFM2.

[0086] In one embodiment, a primary induction coil is not used in place of RF strap 402, a secondary induction coil is not used in place of RF strap 432, and a tertiary induction coil is not used in place of RF strap 434. The primary, secondary, and tertiary induction coils provide a greater amount of inductance compared to the inductance provided by RF straps 402, 432, and 434. For example, the primary induction coil has a greater amount of inductance than the inductance of RF strap 402, the secondary induction coil has a greater amount of inductance than the inductance of RF strap 432, and the tertiary induction coil has a greater amount of inductance than the inductance of RF strap 434.

[0087] In one embodiment, a first induction coil is used in place of RF strap 402, a second induction coil is used in place of RF strap 432, and a third induction coil is used in place of RF strap 434. The first, second, and third induction coils provide the same amount of inductance as that provided by RF straps 402, 432, and 434. For example, the first induction coil has the same amount of inductance as that of RF strap 402, the second induction coil has the same amount of inductance as that of RF strap 432, and the third induction coil has the same amount of inductance as that of RF strap 434.

[0088] 5B is a diagram illustrating one embodiment of system 510 to illustrate the control of variable capacitor Cvx by uniformity control circuit 512. Uniformity control circuit 512 is identical in structure and function to uniformity control circuit 339 (FIG. 4A), except that it includes variable capacitor Cvx instead of capacitor Cx.

[0089] Uniformity control circuit 512 includes portion 403 of RF strap 402 and RF straps 432 and 434. RF strap 402 is coupled to end 514 of variable capacitor Cvx, and RF strap 434 is coupled to opposite end 516 of variable capacitor Cvx. System 510 includes motor 518, driver 520, and host computer 318. One example of motor 518 is a direct current (DC) electric motor. Another example of motor 518 is an alternating current (AC) electric motor. One example of driver 520 includes one or more transistors coupled to each other.

[0090] Processor 320 is coupled to driver 520, which is coupled to motor 518. Motor 518 is coupled to variable capacitor Cvx via connection mechanism 522. One example of connection mechanism 522 is one or more rods, or a combination of two or more rods and one or more gears, each gear connecting one rod to another rod.

[0091] The processor 320 accesses the capacitance C1a of the variable capacitor Cvx from the memory device 322 and generates a control signal representing the capacitance C1a of the variable capacitor Cvx. The capacitance C1a of the variable capacitor Cvx corresponds to the uniformity UNFM1. The processor 320 sends the control signal to the driver 520. In response to receiving the control signal, the driver 520 generates a current signal based on the control signal and sends the current signal to the motor 518. The rotor of the motor 518 rotates relative to the stator of the motor 518, operating the motor 518. When the motor 518 operates, the variable capacitor Cvx is controlled to achieve the capacitance C1a represented by the control signal sent from the processor 320 to the driver 520. For example, one plate of the variable capacitor Cvx rotates relative to the other plate of the variable capacitor Cvx, changing the area of ​​overlap between the two plates to achieve the capacitance C1a. When the variable capacitor Cvx has a capacitance C1a corresponding to uniformity UNFM1, the impedance of the composite RF signal 436 is modified, and the variable capacitor Cvx outputs the composite RF signal 438. Similarly, the processor 320 controls the variable capacitor Cvx to change the capacitance C1a to another capacitance C2a to achieve uniformity UNFM2.

[0092] 5C is a diagram of one embodiment of a system 530 to illustrate the control of variable capacitor Cvx to achieve a predetermined uniformity in processing rate across the upper surface 502 of a substrate S. System 530 is used to illustrate an in-situ method for achieving uniformity in processing rate across the upper surface 502 of a substrate S while the substrate S is being processed in the plasma chamber 304. The uniformity is achieved by controlling the capacitance of variable capacitor Cvx.

[0093] System 530 includes housing 211, host computer 318, and plasma chamber 304. Plasma chamber 304 includes multiple windows 532, 534, and 536. For example, window 532 is recessed in left side wall 538, and windows 534 and 536 are recessed in right side wall 540 of plasma chamber 304.

[0094] An etch rate measurement device (ERMD) is mounted at each window of the plasma chamber 304. For example, ERMD 542 is mounted adjacent to or fixed to window 532 so as to have a line of sight to the interior volume of the plasma chamber 304. Similarly, ERMD 544 is mounted adjacent to or fixed to window 534 so as to have a line of sight to the interior volume of the plasma chamber 304, and ERMD 546 is mounted adjacent to or fixed to window 536 so as to have a line of sight to the interior volume of the plasma chamber 304. For example, ERMD 542 is mounted above the horizontal level on which ERMDs 544 and 546 are mounted so as to have a line of sight to the central region of the substrate S. ERMD 544 is mounted adjacent to sidewall 540 so as to have a line of sight to the right edge region of the substrate S. ERMD 546 is mounted adjacent to sidewall 538 so as to have a line of sight to the left edge region of the substrate S. The left and right edge regions of the substrate S are located on opposite sides of the central region of the substrate S. An example of an ERMD is an optical emission spectrometer (OES).

[0095] ERMD 546 is coupled to processor 320 via a cable. Similarly, ERMD 542 is coupled to processor 320 via a cable, and ERMD 544 is coupled to processor 320 via a cable.

[0096] A table 533 including a correspondence between the uniformity in processing speed and the capacitance of the variable capacitor Cvx is stored in the memory device 322. For example, the table 533 includes a correspondence such as a one-to-one link, association, or mapping between the uniformity UNFM1 and the capacitance C1a. The table 533 also includes a correspondence between the uniformity UNFM2 and the capacitance C2a, and a correspondence between the uniformity UNFMn and the capacitance Cna (n is a positive integer).

[0097] 5B, the processor 320 controls the variable capacitor Cvx to achieve the capacitance C1a during processing of the substrate S. For example, during manufacturing of the substrate S, the substrate S may be cleaned, polished, etched, or have material deposited on it.

[0098] While the substrate S is being processed by the plasma generated in the plasma chamber 304, the ERMD 546 generates an electrical signal representing the intensity of light detected by the ERMD 546. The light detected by the ERMD 546 reflects back toward the ERMD 546 from the left region of the substrate S. The electrical signal output from the ERMD 546 is sent to the processor 320.

[0099] Similarly, ERMD 542 generates an electrical signal representing the intensity of light detected by ERMD 542. The light detected by ERMD 542 reflects from the central region of substrate S toward ERMD 542. The electrical signal output from ERMD 542 is sent to processor 320. ERMD 544 also generates an electrical signal representing the intensity of light detected by ERMD 544. The light detected by ERMD 544 reflects from the right region of substrate S toward ERMD 544. The electrical signal output from ERMD 544 is sent to processor 320. The electrical signals output from ERMDs 546, 542, and 544 represent the intensity of light reflected from the left, central, and right regions of substrate S.

[0100] Processor 320 receives electrical signals from ERMDs 542, 544, and 546 and determines from the electrical signals the amount of substrate S left in the left, center, and right regions at time t1. Similarly, processor 320 receives additional electrical signals from ERMDs 542, 544, and 546 and determines from the additional electrical signals the amount of substrate S left in the left, center, and right regions at time t2. The additional electrical signals received from ERMDs 542, 544, and 546 represent the intensity of light reflected from the left, center, and right regions of substrate S.

[0101] The processor 320 determines a first processing speed in the left region of the substrate as a ratio of the first difference to the second difference. The first difference is the difference between the amount of substrate S left in the left region at time t2 and the amount of substrate S left in the left region at time t1. The second difference is the difference between times t2 and t1. Similarly, the processor 320 determines a second processing speed in the central region of the substrate as a ratio of the third difference to the second difference. The third difference is the difference between the amount of substrate S left in the central region at time t2 and the amount of substrate S left in the central region at time t1. The processor 320 also determines a third processing speed in the right region of the substrate as a ratio of the fourth difference to the second difference. The fourth difference is the difference between the amount of substrate S left in the right region at time t2 and the amount of substrate S left in the right region at time t1.

[0102] The processor 320 determines the uniformity (e.g., measured uniformity) across the upper surface 502 of the substrate S for the first, second, and third processing speeds. The processor 320 accesses the uniformity UNFM1 corresponding to the capacitance C1a from the table 533 and determines whether the measured uniformity is within a predetermined range, e.g., ±0.5%, of the uniformity UNFM1. For example, the processor 320 compares the measured uniformity with the uniformity UNFM1 and determines that the measured uniformity matches the uniformity UNFM1. An example of the predetermined range is a range of measured uniformity values ​​from −0.25% of the uniformity UNFM1 to 0.25% of the uniformity UNFM1. Another example of the predetermined range is a range of measured uniformity values ​​from −0.5% of the uniformity UNFM1 to 0.5% of the uniformity UNFM1. If the processor 320 determines that the measured uniformity matches the uniformity UNFM1, the processor 320 determines that the measured uniformity is within a predetermined range from the uniformity UNFM1. On the other hand, if processor 320 determines that the measured uniformity does not match uniformity UNFM1, processor 320 determines that the measured uniformity is not within a predetermined range from uniformity UNFM1. As another example, processor 320 compares the measured uniformity with uniformity UNFM1 and determines that a predetermined number of values ​​of the measured uniformity (e.g., 70% or more, 75% or more, or 80% or more of the values) are within a predetermined range from the predetermined number of values ​​of uniformity UNFM1. If so determined, processor 320 determines that the measured uniformity is within a predetermined range from uniformity UNFM1. On the other hand, if processor 320 determines that the predetermined number of values ​​of the measured uniformity are not within a predetermined range from the predetermined number of values ​​of uniformity UNFM1, processor 320 determines that the measured uniformity is not within a predetermined range from uniformity UNFM1.

[0103] On the other hand, if the processor 320 determines that the measured uniformity is within the predetermined range from the uniformity UNFM1, the processor 320 does not further control the variable capacitor Cvx to change the capacitance C1a of the variable capacitor Cvx. On the other hand, in response to determining that the measured uniformity is not within the predetermined range from the uniformity UNFM1, the processor 320 controls the variable capacitor Cvx to change the capacitance of the variable capacitor Cvx, and again measures the uniformity in the processing rate across the upper surface 502 of the substrate S and compares it with the uniformity UNFM1. In this manner, the processor 320 continues to control the variable capacitor Cvx until the measured uniformity is within the predetermined range from the uniformity UNFM1. In this manner, the processor 320 controls the variable capacitor Cvx to achieve capacitance values ​​C2a to Cna to achieve corresponding uniformities UNFM2 to UNFMn in the processing rate across the upper surface 502 of the substrate S.

[0104] In one embodiment, the plasma chamber 304 has an annular sidewall, in this embodiment, the left sidewall 538 is the left portion of the sidewall, and the right sidewall 540 is the right portion of the sidewall.

[0105] In one embodiment, the in-situ method described above with reference to FIG. 5C is performed in a lab to determine capacitances C1a-Cna and corresponding uniformities UNFM1-UNFMn. For example, a dummy substrate S is used instead of substrate S. The dummy substrate is a proxy for multiple substrates to be processed in the plasma chamber 304. For example, the dummy substrate has the same structure (e.g., set of layers) as the multiple substrates. When the dummy substrate is placed in the plasma chamber 304, the processor 320 controls the variable capacitor Cvx to achieve capacitance C1a. Once capacitance C1a is achieved, the ERMDs 542, 544, and 546 measure the light intensity in the right, center, and left regions of the dummy substrate and output electrical signals. Based on the electrical signals, the processor 320 determines the uniformity UNFM1 in the process rate across the entire top surface of the dummy substrate and maps the uniformity UNFM1 to capacitance C1a. The mapping between uniformity UNFM1 and capacitance C1a is stored by processor 320 in table 533 of memory device 322. In a similar manner, processor 320 creates multiple mappings between capacitances C2a to Cna and uniformities UNFM2 to UNFMn for dummy substrates and stores the mappings in table 533. Once table 533 with the mappings between uniformities is created in the lab, processor 320 applies table 533 to process multiple substrates to achieve one of uniformities UNFM1 to UNFMn. For example, while processing one of the multiple substrates, processor 320 receives input from a user via an input device. The input indicates uniformity UNFM1. Processor 320 controls variable capacitor Cvx to achieve capacitance C1a corresponding to uniformity UNFM1. An input device is coupled to processor 320. Examples of the input device include a touch screen, a keyboard, a keypad, and a stylus.

[0106] In one embodiment, the measured uniformity includes the amount of substrate S left in more or less than three regions. For example, the measured uniformity includes the amount of substrate S left in a region of substrate S between the center region of substrate S and the right region of substrate S, and the amount of substrate S left in a region of substrate S between the center region of substrate S and the left region of substrate S.

[0107] In one embodiment, plasma chamber 304 has any other number of windows and the same number of ERMDs on sidewalls 538 or 540. Each ERMD is mounted relative to a corresponding one of the windows to detect optical emissions from the plasma in plasma chamber 304. For example, sidewall 538 has two windows and two ERMDs, and sidewall 540 has one window and one ERMD.

[0108] Figure 5D is a diagram of one embodiment of a system 550 to illustrate ex-situ processing to achieve uniformity in the processing rate of a substrate S. System 550 is identical in structure and function to system 530 of Figure 5C, except that thickness measurement device 550 replaces ERMDs 542, 544, and 546 (Figure 5C) in system 550. Thickness measurement device 550 facilitates the ex-situ process.

[0109] Examples of thickness measurement device 522 include electron microscopes and metrology tools available from KLA® Corporation. Thickness measurement device 522 is coupled to processor 320 via a cable.

[0110] The processor 320 controls the variable capacitor Cvx to achieve a capacitance C1 to further achieve uniformity UNFM1 across the entire top surface 502 of the substrate S being processed in the plasma chamber 304. After the substrate S has been processed in the plasma chamber 304, the substrate S is removed from the plasma chamber 304 through an opening 552 in the sidewall 540. A user uses the thickness measuring device 552 to measure a thickness TL of the substrate S at a left region of the substrate S, a thickness TC of the substrate S at a center region of the substrate S, and a thickness TR of the substrate S at a right region of the substrate S. The user provides the calculated uniformity, including the thicknesses TL, TC, and TR, to the processor 320 via an input device.

[0111] The processor 320 determines whether the calculated uniformity is within a predetermined range from the uniformity UNFM1. For example, the processor 320 compares the calculated uniformity with the uniformity UNFM1 and determines that the calculated uniformity matches the uniformity UNFM1. If the processor 320 determines that the calculated uniformity matches the uniformity UNFM1, the processor 320 determines that the calculated uniformity is within a predetermined range from the uniformity UNFM1. On the other hand, if the processor 320 determines that the calculated uniformity does not match the uniformity UNFM1, the processor 320 determines that the calculated uniformity is not within a predetermined range from the uniformity UNFM1. As another example, the processor 320 compares the calculated uniformity with the uniformity UNFM1 and determines that a predetermined number of values ​​of the calculated uniformity (e.g., 70% or more, 75% or more, or 80% or more of the values) are within a predetermined range from the predetermined number of values ​​of the uniformity UNFM1. If so determined, the processor 320 determines that the calculated uniformity is within a predetermined range from the uniformity UNFM1. On the other hand, if it is determined that the predetermined number of values ​​of the calculated uniformity is not within a predetermined range from the predetermined number of values ​​of the uniformity UNFM1, the processor 320 determines that the calculated uniformity is not within a predetermined range from the uniformity UNFM1.

[0112] On the other hand, if the processor 320 determines that the calculated uniformity is within the predetermined range from the uniformity UNFM1, the processor 320 does not further control the variable capacitor Cvx to change the capacitance C1a of the variable capacitor Cvx. On the other hand, in response to determining that the calculated uniformity is not within the predetermined range from the uniformity UNFM1, the processor 320 controls the variable capacitor Cvx to change the capacitance of the variable capacitor Cvx, and recalculates the uniformity in the processing rate across the upper surface 502 of the substrate S and compares it with the uniformity UNFM1. In this manner, the processor 320 continues to control the variable capacitor Cvx until the calculated value of the uniformity is within the predetermined range from the uniformity UNFM1. In this manner, the processor 320 controls the variable capacitor Cvx to achieve the capacitance values ​​C2a to Cna to achieve the corresponding uniformities UNFM2 to UNFMn in the processing rate across the upper surface 502 of the substrate S.

[0113] In one embodiment, the calculated uniformity includes the thickness of the substrate S in more than three or less than three regions of the substrate S. For example, the calculated uniformity includes the thickness of the substrate S remaining in a region of the substrate S between the center region of the substrate S and the right region of the substrate S, and the thickness of the substrate S remaining in a region of the substrate S between the center region of the substrate S and the left region of the substrate S.

[0114] In one embodiment, the ex situ method described above with reference to FIG. 5D is performed in a lab to determine capacitances C1a-Cna and corresponding uniformities UNFM1-UNFMn. For example, a dummy substrate S is used instead of the substrate S. When the dummy substrate S is placed in the plasma chamber 304 for processing, the processor 320 controls the variable capacitor Cvx to achieve capacitance C1a. When the variable capacitor Cvx has capacitance C1a, the user removes the dummy substrate S from the plasma chamber 304 and uses the thickness measurement device 552 to determine the uniformity in the process rate across the entire top surface of the dummy substrate. The uniformity is determined to be UNFM1. The uniformity UNFM1 is provided by the user to the processor 320 via an input device for storage in table 533 in the memory device 322 and corresponds to the capacitance C1a of the variable capacitor Cvx. Similarly, the processor 320 controls the variable capacitor Cvx to achieve capacitances C2a-Cna and determines the corresponding uniformity for a set of dummy substrates. The correspondence between statements C2a-Cna and uniformities UNFM2-UMFMn is stored in table 533. Table 533 is then applied by processor 320 to control variable capacitor Cvx during processing of multiple substrates in plasma chamber 304 to achieve corresponding uniformities UNFM1-UNFMn. For example, processor 320 controls variable capacitor Cvx to have capacitance C1a to achieve uniformity UNFM1 across the entire top surface 502 of substrate S, and controls variable capacitor Cvx to have capacitance C2a to achieve uniformity UNFM2 across the entire top surface of another substrate being processed in plasma chamber 304.

[0115] 6 is a diagram of one embodiment of an impedance matching circuit 601 to illustrate the coupling of uniformity control circuit 339 and impedance matching circuit 601. Impedance matching circuit 601 is an example of impedance matching circuit 204 (FIG. 3).

[0116] The impedance matching circuit 601 includes branch circuits 602A and 602B. Branch circuit 602A is an example of the first branch circuit described above with reference to FIG. 3. Branch circuit 602B is an example of the second branch circuit described above with reference to FIG. 3. Branch circuit 602A includes circuit components such as inductor L1, inductor L2, capacitor C1, capacitor C4, capacitor C5, capacitor C6, and inductor L3. Inductor L3, sometimes referred to as an isolation coil, reduces the chance that the RF power of RF signal 304B passing through branch circuit 602B will interfere with the components of branch circuit 602A. Capacitors C5 and C6 are direct current (DC) blocking capacitors, which will be described in more detail below. Branch circuit 602B includes circuit components such as inductor L4, capacitor C2, capacitor C7, and capacitor C3. Capacitors C1, C2, and C3 are variable capacitors. C1 and C2 are main capacitors, and C3 is a backup capacitor. Inductors L1-L4 are coils that are wound to form inductors and are not RF straps.

[0117] Branch circuit 602B further includes RF strap portion 604A, RF strap portion 604B, RF strap 604C, RF strap 604D, and RF strap 604E. Portions 604A and 604B are portions of a single RF strap. As an example, an RF strap, as used herein, is a flat, elongated piece of metal made from a conductor such as copper or a copper alloy. Illustratively, an RF strap has a length, a width, and a thickness. The length of the RF strap is greater than the width of the RF strap, and the width of the RF strap is greater than the thickness of the RF strap. As another example, an RF strap is a substantially rectangular volume or occupies a rectangular volume and has flexibility to be bent or reshaped. An example of a rectangular volume is the volume occupied by a rectangular bar.

[0118] Inductor L1 is coupled to input I1 of housing 211 and to inductor L2, and capacitor C1 is coupled to the point where inductor L1 is coupled to inductor L2, and capacitor C1 is coupled to ground potential.

[0119] Inductor L2 is coupled to capacitor C6, and capacitor C4 is coupled to the point where inductor L2 is coupled to capacitor C6. Capacitor C4 is also coupled to ground potential. Capacitor C6 is coupled in parallel with capacitor C5. Capacitor C6 is coupled to inductor L3, and inductor L3 is coupled to output O4 of impedance matching circuit 601.

[0120] Inductor L4 is coupled to input I2 of housing 211 and to a ground connection. Inductor L4 is coupled to a point on RF strap 604D. An example of input I2 is the end of RF strap 604D. Capacitor C2 is coupled to point P2 between RF straps 604D and 604E. RF straps 604D and 604E are connected to each other at point P2. Capacitor C2 is also coupled to a ground connection. Capacitor C7 is coupled to RF strap 604E and RF strap portion 604A.

[0121] Capacitor C3 is coupled to RF strap 604C, which is coupled to point P1 of branch circuit 602B. Point P1 couples RF strap portion 604A to RF strap portion 604B. RF strap portion 604A is coupled to RF strap portion 604B at point P1. Capacitor C3 is also coupled to a ground connection. RF strap portion 604B is coupled to output O4 of impedance matching circuit 601.

[0122] Each of the RF strap portions 604A and 604B and each of the RF straps 604C-604E has a respective inductance. For example, RF strap portion 604A has an inductance L A , RF strap portion 604B has another inductance L B , RF strap 604C has yet another inductance L C , RF strap 604D has an inductance L D , and RF strap 604E has an inductance L E . Note that, by way of example, any of RF strap portions 604A, 604B, 604C, 604D, and 604E are not coiled to form an inductor but are simply flat, elongated pieces of metal.

[0123] As an example, inductor L1 has an inductance in the range of 45 microhenries (μH) to 55 μH. As another example, inductor L2 has an inductance in the range of 35 μH to 41 μH. As yet another example, capacitor C1 has a capacitance in the range of 60 picofarads (pF) to 2000 pF. As another example, capacitor C4 has a capacitance in the range of 110 pF to 120 pF. And as yet another example, capacitor C5 has a capacitance in the range of 2700 pF to 2900 pF. As another example, inductor L3 has an inductance in the range of 2.1 μH to 2.3 μH.

[0124] As yet another example, inductor L4 has an inductance in the range of 0.44 μH to 0.46 μH. Also, as another example, capacitor C2 has a capacitance in the range of 25 pF to 250 pF. As another example, capacitor C7 has a capacitance in the range of 7 pF to 17 pF. As yet another example, capacitor C3 has a capacitance in the range of 3 pF to 30 pF.

[0125] UCC 339 is coupled between output O4 and output O3. For example, UCC 339 is coupled in parallel to portion 403 of RF strap 402. End E1 of UCC 339 is coupled to output O4 of impedance matching circuit 601, and end E2 is coupled to output O3 of housing 211.

[0126] An RF signal 304A generated by an LF RF generator is received at input I1 and transmitted through inductor L1, inductor L2, capacitors C5 and C6, and inductor L3 to output O4. Capacitors C1, C4, C5, and C6, and inductors L1-L3 change the impedance of the RF signal 304A received at input I1, outputting a modified RF signal 610A.

[0127] Additionally, RF signal 304B generated by HF RF generator is received at input 12 and transmitted to output 04 via RF strap 604D, point P2, RF strap 604E, capacitor C7, RF strap portion 604A, and RF strap portion 604B. Inductor L4, RF strap 604D, capacitor C2, RF strap 604E, capacitor C7, RF strap portion 604A, RF strap 604C, capacitor C3, and RF strap portion 604B modify the impedance of RF signal 304B received at input 12 to output modified RF signal 610B.

[0128] Subtract circuit 602A modifies the impedance of low frequency RF signal 304A received at input I1 to reduce power reflected from plasma chamber 304 through impedance match circuit 601 back to the LF RF generator. The impedance is modified to match the impedance of a load coupled to output O4 with the impedance of a source coupled to input I1, and modified RF signal 610A is output from the output of inductor L3. Modified signal 610A is an example of the first modified RF signal described above with reference to FIG. 3. Examples of loads coupled to output O4 include plasma chamber 304, RF transmission line 302 coupling impedance match circuit 601 to plasma chamber 304, and uniformity control circuit 339. Examples of sources coupled to input I1 include an LF RF generator and RF cable 208A coupling the LF RF generator to input I1.

[0129] Similarly, branch circuit 602B modifies the impedance of high frequency RF signal 304B received at input I2 to reduce power reflected from plasma chamber 304 back through impedance matching circuit 601 toward the HF RF generator. The impedance is modified to match the impedance of a load coupled to output O4 with the impedance of a source coupled to input I2, and modified RF signal 610B is output from the output of RF strap portion 604B. Modified RF signal 610B is an example of the second modified RF signal described above with reference to FIG. 3. Examples of sources coupled to input I2 include an HF RF generator and RF cable 208B (FIG. 2) coupling the high frequency RF generator to input I2. Modified signals 610A and 610B output from inductor L3 and RF strap portion 304B are combined, such as by being summed, at output O4 to provide combined RF signal 312 at output O4.

[0130] In one embodiment, any of the capacitors or inductors shown in Figure 6 are fixed or variable. For example, one or more of capacitors C4-C7 are fixed capacitors. As another example, one or more of inductors L1-L4 are variable inductors whose inductance can be changed.

[0131] In one embodiment, two RF straps are used instead of RF strap portions 604A and 604B of the RF strap. For example, a first RF strap having the inductance of RF strap portion 604A is connected to a second RF strap having the inductance of RF strap portion 604B via a connector. Examples of connectors are described above.

[0132] In some embodiments, the impedance matching circuit 601 includes a different number of capacitors than those shown in Figure 6. For example, one capacitor replaces capacitors C5 and C6. In some embodiments, the impedance matching circuit 601 includes a different number of inductors than those shown in Figure 6.

[0133] In one embodiment, a variable capacitor Cvx is used instead of the fixed capacitor Cx of the UCC339.

[0134] 7 is one embodiment of a graph 700 illustrating the change in etch rate uniformity with a change in capacitance of a variable capacitor (FIG. 5B) or a change in capacitance of a fixed capacitor (FIG. 5A). Graph 700 is generated when the HF RF generator is operating and the LF RF generator is not operating. Illustratively, graph 700 is generated when the HF RF generator is generating RF power and the LF RF generator is not generating RF power.

[0135] Graph 700 plots uniformity on the y-axis and the radius of the substrate S on the x-axis. The uniformity in the etch rate across the top surface 502 of the substrate S varies as the first plate of a capacitor, such as capacitor Cx or variable capacitor Cvx, rotates relative to the second plate of the capacitor. For example, when the number of capacitor turns (e.g., steps or clicks) of capacitor Cx or Cvx is CT6, the uniformity in the etch rate is shown by curve 702. When the number of capacitor turns of capacitor Cx or Cvx is CT7, the uniformity in the etch rate is shown by curve 704. When the number of capacitor turns of capacitor Cx or Cvx is CT17, the uniformity in the etch rate is shown by curve 706. As shown, curve 702 has the highest uniformity of the uniformities of curves 702, 704, and 706. Therefore, controlling the number of capacitor turns of the first plate relative to the second plate of the capacitor controls the uniformity in the etch rate across the top surface 502 of the substrate S.

[0136] 8 is one embodiment of a graph 800 illustrating the change in etch rate uniformity with a change in capacitance of the variable capacitor (FIG. 5B) or a change in capacitance of the fixed capacitor (FIG. 5A). Graph 800 is generated when both the HF RF generator and the LF RF generator are operating.

[0137] Graph 800 plots uniformity on the y-axis and the radius of the substrate S on the x-axis. The uniformity in etch rate across the top surface 502 of the substrate S varies as the number of capacitor turns (e.g., steps or clicks) on a first plate of a capacitor, such as capacitor Cx or variable capacitor Cvx, relative to the second plate of the capacitor is varied. For example, when capacitor Cx or Cvx has 10 capacitor turns, the uniformity in etch rate is shown by curve 802. When capacitor Cx or Cvx has 20 capacitor turns, the uniformity in etch rate is shown by curve 804. When capacitor Cx or Cvx has 0 capacitor turns, the uniformity in etch rate is shown by curve 806. When capacitor Cx or Cvx has 9 capacitor turns, the uniformity in etch rate is shown by curve 808. When capacitor Cx or Cvx has 4 capacitor turns, the uniformity in etch rate is shown by curve 810. As shown, curve 804 has the highest uniformity of the uniformities of curves 802-810.

[0138] The embodiments described herein may be practiced with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0139] In some embodiments, the controller is part of a system that may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of semiconductor wafers or substrates. This electronics is referred to as a "controller," which may control various components or subcomponents of one or more systems. Depending on the processing requirements and / or type of system, the controller is programmed to control any of the processes disclosed herein, such as delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and operation settings, and wafer loading and unloading from the tool and other transfer tools and / or load locks connected or interfaced to the particular system.

[0140] Broadly speaking, in various embodiments, a controller is defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint metrology, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers (e.g., software) that execute the program instructions. Program instructions are instructions communicated to the controller in the form of various personalizations (or program files) that define parameters, factors, variables, etc. for performing a particular process on or for a semiconductor wafer or for a system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0141] The controller, in some embodiments, is part of a computer that is integrated into the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a host computer system in the "cloud" or at a fab that allows remote access to wafer processing. By allowing remote access to the system, the computer can monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance criteria from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0142] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data defining parameters, factors, and / or variables for each processing step performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, a controller may be distributed, such as by including one or more separate controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) combined to control a process on the chamber.

[0143] Without being limited thereto, in various embodiments, exemplary systems to which the present methods may be applied include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, clean chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or production of semiconductor wafers.

[0144] It is further noted that in some embodiments, the above operations apply to several types of plasma chambers (e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc.). For example, one or more RF generators are coupled to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat coil, etc.

[0145] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, main computers, other controllers, or tools used in material transport to move containers of wafers into and out of tool locations and / or load ports within a semiconductor production factory.

[0146] In view of the above embodiments, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0147] Some embodiments also relate to hardware units or apparatus for performing these operations. An apparatus is specially configured for a special-purpose computer. When defined as a special-purpose computer, the computer performs other processes, program execution, or routines that are not part of the special purpose computer while remaining operable for the special purpose.

[0148] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0149] In one or more embodiments, the invention may also be manufactured as computer-readable code on a non-primary computer-readable medium. The non-primary computer-readable medium is a data storage hardware unit (e.g., a memory device) that stores data, which is then read by a computer system. Examples of non-primary computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recording media (CD-Rs), CD-rewritable media (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-primary computer-readable medium comprises computer-readable tangible media distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed fashion.

[0150] Although the method operations above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, the method operations may be adjusted to occur at slightly different times, may be distributed in a system that allows the method operations to occur at various intervals, or may be performed in a different order than described above.

[0151] It should be further noted that in embodiments, one or more features from any of the above-described embodiments may be combined with one or more features of any other of the above-described embodiments without departing from the scope described in the various embodiments described in this disclosure.

[0152] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. An impedance matching box housing, an impedance matching circuit having an input configured to be coupled to a radio frequency (RF) generator and an output coupled to the first RF strap; a uniformity control circuit coupled in parallel with a portion of the first RF strap to modify a uniformity in a processing rate of the substrate as the substrate is processed in the plasma chamber; an impedance matching box housing including:

2. The impedance matcher housing of claim 1 , wherein the first RF strap is configured to be coupled to an RF transmission line.

3. 2. The impedance matcher housing of claim 1, wherein the uniformity control circuit includes a capacitor coupled in parallel to a portion of the first RF strap.

4. 2. The impedance matching box housing of claim 1, wherein the uniformity control circuit includes a capacitor, the capacitor having a first end and a second end, the first end coupled to a first point on the first RF strap, and the second end coupled to a second point on the first RF strap.

5. 5. The impedance matching box housing of claim 4, wherein the uniformity control circuit includes a second RF strap and a third RF strap, a first end of the capacitor coupled to a first point on the first RF strap via the second RF strap, and a second end of the capacitor coupled to a second point on the first RF strap via the third RF strap.

6. 6. The impedance matcher housing of claim 5, wherein the first RF strap has an internal inductance, the second RF strap has an internal inductance, and the third RF strap has an internal inductance.

7. 6. The impedance matching box housing according to claim 5, wherein the first RF strap, the second RF strap, and the third RF strap are each an elongated metal piece.

8. 6. The impedance matcher housing of claim 5, wherein the first RF strap, the second RF strap, and the third RF strap are not inductive coils.

9. 2. The impedance matching box housing of claim 1, wherein the uniformity control circuit includes a variable capacitor.

10. 2. The impedance matching box of claim 1, wherein the uniformity control circuit includes a variable capacitor, the variable capacitor configured to be coupled to a motor to vary a capacitance of the variable capacitor.

11. 11. The impedance matcher housing of claim 10, wherein the capacitance of the variable capacitor is configured to be modified to achieve uniformity in processing speed across a top surface of the substrate.

12. 11. The impedance matcher housing of claim 10, wherein the capacitance of the variable capacitor is configured to be modified based on a measurement of uniformity in processing speed across a top surface of the substrate.

13. 2. The impedance matcher housing of claim 1, wherein the first RF strap is an elongated metal piece and is not an RF coil.

14. a uniformity control circuit comprising: a first radio frequency (RF) strap; a second RF strap coupled to the first RF strap; a capacitor coupled to the second RF strap; a third RF strap coupled to the capacitor and the first RF strap, the first RF strap configured to be coupled between an output of the impedance matching circuit and an RF transmission line coupled to a plasma chamber.

15. 15. The uniformity control circuit of claim 14, wherein the first RF strap has a first point and a second point, the second RF strap has a first end and a second end, and the first end of the second RF strap is coupled to the first point on the first RF strap.

16. 16. The uniformity control circuit of claim 15, wherein the capacitor has a first end and a second end, the first end of the capacitor coupled to the second end of the second RF strap.

17. 17. The uniformity control circuit of claim 16, wherein the third RF strap has a first end and a second end, the first end of the third RF strap coupled to the second end of the capacitor and the second end of the third RF strap coupled to the second point on the first RF strap.

18. 20. The uniformity control circuit of claim 17, wherein the capacitor is a variable capacitor having a capacitance, the variable capacitor configured to be coupled to a motor to modify the capacitance, the capacitance modified to achieve uniformity in processing speed across a top surface of a substrate.

19. 15. The uniformity control circuit of claim 14, wherein the capacitor is a first fixed capacitor, the first fixed capacitor configured to be replaced with a second fixed capacitor to achieve uniformity in processing rate across an upper surface of a substrate.

20. 15. The uniformity control circuit of claim 14, wherein the capacitor is a variable capacitor having a capacitance, the variable capacitor configured to be coupled to a motor to modify the capacitance, the capacitance modified based on a measurement of uniformity in processing speed across a top surface of a substrate.

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