Power device and method of manufacturing the same

Abstract

The present invention relates to a power device and a method for manufacturing the same.SOLUTION: The method includes providing a semiconductor substrate, growing an epitaxial layer on the semiconductor substrate, forming an insulating layer on the epitaxial layer, forming a metal mask layer on the insulating layer, and performing an ion implantation process from the metal mask layer to the epitaxial layer. The metal mask layer includes an ion implantation blocking region and an ion implantation penetration region.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] Cross-references to related applications and priority claims This application claims priority from Taiwan Application No. 113130755, filed August 15, 2024.

[0002] The present disclosure relates to a power device and a method for manufacturing the same. More specifically, the present disclosure relates to a power device having a low drain-source on-resistance (RDS(on)), a high breakdown voltage, and a high current capability, and a method for manufacturing the device. [Background technology]

[0003] Since the first wafers were released in 1991, the evolution of silicon carbide (SiC) has been fairly slow, with the first fully SiC commercial MOSFETs only being released two decades later. Ultimately, it was Tesla and its 400V inverter that brought silicon carbide materials to the forefront of development in 2018. Since then, interest in SiC-based products, characterized by high power density, high efficiency, and high-temperature performance, has grown, delighting the automotive market segment seeking solutions to meet the requirements of under-the-hood applications. Over the past five years, technological innovations related to SiC power MOSFETs have undergone a series of innovations aimed at dramatically improving device performance and making them unique in their use. The fact that the cost of SiC wafers currently on the market is very high necessitates the need to shrink the die size to reduce the cost of final devices. From this perspective, more and more companies are interested in innovations to gain advantages in terms of device cost and performance.

[0004] Currently, the most advanced SiC MOSFET technology in the power semiconductor market is called CoolSiC. This technology is Infineon's hybrid superjunction patented technology (SJ patented technology). This technology uses a very small cell pitch of approximately 1-3 μm and currently accounts for approximately 10-20% of the SiC MOSFET market. More specifically, this technology is Micro-Trench CoolSiC Technology Gen.2. Micro-Trench CoolSiC offers significant advantages and is considered state-of-the-art. In fact, with the support of highly accurate simulators, we were able to understand the key critical parameters for increasing current density per unit area and improving overall device performance. In fact, due to the effect created by the channel structure (inversion channel) for current conduction, a clean, defect-free channel crystal structure provides high levels of electron mobility. This minimizes channel resistance, increasing current density per unit area while reducing the overall device RDS(on).

[0005] Figure 1 is a schematic diagram showing the RDS(on) contribution of each component in a conventional SiC MOSFET high-voltage wafer. The vertical axis represents the cumulative percentage of the resistance of each component relative to the RDS(on). The components shown in Figure 1 include the packaging area ("PKG" in the figure), the inactive area ("IA" in the figure), the die drift area ("DR" in the figure), the junction area ("JFET" in the figure), the channel area ("CH" in the figure), and the substrate area ("SUB" in the figure). One of the major contributors is the die drift area (DR). It is clear that research and development efforts to date have significantly improved the channel resistance, increasing channel mobility to acceptable levels and significantly reducing the contribution to RDS(on). The drift layer level remains a significant contributor to RDS(on), accounting for more than 40–50% of the total RDS(on) for high-voltage (>400 V) dies. This principle applies not only to SiC MOSFETs but also to silicon MOSFETs in conventional high-voltage technologies.

[0006] Therefore, in view of the deficiencies of the prior art, the applicant of the present application has invented the present invention, "a power device and a manufacturing method thereof," in order to overcome the drawbacks of the prior art. The contents of the present invention are as follows. Summary of the Invention [Problem to be solved by the invention]

[0007] As mentioned above, the main cause of the high RDS(on) in standard DMOS power MOSFETs is the large influence of the drift region, which can be improved by introducing superjunction technology. First proposed in 1978 by Masami Shirota and Shigeo Kaneda of Osaka University, this technology involves forming a deep, lightly doped P-pillar region beneath the P-body region. This P-doped silicon pillar functions to create a balancing charge between the P-pillar and the drift layer region. This balancing effect temporarily reduces the doping concentration of the drift layer, allowing it to withstand higher voltages without reducing the actual drift layer concentration. This lightly doped P-pillar region balances the N-type doping concentration of the adjacent drift region, temporarily reducing the N-type doping concentration of the drift region during device turn-off. Compared to conventional structures, reducing the N-type doping allows the drift region to withstand a higher breakdown voltage during device turn-off and then returns to its normal concentration during device turn-on, thereby reducing RDS(on). Unlike conventional structures, there is no need to intentionally reduce the N-type doping concentration in the drift region during device fabrication to increase the breakdown voltage, which ultimately leads to an increase in RDS(on). On average, the RDS(on) of the new structure is reduced by approximately 30% to 40%. As shown in Figure 2, after adopting the new structure, the contribution of the drift layer to RDS(on) is significantly reduced. [Means for solving the problem]

[0008] Although superjunction technology is mature and widely used in silicon power devices, SiC is a completely different material from silicon. Therefore, a different technology is required to fabricate a superjunction structure using SiC. When forming a P-pillar region in silicon, doping materials can be gradually introduced by thermal diffusion using a high-temperature process or implanted using an ion implanter. However, due to the material properties of SiC, dopant introduction by thermal diffusion is nearly impossible; dopants can only be implanted by forced implantation using an ion implanter. To achieve a superjunction P-pillar region structure, multiple implants at different energies are required for SiC, with the maximum implant energy ranging from 0.5 MeV to 12 MeV. Clearly, such high-energy processing poses many process challenges that must be overcome, such as the selection of mask materials for selective implantation. Such high-energy processing can be achieved through specific structures and processes. This disclosure provides a detailed description of how to build a power MOSFET using SJ technology.

[0009] Due to its crystalline structure, SiC is not suitable for thermal diffusion doping. Therefore, dopant introduction into SiC is achieved exclusively by high-energy ion implantation. Forming deep P-type pillars in SiC SJ structures requires multiple ion implantations at various energies ranging from 0.5 MeV to 12 MeV. This high-energy process poses several technical challenges, including the need for specialized implantation masks. This disclosure details a method for fabricating power MOSFETs using SJ technology and SiC materials.

[0010] In one aspect, the present invention provides a method for manufacturing a semiconductor device for forming a superjunction (SJ) structure in a silicon carbide substrate. The method includes the following steps: providing a heavily doped semiconductor substrate; growing an epitaxial layer on the heavily doped semiconductor substrate; depositing a first insulating layer on the epitaxial layer, followed by depositing a metal seed layer on the first insulating layer; depositing a photoresist layer on the metal seed layer; the photoresist layer having a first portion and a second portion; removing the first portion of the photoresist layer, leaving the second portion of the photoresist layer on the metal seed layer; forming a metal mask layer on the metal seed layer using an electroplating process or a chemical coating process; removing the remaining second portion of the photoresist layer after forming the metal mask layer; and performing a first ion implantation of a P-type dopant into the epitaxial layer. As a result of the first ion implantation, the epitaxial layer comprises a lightly doped first carrier region and a second carrier region. The lightly doped first carrier region includes a first epitaxial region and a second epitaxial region that are not covered by the metal mask layer, and the second carrier region is indirectly covered by the metal mask layer, i.e., the second carrier region is located below the region covered by the metal mask layer.

[0011] In another aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: providing a semiconductor substrate; growing an epitaxial layer on the semiconductor substrate; forming an insulating layer on the epitaxial layer; and forming a metal mask layer on the insulating layer. The metal mask layer includes an ion implantation blocking region and an ion implantation penetration region. After forming the metal mask layer, an ion implantation process is performed on the epitaxial layer from above the metal mask layer.

[0012] In another aspect, the present invention provides a super-junction semiconductor structure. The super-junction semiconductor structure includes a silicon carbide semiconductor substrate, a silicon carbide epitaxial layer grown on the silicon carbide semiconductor substrate, and a transistor. The epitaxial layer includes a lightly doped region formed by subjecting the epitaxial layer to an ion implantation process. The lightly doped region includes an epitaxial layer region at a first depth and an epitaxial layer region at a second depth. The transistor includes a body and a source. The lightly doped region is connected to the body. The source is disposed on the lightly doped region. [Brief explanation of the drawings]

[0013] Embodiments and advantages of the present invention will become more readily apparent to those skilled in the art upon review of the following detailed description and accompanying drawings. [Figure 1] FIG. 1 is a schematic diagram illustrating the effect of various parts of a conventional SiC MOSFET device on RDS(on). [Figure 2] FIG. 10 is a diagram illustrating the contribution of the drift layer to RDS(on). [Figure 3-10] 1A-1C are schematic diagrams illustrating a manufacturing process for a semiconductor device according to a preferred embodiment of the present disclosure. [Figure 11-16] 1A-1C are schematic diagrams illustrating a manufacturing process for the body of a transistor according to a preferred embodiment of the present disclosure. [Figure 17-19] 1A-1C are schematic diagrams illustrating a manufacturing process for the second carrier region of a transistor according to a preferred embodiment of the present disclosure. [Figure 20-26] 1A-1D are schematic diagrams illustrating the fabrication of a working channel portion and a peripheral body of a transistor according to a preferred embodiment of the present disclosure. [Figure 27] 1A-1C are schematic diagrams illustrating the fabrication results of edge terminals of a transistor according to a preferred embodiment of the present disclosure. [Figure 28] FIG. 1 is a schematic diagram illustrating the results of forming a barrier layer (graphite layer) by thermal conversion during an annealing process according to a preferred embodiment of the present disclosure. [Figure 29]FIG. 1 is a schematic diagram illustrating the results of removing a barrier layer according to a preferred embodiment of the present disclosure. [Figure 30] 1A-1C are schematic diagrams illustrating the fabrication results of a gate dielectric layer of a transistor according to a preferred embodiment of the present disclosure. [Figure 31] 1A-1C are schematic diagrams illustrating the results of depositing a polysilicon layer according to a preferred embodiment of the present disclosure. [Figure 32] 1 is a schematic diagram illustrating the results of depositing a top metal layer according to a preferred embodiment of the present disclosure. [Figure 33] 1 is a schematic diagram illustrating the results of depositing a protective layer according to a preferred embodiment of the present disclosure. [Figure 34] FIG. 34 is a schematic diagram illustrating the results of depositing metal contact pads on the backside of a wafer (see FIG. 33) according to a preferred embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be more particularly described with reference to the following embodiments. It should be noted that the following description of preferred embodiments of the present invention is presented for purposes of illustration and description only and is not intended to be exhaustive or limited to the precise forms disclosed.

[0015] Unless otherwise limited or stated in specific instances, the following definitions apply to terms used throughout this specification.

[0016] As used herein, the terms "comprise" or "include" mean that the presence of one or more other components, steps and / or elements in addition to the stated components, steps and / or elements is not excluded.

[0017] The term "about" as used herein means that there is an approximate or acceptable error range so as to avoid limiting the present invention to the exact or absolute numerical values ​​disclosed. The term "a" as used herein means that the object of the indefinite article is one or more than one.

[0018] 3 to 10 are schematic diagrams illustrating a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. The method includes the following steps: As shown in FIG. 3, a heavily doped semiconductor substrate 100 is prepared, and an epitaxial layer 101 is grown on the heavily doped semiconductor substrate 100. The heavily doped semiconductor substrate may have a c-axis orientation. As shown in FIG. 4, a first insulating layer 102-1 is deposited on the epitaxial layer 101. The first insulating layer 102-1 may have a single-layer structure or a multi-layer structure. As shown in FIG. 5, a metal seed layer 103 having a first thickness TK1 is deposited on the first insulating layer 102-1. As shown in FIG. 6, a photoresist layer PR having a second thickness TK2 is deposited on the metal seed layer 103, where the photoresist layer PR includes a first portion PR1 and a second portion PR2. As shown in FIG. 7, the first portion PR1 of the photoresist layer PR is removed using a first photolithography process, and the second portion PR2 of the photoresist layer PR is left on the metal seed layer 103. As shown in FIG. 8, a metal mask layer HMSK having a second thickness TK2 is formed on the metal seed layer 103 using an electroplating process or a chemical coating process. Here, the second thickness TK2 is greater than the first thickness TK1. As shown in FIG. 9, the second portion PR2 of the photoresist layer PR is removed, exposing a portion of the metal seed layer 103 between the metal mask layer HMSK. As shown in FIG. 10, a first ion implantation UEI1 is performed on the first epitaxial region 1011 and the second epitaxial region 1012 of the epitaxial layer 101 to form a lightly doped first carrier region 1010 having a low doping concentration. As a result, the epitaxial layer 101 includes the lightly doped first carrier region 1010, which is not covered or protected by the metal mask layer HMSK, and a second carrier region. The second carrier region can be defined as a region outside the lightly doped first carrier region 1010 in the epitaxial layer 101, or a region indirectly covered and protected by the metal mask layer. The first ion implantation is performed multiple times at varying energy levels to achieve an implant depth in the range of 0.5 μm to 50 μm, with the energy intensity being in the megaelectronvolt (MeV) range.

[0019] 3 to 10 illustrate a specialized process for fabricating semiconductors with superjunction structures using SiC-based materials. Because the crystal lattice arrangement of SiC materials is denser than that of materials commonly used for silicon-based substrates, very high energy is required for ion implantation into SiC material substrates, especially deep regions of the SiC material substrate. Because commonly used photoresist masks cannot block very high-energy ion implantation, a "hard mask" must be used to block the ion implantation. While a very thick insulator or nitride hard mask may be able to block very high-energy ion implantation, it is difficult to remove later. Furthermore, these materials generally have high internal stress, and a thick layer may cause wafer warpage. Therefore, metal is a more practical option because it can provide sufficient strength with low stress. Because thick metal layers are relatively expensive, this disclosure employs electroplating or electroless (chemical) plating to deposit a thick metal layer only in the areas where ion implantation needs to be blocked. Furthermore, a thicker metal mask layer (HMSK) can be used as the ion implantation blocking region (BLK) and a thinner metal seed layer (103) can be used as the ion implantation penetration region (PTH).

[0020] 11-16 are schematic diagrams illustrating a process for fabricating the bodies PB1 and PB2 of the transistor 10 (shown in FIG. 40) according to a preferred embodiment of the present disclosure. In any embodiment of the present disclosure, the fabrication method further includes the following body fabrication steps: As shown in FIG. 11, the metal mask layer HMSK and the metal seed layer 103 are removed; as shown in FIG. 12, the first insulating layer 102-1 is removed to form a first semi-finished product HS1. The first semi-finished product HS1 includes a heavily doped semiconductor substrate 100 and an epitaxial layer 101. The epitaxial layer 101 includes a lightly doped first carrier region 1010 and a second carrier region 101. As shown in FIG. 13, the first semi-finished product HS1 is thermally annealed at a temperature exceeding 1000° C.; as shown in FIG. 14, a second insulating layer 102-2 is deposited on the epitaxial layer 101 of the first semi-finished product HS1. The second insulating layer 102-2 may include a silicon oxide precursor layer and a silane oxide material layer. The silicon oxide precursor layer can be, for example, tetraethoxysilane (TEOS). As shown in FIG. 15, the second insulating layer 102-2 on the lightly doped first carrier region 1010 is etched to form a body structure PBS. As shown in FIG. 16, a second ion implantation HEI2 is performed in the region between the body structure PBS and the first epitaxial region 1011 and in the region between the body structure PBS and the second epitaxial region 1012 to form a first body PB1 and a second body PB2, respectively, in which the epitaxial layer is doped with first carriers. The first body PB1 and the second body PB2 each have a first carrier doping depth Xj1 on the micrometer level. The second ion implantation is performed at a substrate temperature of 100°C to 1000°C and an energy level of 5 keV to 500 keV, with the body carrier concentrations of the first body PB1 and the second body PB2 being approximately 1e5 to 1e20 carriers / cm. 2 The first carrier is a P-type carrier such as aluminum (Al) or boron (B), and the second carrier is an N-type carrier.

[0021] 17 to 19 are schematic diagrams illustrating a manufacturing process of the heavily doped second carrier region 1020 (see FIG. 19) of the transistor 10 according to a preferred embodiment of the present disclosure. In any embodiment of the present disclosure, the manufacturing method may further include the following steps for manufacturing the second carrier region: Removing the second insulating layer 102-2 to form a second semi-finished product HS2. As shown in FIG. 17, depositing a third insulating layer 102-3 on the epitaxial layer 101, the first body PB1, and the second body PB2 of the second semi-finished product HS2. The third insulating layer 102-3 includes a third silicon oxide precursor layer 102-31 and a third silane oxide material layer 102-32. The third layer thickness TK3 of the third silicon oxide precursor layer 102-31 and the fourth layer thickness TK4 of the third silane oxide material layer 102-32 are nanometer-scale thicknesses. The third silicon oxide precursor layer 102-31 may be, for example, tetraethoxysilane (TEOS). 18, the third insulating layer 102-3 on the first body PB1 and the second body PB2 is etched until at least a portion of the first body PB1 and the second body PB2 is exposed. The exposed portions are surfaces of silicon carbide material. As shown in FIG. 19, the first body PB1 and the second body PB2 are doped with second carriers N+ by third ion implantation HEI3 under the condition that the temperature of the heavily doped semiconductor substrate 100 is 100 to 1000°C, thereby forming heavily doped second carrier regions 1020. The heavily doped second carrier region 1020 has a second carrier layer thickness TKC2 on the micrometer level. The heavily doped second carrier region 1020 has a second carrier doping depth Xj2 on the micrometer level. The implantation energy used in the third ion implantation HEI3 is in the range of 5 kEV to 500 kEV.

[0022] 20-26 are schematic diagrams illustrating a manufacturing process for the working channel portion WCH (FIG. 23) and the peripheral structure body PBR (FIG. 26) of the transistor 10 according to a preferred embodiment of the present invention. In any embodiment of the present invention, the manufacturing method may further include the following steps for manufacturing the working channel portion and the peripheral structure body. As shown in FIG. 20, the third insulating layer 102-3 is etched until the epitaxial layer 101 and the heavily doped second carrier regions 1020 are exposed to form a third semi-finished product HS3. As shown in FIG. 21, a fourth insulating layer 102-4 is deposited on the epitaxial layer 101, the first body PB1, the second body PB2, and the heavily doped second carrier regions 1020 of the third semi-finished product HS3. The fourth insulating layer 102-4 includes a fourth silicon oxide precursor layer 102-41 and a fourth silane oxide material layer 102-42. The fourth silicon oxide precursor layer 102-41 and the fourth silane oxide material layer 102-42 each have a nanometer-level thickness. As shown in FIG. 22, a second photolithography process is used to form a working channel pattern structure WCHS on the fourth insulating layer 102-4. As shown in FIG. 23, a fourth ion implantation HEI4 is performed on the epitaxial layer 101 below the working channel pattern structure WCHS to form a working channel portion WCH. The working channel portion WCH has a micrometer-level doping depth Xj3. The implantation energy used in the fourth ion implantation HEI4 is in the range of 5 kV to 500 kV. As shown in FIG. 24, the fourth insulating layer 102-4 is replaced with a fifth insulating layer 102-5. As shown in FIG. 25, a third photolithography process is used to form a peripheral body pattern structure PBRS on the fifth insulating layer 102-5. 26, a fifth ion implantation HEI5 is performed on the epitaxial layer 101 below the peripheral body pattern structure PBRS to form a heavily doped peripheral body pattern structure PBR. The doping depth of the heavily doped peripheral body pattern structure PBR is approximately the same as the doping depth of the first body PB1 and the second body PB2. The implantation energy range of the fifth ion implantation HEI5 is 5k to 500k eV, the implanted carriers are, for example, aluminum Al, and the implanted carrier concentration is approximately 1e5 to 1e20 carriers / cm. 2 is.

[0023] 27 is a schematic diagram illustrating the fabrication result of the edge terminal RET of the transistor 10 according to a preferred embodiment of the present disclosure. In any embodiment of the present disclosure, the edge terminal RET of the transistor 10 is fabricated by replacing the fifth insulating layer 105-2 and then performing a photolithography and etching process to form the edge terminal RET, as shown in FIG.

[0024] 28 is a schematic diagram illustrating the result of adding a barrier layer GPH during thermal annealing according to a preferred embodiment of the present disclosure. In any embodiment of the present disclosure, the barrier layer is used to ensure material precipitation during annealing, as shown in FIG. 28. This process can improve the surface conductivity of the SiC material preform HS4 after removing the barrier layer.

[0025] 29 is a schematic diagram showing the result of removing the barrier layer according to a preferred embodiment of the present disclosure. As shown in FIG. 29, in any embodiment of the present disclosure, the barrier layer can be removed using a dry etching apparatus using an etching gas that does not damage the surface of the SiC.

[0026] 30 is a schematic diagram illustrating the fabrication result of a gate dielectric layer GO of a transistor 10 (shown in FIG. 40) according to a preferred embodiment of the present invention. In any embodiment of the present invention, as shown in FIG. 30, an insulating layer 102-6 is formed on a SiC material semi-finished product HS4 at a high temperature to form a gate dielectric layer GO.

[0027] 31 is a schematic diagram showing the result of depositing a polysilicon layer according to a preferred embodiment of the present invention: A polysilicon layer 106 is deposited on the gate dielectric layer GO, and has a thickness TK5 of about 4000 Å.

[0028] 32 is a schematic diagram showing the result of depositing a top metal layer according to a preferred embodiment of the present invention, which includes a bonding layer 108, a bonding layer 109 and a top metal layer 110.

[0029] 33 is a schematic diagram showing the result of depositing a protective layer PSV according to a preferred embodiment of the present invention. In any embodiment of the present invention, the step of depositing the protective layer PSV includes the steps of depositing a PSV layer 111 on the top metal layer 110 and depositing a PSV layer 112 on the PSV layer 111.

[0030] 34 is a schematic diagram showing the result of depositing metal contact pads MC on the back surface BS of a wafer WF (see FIG. 33) according to a preferred embodiment of the present invention. First, a metal layer 113 is formed on the back surface BS of a heavily doped semiconductor substrate 100, followed by thermal annealing at a high temperature. Next, a metal layer 114 is deposited on the metal layer 113.

[0031] 34 shows a completed transistor 10 having a super-junction semiconductor structure. The super-junction semiconductor structure includes a silicon carbide semiconductor substrate 121 and a silicon carbide epitaxial layer 122. The silicon carbide epitaxial layer 122 is grown on the silicon carbide semiconductor substrate 121 and includes a lightly doped region 1220. The lightly doped region 1220 has a low doping concentration and is formed by subjecting the silicon carbide epitaxial layer 122 to an ion implantation process. The lightly doped region 1220 is electrically connected to the body PB of the transistor 10.

[0032] In any embodiment of the present disclosure, the super-junction semiconductor structure further includes two sources 10S of the transistor 10, a gate insulating layer GO of the transistor 10, a junction field-effect channel (WCH) of the transistor 10, a peripheral body PBR of the transistor 10, and a polysilicon gate PG. The gate insulating layer GO is configured between the two sources 10S and the body PB and is connected to the two sources 10S and the body PB. The junction field-effect channel WCH is configured within the silicon carbide epitaxial layer 122 and between the lightly doped region 1220, the body PB, and the gate insulating layer GO, and is connected to the silicon carbide epitaxial layer 122, the body PB, and the gate insulating layer GO. The peripheral structure body PBR is connected to the body PB and the lightly doped region 1220 within the silicon carbide epitaxial layer 122. The polysilicon gate PG is disposed on the two sources 10S, the body PB, the junction field-effect channel WCH, the silicon carbide epitaxial layer 122 and the gate dielectric layer GO, and is connected to the gate dielectric layer GO.

[0033] In any embodiment of the present disclosure, the body PB has heavily doped first carriers. The silicon carbide semiconductor substrate 121, the two sources 10S, and the junction field-effect channel WCH have heavily doped second carriers. The first carriers are P-type carriers such as holes, and the second carriers are N-type carriers such as electrons. The silicon carbide semiconductor substrate 121 is a heavily doped semiconductor substrate, for example, an N-type or P-type heavily doped semiconductor substrate. The silicon carbide epitaxial layer 122 is an N-type or P-type silicon carbide epitaxial layer. The lightly doped region 1220 includes an epitaxial layer portion 1221 of a first depth and an epitaxial layer portion 1222 of a second depth. The thickness TK1221 of the epitaxial layer portion 1221 of the first depth is smaller than the thickness TK1222 of the epitaxial layer portion 1222 of the second depth.

[0034] The present invention is a truly innovative invention and has extremely important industrial value, so it is necessary to file a patent application in accordance with the law, and the present invention can be modified in any way by those skilled in the art without departing from the scope of protection claimed in the attached patent application. [Explanation of symbols]

[0035] 10: Transistor 10S: Sauce 100: Highly doped semiconductor substrate 101: Epitaxial layer 102-1: First insulating layer 102-2: Second insulating layer 102-3: Third insulating layer 102-4: Fourth insulating layer 102-5: Fifth insulating layer 102-6: Insulating layer 102-31: Third silicon oxide precursor layer 102-32: Third silane oxide material layer 102-41: Fourth silicon oxide precursor layer 102-42: Fourth silane oxide material layer 103: Metal seed layer 106: Polysilicon layer 108, 109: Bonding layer 110: Top metal layer 111, 112:PSV layer 113, 114: Metal layer 121: Silicon carbide semiconductor substrate 122: Silicon carbide epitaxial layer 1010: Lightly doped first carrier region 1011: First epitaxial region 1012: Second epitaxial region 1020: Highly doped second carrier region 1220: Lightly doped region 1221: First depth epitaxial layer 1222: Second depth epitaxial layer BLK: Ion implantation blocking region BS: Back GO: gate dielectric layer GPH: Barrier layer HEI2: Second ion implantation HEI3: Third ion implantation HEI4: Fourth ion implantation HEI5: Fifth ion implantation HMSK: Metal mask layer HS1: First semi-finished product HS2: Second semi-finished product HS3: Third semi-finished product HS4:SiC material semi-finished products MC: Metal contact pad PB: Body PBR: Peripheral structure body PBRS: Peripheral Body Pattern Structure PBS:Body Structure PB1: First body PB2: Second body PG: Polysilicon gate PR: photoresist layer PR1:First part PR2:Second part PSV:Protective layer PTH: Ion implantation penetration area RET: Edge terminal TK1, TK2, TK3, TK4, TK5, TKC2, TK1221, TK1222: Thickness UEI1: First ion implantation WCH: Working channel WCHS: Working Channel Pattern Structure WF: wafer Xj1, Xj2, Xj3: Depth

Claims

1. A method for manufacturing a semiconductor device for forming a superjunction structure (SJ structure) on a silicon carbide substrate, comprising: providing a heavily doped semiconductor substrate; growing an epitaxial layer on the heavily doped semiconductor substrate; depositing a first insulating layer on the epitaxial layer; depositing a metal seed layer on the first insulating layer; depositing a photoresist layer on the metal seed layer, the photoresist layer including a first portion and a second portion; removing the first portion of the photoresist layer and leaving the second portion of the photoresist layer on the metal seed layer; forming a metal mask layer on the metal seed layer using an electroplating process or a chemical coating process; removing the second portion of the photoresist layer; performing a first ion implantation of a P-type dopant into the epitaxial layer such that the epitaxial layer comprises a lightly doped first carrier region including a first epitaxial region and a second epitaxial region not covered by the metal mask layer, and a second carrier region covered by the metal mask layer.

2. 2. The method of claim 1, wherein the step of removing portions of the photoresist layer is performed by a photolithography process, and the semiconductor device is a power device.

3. the metal seed layer has a first thickness; the metal mask layer and the photoresist layer each have a second thickness; the second thickness is greater than the first thickness; the power device is a SiC element, the lightly doped first carrier region is a P-type carrier region; The method of claim 2 , wherein the second carrier region is an N-type carrier region.

4. 10. The method of claim 1, wherein the first ion implantation is performed multiple times at varying energy levels to achieve an implant depth in the range of 0.5 μm to 50 μm.

5. 2. The method of claim 1, wherein the first insulating layer has a single-layer structure or a multi-layer structure, and the P-type dopant is Al or B.

6. removing the metal mask layer, the metal seed layer, and the first insulating layer to form a first workpiece, the first workpiece comprising the heavily doped semiconductor substrate and the epitaxial layer, the epitaxial layer including the lightly doped first carrier region and the second carrier region; thermally annealing the first semi-finished product; depositing a second insulating layer on the epitaxial layer of the first workpiece; etching the second insulating layer over the lightly doped first carrier region to form a body structure; 10. The method of claim 1, further comprising: performing a second ion implantation into the body structure over the first epitaxial region and the second epitaxial region to form a first body and a second body in the epitaxial layer.

7. The second ion implantation is performed at a substrate temperature of 100° C. to 1000° C. and an energy level in the range of 5 keV to 500 keV, and the first body and the second body have a first carrier doping depth on the micrometer scale and a carrier density of 1e5 to 1e20 carriers / cm. 2 and an injected carrier concentration in the range of

8. removing the second insulating layer to form a second workpiece; depositing a third insulating layer on the second workpiece, the third insulating layer comprising a third silicon oxide precursor layer and a third silane oxide material layer; etching a third insulating layer over the first and second bodies; 7. The method of claim 6, further comprising: performing a third ion implantation of second carriers into the first and second bodies to form heavily doped second carrier regions in the first and second bodies within the epitaxial layer.

9. 9. The method of claim 8, wherein either the third silicon oxide precursor layer or the third silane oxide material layer has a thickness on the nanometer scale.

10. 9. The method of claim 8, wherein the third ion implantation is performed at a substrate temperature of 100°C to 1000°C, an energy level of 5 keV to 500 keV, and a doping depth on the micrometer scale, so that the heavily doped second carrier region has a thickness on the micrometer scale.

11. etching the third insulating layer remaining on the epitaxial layer to form a third workpiece; depositing a fourth insulating layer on the epitaxial layer of the third semi-finished product, the fourth insulating layer comprising a fourth silicon oxide precursor layer and a fourth silane oxide material layer; forming a working channel pattern structure in the fourth insulating layer; performing a fourth ion implantation into the epitaxial layer beneath the working channel pattern structure to form a working channel portion; replacing the fourth insulating layer with a fifth insulating layer; forming a peripheral body pattern structure in the fifth insulating layer; 10. The method of claim 8, further comprising: performing a fifth ion implant into the epitaxial layer beneath the peripheral body pattern structure to form a heavily doped peripheral body.

12. either the fourth silicon oxide precursor layer or the fourth silane oxide material layer has a nanometer-scale thickness; the working channel pattern structure and the peripheral body pattern structure are formed by a photolithography process; 12. The method of claim 11, wherein either the working channel portion or the heavily doped peripheral body has a micrometer-scale doping depth, and either the fourth ion implantation or the fifth ion implantation has an implant energy in the range of 5 keV to 500 keV.

13. the first ion implantation is performed multiple times at different energy levels in the megaelectronvolt (MeV) range; the metal seed layer and the metal mask layer comprise tungsten (W); 2. The method of claim 1, wherein the heavily doped semiconductor substrate is an N-type or P-type heavily doped semiconductor substrate having a C-axis crystal orientation.

14. providing a semiconductor substrate; growing an epitaxial layer on the semiconductor substrate; forming an insulating layer on the epitaxial layer; forming a metal mask layer on the insulating layer, the metal mask layer including an ion implantation blocking region and an ion implantation penetration region; performing an ion implantation process on the epitaxial layer over the metal mask layer.

15. 15. The method of claim 14, wherein the metal mask layer comprises tungsten and the semiconductor substrate is a heavily doped semiconductor substrate.

16. depositing a metal seed layer having a first thickness on the insulating layer; depositing a photoresist layer having a second thickness on the metal seed layer, the photoresist layer including a first portion and a second portion; removing the first portion of the photoresist layer and leaving the second portion of the photoresist layer on the metal seed layer; forming the metal mask layer having the second thickness on the metal seed layer using an electroplating process, wherein the ion implantation stop region has the second thickness and the ion implantation penetration region has the first thickness, the second thickness being greater than the first thickness; removing the second portion of the photoresist layer; performing the ion implantation process on the epitaxial layer multiple times at different energy levels to form a lightly doped first carrier region including a first epitaxial region and a second epitaxial region, the energy levels being related to a first carrier implantation depth; removing the metal mask layer, the metal seed layer, and the insulating layer to form a first workpiece including the heavily doped semiconductor substrate and the epitaxial layer; thermally annealing the first semi-finished product; depositing a second insulating layer on the epitaxial layer of the first workpiece; etching the second insulating layer over the lightly doped first carrier region to form a body structure; performing a second ion implantation into the body structure over the first epitaxial region and the second epitaxial region to form a first body and a second body having a micrometer-scale first carrier doping depth; removing the second insulating layer to form a second workpiece; depositing the third insulating layer on the second workpiece; etching the third insulating layer over the first and second bodies; 16. The method of claim 15, further comprising: performing a third ion implantation of second carriers into the first and second bodies to form heavily doped second carrier regions in the epitaxial layer in the first and second bodies.

17. etching the third insulating layer remaining on the epitaxial layer to form a third semi-finished product; depositing a fourth insulating layer on the epitaxial layer of the third semi-finished product; forming a working channel pattern structure in the fourth insulating layer; performing a fourth ion implantation into the epitaxial layer beneath the working channel pattern structure to form a working channel portion; replacing the fourth insulating layer with a fifth insulating layer; forming a peripheral body pattern structure in the fifth insulating layer; 17. The method of claim 16, further comprising: performing a fifth ion implant into the epitaxial layer beneath the peripheral body pattern structure to form a heavily doped peripheral body, the epitaxial layer being an N-type or P-type epitaxial layer and comprising a first epitaxial layer and a second epitaxial layer, either of the first epitaxial layer and the second epitaxial layer having a micrometer-scale thickness.

18. a silicon carbide semiconductor substrate; a silicon carbide epitaxial layer grown on the silicon carbide semiconductor substrate, the silicon carbide epitaxial layer comprising a lightly doped region formed by subjecting the silicon carbide epitaxial layer to an ion implantation process, the lightly doped region comprising an epitaxial layer region at a first depth and an epitaxial layer region at a second depth; 1. A super-junction semiconductor structure comprising: a transistor having a body and a source, the lightly doped region connected to the body and the source disposed in the lightly doped region.

19. The transistor is a gate dielectric layer disposed on and connected to the source and the body; a junction field effect channel (JFET) disposed between and connected to the silicon carbide epitaxial layer, the body, and the gate dielectric layer; a peripheral body connected to the body and to a lightly doped region of the silicon carbide epitaxial layer; a polysilicon gate disposed on the source, the body, the JFET, the silicon carbide epitaxial layer, and the gate dielectric layer and connected to the gate dielectric layer; 20. The super-junction semiconductor structure of claim 18, wherein the body has a heavily doped first carrier, and the silicon carbide semiconductor substrate, the source, and the JFET have a heavily doped second carrier.

20. the first carrier is a P-type carrier, and the second carrier is an N-type carrier; the silicon carbide semiconductor substrate is a heavily N-doped or P-doped semiconductor substrate; the heavily N-doped or P-doped semiconductor substrate has a C-axis crystal orientation; the silicon carbide epitaxial layer is an N-type or P-type silicon carbide epitaxial layer; and 20. The super-junction semiconductor structure of claim 19, wherein either the epitaxial layer region of the first depth or the epitaxial layer region of the second depth has a thickness on the micrometer scale.

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