Polarization super junction field effect transistor, semiconductor stacked structure, and electrical device

Abstract

To provide a polarization super junction GaN-based field effect transistor capable of easily realizing a normally-off state without using a complicated circuit.SOLUTION: The field-effect transistor has an undoped GaN layer 11, an AlxGa1-xN layer 12 having an opening 13, an undoped GaN layer 16 provided on a part of the undoped GaN layer 11 from the sidewall of the opening 13, an island-like AlyGa1-yN layer 15 extending over the undoped GaN layer 11, the undoped GaN layer 16 and the AlxGa1-xN layer 12, a source electrode 19 and a drain electrode 20 on the AlxGa1-xN layer 12, and a gate electrode 18 on the undoped GaN layer 16. The undoped GaN layer 11 and the AlxGa1-xN layer 12 have a c-plane orientation, and at least a part of a portion of the AlyGa1-yN layer 15 on the undoped GaN layer 14 has a plane orientation which is a semipolar plane inclined with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a polarization super junction field effect transistor, a semiconductor laminated structure, and an electric device using the polarization super junction field effect transistor. [Background technology]

[0002] Conventionally, a polarization super junction (psj) GaN-based field effect transistor (FET) has been known as a power transistor (see Patent Documents 1 and 2). This polarization super junction GaN-based field effect transistor has an undoped GaN layer, an Al x Ga 1-x The polarization super-junction GaN-based field-effect transistor has a structure in which an N layer and an undoped GaN layer are stacked in sequence. This polarization super-junction GaN-based field-effect transistor is capable of high voltage, high output, high efficiency, and high-speed operation, which are difficult to achieve with silicon (Si)-based power transistors.

[0003] The polarization super-junction GaN-based field effect transistors described in Patent Documents 1 and 2 are mainly formed by the undoped GaN layer and Al layer below the gate electrode, including the portion directly below the gate electrode, during non-operation (thermal equilibrium state). x Ga 1-x Since two-dimensional electron gas exists in the undoped GaN layer near the heterointerface with the N layer, the gate voltage V g When a voltage is applied between the source and drain electrodes in the case of V = 0 V or in the open state, a current flows between the source and drain electrodes, making it a so-called normally-on transistor.

[0004] On the other hand, transistors are often required to have a so-called fail-safe operation, in which the transistor is in an off state when a control signal (gate signal) is lost.The normally-on polarization super-junction GaN-based field effect transistors described in Patent Documents 1 and 2 can be made into normally-off type by assembling a cascode circuit or modified cascode circuit using a low-voltage normally-off SiMOS transistor, but this has the disadvantage of making the circuit more complicated.

[0005] A normally-off vertical GaN transistor has been proposed in which an n-type GaN drift layer, a p-type GaN well layer, and a carbon-doped GaN layer are sequentially stacked on a GaN substrate, a V-groove is formed in the carbon-doped GaN layer and the p-type GaN well layer reaching the n-type GaN drift layer, an undoped GaN layer, an undoped AlGaN layer, and a p-type GaN layer are sequentially stacked to fill this V-groove, a source electrode is formed on the periphery of these undoped GaN layer, undoped AlGaN layer, and p-type GaN layer, a drain electrode is formed on the back surface of the GaN substrate, and a gate electrode is formed on the p-type GaN layer (see Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5828435 [Patent Document 2] Patent No. 5669119 [Non-patent literature]

[0007] [Non-Patent Document 1] Daisuke Shibata et al., “1.7kV / 1.0mΩcm2 Normally-off Vertical GaN Transistor on GaN substrate with Regrown p-GaN / AlGaN / GaN Semipolar Gate Structure”, IEDM16-248 [Non-patent document 2] Doctoral dissertation by Tomoyuki Tanikawa, Nagoya University, "Selective MOVPE growth of semipolar and nonpolar nitride semiconductors on processed silicon substrates" (2012) Summary of the Invention [Problem to be solved by the invention]

[0008] The problem to be solved by this invention is to provide a polarization super-junction GaN-based field effect transistor that can easily realize a normally-off type transistor without using complicated circuits, and to provide a high-performance electrical device that uses this polarization super-junction GaN-based field effect transistor.

[0009] The problem to be solved by this invention is to provide a semiconductor laminated structure suitable for use in manufacturing a polarization super-junction GaN-based field effect transistor, which can easily realize a normally-off type transistor without using a complex circuit. [Means for solving the problem]

[0010] In order to solve the above problems, the present invention provides: a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a portion of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; a fifth semiconductor layer above the fourth semiconductor layer; a sixth semiconductor layer above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; a gate electrode electrically connected to the sixth semiconductor layer; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers; the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; At least a part of the fourth semiconductor layer on the third semiconductor layer has a plane orientation that forms a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane, forming a polarization super junction field effect transistor.

[0011] The group III nitride semiconductor layer generally comprises at least one group III element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga) and indium (In) and at least one group V element selected from the group consisting of N (nitrogen), phosphorus (P) and arsenic (As). The group III nitride semiconductor layer is most commonly Al p B q Ga 1-p-q-r In r N (where 0≦p≦1, 0≦q≦1, 0≦r≦1, 0≦p+q+r<1), typically Al p Ga 1-p-r In r N (where 0≦p≦1, 0≦r≦1, 0≦p+r<1). Most typically, the first, third, and fifth semiconductor layers are undoped GaN layers, and the second semiconductor layer is Al p Ga 1-p N layer (for example, 0.17≦p≦0.35), and the fourth semiconductor layer is Al s Ga 1-sFor the N layer (0 < s < p), the sixth semiconductor layer is a p-type GaN layer (including cases where it consists of a plurality of layers with different acceptor concentrations) or a p-type GaN layer and a p-type In t Ga 1-t N layer (0 < t < 1). Al p Ga 1-p The AlGaN layer is typically undoped, but can be an n-type or p-type AlGaN layer doped with a donor (n-type impurity) or an acceptor (p-type impurity), p Ga 1-p for example, an n-type AlGaN layer doped with Si p Ga 1-p can also be used. The AlGaN layer s Ga 1-s is similar to the AlGaN layer. The p-type InGaN layer p Ga 1-p is the same. The In composition t and thickness u of the p-type InGaN layer are typically selected such that s × u ≦ 0.20 × 5 [nm].

[0012] The group-III nitride semiconductor layer has a wurtzite structure. The plane orientations that become semi-polar planes inclined with respect to the c-plane are {11-24} (39.1 degrees), {11-22} (58.4 degrees), {11-21} (72.9 degrees), {1-102} (43.2 degrees), {1-101} (62.0 degrees), {2-201} (75.1 degrees), etc. The numbers in parentheses indicate the inclination angles from the c-plane when considering the GaN layer as the group-III nitride semiconductor layer. The plane orientations that become non-polar planes perpendicular to the c-plane are {11-20}, {1-100}. The {1-102} plane is called the r-plane, the {11-20} plane is called the a-plane, and the {1-100} plane is called the m-plane.

[0013] ​​​​​​When at least a portion of the fourth semiconductor layer above the third semiconductor layer has a plane orientation that forms a semipolar plane tilted relative to the c-plane, the polarization field of that portion of the fourth semiconductor layer is oriented perpendicular to the plane (growth plane) of the fourth semiconductor layer, thereby reducing the polarization field strength. This tilted fourth / third semiconductor layer structure prevents two-dimensional electron gas from forming in at least a portion of the third semiconductor layer near the heterointerface between the third and fourth semiconductor layers when the gate voltage applied to the gate electrode is turned off, thereby contributing to a normally-off state of the polarization superjunction field-effect transistor through an increase in the gate threshold voltage. The composition and thickness of the fourth semiconductor layer are selected, taking into account the effect of reducing the polarization field strength, so that two-dimensional electron gas is not formed in at least a portion of the third semiconductor layer near the heterointerface between the third and fourth semiconductor layers. When at least a portion of the fourth semiconductor layer above the third semiconductor layer has a plane orientation that forms a nonpolar plane perpendicular to the c-plane, there is no polarization field in that portion of the fourth semiconductor layer. Therefore, when the gate voltage applied to the gate electrode is turned off, it is possible to prevent two-dimensional electron gas from being formed in at least a part of the third semiconductor layer in the vicinity of the heterointerface between the third semiconductor layer and the fourth semiconductor layer, which contributes to the normally-off state of the polarization superjunction field effect transistor through an increase in the gate threshold voltage.

[0014] The third semiconductor layer typically has a trapezoidal cross-sectional shape. In this case, the opening in the second semiconductor layer typically has an inverted trapezoidal cross-sectional shape. The third semiconductor layer on one side of the opening and the third semiconductor layer on the opposite side may be arranged to contact each other at the center of the opening. In this case, the first semiconductor layer is not exposed inside the opening.

[0015] In this polarization super-junction field-effect transistor, when a gate voltage applied to the gate electrode is turned off, a two-dimensional electron gas is formed in the first semiconductor layer near the heterointerface between the first semiconductor layer and the second semiconductor layer, a two-dimensional electron gas is formed in the first semiconductor layer near the heterointerface between the first semiconductor layer and the fourth semiconductor layer, or no two-dimensional electron gas is formed, and a two-dimensional electron gas is not formed in at least a portion of the third semiconductor layer near the heterointerface between the third semiconductor layer and the fourth semiconductor layer, an n-channel is formed near the heterointerface between the second semiconductor layer and the third semiconductor layer, and a two-dimensional hole gas is partially formed in the fifth semiconductor layer near the heterointerface between the fifth semiconductor layer and the fourth semiconductor layer. In other words, a two-dimensional electron gas is not formed in at least a portion of the third semiconductor layer near the heterointerface between the third semiconductor layer and the fourth semiconductor layer, and therefore the n-channel between the source electrode and the drain electrode is interrupted in this portion. Therefore, this polarization super-junction field-effect transistor is a normally-off type. On the other hand, when the gate voltage applied to the gate electrode is on, a two-dimensional electron gas is induced in the third semiconductor layer in the vicinity of the heterointerface between the third semiconductor layer and the fourth semiconductor layer, thereby forming a continuous n-channel between the source electrode and the drain electrode.

[0016] This polarization superjunction field effect transistor is most typically constructed as follows.

[0017] That is, the present invention is a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layer(0 <x<1)と、 a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-xan N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layer(y <x)と、 The above Al y Ga 1-y a third undoped GaN layer above the N layer; a p-type GaN layer above the third undoped GaN layer; The above Al x Ga 1-x a source electrode and a drain electrode on the N layer; a gate electrode electrically connected to the p-type GaN layer; and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-y At least a part of the N layer on the second undoped GaN layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane, forming a polarization superjunction field effect transistor.

[0018] In this polarization superjunction field-effect transistor, Al y Ga 1-y When at least a part of the portion of the N layer on the second undoped GaN layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane, the Al in that portion y Ga 1-y The polarization field of the N layer is y Ga 1-y Since the orientation is perpendicular to the surface (growth surface) of the N layer, the polarization field strength can be reduced. y Ga 1-y The gradient structure of the N layer / second undoped GaN layer allows the second undoped GaN layer and Al y Ga 1-yThis prevents the formation of two-dimensional electron gas in at least a portion of the second undoped GaN layer near the heterointerface with the N layer, which contributes to the normally-off state of the polarization superjunction field-effect transistor through an increase in the gate threshold voltage. y Ga 1-y The Al composition y and thickness of the N layer are determined by taking into account the effect of reducing the polarization field strength described above. y Ga 1-y The AlN layer is selected so that two-dimensional electron gas is not formed in at least a portion of the second undoped GaN layer in the vicinity of the heterointerface with the N layer. y Ga 1-y When at least a part of the portion of the N layer on the second undoped GaN layer has a plane orientation that is a nonpolar plane perpendicular to the c-plane, the Al in that portion y Ga 1-y There is no polarization field in the N layer. Therefore, when the gate voltage applied to the gate electrode is turned off, the second undoped GaN layer and the Al y Ga 1-y This prevents the formation of two-dimensional electron gas in at least a portion of the second undoped GaN layer near the heterointerface with the N layer, and contributes to the normally-off state of the polarization superjunction field-effect transistor through an increase in the gate threshold voltage. Note that the tilt angle dependence of the polarization electric field of GaN-based semiconductors with respect to the c-axis is described, for example, in Non-Patent Document 2.

[0019] The second undoped GaN layer typically has a trapezoidal cross section. x Ga 1-x The opening in the N layer typically has an inverted trapezoidal cross section. The second undoped GaN layer on one side of the opening and the second undoped GaN layer on the other side may be arranged to contact each other at the center of the opening. In this case, the first undoped GaN layer is not exposed inside the opening.

[0020] In this polarization superjunction field effect transistor, when the gate voltage applied to the gate electrode is turned off, the first undoped GaN layer and the Al x Ga1-x A two-dimensional electron gas is formed in the first undoped GaN layer in the vicinity of the heterointerface between the first undoped GaN layer and the Al layer. y Ga 1-y A two-dimensional electron gas is formed in the first undoped GaN layer in the vicinity of the heterointerface between the first undoped GaN layer and the AlN layer, or a two-dimensional electron gas is not formed in the first undoped GaN layer and the AlN layer. y Ga 1-y Two-dimensional electron gas is not formed in at least a part of the second undoped GaN layer in the vicinity of the heterointerface with the AlN layer. x Ga 1-x An n-channel is formed near the heterointerface between the N layer and the second undoped GaN layer, and an n-channel is formed near the heterointerface between the third undoped GaN layer and the Al y Ga 1-y A two-dimensional hole gas is partially formed in the third undoped GaN layer near the heterointerface between the second undoped GaN layer and the AlN layer. y Ga 1-y Since no two-dimensional electron gas is formed in at least a part of the second undoped GaN layer near the heterointerface with the N layer, the n-channel between the source electrode and the drain electrode is interrupted in this part. Therefore, this polarization superjunction field effect transistor is a normally-off type. On the other hand, when the gate voltage applied to the gate electrode is on, y Ga 1-y A two-dimensional electron gas is induced in the second undoped GaN layer near the heterointerface with the N layer, forming a continuous n-channel between the source and drain electrodes. x Ga 1-x The n-channel formed near the heterointerface between the N layer and the second undoped GaN layer is Al x Ga 1-x This is because when an opening in the N layer is formed by dry etching, the sidewalls (etched end faces) of the opening usually become n-type.

[0021] Al y Ga 1-yThe inclination angle of at least a part of the N layer on the second undoped GaN layer with respect to the c-plane is generally 5 degrees or more and 90 degrees or less.

[0022] When the second undoped GaN layer has a trapezoidal cross section, Al y Ga 1-y The length of the projection of the portion of the N layer extending from the slope of the second undoped GaN layer on one side to the slope of the second undoped GaN layer on the other side onto the first undoped GaN layer in the direction connecting the source electrode and the drain electrode is defined as L. r The length of the projection of the slope of the second undoped GaN layer on one side onto the first undoped GaN layer in the above direction is L s1 The length of the projection of the slope of the second undoped GaN layer on the opposite side onto the first undoped GaN layer in the above direction is L s2 , Al y Ga 1-y The inclination angle of at least a part of the portion of the N layer on one side of the second undoped GaN layer with respect to the c-plane is θ1, and Al y Ga 1-y When the inclination angle of at least a part of the N layer on the second undoped GaN layer on the opposite side with respect to the c-plane is θ2, typically, 0.1 cos θ1≦2L s1 / L r ≦1 and 0.1cosθ2≦2L s2 / L r When the second undoped GaN layer on one side and the second undoped GaN layer on the other side are provided so as to contact each other at the center of the opening, L r =L s1 +L s2 holds true.

[0023] The present invention also provides: a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a portion of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer and the third semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer and the third semiconductor layer are undoped semiconductor layers, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; At least a part of the fourth semiconductor layer on the third semiconductor layer is a semiconductor laminated structure having a plane orientation that forms a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

[0024] The present invention also provides: a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layer(0 <x<1)と、 a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-x an N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layer(y <x)と、 and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-yAt least a part of the N layer on the second undoped GaN layer is a semiconductor laminated structure having a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

[0025] The present invention also provides: having at least one transistor, The transistor is a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a portion of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and extending on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; a fifth semiconductor layer above the fourth semiconductor layer; a sixth semiconductor layer above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; a gate electrode electrically connected to the sixth semiconductor layer; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers; the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; a polarization superjunction field effect transistor in which at least a part of the portion of the fourth semiconductor layer on the third semiconductor layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane; It is an electrical device.

[0026] Here, electrical equipment includes almost anything that uses electricity, regardless of application, function, size, etc., such as electronic devices, mobile devices, power plants, construction machinery, machine tools, etc. Electronic devices include robots, computers, game devices, in-vehicle devices, home appliances (air conditioners, etc.), industrial products, mobile phones, mobile devices, IT devices (servers, etc.), power conditioners used in solar power generation systems, power transmission systems, etc. Mobile devices include railroad cars, automobiles (electric vehicles, etc.), motorcycles, aircraft, rockets, spacecraft, etc.

[0027] In the invention of this electrical device, with respect to matters other than those mentioned above, what has been explained in relation to the invention of the polarization super junction field effect transistor above is valid, unless it is contrary to the nature of the device.

[0028] The present invention also provides: having at least one transistor, The transistor is a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layer(0 <x<1)と、 a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-x an N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layer(y <x)と、 The above Al y Ga 1-y a third undoped GaN layer above the N layer; a p-type GaN layer above the third undoped GaN layer; The above Al x Ga 1-x a source electrode and a drain electrode on the N layer; a gate electrode electrically connected to the p-type GaN layer; and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-y a polarization superjunction field effect transistor in which at least a part of the N layer on the second undoped GaN layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane; It is an electrical device.

[0029] In this electric device invention, what has been explained in relation to the electric device invention above is also valid. [Effects of the Invention]

[0030] According to the present invention, when the gate voltage is turned off, at least a part of the third semiconductor layer in the vicinity of the heterointerface between the third semiconductor layer and the fourth semiconductor layer or the second undoped GaN layer and Al y Ga 1-y Since no two-dimensional electron gas is formed in at least a portion of the second undoped GaN layer in the vicinity of the heterointerface with the N layer, a normally-off polarization super-junction GaN-based field-effect transistor can be easily realized without using complex circuits, and high-performance electronic devices can be realized using this normally-off polarization super-junction GaN-based field-effect transistor. [Brief explanation of the drawings]

[0031] [Figure 1] 1 is a cross-sectional view showing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 2]1 is an enlarged cross-sectional view showing a portion including an undoped GaN layer 14 and an Aly Ga1-y N layer 15 thereon in a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 3] 1 is an enlarged cross-sectional view showing a portion including an undoped GaN layer 14 and an Aly Ga1-y N layer 15 thereon on one side of a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 4] 2 is a schematic diagram showing an energy band diagram along the direction of the dashed-dotted arrow in FIG. 1 when the gate voltage of the polarization super-junction GaN-based FET according to the first embodiment of the present invention is off. FIG. [Figure 5] 2 is a schematic diagram showing an energy band diagram along the direction of the dashed-dotted arrow in FIG. 1 when the gate voltage of the polarization super-junction GaN-based FET according to the first embodiment of the present invention is on; FIG. [Figure 6] 2 is a schematic diagram showing an energy band diagram along the direction of the dashed arrow in FIG. 1 when the gate voltage of the polarization super-junction GaN-based FET according to the first embodiment of the present invention is off. FIG. [Figure 7] 2 is a schematic diagram showing an energy band diagram along the direction of the dashed arrow in FIG. 1 when the gate voltage of the polarization super-junction GaN-based FET according to the first embodiment of the present invention is on; FIG. [Figure 8] 1 is a cross-sectional view showing a state of a polarization super-junction GaN-based FET according to a first embodiment of the present invention when a gate voltage is on. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 13]1A to 1C are cross-sectional views illustrating a method for manufacturing a polarization super-junction GaN-based FET according to a first embodiment of the present invention. [Figure 14] FIG. 10 is a cross-sectional view showing a polarization super-junction GaN-based FET according to a second embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view showing a polarization super-junction GaN-based FET according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described.

[0033] First Embodiment [Polarization super-junction GaN-based FET]

[0034] As shown in FIG. 1, in the polarization super-junction GaN-based FET according to the first embodiment, an undoped GaN layer 11 and an Al layer 20 are formed on a substrate 10 via a buffer layer (not shown). x Ga 1-x The undoped GaN layer 11 and the AlN layer 12 are stacked in this order. x Ga 1-x The N layers 12 all have a c-plane orientation. The substrate 10 is preferably a substrate on which a GaN-based semiconductor grows along the c-plane, such as a c-plane sapphire substrate, a Si substrate, or a SiC substrate. The substrate 10 may be omitted. The buffer layer may be made of, for example, polycrystalline or amorphous GaN, AlN, AlGaN, or an AlGaN / GaN superlattice. x Ga 1-x The N layer 12 is typically undoped, but may be doped with n-type or p-type Al doped with donors (n-type impurities) or acceptors (p-type impurities). x Ga 1-x It may also be an N layer. x Ga 1-x The Al composition x and thickness of the N layer 12 are determined by the undoped GaN layer 11 and Al x Ga 1-xThe undoped GaN layer 11 in the vicinity of the heterointerface with the N layer 12 is selected such that a two-dimensional electron gas (2DEG) is formed therein, and x is generally 0.2 ≤ x ≤ 0.3.

[0035] Al x Ga 1-x The N layer 12 is provided with an opening 13 that reaches the undoped GaN layer 11. This opening 13 has a trapezoidal cross-sectional shape. This opening 13 is Al x Ga 1-x The opening 13 may stop at the N layer 12 or may be provided so as to reach a depth in the middle of the thickness direction of the undoped GaN layer 11. In FIG. 1, the latter example is shown. The sidewalls of this opening 13 are Al x Ga 1-x inclined with respect to the main surface of the N layer 12 (parallel to the main surface of the substrate 10), and thus inclined with respect to the c-plane. Specifically, the sidewalls of the opening 13 are inclined at an angle of, for example, 60 degrees or more and less than 90 degrees with respect to the c-plane. An undoped GaN layer 14 is provided on a part of the undoped GaN layer 11 inside this opening 13 from both sidewalls of the opening 13. The undoped GaN layer 14 has a trapezoidal cross-sectional shape, and its inclined surface is inclined with respect to the c-plane and has a plane orientation that becomes a semi-polar plane. The undoped GaN layer 14 is not provided at the central part of the opening 13, and the undoped GaN layer 11 is exposed at the central part of the opening 13. Al x Ga 1-x An Al y Ga 1-y N layer 15 (y < x) and an undoped GaN layer 16 are sequentially provided. Al y Ga 1-y The portion of the Al y Ga 1-y N layer 15 on the inclined surface of the undoped GaN layer 14 has a plane orientation that becomes a semi-polar plane inclined with respect to the c-plane, similar to the undoped GaN layer 14. Al x Ga 1-xThe upper portion of the N layer 12 and the upper portion of the undoped GaN layer 11 have a c-plane orientation, and their surfaces are polar planes. The undoped GaN layer 14 on one side of the opening 13 in FIG. 1 is generally asymmetric with the undoped GaN layer 14 on the opposite side. y Ga 1-y The Al composition y and thickness of the N layer 15 are Al y Ga 1-y N layer 15 and this Al y Ga 1-y The y is selected so that a 2DEG is formed in the undoped GaN layer 11 and the undoped GaN layer 14 in the vicinity of the heterointerface between the upper and lower portions of the undoped GaN layer 11 and the undoped GaN layer 14 where the N layer 15 is in contact, but may also be selected so that a 2DEG is not formed. y is generally 0.15≦y≦0.25.

[0036] Al y Ga 1-y The N layer 15 and the undoped GaN layer 16 are surrounded by Al. x Ga 1-x The N layer 12 is exposed. A p-type GaN layer 17 is stacked on the undoped GaN layer 16 above the opening 13. The p-type GaN layer 17 is doped with magnesium (Mg) as a p-type impurity. The p-type GaN layer 17 is y Ga 1-y The central portion has a depressed shape reflecting the fact that the central portions of the N layer 15 and the undoped GaN layer 16 are depressed.

[0037] A gate electrode 18 is provided on the p-type GaN layer 17. The gate electrode 18 is made of a metal with a large work function, typically nickel (Ni), to make ohmic contact with the p-type GaN layer 17. The gate electrode 18 may be made of a laminated film in which another metal film is laminated on a Ni film. x Ga 1-x On the N layer 12, Al y Ga 1-yA source electrode 19 is provided on one side of the island-shaped laminated structure consisting of the N layer 15 and the undoped GaN layer 16, and a drain electrode 20 is provided on the other side. As will be described later, the source electrode 19 and the drain electrode 20 are formed by bonding the undoped GaN layer 11 and the Al x Ga 1-x The source electrode 19 and the drain electrode 20 are made of a metal with a low work function, typically titanium (Ti), so as to be in ohmic contact with the 2DEG formed in the undoped GaN layer 11 in the vicinity of the heterointerface with the N layer 12. The source electrode 19 and the drain electrode 20 may be made of a laminated film in which an aluminum (Al) film, a nickel (Ni) film, a gold (Au) film, or the like is laminated on a Ti film.

[0038] In this polarization super-junction GaN-based FET, the end of the p-type GaN layer 17 on the drain electrode 20 side and the Al y Ga 1-y The N layer 15 and the undoped GaN layer 16 in the portion between the end of the undoped GaN layer 16 facing the drain electrode 20, Al y Ga 1-y N layer 15, Al x Ga 1-x The N layer 12 and the undoped GaN layer 11 form a polarization super junction region (psj region). y Ga 1-y The distance between the ends of the N layer 15 and the undoped GaN layer 16 facing the drain electrode 20 is the length L psj The p-type GaN layer 17 and the undoped GaN layer 16 directly below the p-type GaN layer 17, Al y Ga 1-y N layer 15, Al x Ga 1-x The N layer 12 and the undoped GaN layer 11 form a gate electrode contact region.

[0039] As shown in Figure 2, in this polarization super-junction GaN-based FET, Al y Ga 1-yThe inclination angle of the portion of the N layer 15 having a plane orientation that forms a semipolar plane inclined to the c-plane, i.e., the inclination angle of the slope of the undoped GaN layer 14, is 5 degrees or more and 90 degrees or less. More specifically, as already mentioned, the undoped GaN layer 14 on one side of the opening 13 and the undoped GaN layer 14 on the opposite side of the opening 13 are generally asymmetric with each other, and therefore, the Al y Ga 1-y Since the N layer 15 is also asymmetric, the inclination angle of the undoped GaN layer 14 on one side, and therefore the Al y Ga 1-y The inclination angle of the N layer 15 is θ1, and the inclination angle of the undoped GaN layer 14 on the opposite side is θ2. y Ga 1-y If the inclination angle of the N layer 15 is θ2, then 5 degrees≦θ1≦90 degrees and 5 degrees≦θ2≦90 degrees. The larger θ1 and θ2 are, the higher the gate threshold voltage tends to be. y Ga 1-y The length of the projection of the portion of the N layer 15 extending from one side of the slope of the undoped GaN layer 14 onto the other side of the slope of the undoped GaN layer 14 onto the undoped GaN layer 11 in the direction connecting the source electrode 19 and the drain electrode 20 is defined as L. r The length of the projection of the slope of the undoped GaN layer 14 on one side onto the undoped GaN layer 11 in the above direction is L s1 The length of the projection of the slope of the undoped GaN layer 14 on the opposite side onto the undoped GaN layer 11 in the above direction is L s2 In general, 0.1cosθ1≦2L s1 / L r ≦1 and 0.1cosθ2≦2L s2 / L r ≦1. L s1 / L r Or L s2 / L r The larger the gate threshold voltage, the higher the gate voltage tends to be. r It is preferable that is small.

[0040] FIG. 3 shows the undoped GaN layer 14 and the Al layer on it on one side of this polarization super-junction GaN-based FET. y Ga 1-y3 is an enlarged cross-sectional view showing a portion including the N layer 15. As shown in FIG. y Ga 1-y The portion of the N layer 15 above the slope of the undoped GaN layer 14 has a plane orientation that is a semipolar plane tilted with respect to the c-plane. y Ga 1-y The polarization field of the N layer 15 (shown by the arrows pointing from + to - in FIG. 3) is y Ga 1-y Since the direction is perpendicular to the surface (growth surface) of the N layer 15, the polarization field strength can be reduced. y Ga 1-y The virtual polarization electric field in the direction perpendicular to the c-plane of the N layer 15 (c-axis direction) is indicated by the dashed arrow. y Ga 1-y Due to the gradient structure of the N layer 15 / undoped GaN layer 14, when the gate voltage applied to the gate electrode 18 is turned off, the undoped GaN layer 14 and Al y Ga 1-y This prevents the formation of 2DEG in at least a portion of the undoped GaN layer 14 near the heterointerface with the N layer 15, which contributes to the normally-off state of the polarization superjunction GaN-based FET through an increase in the gate threshold voltage. y Ga 1-y The Al composition y and thickness of the N layer 15 are determined by taking into consideration the effect of reducing the polarization field strength described above. y Ga 1-y No 2DEG is formed in the undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15, and the Al y Ga 1-y The undoped GaN layer 14 and the Al layer 15 having a c-plane orientation in the portion of the N layer 15 above the top surface of the undoped GaN layer 14 and in the vicinity of the heterointerface between the undoped GaN layer 14 and the undoped GaN layer 14 inside the opening 13. y Ga 1-y The undoped GaN layer 11 in the vicinity of the heterointerface between the N layer 15 and the undoped GaN layer 11 is selected so that a 2DEG is formed.

[0041] [Operation of polarization super-junction GaN-based FET] (When gate voltage is off) The energy band diagram of this polarization super-junction GaN-based FET along the direction of the dashed arrow in Figure 1 when the gate voltage is off is shown in Figure 4, and the energy band diagram along the direction of the dashed arrow in Figure 1 when the gate voltage is off is shown in Figure 6. In Figures 4 and 6, the vertical axis represents the electron energy, E C is the energy at the bottom of the conduction band, E V is the energy at the top of the valence band, E F indicates the Fermi level (the same applies to FIGS. 5 and 7 described later). When the gate voltage is off, as shown in FIG. 1, x Ga 1-x The undoped GaN layer 11 and the undoped GaN layer 11 and Al layer 12 are in the vicinity of the heterointerface between the undoped GaN layer 11 and the Al layer 12. y Ga 1-y The 2DEG 22 is formed in the undoped GaN layer 11 in the vicinity of the heterointerface with the N layer 15, and the Al y Ga 1-y The 2DEG 22 is not formed in the undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15. x Ga 1-x An n-channel 23 is formed near the heterointerface between the N layer 12 and the undoped GaN layer 14, and an n-channel 23 is formed near the heterointerface between the undoped GaN layer 16 and the Al y Ga 1-y The undoped GaN layer 16 is partially doped with Al in the vicinity of the heterointerface between the N layer 15 and the undoped GaN layer 16. y Ga 1-y The 2DHG 21 is formed in the portion excluding the upper portion of the slope of the semipolar surface of the N layer 15. That is, the Al y Ga 1-ySince the 2DEG 22 is not formed in the undoped GaN layer 14 near the heterointerface with the N layer 15, the n-channel between the source electrode 19 and the drain electrode 20 is interrupted in this area. Therefore, this polarization super-junction GaN-based FET is a normally-off type. In FIG. 1, when the gate voltage is off, y Ga 1-y N layer 15 and this Al y Ga 1-y Although the example shows a case where 2DEG 22 is formed in undoped GaN layer 11 and undoped GaN layer 14 in the vicinity of the heterointerface between undoped GaN layer 11 and the upper base portion of undoped GaN layer 14 where N layer 15 is in contact, there is also a case where 2DEG 22 is not formed.

[0042] (When gate voltage is on) A gate voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 18 of this polarization super-junction GaN-based FET. FIG. 5 shows the energy band diagram of this polarization super-junction GaN-based FET along the direction of the dashed arrow in FIG. 1 when the gate voltage is on, and FIG. 7 shows the energy band diagram along the direction of the dashed arrow in FIG. 1 when the gate voltage is on. In FIGS. 5 and 7, E Fn is the electron quasi-Fermi level, E Fp indicates the quasi-Fermi level of holes. At this time, as shown in FIG. 8, the undoped GaN layer 14 and the Al y Ga 1-y Since a 2DEG 22 is induced in the undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15, a continuous n-channel is formed between the source electrode 19 and the drain electrode 20. At this time, by applying a positive voltage to the drain electrode 20 with respect to the source electrode 19 in advance, a current flows from the drain electrode 20 to the source electrode 19. In this way, the polarization super-junction GaN-based FET is turned on.

[0043] [Manufacturing method for polarization super-junction GaN-based FET] As shown in FIG. 9, first, a buffer layer, an undoped GaN layer 11, and an Al layer are grown on a substrate 10 by, for example, a conventionally known MOCVD (metal organic chemical vapor deposition) method using TMG (trimethylgallium) as a Ga source, TMA (trimethylaluminum) as an Al source, NH3 (ammonia) as a nitrogen source, and N2 gas and H2 gas as carrier gases. x Ga 1-x The undoped GaN layer 11 and the AlN layer 12 are grown sequentially. x Ga 1-x The growth temperature of the N layer 12 is, for example, about 1100° C. The undoped GaN layer 11 and the Al x Ga 1-x Hydrogen (H2) and nitrogen (N2) are used as carrier gases when growing the N layer 12. The substrate 10 can be a sapphire substrate (e.g., a C-plane sapphire substrate), a Si substrate, a SiC substrate, or the like. The buffer layer can be a GaN layer, an AlN layer, an AlGaN layer, an AlGaN / GaN superlattice layer, or the like. When a GaN layer is used as the buffer layer, it is grown at a low temperature of, for example, about 530°C.

[0044] Next, as shown in Figure 10, x Ga 1-x After forming a mask such as a resist pattern having an opening corresponding to the opening 13 on the N layer 12, Al x Ga 1-x The N layer 12 is etched until the undoped GaN layer 11 is exposed. This etching may be performed until shallow grooves are formed in the undoped GaN layer 11 (over-etching) as needed. Figure 10 shows the case where over-etching is performed until shallow grooves are formed in the undoped GaN layer 11.

[0045] Next, as shown in FIG. 11, an undoped GaN layer 14 is grown by MOCVD on the sidewall of the opening 13 from the sidewall of the opening 13 to a part of the undoped GaN layer 11 inside the opening 13. Subsequently, Al x Ga 1-xThe entire surface including the N layer 12 and the undoped GaN layer 14 is grown by MOCVD. y Ga 1-y An N layer 15, an undoped GaN layer 16, and a p-type GaN layer 17 are grown in this order. The undoped GaN layer 14 starts growing laterally from the sidewall of the opening 13, and stops growing when it reaches the state shown in FIG. 1. y Ga 1-y The growth temperatures of the N layer 15, the undoped GaN layer 16 and the p-type GaN layer 17 are the same as those of the undoped GaN layer 11 and the Al x Ga 1-x The temperature is, for example, about 1100° C., similar to the N layer 12. Biscyclopentadienyl magnesium (CpMg) is used as a p-type dopant when growing the p-type GaN layer 17. y Ga 1-y H2 and N2 are used as carrier gases when growing the N layer 15, the undoped GaN layer 16, and the p-type GaN layer 17.

[0046] Next, a mask (not shown) such as a resist pattern having a shape corresponding to the device formation region is formed on the p-type GaN layer 17, and then the p-type GaN layer 17, the undoped GaN layer 16, and the Al y Ga 1-y N layer 15, Al x Ga 1-x The N layer 12 and the undoped GaN layer 11 are sequentially etched to a depth partway along the thickness direction of the undoped GaN layer 11 to pattern them into a predetermined shape, thereby performing element isolation. Thereafter, the mask is removed.

[0047] Next, a mask (not shown), such as a resist pattern, having a shape corresponding to the planar shape of p-type GaN layer 17 shown in Fig. 1 is formed on p-type GaN layer 17, and then p-type GaN layer 17 is etched using this mask to pattern it into a predetermined shape. The mask is then removed. In this way, p-type GaN layer 17 having the predetermined shape is formed, as shown in Fig. 12.

[0048] Next, a mask (not shown) such as a resist pattern having a shape corresponding to the planar shape of the undoped GaN layer 16 shown in FIG. 1 is formed so as to cover the p-type GaN layer 17, and then the undoped GaN layer 16 and Al y Ga 1-y N layer 15 is Al x Ga 1-x The N layer 12 is etched until it is exposed and patterned into a predetermined shape. After this, the mask is removed. Thus, as shown in FIG. 13, the undoped GaN layer 16 and the Al y Ga 1-y The N layer 15 is patterned into islands.

[0049] Next, the exposed Al x Ga 1-x After forming a source electrode 19 and a drain electrode 20 on the N layer 12 , a gate electrode 18 is formed on the p-type GaN layer 17 .

[0050] As a result of the above, the intended polarization super-junction GaN-based FET shown in Figure 1 is manufactured.

[0051] (Example) L r We fabricated polarization super-junction GaN-based FETs with different θ1 and θ2 angles and evaluated the gate threshold voltage. x Ga 1-x The N layer 12 has x=0.25, a thickness of 40 nm, and Al y Ga 1-y The N layer 15 had a thickness of 15 nm and y=0.17, and the undoped GaN layer 16 had a thickness of 30 nm. y Ga 1-y The distance between the side of the N layer 15 on the source electrode 19 side and the source electrode 19 and Al y Ga 1-y The distance between the drain electrode 20 and the side of the N layer 15 on the drain electrode 20 side is 3 μm. y Ga 1-y The distance between the side surface of N layer 15 on the source electrode 19 side and the side surface of p-type GaN layer 17 on the source electrode 19 side was set to 1 μm. The results were as follows.

[0052] Lr (μm) θ1, θ2 (degrees) Gate threshold voltage (V) 7 9 0.6 5 12 0.8 3 15 1.0

[0053] As described above, according to the first embodiment, when the gate voltage is off, the Al y Ga 1-y Since the 2DEG 22 is not formed in the undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15, a normally-off type polarization super-junction GaN-based FET can be easily realized.

[0054] Second Embodiment [Polarization super-junction GaN-based FET]

[0055] 14, the polarization super-junction GaN-based FET according to the second embodiment differs from the polarization super-junction GaN-based FET according to the first embodiment in that the p-type GaN layer 17 extends to the psj region, as in Patent Document 2. Other aspects are the same as those of the polarization super-junction GaN-based FET according to the first embodiment.

[0056] [Manufacturing method for normally-off polarization super-junction GaN-based FET] The method for manufacturing this normally-off type polarization super junction GaN-based FET is the same as the method for manufacturing the polarization super junction GaN-based FET according to the first embodiment, except that a p-type GaN layer 17 is finally formed on the undoped GaN layer 16 in the gate electrode contact region and the psj region.

[0057] According to the second embodiment, it is possible to obtain the same advantages as the first embodiment.

[0058] Third Embodiment [Polarization super-junction GaN-based FET]

[0059] As shown in Fig. 15, in the polarization super-junction GaN-based FET according to the third embodiment, the sidewall of the opening 13 is perpendicular to the c-plane, and an undoped GaN layer 14 is provided on this sidewall. This undoped GaN layer 14 has a rectangular cross section, and the side surface is perpendicular to the c-plane. x Ga 1-x Al is deposited on the N layer 12, the undoped GaN layer 14, and the undoped GaN layer 11 inside the opening 13. y Ga 1-y An N layer 15, an undoped GaN layer 16, and a p-type GaN layer 17 are sequentially formed. y Ga 1-y The N layer 15 has a cross-sectional shape that is bent perpendicular to the c-plane at the side of the undoped GaN layer 14, reflecting the cross-sectional shape of the undoped GaN layer 14. y Ga 1-y The undoped GaN layer 16 and the p-type GaN layer 17 on the N layer 15 are Al y Ga 1-y The portion of the N layer 15 that corresponds to the portion of the N layer 15 that has a cross-sectional shape that is bent perpendicularly to the c-plane has a cross-sectional shape that is bent obliquely. In this case, the undoped GaN layer 14 has a plane orientation that is a nonpolar plane perpendicular to the c-plane. y Ga 1-y The side surface of the N layer 15 on the undoped GaN layer 14 has a plane orientation that is a nonpolar plane perpendicular to the c-plane, similar to the undoped GaN layer 14. Therefore, when the gate voltage is turned off, the Al y Ga 1-y The undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15 does not have a 2DEG 22, and therefore this polarization super-junction GaN-based FET is normally off. When the gate voltage is on, the Al y Ga 1-y A 2DEG 22 is induced in the undoped GaN layer 14 in the vicinity of the heterointerface with the N layer 15, and the polarization super-junction GaN-based FET is turned on. The other points are the same as those of the polarization super-junction GaN-based FET according to the first embodiment.

[0060] [Manufacturing method for normally-off polarization super-junction GaN-based FET] The method for manufacturing this normally-off type polarization super junction GaN-based FET is the same as the method for manufacturing the polarization super junction GaN-based FET according to the first embodiment.

[0061] According to the third embodiment, it is possible to obtain the same advantages as the first embodiment.

[0062] Although the embodiments and examples of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments and examples, and various modifications based on the technical concept of the present invention are possible.

[0063] For example, the numerical values, structures, shapes, materials, etc. given in the above-described embodiments and examples are merely examples, and different numerical values, structures, shapes, materials, etc. may be used as needed. [Explanation of symbols]

[0064] 10...substrate, 11...undoped GaN layer, 12...Al x Ga 1-x N layer, 13...opening, 14...undoped GaN layer, 15...Al y Ga 1-y N layer, 16... undoped GaN layer, 17... p-type GaN layer, 18... gate electrode, 19... source electrode, 20... drain electrode, 21... 2DHG, 22... 2DEG, 23... n-channel

Claims

1. a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a part of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and provided to extend on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; a fifth semiconductor layer above the fourth semiconductor layer; a sixth semiconductor layer above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; a gate electrode electrically connected to the sixth semiconductor layer; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers; the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; At least a part of the fourth semiconductor layer on the third semiconductor layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

2. 2. The polarization superjunction field effect transistor of claim 1, wherein said third semiconductor layer has a trapezoidal cross-sectional shape.

3. 3. The polarization superjunction field effect transistor according to claim 1, wherein said opening has an inverted trapezoidal cross section.

4. 3. The polarization superjunction field effect transistor according to claim 1, wherein, when a gate voltage applied to the gate electrode is turned off, a two-dimensional electron gas is formed in the first semiconductor layer in a portion near a heterointerface between the first semiconductor layer and the second semiconductor layer, and a two-dimensional electron gas is formed in the first semiconductor layer in a portion near a heterointerface between the first semiconductor layer and the fourth semiconductor layer, or, alternatively, no two-dimensional electron gas is formed, and no two-dimensional electron gas is formed in at least a part of the third semiconductor layer in a portion near a heterointerface between the third semiconductor layer and the fourth semiconductor layer, an n-channel is formed in the vicinity of the heterointerface between the second semiconductor layer and the third semiconductor layer, and a two-dimensional hole gas is partially formed in the fifth semiconductor layer in a portion near a heterointerface between the fifth semiconductor layer and the fourth semiconductor layer.

5. a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layers (0<x<1), a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-x an N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layers (y<x), The above Al y Ga 1-y a third undoped GaN layer above the N layer; a p-type GaN layer above the third undoped GaN layer; The above Al x Ga 1-x a source electrode and a drain electrode on the N layer; a gate electrode electrically connected to the p-type GaN layer; and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-y At least a portion of the N layer above the second undoped GaN layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

6. 6. The polarization superjunction field effect transistor of claim 5, wherein said second undoped GaN layer has a trapezoidal cross-sectional shape.

7. 7. The polarization superjunction field effect transistor according to claim 5, wherein said opening has an inverted trapezoidal cross section.

8. When the gate voltage applied to the gate electrode is turned off, the first undoped GaN layer and the Al x Ga 1-x A two-dimensional electron gas is formed in the first undoped GaN layer in a portion near a heterointerface between the first undoped GaN layer and the Al layer. y Ga 1-y A two-dimensional electron gas is formed in the first undoped GaN layer in a portion near a heterointerface between the first undoped GaN layer and the Al layer, or a two-dimensional electron gas is not formed in the first undoped GaN layer in a portion near a heterointerface between the second undoped GaN layer and the Al layer. y Ga 1-y A two-dimensional electron gas is not formed in at least a part of the second undoped GaN layer in the vicinity of a heterointerface with the N layer, and the Al x Ga 1-x An n-channel is formed in the vicinity of a heterointerface between the N layer and the second undoped GaN layer, and an n-channel is formed in the vicinity of a heterointerface between the third undoped GaN layer and the Al y Ga 1-y 7. The polarization superjunction field effect transistor according to claim 5, wherein a two-dimensional hole gas is partially formed in said third undoped GaN layer in the vicinity of the heterointerface with the N layer.

9. The above Al y Ga 1-y 6. The polarization superjunction field effect transistor according to claim 5, wherein the inclination angle of at least a part of the N layer on said second undoped GaN layer with respect to the c-plane is between 5 degrees and 90 degrees.

10. The second undoped GaN layer has a trapezoidal cross section, and the Al y Ga 1-y The length of the projection of the portion of the N layer extending from the slope of the second undoped GaN layer on one side to the slope of the second undoped GaN layer on the opposite side onto the first undoped GaN layer in the direction connecting the source electrode and the drain electrode is L. r The length of the projection of the slope of the second undoped GaN layer on one side onto the first undoped GaN layer in the above direction is L s1 , the length of the projection of the slope of the second undoped GaN layer on the opposite side onto the first undoped GaN layer in the above direction is L s2 , the above Al y Ga 1-y The inclination angle of at least a part of the portion of the N layer on the second undoped GaN layer on one side thereof with respect to the c-plane is θ 1 , the above Al y Ga 1-y The inclination angle of at least a part of the N layer on the second undoped GaN layer on the opposite side with respect to the c-plane is θ 2 When this is the case, 0.1 cosθ 1 ≦2L s1 / L r ≦1 and 0.1 cos θ 2 ≦2L s2 / L r 6. The polarization superjunction field effect transistor of claim 5, wherein .ltoreq.

1.

11. a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a part of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and provided to extend on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer and the third semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer and the third semiconductor layer are undoped semiconductor layers, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; A semiconductor laminated structure in which at least a part of the portion of the fourth semiconductor layer on the third semiconductor layer has a plane orientation that forms a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

12. a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layers (0<x<1), a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-x an N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layers (y<x), and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-y The semiconductor laminated structure has a plane orientation in which at least a part of the N layer on the second undoped GaN layer is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane.

13. having at least one transistor, The transistor is a first semiconductor layer; a second semiconductor layer above the first semiconductor layer and having an opening; a third semiconductor layer provided on a sidewall of the opening and on a part of the first semiconductor layer inside the opening; a fourth semiconductor layer having an island shape and provided to extend on the second semiconductor layer, the third semiconductor layer, and the first semiconductor layer inside the opening; a fifth semiconductor layer above the fourth semiconductor layer; a sixth semiconductor layer above the fifth semiconductor layer; a source electrode and a drain electrode on the second semiconductor layer; a gate electrode electrically connected to the sixth semiconductor layer; and the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer are Group III nitride semiconductor layers; the band gaps of the second semiconductor layer and the fourth semiconductor layer are larger than the band gaps of the first semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the band gap of the fourth semiconductor layer is smaller than the band gap of the second semiconductor layer; the first semiconductor layer and the third semiconductor layer have the same band gap; the first semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer are undoped semiconductor layers; the sixth semiconductor layer is a p-type semiconductor layer, the first semiconductor layer and the second semiconductor layer have a c-plane orientation; a polarization superjunction field effect transistor in which at least a part of the portion of the fourth semiconductor layer on the third semiconductor layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane; Electrical equipment.

14. having at least one transistor, The transistor is a first undoped GaN layer; an Al layer having an opening above the first undoped GaN layer; x Ga 1-x N layers (0<x<1), a second undoped GaN layer provided on a portion of the first undoped GaN layer extending from a sidewall of the opening to the interior of the opening; The above Al x Ga 1-x an N layer, the second undoped GaN layer, and an island-shaped Al layer extending on the first undoped GaN layer inside the opening; y Ga 1-y N layers (y<x), The above Al y Ga 1-y a third undoped GaN layer above the N layer; a p-type GaN layer above the third undoped GaN layer; The above Al x Ga 1-x a source electrode and a drain electrode on the N layer; a gate electrode electrically connected to the p-type GaN layer; and the first undoped GaN layer and the Al x Ga 1-x The N layer has a c-plane orientation, The above Al y Ga 1-y A polarization superjunction field effect transistor in which at least a part of the N layer on the second undoped GaN layer has a plane orientation that is a semipolar plane tilted with respect to the c-plane or a nonpolar plane perpendicular to the c-plane. Electrical equipment.

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