nitride semiconductor devices

Abstract

Improve gate reliability. [Solution] The nitride semiconductor device includes a gate layer (30), a gate wiring (72) connected to a gate electrode (40) through a gate via (72A), an active region (A1), and a non-active region (A2) adjacent to the active region (A1) and in which the gate via (72A) and the gate wiring (72) are arranged. The gate layer (30) includes a portion located in the active region (A1), a plurality of main gate portions (30C) extending in a second direction and spaced apart in a first direction, a via connection portion (30D) located in a region in the non-active region (A2) between two main gate portions (30C) adjacent to each other in the first direction and connected to the gate via (72A), and a linking portion (30E) independently linking the ends of the two main gate portions (30C) adjacent to each other in the first direction to the via connection portion (30D). The linking portion (30E) includes a diagonal portion (30E1) extending diagonally relative to the main gate portions (30C).

Description

[Technical Field]

[0001] The present invention relates to a nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use the two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as the conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer. Furthermore, in the nitride semiconductor device described in Patent Document 1, a gate layer, which is a GaN layer (p-type GaN layer) doped with acceptor-type impurities, is provided on the electron supply layer and directly below the gate electrode. In this configuration, the gate layer raises the energy level of the conduction band in the region directly below it near the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer. This allows the nitride semiconductor device to operate normally off. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0005] [overview] As described above, in a nitride semiconductor device including a gate layer and a gate electrode formed on the gate layer, gate reliability may decrease due to deterioration of the Schottky junction between the gate layer and the gate electrode.

[0006] a gate electrode located on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, the passivation layer having a source opening and a drain opening spaced apart from each other in a first direction; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening; and a gate wiring located on the passivation layer and electrically connected to the gate electrode through a gate via passing through the passivation layer. In a planar view, the gate layer includes an active region including the source electrode and the drain electrode, and a non-active region that is located adjacent to the active region in a second direction perpendicular to the first direction and in which the gate via and the gate wiring are located, the gate layer including a portion located in the active region, a plurality of main gate portions that extend in the second direction and are spaced apart in the first direction, a via connection portion that is located in a region in the non-active region between two of the main gate portions that are adjacent in the first direction and is connected to the gate via, and a connecting portion that independently connects the ends of the two main gate portions that are adjacent in the first direction to the via connection portion, and the connecting portion includes a diagonal portion that extends diagonally relative to the main gate portions. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. [Figure 2]FIG. 2 is a schematic plan view showing a part of the interior of the nitride semiconductor device of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. [Figure 4] FIG. 4 is an enlarged view of a portion of FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. [Figure 6] 6A to 6C are schematic cross-sectional views showing exemplary manufacturing steps for a nitride semiconductor device. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] 8A to 8C are schematic cross-sectional views showing an exemplary manufacturing process for the portion of the nitride semiconductor device shown in FIG. 3 subsequent to the process shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] 14A to 14C are schematic cross-sectional views showing an exemplary manufacturing process for the portion of the nitride semiconductor device shown in FIG. 5 subsequent to the process shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG.

[0008] [Detailed explanation] Hereinafter, embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] Terms such as "first," "second," and "third" used in this disclosure are used to clearly distinguish components of an object and are not used to rank the objects. Furthermore, the expression "at least one" used in this disclosure means one or more of a desired plurality of options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [Overall configuration of nitride semiconductor device] The overall configuration of a nitride semiconductor device 10 according to the first embodiment will be described with reference to Figures 1 to 3. Figure 1 shows a schematic planar structure of an exemplary nitride semiconductor device 10 according to the first embodiment. Figure 2 shows a schematic enlarged planar structure of a portion of the internal structure of the nitride semiconductor device 10 of Figure 1. Figure 3 shows a schematic cross-sectional structure of the nitride semiconductor device 10 taken along line F3-F3 of Figure 2.

[0012] As shown in FIG. 1, the nitride semiconductor device 10 includes a chip body 12. The chip body 12 is formed, for example, in the shape of a rectangular flat plate. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 and other drawings is a direction orthogonal to the main surface of the chip body 12 (top surface 13 in FIG. 1). The term "plan view" used in this disclosure refers to viewing the nitride semiconductor device 10 from above in the Z-axis direction, unless explicitly stated otherwise.

[0013] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. In the example shown in FIG. 1 , the nitride semiconductor device 10 includes one gate pad 14, multiple source pads 16, and multiple drain pads 18. The gate pad 14, multiple source pads 16, and multiple drain pads 18 are formed on the top surface 13 of the chip body 12. These pads 14, 16, and 18 can be used as external connection terminals of the nitride semiconductor device 10.

[0014] Each of the gate pad 14, the source pad 16, and the drain pad 18 is formed, for example, in a rectangular shape in a plan view. The gate pad 14 can be disposed, for example, at one corner of the upper surface 13. Each of the source pads 16 and the drain pad 18 extends in the Y-axis direction in a plan view. The source pads 16 and the drain pads 18 are alternately arranged one by one in the X-axis direction, which is perpendicular to the Y-axis direction. In this way, each of the source pads 16 and the drain pads 18 can be said to extend in a direction (Y-axis direction) perpendicular to the arrangement direction of these pads 16, 18 in a plan view. Note that the shapes of each of the gate pad 14, the source pad 16, and the drain pad 18 in a plan view can be arbitrarily changed. Furthermore, the arrangement of the gate pad 14, the source pad 16, and the drain pad 18 can be arbitrarily changed.

[0015] 3, the nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a substrate 20, a buffer layer 22 formed on the substrate 20, an electron transit layer 24 formed on the buffer layer 22, and an electron supply layer 26 formed on the electron transit layer 24.

[0016] The substrate 20 may be made of silicon (Si), alumina (Al2O3), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the substrate 20 is a heterogeneous substrate such as silicon (Si), aluminum oxide (Al2O3), or silicon carbide (SiC). In one example, the substrate 20 is a Si substrate. The thickness of the substrate 20 may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction corresponds to the thickness direction of the substrate 20.

[0017] The buffer layer 22 may be made of any material capable of suppressing wafer warpage and cracking due to mismatch in thermal expansion coefficients between the substrate 20 and the electron transit layer 24. The buffer layer 22 may include one or more nitride semiconductor layers. For example, the buffer layer 22 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 22 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0018] The electron transport layer 24 is composed of a nitride semiconductor. The electron transport layer 24 may be, for example, a GaN layer. The thickness of the electron transport layer 24 may be, for example, 0.1 μm or more and 2 μm or less. The electron transport layer 24 may include one or more nitride semiconductor layers. Also, in order to suppress the leakage current in the electron transport layer 24, impurities may be introduced into a part of the electron transport layer 24 to make the region other than the surface layer region of the electron transport layer 24 semi-insulating. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon is, for example, 1×10 19 cm -3 or more.

[0019] The electron supply layer 26 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 24. The electron supply layer 26 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 26 which is an AlGaN layer has a larger bandgap than the electron transport layer 24 which is a GaN layer. In one example, the electron supply layer 26 is composed of Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 26 may be, for example, 5 nm or more and 20 nm or less.

[0020] The electron transport layer 24 and the electron supply layer 26 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 24 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 26 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 24 and the electron supply layer 26 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the electron transport layer 24, the energy level of the conduction band of the electron transport layer 24 near the hetero-junction interface between the electron transport layer 24 and the electron supply layer 26 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 28 is formed in the electron transport layer 24 at a position close to the hetero-junction interface between the electron transport layer 24 and the electron supply layer 26 (for example, at a distance of about several nm from the interface).

[0021] The nitride semiconductor device 10 includes a gate layer 30 formed on a portion of the electron supply layer 26 , and a gate electrode 40 formed on the gate layer 30 . The gate layer 30 is made of a nitride semiconductor. In one example, the gate layer 30 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 26 and containing acceptor-type impurities. In one example, the gate layer 30 is GaN doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0022] The gate electrode 40 includes one or more metal layers. In one example, the gate electrode 40 may be a titanium nitride (TiN) layer. In another example, the gate electrode 40 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 40 is composed of a material that forms a Schottky junction with the gate layer 30. An example of such a material is TiN. The thickness of the gate electrode 40 may be, for example, 50 nm or more and 200 nm or less.

[0023] The nitride semiconductor device 10 includes a first passivation layer 50. The first passivation layer 50 covers the electron supply layer 26, the gate layer 30, and the gate electrode 40. The first passivation layer 50 may be composed of, for example, one or any combination of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON). The thickness of the first passivation layer 50 may be, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm. The first passivation layer 50 includes a source opening 50A and a drain opening 50B, each of which exposes a portion of the upper surface 26A of the electron supply layer 26. In the first passivation layer 50, the source opening 50A and the drain opening 50B are spaced apart from each other in the X-axis direction, which is the first direction.

[0024] The nitride semiconductor device 10 includes a source electrode 42 formed in the source opening 50A and a drain electrode 44 formed in the drain opening 50B. The source electrode 42 includes a source contact portion 42A that contacts the electron supply layer 26 through the source opening 50A. The drain electrode 44 includes a drain contact portion 44A that contacts the electron supply layer 26 through the drain opening 50B.

[0025] The source electrode 42 and the drain electrode 44 include one or more metal layers. In one example, the source electrode 42 and the drain electrode 44 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 42 and the drain electrode 44 are composed of a first metal layer in contact with the electron supply layer 26, a second metal layer stacked on the second metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0026] A source contact portion 42A of the source electrode 42 is filled in the source opening 50A. The source contact portion 42A is in ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the source opening 50A. A drain contact portion 44A of the drain electrode 44 is filled in the drain opening 50B. The drain contact portion 44A is in ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the drain opening 50B. Although not shown, the substrate 20 is electrically connected to the source electrode 42. As a result, a voltage having the same potential as that of the source electrode 42 is applied to the substrate 20.

[0027] In a structure in which the gate layer 30 is formed of a nitride semiconductor containing acceptor-type impurities, the conduction path (channel) is blocked by depletion of the 2DEG 28 in the region directly below the gate layer 30 at zero bias, i.e., when no voltage is applied to the gate electrode 40. This realizes a normally-off HEMT in which the gate threshold voltage is a positive value.

[0028] The nitride semiconductor device 10 includes a field plate electrode 46 provided on the first passivation layer 50. The field plate electrode 46 is electrically connected to the source electrode 42. In the example shown in FIG. 3, the field plate electrode 46 is formed integrally with the source electrode 42. That is, a part of the source electrode 42 is provided as the field plate electrode 46. Therefore, a voltage having the same potential as that of the source electrode 42 is applied to the field plate electrode 46. The field plate electrode 46 is also called a source field plate. The field plate electrode 46 covers the entire gate layer 30 in a plan view.

[0029] The field plate electrode 46 is spaced apart from the drain electrode 44. The field plate electrode 46 includes an end 46A located between the gate layer 30 and the drain electrode 44 in a plan view. The field plate electrode 46 plays a role in reducing electric field concentration near the end of the gate electrode 40 and in the gate layer 30 when a drain voltage is applied to the drain electrode 44 in a zero bias state where no voltage is applied to the gate electrode 40.

[0030] The nitride semiconductor device 10 includes a second passivation layer 60, a source wiring 74, and a drain wiring 76. The second passivation layer 60 covers the source electrode 42 and the drain electrode 44. If a field plate electrode 46 is provided, the second passivation layer 60 also covers the field plate electrode 46. The second passivation layer 60 has a source wiring opening 60A and a drain wiring opening 60B. The source wiring opening 60A exposes the source electrode 42 from the second passivation layer 60. The drain wiring opening 60B exposes the drain electrode 44 from the second passivation layer 60.

[0031] The second passivation layer 60 may be made of a material containing, for example, any one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the second passivation layer 60 is made of a material containing SiO2. In this embodiment, the first passivation layer 50 and the second passivation layer 60 form a passivation layer.

[0032] A source wiring 74 and a drain wiring 76 are disposed on the second passivation layer 60 so as to be spaced apart from each other. The source wiring 74 contacts the source electrode 42 through a source wiring opening 60A. The drain wiring 76 contacts the drain electrode 44 through a drain wiring opening 60B.

[0033] Each of the source wiring 74 and the drain wiring 76 is made of one or more metal layers. The metal layers may be made of a material containing any one of copper (Cu), Al, Ti, and TiN. In one example, each of the source wiring 74 and the drain wiring 76 is formed of a stacked structure of Ti, TiN, AlCu, and TiN.

[0034] For example, the source wiring 74 and the drain wiring 76 are covered by an interlayer insulating layer (not shown). In one example, the source pad 16 and the drain pad 18 shown in FIG. 1 are formed on the interlayer insulating layer. For example, the source wiring 74 is connected to the source pad 16 by a source connecting conductor (not shown) that penetrates the interlayer insulating layer. The drain wiring 76 is connected to the drain pad 18 by a drain connecting conductor (not shown) that penetrates the interlayer insulating layer.

[0035] [Cross-sectional shape of gate layer] The gate layer 30 is in contact with the electron supply layer 26 and includes a ridge portion 32 including an upper surface 30A on which the gate electrode 40 is formed. The gate layer 30 is in contact with the electron supply layer 26 and may include an extension portion 33 that is thinner than the ridge portion 32 and extends outward in a planar view from the ridge portion 32. The extension portion 33 may include a source-side extension portion 34 and a drain-side extension portion 36.

[0036] The source-side extension 34 extends from the ridge 32 toward the source opening 50A. The source-side extension 34 partially covers the surface of the electron supply layer 26 between the ridge 32 and the source opening 50A in a plan view. The source-side extension 34 does not reach the source electrode 42 embedded in the source opening 50A.

[0037] The drain-side extension 36 extends from the ridge 32 toward the drain opening 50B. The drain-side extension 36 partially covers the surface of the electron supply layer 26 between the ridge 32 and the drain opening 50B in a plan view. The drain-side extension 36 does not reach the drain electrode 44 embedded in the drain opening 50B.

[0038] The ridge portion 32 is located between the source side extension portion 34 and the drain side extension portion 36, and is formed integrally with the source side extension portion 34 and the drain side extension portion 36. Due to the presence of the source side extension portion 34 and the drain side extension portion 36, the bottom surface 30B of the gate layer 30 has a larger area than the top surface 30A.

[0039] In the example shown in FIG. 3 , the drain-side extension 36 may extend further outward from the ridge 32 in a planar view than the source-side extension 34. That is, the drain-side extension 36 may have a dimension in the X-axis direction that is larger than that of the source-side extension 34. The source-side extension 34 may have a dimension in the X-axis direction that is, for example, not less than 0.2 μm and not more than 0.3 μm. On the other hand, the drain-side extension 36 may have a dimension in the X-axis direction that is, for example, not less than 0.2 μm and not more than 0.6 μm. Note that, when a field plate electrode 46 is provided, an end 46A of the field plate electrode 46 may be located between the drain-side extension 36 and the drain electrode 44 in a planar view.

[0040] The ridge portion 32 corresponds to a relatively thick portion of the gate layer 30. The ridge portion 32 may have a thickness of, for example, 80 nm or more and 150 nm or less. In one example, the ridge portion 32 may have a thickness greater than 110 nm. The source side extension portion 34 and the drain side extension portion 36 have a thickness smaller than that of the ridge portion 32. In one example, the source side extension portion 34 and the drain side extension portion 36 may have a thickness equal to or less than half the thickness of the ridge portion 32.

[0041] Each of the source side extension 34 and the drain side extension 36 may include a flat portion having a substantially constant thickness. For example, the flat portion of the source side extension 34 and the drain side extension 36 may have a thickness of 5 nm or more and 25 nm or less. In this specification, "substantially constant thickness" refers to a thickness that is within a manufacturing variation range (e.g., 20%). Although not shown, each of the source side extension 34 and the drain side extension 36 may further include an intermediate portion between the flat portion and the ridge portion 32 that is thicker than the flat portion. For example, the intermediate portion may have a thickness that gradually decreases with increasing distance from the ridge portion 32.

[0042] [Example Planar Layout of a Nitride Semiconductor Device] Next, an exemplary formation pattern 100 of a HEMT structure (nitride semiconductor device 10) will be described with reference to FIG. 2. FIG. 4 is an enlarged view of a portion of the formation pattern 100 shown in FIG. 2. For ease of understanding, the same components in FIGS. 2 and 4 as those in FIG. 3 are denoted by the same reference numerals. The first passivation layer 50, the source electrode 42, and the second passivation layer 60 are depicted as being transparent so that the gate layer 30 and the gate electrode 40 can be seen. The end 46A of the field plate electrode 46 and the drain electrode 44 are depicted with dashed lines. The gate wiring 72, the source wiring 74, and the drain wiring 76 are depicted with two-dot chain lines. The gate wiring 72, the source wiring 74, and the drain wiring 76 each extend in the X-axis direction and are spaced apart from one another in the Y-axis direction. Details of the gate wiring 72 will be described later.

[0043] As shown in FIG. 2, a plurality of source openings 50A and a plurality of drain openings 50B are formed in the first passivation layer 50 (see FIG. 3). The plurality of source openings 50A and the plurality of drain openings 50B are alternately formed one by one in the X-axis direction. The source openings 50A and the drain openings 50B adjacent to each other in the X-axis direction are formed with an interval in the X-axis direction. Each source opening 50A and each drain opening 50B extends in the Y-axis direction in a planar view. Here, in this embodiment, the X-axis direction corresponds to the "first direction," and the Y-axis direction corresponds to the "second direction." Therefore, the second direction is perpendicular to the first direction in a planar view.

[0044] In the illustrated example, the source openings 50A are spaced apart from each other in a row in pairs in the Y-axis direction, and the drain openings 50B are spaced apart from each other in a row in pairs in the Y-axis direction.

[0045] Because each source opening 50A is filled with a source contact portion 42A and each drain opening 50B is filled with a drain contact portion 44A, it can be said that the multiple source contact portions 42A and the multiple drain contact portions 44A are alternately arranged one by one in the X-axis direction. It can also be said that the source contact portions 42A and the drain contact portions 44A that are adjacent in the X-axis direction are arranged with a gap in the X-axis direction. It can also be said that the multiple source contact portions 42A are arranged in a row, two by two, spaced apart from each other in the Y-axis direction. It can also be said that the multiple drain contact portions 44A are arranged in a row, two by two, spaced apart from each other in the Y-axis direction.

[0046] Each source contact portion 42A and each drain contact portion 44A extends in the Y-axis direction in plan view. A field plate electrode 46 (see FIG. 3) is formed over substantially the entire forming pattern 100. A plurality of drain electrode openings 46B that form an end portion 46A are formed in the field plate electrode 46. A drain electrode 44 is formed in each drain electrode opening 46B. In other words, the field plate electrode 46 is formed so as to surround the drain electrode 44 in plan view.

[0047] Here, the formation pattern 100 includes an active region A1 that contributes to transistor operation and an inactive region A2 that does not contribute to transistor operation. In the illustrated example, the active region A1 and the inactive region A2 are partitioned in the Y-axis direction. That is, the active region A1 and the inactive region A2 are formed side by side in the Y-axis direction.

[0048] The active region A1 is a region including the source electrode 42, the drain electrode 44, and the gate electrode 40. The active region A1 includes a region where a current flows between the source and drain when a voltage is applied to the gate electrode 40. The active region A1 extends in the X-axis direction. The active region A1 includes a source opening 50A and a drain opening 50B. In the illustrated example, two source openings 50A and two drain openings 50B are formed in the Y-axis direction, and therefore two active regions A1 are formed spaced apart from each other in the Y-axis direction. In other words, the number of active regions A1 is set according to the number of source openings 50A or drain openings 50B arranged in the Y-axis direction. In each active region A1, the structure of the nitride semiconductor device shown in FIG. 3 is repeatedly and continuously formed along the X-axis direction.

[0049] The inactive region A2 is disposed adjacent to the active region A1 in the Y-axis direction (second direction) perpendicular to the X-axis direction (first direction), and is a region in which a gate via 72A and a gate wiring 72 (described later) are disposed. The inactive region A2 refers to a region that does not contribute to determining the amount of current flowing between the source and drain when a voltage is applied to the gate electrode 40.

[0050] In one example, the non-active region A2 is a region in which the drain electrode 44 (drain opening 50B) is not provided in the Y-axis direction. The non-active region A2 includes a first region in which the source electrode 42 (source opening 50A) is provided in the Y-axis direction but the drain electrode 44 is not provided. The non-active region A2 also includes a second region in which neither the source electrode 42 (source opening 50A) nor the drain electrode 44 (drain opening 50B) is provided in the Y-axis direction. Note that when the positions of both ends of the drain electrode 44 (drain opening 50B) and the positions of both ends of the source electrode 42 (source opening 50A) are aligned in the Y-axis direction, the first region is not formed.

[0051] The inactive region A2 is disposed adjacent to one active region A1 in the Y-axis direction, and the inactive region A2 is disposed between two active regions A1 aligned in the Y-axis direction. The gate layer 30 and the gate electrode 40 are formed continuously between the active region A1 and the non-active region A2 adjacent to each other in the Y-axis direction. In the active region A1, two gate layers 30 and gate electrodes 40 arranged side by side in the X-axis direction with the source electrode 42 (source opening 50A) sandwiched therebetween are connected to each other in the non-active region A2. As a result, the gate layer 30 and the gate electrode 40 are formed in a ring shape surrounding the source electrode 42 (source opening 50A) in a plan view.

[0052] [Gate layer layout] As shown in FIG. 4, the gate layer 30 includes a main gate portion 30C, a via connection portion 30D, and a linking portion 30E.

[0053] The main gate portion 30C extends in the Y-axis direction, including a portion located in the active region A1. A plurality of main gate portions 30C are arranged spaced apart in the X-axis direction. An end of the main gate portion 30C may be located outside the active region A1, i.e., in the non-active region A2.

[0054] The cross-sectional shape of the main gate portion 30C is the same throughout the Y-axis direction. Therefore, the portion of the main gate portion 30C located in the inactive region A2 also includes the ridge portion 32, source-side extension portion 34, and drain-side extension portion 36, all of which have the same cross-sectional shape. Furthermore, a gate electrode 40 is located on the ridge portion 32 of the main gate portion 30C throughout the Y-axis direction. The cross-sectional shape of the gate electrode 40 on the main gate portion 30C is the same throughout the Y-axis direction.

[0055] Here, the width of the upper surface 30A of the gate layer 30 in the main gate portion 30C is defined as width H1 (hereinafter referred to as width H1 of the main gate portion 30C). The width H1 of the main gate portion 30C is, for example, not less than 600 nm and not more than 800 nm.

[0056] The width of the gate electrode 40 in the main gate portion 30C is defined as width H2 (hereinafter referred to as electrode width H2 of the main gate portion 30C). The electrode width H2 of the main gate portion 30C is, for example, not less than 500 nm and not more than 700 nm.

[0057] The separation distance in the X-axis direction between two adjacent main gate portions 30C sandwiching the source opening 50A (source electrode 42) in the X-axis direction is defined as separation distance L1 (hereinafter referred to as separation distance L1 of the main gate portions 30C). The separation distance L1 of the main gate portions 30C is, for example, 2.2 μm or more and 2.6 μm or less.

[0058] The via connection portion 30D is disposed in a region in the inactive region A2 between two main gate portions 30C adjacent to each other in the X-axis direction with a source opening 50A sandwiched therebetween. The via connection portion 30D is disposed in a region between two source openings 50A (source electrodes 42) adjacent to each other in the Y-axis direction, spaced apart from the two source openings 50A. The shape of the via connection portion 30D in a planar view is not particularly limited, and may be, for example, a polygonal, circular, or elliptical shape. An example of the shape of the via connection portion 30D in a planar view is a polygonal shape such as an octagonal shape.

[0059] The via connection portion 30D is connected to the end portion in the Y-axis direction of the main gate portion 30C via the linking portion 30E. The linking portion 30E independently links the end portion of each of the two main gate portions 30C adjacent to each other in the X-axis direction with the source opening 50A in between to the via connection portion 30D. Therefore, the two main gate portions 30C adjacent to each other in the X-axis direction with the source opening 50A in between are connected to each other via the two linking portions 30E and the via connection portion 30D.

[0060] In one example, the via connection portion 30D is connected to four main gate portions 30C via the connecting portion 30E. The four main gate portions 30C include two main gate portions 30C arranged in the X-axis direction with the source electrode 42 sandwiched therebetween, and two main gate portions 30C arranged in the Y-axis direction with the inactive region A2 sandwiched therebetween. In other words, the four main gate portions 30C are connected to each other via the via connection portion 30D and the connecting portion 30E. Note that in the inactive region A2, the main gate portions 30C connected to each other via the via connection portion 30D and the connecting portion 30E may be only the two main gate portions 30C arranged in the X-axis direction with the source electrode 42 sandwiched therebetween.

[0061] Each of the coupling portions 30E includes a diagonal line portion 30E1 extending diagonally relative to the main gate portion 30C in a plan view. The diagonal line portion 30E1 extends diagonally from the end of the main gate portion 30C toward the via connection portion 30D and linearly in a direction approaching the via connection portion 30D. In the example shown in FIGS. 2 and 4, the entire coupling portion 30E is the diagonal line portion 30E1. In other words, a first end portion, which is an end portion on one side of the diagonal line portion 30E1, is coupled to the main gate portion 30C, and a second end portion, which is an end portion on the other side of the diagonal line portion 30E1, is coupled to the via connection portion 30D. In this case, the diagonal line portion 30E1 may couple the end of the main gate portion 30C and the via connection portion 30D over the shortest distance.

[0062] The inclination angle θ of the oblique line portion 30E1 relative to the main gate portion 30C may be, for example, 30 degrees or more and 60 degrees or less. The inclination angle θ is preferably 35 degrees or more and 55 degrees or less, and more preferably 40 degrees or more and 50 degrees or less. The inclination angle θ is preferably set so that the end of the main gate portion 30C and the via connection portion 30D can be connected over a shorter distance.

[0063] 2 and 4, the entire coupling portion 30E is shown as the hatched portion 30E1, but a portion of the coupling portion 30E may be shown as the hatched portion 30E1. For example, the coupling portion 30E may have a portion other than the hatched portion 30E1, such as a curved portion or an irregularly shaped portion, between one or both of the first end of the hatched portion 30E1 and the main gate portion 30C and between the second end of the hatched portion 30E1 and the via connection portion 30D. In this case, the length ratio of the hatched portion 30E1 to one coupling portion 30E in the extension direction of the coupling portion 30E is, for example, 50% or more, and preferably 75% or more.

[0064] The coupling portion 30E, including the hatched portion 30E1, includes a ridge portion 32, a source-side extension portion 34, and a drain-side extension portion 36, similar to the main gate portion 30C. The source-side extension portion 34 of the coupling portion 30E is continuous with the source-side extension portion 34 of the main gate portion 30C and is formed along the edge of the hatched portion 30E1. Similarly, the drain-side extension portion 36 of the coupling portion 30E is continuous with the drain-side extension portion 36 of the main gate portion 30C and is formed along the edge of the hatched portion 30E1.

[0065] The cross-sectional shape of the coupling portion 30E, as an example, is the same as that of the main gate portion 30C. The cross-sectional shape of the coupling portion 30E, including the hatched portion 30E1, may be partially or entirely different from that of the main gate portion 30C. For example, the width of the ridge portion 32 of the coupling portion 30E may be different from that of the main gate portion 30C, or one or both of the source-side extension portion 34 and the drain-side extension portion 36 may be omitted.

[0066] The width of the upper surface 30A of the gate layer 30 at the hatched portion 30E1 is defined as width H3 (hereinafter referred to as width H3 of the hatched portion 30E1). The width H3 of the hatched portion 30E1 is, for example, 1.5 times or less the width H1 of the main gate portion 30C. The width H3 of the hatched portion 30E1 is, for example, 0.75 times or more the width H1 of the main gate portion 30C. The width H3 of the hatched portion 30E1 may be constant or may vary in its extension direction. For example, the width H3 of the hatched portion 30E1 is the same as the width H1 of the main gate portion 30C and is constant in its extension direction. In this case, the average width of the hatched portion 30E1 can be regarded as width H3.

[0067] A gate electrode 40 is located on the ridge portion 32 of the connecting portion 30E, continuing from above the main gate portion 30C. The gate electrode 40 is located over the entire extension direction of the connecting portion 30E. The thickness of the gate electrode 40 located on the connecting portion 30E is the same as the thickness of the gate electrode 40 located on the main gate portion 30C. The width H4 of the gate electrode 40 located on the connecting portion 30E may be the same as or different from the width H2 of the gate electrode 40 located on the main gate portion 30C. The width H4 of the gate electrode 40 located on the connecting portion 30E is, for example, 1.5 times or less the width H2 of the gate electrode 40 located on the main gate portion 30C. The width H4 of the gate electrode 40 located on the connecting portion 30E is, for example, 0.7 times or more the width H2 of the gate electrode 40 located on the main gate portion 30C. The width H4 of the gate electrode 40 located on the connecting portion 30E may be constant or may vary in the extension direction. When the width of the gate electrode 40 varies, the average value of the width of the gate electrode 40 can be regarded as the width H4. An example of the width H4 of the gate electrode 40 located on the coupling portion 30E is the same as the width H2 of the gate electrode 40 located on the main gate portion 30C, and is a constant width in the extension direction.

[0068] In plan view, the area of ​​each of the connecting portions 30E is, for example, 0.8 μm 2 less than or equal to 0.6 μm, preferably 2 The area of ​​each of the connecting portions 30E is, for example, 0.4 μm 2 That is all. The area of ​​each coupling portion 30E can be defined as the area of ​​the upper surface 30A of the gate layer 30, which is the surface on which the gate electrode 40 is formed. In FIG. 4, for ease of understanding, dashed lines are added to the boundary between the coupling portion 30E and the main gate portion 30C, and the boundary between the coupling portion 30E and the via connection portion 30D.

[0069] The area of ​​the interface between each of the connecting portions 30E and the gate electrode 40 is, for example, 0.75 μm 2 less than or equal to 0.55 μm, preferably 2 The area of ​​the interface is, for example, 0.35 μm or less.2 That's all.

[0070] Similar to the main gate portion 30C and the coupling portion 30E, the via connection portion 30D may include a ridge portion 32, a source-side extension portion 34, and a drain-side extension portion 36. In the via connection portion 30D, the source-side extension portion 34 is located so as to extend continuously from the coupling portion 30E at an edge portion located at the end in the Y-axis direction. In the via connection portion 30D, the drain-side extension portion 36 is located so as to extend continuously from the coupling portion 30E at an edge portion located at the end in the X-axis direction.

[0071] The source-side extension 34 of the via connection portion 30D means a portion that is continuous from the source-side extension 34 of the main gate portion 30C via the source-side extension 34 of the coupling portion 30E and is formed along the edge of the via connection portion 30D. Similarly, the drain-side extension 36 of the via connection portion 30D means a portion that is continuous from the drain-side extension 36 of the main gate portion 30C via the drain-side extension 36 of the coupling portion 30E and is formed along the edge of the via connection portion 30D.

[0072] The width in the X-axis direction of the upper surface 30A of the gate layer 30 at the via connection portion 30D is defined as width H5A (hereinafter referred to as the first-direction width H5A of the via connection portion 30D). The first-direction width H5A of the via connection portion 30D is, for example, three times or less the width H1 of the main gate portion 30C, and preferably 2.5 times or less the width H1 of the main gate portion 30C. Furthermore, the first-direction width H5A of the via connection portion 30D is, for example, two or more times the width H1 of the main gate portion 30C.

[0073] The first-direction width H5A of the via connection portion 30D is 0.7 times or less the separation distance L1 of the main gate portion 30C, and is preferably shorter than the separation distance L1 of the main gate portion 30C. The first-direction width H5A of the via connection portion 30D is, for example, 0.5 times or more the separation distance L1 of the main gate portion 30C. In one example, the first-direction width H5A of the via connection portion 30D is greater than the width H1 of the main gate portion 30C and less than the sum (H1+L1) of the width H1 of the main gate portion 30C and the separation distance L1 of the main gate portion 30C.

[0074] The width in the Y-axis direction of the upper surface 30A of the gate layer 30 at the via connection portion 30D is defined as width H5B (hereinafter referred to as the second-direction width H5B of the via connection portion 30D). Furthermore, the separation distance between the upper surface 30A of the gate layer 30 at the via connection portion 30D and the source opening 50A in the Y-axis direction in a plan view is defined as separation distance L2. The second-direction width H5B of the via connection portion 30D is, for example, 0.3 times or less the separation distance L2. Furthermore, the second-direction width H5B of the via connection portion 30D is, for example, 0.15 times or more the separation distance L2.

[0075] A gate electrode 40 is located on the ridge portion 32 of the via connection portion 30D, continuing from on the coupling portion 30E. The thickness of the gate electrode 40 located on the via connection portion 30D is the same as the thickness of the gate electrode 40 located on the main gate portion 30C. An example of the gate electrode 40 located on the via connection portion 30D has a shape in plan view that is substantially similar to the shape of the via connection portion 30D in plan view, but is slightly smaller than the shape of the via connection portion 30D in plan view.

[0076] In plan view, the area of ​​each via connection portion 30D is, for example, 4 μm 2 less than or equal to 3.3 μm, preferably 2 The area of ​​each via connection portion 30D is, for example, 2 μm 2 The area of ​​each via connection portion 30D can be defined as the area of ​​the upper surface 30A of the gate layer 30, which is the surface on which the gate electrode 40 is formed.

[0077] The area of ​​the interface where each via connection portion 30D contacts the gate electrode 40 is, for example, 3.5 μm 2 less than or equal to 3 μm, preferably 2 The area of ​​the interface is, for example, 1.5 μm or less. 2 That's all.

[0078] [Via connection details] The cross-sectional shape of the via connection portion 30D and the gate via 72A will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view taken along line 5-5 in Fig. 4.

[0079] The via connection portion 30D, which is part of the gate layer 30, is in contact with the electron supply layer 26 and includes a ridge portion 32 including an upper surface 30A on which a gate electrode 40 is formed. The via connection portion 30D is in contact with the electron supply layer 26 and may include an extension portion 33 that is thinner than the ridge portion 32 and extends outward from the ridge portion 32 in a plan view. The cross-sectional view of FIG. 5 illustrates a drain-side extension portion 36 as the extension portion 33. The gate electrode 40 is formed on the upper surface 30A of the via connection portion 30D.

[0080] In the non-active region A2, the first passivation layer 50 covers the electron supply layer 26, the gate layer 30, and the gate electrode 40. The second passivation layer 60 covers the first passivation layer 50 in the non-active region A2.

[0081] The nitride semiconductor device 10 includes a gate wiring 72 disposed on the second passivation layer 60. On the second passivation layer 60, the gate wiring 72 is disposed so as to be spaced apart from each of the source wiring 74 and the drain wiring 76.

[0082] A portion of the gate wiring 72 is located above the gate electrode 40 located in the via connection portion 30D. The first passivation layer 50 and the second passivation layer 60 include a gate wiring opening 50C that penetrates between the gate electrode 40 located above the via connection portion 30D and the gate wiring 72. A portion of the gate wiring 72 is filled in the gate wiring opening 50C to form a gate via 72A located above the via connection portion 30D. The gate via 72A electrically connects the gate electrode 40 located in the via connection portion 30D and the gate wiring 72.

[0083] The gate wiring 72 is composed of one or more metal layers. The metal layer may be composed of a material containing any one of copper (Cu), Al, Ti, and TiN. In one example, the gate wiring 72 is formed of a stacked structure of Ti, TiN, AlCu, and TiN.

[0084] For example, the gate wiring 72 is covered with an interlayer insulating layer (not shown). In one example, the gate pad 14 shown in Fig. 1 is formed on the interlayer insulating layer. For example, the gate wiring 72 is connected to the gate pad 14 by a gate connection conductor (not shown) that penetrates the interlayer insulating layer.

[0085] 4, an example of the gate via 72A is located adjacent to the source opening 50A in the Y-axis direction. In other words, at least a portion of the gate via 72A is located on an imaginary extension line of the source opening 50A in the Y-axis direction. Furthermore, the gate via 72A does not necessarily have to be located adjacent to the source opening 50A in the Y-axis direction.

[0086] The first direction length L3 of the gate via 72A, which is the length in the X-axis direction, is shorter than, for example, the separation distance L1 of the main gate portion 30C. The first direction length L3 of the gate via 72A may be equal to or greater than the separation distance L1 of the main gate portion 30C. Furthermore, the first direction length L3 of the gate via 72A is, for example, equal to or less than the first direction length L4, which is the length in the X-axis direction of the source opening 50A. The first direction length L3 of the gate via 72A may be longer than the first direction length L4 of the source opening 50A.

[0087] [Method of manufacturing a nitride semiconductor device] An example of a manufacturing method for the nitride semiconductor device 10 will be briefly described with reference to FIGS. 6 to 18. FIGS. 6 to 18 show schematic cross-sectional structures illustrating exemplary manufacturing steps for the nitride semiconductor device 10. FIGS. 6 and 7 show cross-sectional shapes common to the active region A1 and the non-active region A2. FIGS. 8 to 13 show cross-sectional shapes in the active region A1, for example, cross-sectional shapes at the same position as the cross-sectional shape in FIG. 3. FIGS. 14 to 18 show cross-sectional shapes in the non-active region A2, for example, cross-sectional shapes at the same position as the cross-sectional shape in FIG. 5. For ease of understanding, in FIGS. 6 to 18, components similar to those in FIGS. 3 and 5 may be assigned the same reference numerals.

[0088] As shown in FIG. 6, the method for manufacturing the nitride semiconductor device 10 includes forming, on a substrate 20, an electron transit layer 24 made of a nitride semiconductor, and forming an electron supply layer 26 made of a nitride semiconductor.

[0089] In one example, a buffer layer 22 may be formed on a substrate 20, such as a Si substrate, and then an electron transit layer 24 may be formed on the buffer layer 22. The buffer layer 22 and the electron transit layer 24 may be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0090] Although detailed illustration is omitted, in one example, the buffer layer 22 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the substrate 20 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order, starting from the side closest to the AlN layer. The electron transit layer 24 formed on the buffer layer 22 may be a GaN layer.

[0091] Next, the electron supply layer 26 may be formed on the electron transit layer 24. The electron supply layer 26 may be epitaxially grown using, for example, an MOCVD method. The electron transit layer 24 may be a GaN layer, while the electron supply layer 26 may be an AlGaN layer. Therefore, the nitride semiconductor constituting the electron supply layer 26 has a larger band gap than the electron transit layer 24.

[0092] The method for manufacturing the nitride semiconductor device 10 includes forming a semiconductor layer 82 on the electron supply layer 26. The semiconductor layer 82 may be composed of a nitride semiconductor containing acceptor-type impurities. In one example, the semiconductor layer 82 containing acceptor-type impurities can be formed by doping the semiconductor layer 82 with Mg during growth. The semiconductor layer 82 may be composed of, for example, GaN. The semiconductor layer 82 is composed of a nitride semiconductor having a smaller bandgap than the electron supply layer 26. The semiconductor layer 82 is a semiconductor layer that constitutes the gate layer 30 (see FIG. 3 ). The semiconductor layer 82 can be epitaxially grown using, for example, an MOCVD method.

[0093] As shown in FIGS. 7 to 8 and 14, the method for manufacturing the nitride semiconductor device 10 includes forming the gate electrode 40 on the semiconductor layer 82. As shown in FIGS. As shown in Fig. 7, an electrode layer 84 is formed on the semiconductor layer 82. The electrode layer 84 can be formed on the semiconductor layer 82 by, for example, sputtering. The electrode layer 84 may be formed over the entire upper surface of the semiconductor layer 82. The electrode layer 84 is, for example, a TiN layer. The electrode layer 84 is a metal layer that constitutes the gate electrode 40 (see Fig. 3).

[0094] 8 and 14, a portion of the electrode layer 84 is removed in the active region A1 and the non-active region A2 to form the gate electrode 40. In one example, a mask is formed on the electrode layer 84. The mask is formed on a portion of the upper surface of the electrode layer 84, more specifically, on a region of the upper surface of the electrode layer 84 where the gate electrode 40 is to be formed. The electrode layer 84 exposed from the mask is then removed to form the gate electrode 40. The mask is removed after the gate electrode 40 is formed.

[0095] 9 and 15, the method for manufacturing the nitride semiconductor device 10 includes forming the gate layer 30 by etching the semiconductor layer 82. For example, the semiconductor layer 82 is etched by plasma etching. A chlorine-based (Cl2-based) gas can be used for the plasma etching. As a result, the gate layer 30 including the ridge portion 32 immediately below the gate electrode 40 and the extension portion 33 is formed in the semiconductor layer 82 in the active region A1 and the non-active region A2.

[0096] 10 and 16, the method for manufacturing the nitride semiconductor device 10 includes forming a first passivation layer 50 on the electron supply layer 26, the gate layer 30, and the gate electrode 40. The first passivation layer 50 is formed by, for example, an LPCVD method. The first passivation layer 50 may be formed of at least one of SiN, SiO, SiON, AlO, AlN, and AlON. In one example, the first passivation layer 50 is formed of SiN.

[0097] 10 , in the active region A1, a source opening 50A and a drain opening 50B are formed penetrating the first passivation layer 50 in the Z-axis direction to expose the electron supply layer 26. The source opening 50A and the drain opening 50B are formed by, for example, etching. The source opening 50A and the drain opening 50B are each formed in the gate layer 30 so as to be located closer to the source opening 50A than the drain opening 50B.

[0098] As shown in FIG. 11 , the manufacturing method of the nitride semiconductor device 10 includes forming a source electrode 42, a drain electrode 44, and a field plate electrode 46 in the active region A1. An electrode layer 86 is formed on the first passivation layer 50. The electrode layer 86 is a metal layer that constitutes the source electrode 42, the drain electrode 44, and the field plate electrode 46. The electrode layer 86 is formed to fill each of the source opening 50A and the drain opening 50B and to contact the electron supply layer 26 through the source opening 50A and the drain opening 50B. This forms the source contact portion 42A and the drain contact portion 44A. In one example, the electrode layer 86 may include at least one of Ti, TiN, Al, AlSiCu, and AlCu. Next, the electrode layer 86 is selectively removed by lithography and etching. This forms the source electrode 42, the drain electrode 44, and the field plate electrode 46 from the electrode layer 86.

[0099] 12 and 17, the manufacturing method of the nitride semiconductor device 10 includes forming a second passivation layer 60 on the source electrode 42, the drain electrode 44, the field plate electrode 46, and a portion of the first passivation layer 50 in the active region A1 and the non-active region A2. The second passivation layer 60 is formed by, for example, an LPCVD method. The second passivation layer 60 may be formed of at least one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the second passivation layer 60 is formed of SiN.

[0100] 12, in the active region A1, a source wiring opening 60A exposing the source electrode 42 and a drain wiring opening 60B exposing the drain electrode 44 are formed by penetrating the second passivation layer 60 in the Z-axis direction. Also, as shown in Fig. 17, above the via connection portion 30D in the non-active region A2, a gate wiring opening 50C is formed by penetrating the first passivation layer 50 and the second passivation layer 60 in the Z-axis direction and exposing the gate electrode 40. The source wiring opening 60A, the drain wiring opening 60B, and the gate wiring opening 50C are formed by, for example, etching.

[0101] 13 and 18 , the method for manufacturing the nitride semiconductor device 10 includes forming a source wiring 74 and a drain wiring 76 in the active region A1, and forming a gate wiring 72 in the non-active region A2. An electrode layer 88 is formed on the second passivation layer 60. The electrode layer 88 is a metal layer that constitutes the gate wiring 72, the source wiring 74, and the drain wiring 76.

[0102] As shown in FIG. 13 , the electrode layer 88 is formed to fill the source wiring opening 60A and to be in contact with the source electrode 42 through the source opening 50A. The electrode layer 88 is formed to fill the drain opening 50B and to be in contact with the drain electrode 44 through the drain opening 50B. As shown in FIG. 18 , the electrode layer 88 is formed to fill the gate wiring opening 50C and to be in contact with the source electrode 42 through the gate wiring opening 50C. The portion of the electrode layer 88 filling the gate wiring opening 50C becomes the gate via 72A. In one example, the electrode layer 88 may contain at least one of copper (Cu), Al, Ti, and TiN. Next, the electrode layer 88 is selectively removed by lithography and etching. As a result, the gate wiring 72, the source wiring 74, and the drain wiring 76 are formed from the electrode layer 88. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0103] [Operation of the embodiment] The operation of the nitride semiconductor device 10 of the embodiment will be described. As shown in FIGS. 2 and 3 , the nitride semiconductor device 10 includes, in an active region A1, a substrate 20, an electron transit layer 24 located on the substrate 20, an electron supply layer 26 located on the electron transit layer 24 and having a larger band gap than the electron transit layer 24, a gate layer 30 located on the electron supply layer 26 and containing acceptor-type impurities, and a gate electrode 40 located on the gate layer 30.

[0104] As described above, when a semiconductor device includes the gate layer 30 and the gate electrode 40 formed on the gate layer 30, gate reliability may decrease due to deterioration of the Schottky junction between the gate layer 30 and the gate electrode 40. The probability of deterioration of the Schottky junction increases as the area of ​​the Schottky junction surface between the gate layer 30 and the gate electrode 40 (hereinafter referred to as the Schottky junction surface) increases.

[0105] In the nitride semiconductor device 10 of this embodiment, the area of ​​the Schottky junction surface in the non-active region A2 is reduced by forming a specific planar layout of the gate layer 30 and the gate electrode 40 arranged in the non-active region A2 adjacent to the active region A1 in the Y-axis direction. The portions of the gate layer 30 and the gate electrode 40 arranged in the non-active region A2 are provided as portions for connection to the gate wiring 72 through the gate via 72A.

[0106] More specifically, the gate layer 30 includes a main gate portion 30C, a via connection portion 30D, and a linking portion 30E in the non-active region A2. The main gate portion 30C includes a portion located in the active region A1, and is provided in a plurality of portions extending in the second direction and spaced apart in the first direction. The via connection portion 30D is located in a region between two main gate portions 30C adjacent to each other in the first direction in the non-active region A2, and is connected to the gate via 72A. The linking portion 30E independently links the ends of two main gate portions 30C adjacent to each other in the X-axis direction to the via connection portion 30D. The linking portion 30E includes a diagonal portion 30E1 extending diagonally relative to the main gate portions 30C.

[0107] By forming at least a portion of the coupling portion 30E connecting the end of the main gate portion 30C and the via connection portion 30D as a straight-lined oblique portion 30E1, the length of the coupling portion 30E can be shortened. The length of the coupling portion 30E becomes shorter as the proportion of the oblique portion 30E1 in the coupling portion 30E increases. Furthermore, the length of the coupling portion 30E can be particularly shortened by forming the coupling portion 30E in a shape that connects the end of the main gate portion 30C and the via connection portion 30D over the shortest distance. Furthermore, by shortening the length of the coupling portion 30E, the Schottky junction surface between the gate layer 30 and the gate electrode 40 in the coupling portion 30E can be made smaller.

[0108] In this way, by forming the planar layout of the gate layer 30 and the gate electrode 40 arranged in the non-active region A2 into the above-mentioned specific shape, the area of ​​the Schottky junction surface in the non-active region A2 can be reduced. The reduced area of ​​the Schottky junction surface reduces the probability of deterioration of the Schottky junction at the Schottky junction surface between the gate layer 30 and the gate electrode 40.

[0109] [Effects of the embodiment] According to the nitride semiconductor device 10 of the embodiment, the following effects can be obtained. (1) The nitride semiconductor device 10 includes an electron transit layer 24, an electron supply layer 26 located on the electron transit layer 24 and having a bandgap larger than that of the electron transit layer 24, a gate layer 30 located on the electron supply layer 26 and containing acceptor-type impurities, a gate electrode 40 located on the gate layer 30, passivation layers 50 and 60 covering the electron supply layer 26, the gate layer 30, and the gate electrode 40 and having a source opening 50A and a drain opening 50B spaced apart from each other in a first direction, a source electrode 42 in contact with the electron supply layer 26 through the source opening 50A, and a drain electrode 44 in contact with the electron supply layer 26 through the drain opening 50B, and a gate wiring 72 located on the passivation layers 50 and 60 and electrically connected to the gate electrode 40 through a gate via 72A passing through the passivation layers 50 and 60. In a planar view, the nitride semiconductor device 10 further includes an active region A1 including a source electrode 42 and a drain electrode 44, and a non-active region A2 arranged adjacent to the active region A1 in a second direction perpendicular to the first direction, and in which a gate via 72A and a gate wiring 72 are arranged.

[0110] The gate layer 30 includes a plurality of main gate portions 30C extending in the second direction and spaced apart in the first direction, including a portion located in the active region A1, a via connection portion 30D located in a region between two main gate portions 30C adjacent in the first direction in the inactive region A2 and connected to the gate via 72A, and a linking portion 30E that independently links the ends of the two main gate portions 30C adjacent in the first direction to the via connection portion 30D. The linking portion 30E includes a diagonal portion 30E1 extending diagonally relative to the main gate portions 30C.

[0111] According to this configuration, the area of ​​the Schottky junction surface in the non-active region A2 can be reduced based on the planar layout of the gate layer 30 and the gate electrode 40 disposed in the non-active region A2. This reduces the probability of deterioration of the Schottky junction at the Schottky junction surface between the gate layer 30 and the gate electrode 40. As a result, the gate reliability of the nitride semiconductor device 10 is improved.

[0112] (2) The entire coupling portion 30E is a diagonal line portion 30E1. A first end of the diagonal line portion 30E1 is connected to an end of the main gate portion 30C, and a second end of the diagonal line portion 30E1 is connected to the via connection portion 30D.

[0113] According to this configuration, the Schottky junction surface of the gate layer 30 can be further reduced in the non-active region A2, resulting in a more pronounced effect of (1) above. (3) In plan view, the hatched portion 30E1 connects the end of the main gate portion 30C and the via connection portion 30D over the shortest distance.

[0114] This configuration shortens the length of the shaded portion 30E1, thereby further reducing the Schottky junction surface of the gate layer 30 in the inactive region A2, thereby achieving the effect (1) above more significantly.

[0115] <Example of change> The above embodiment can be modified as follows: Furthermore, the above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0116] The nitride semiconductor device 10 is not limited to a HEMT using GaN, but may be a semiconductor device using other nitride semiconductors. The nitride semiconductor device 10 is not limited to being configured with the numerical values ​​or numerical ranges described in the above embodiments.

[0117] The gate layer 30 is not limited to a configuration including both the source-side extension portion 34 and the drain-side extension portion 36. For example, the gate layer 30 may have the drain-side extension portion 36 but omit the source-side extension portion 34, or may have the source-side extension portion 34 but omit the drain-side extension portion 36. The extension portion 33 may be formed only in the main gate portion 30C. In other words, the gate layer 30 may include the main gate portion 30C having the extension portion 33, and the via connection portion 30D and the coupling portion 30E not having the extension portion 33. The gate layer 30 may also not include the extension portion 33.

[0118] The formation pattern 100 of the nitride semiconductor device 10 may have at least one structure in which the ends of two main gate portions 30C adjacent in the first direction are connected to each other via a via connection portion 30D and a linking portion 30E. In other words, it is not necessary for all of the ends of two main gate portions 30C adjacent in the first direction to be connected to each other via a via connection portion 30D and a linking portion 30E, and some of the ends may be connected by other structures. For example, the formation pattern 100 of the nitride semiconductor device 10 may include a semicircular arc-shaped linking portion that connects the ends of two main gate portions 30C adjacent in the first direction.

[0119] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0120] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0121] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0122] [Appendix 1] an electron transit layer (24); an electron supply layer (26) located on the electron transit layer (24) and having a band gap larger than that of the electron transit layer (24); a gate layer (30) located on the electron supply layer (26) and containing acceptor-type impurities; a gate electrode (40) located on the gate layer (30); a passivation layer (50, 60) covering the electron supply layer (26), the gate layer (30), and the gate electrode (40), and having a source opening (50A) and a drain opening (50B) arranged spaced apart from each other in a first direction (X-axis direction); a source electrode (42) in contact with the electron supply layer (26) through the source opening (50A); a drain electrode (44) in contact with the electron supply layer (26) through the drain opening (50B); a gate wiring (72) located on the passivation layer (50, 60) and electrically connected to the gate electrode (40) through a gate via (72A) passing through the passivation layer (50, 60); an active region (A1) including the source electrode (42) and the drain electrode (44) in a plan view; a non-active region (A2) arranged adjacent to the active region (A1) in a second direction (Y-axis direction) perpendicular to the first direction (X-axis direction), in which the gate via (72A) and the gate wiring (72) are arranged; Including, The gate layer (30) a plurality of main gate portions (30C) extending in the second direction (Y-axis direction) and spaced apart from each other in the first direction (X-axis direction), the main gate portions (30C) including portions located in the active region (A1); a via connection portion (30D) located in a region between two of the main gate portions (30C) adjacent to each other in the first direction (X-axis direction) in the inactive region (A2) and connected to the gate via (72A); and connecting portions (30E) that independently connect ends of two of the main gate portions (30C) adjacent to each other in the first direction (X-axis direction) to the via connection portion (30D), The nitride semiconductor device (10) is configured such that the coupling portion (30E) includes a diagonal line portion (30E1) extending diagonally relative to the main gate portion (30C).

[0123] [Appendix 2] The entire connecting portion (30E) is the shaded portion (30E1), a first end of the oblique line portion (30E1) connected to an end of the main gate portion (30C); 2. The nitride semiconductor device (10) according to claim 1, wherein a second end of the diagonal line portion (30E1) is connected to the via connection portion (30D).

[0124] [Appendix 3] 3. The nitride semiconductor device (10) according to claim 2, wherein, in plan view, the hatched portion (30E1) connects the end of the main gate portion (30C) and the via connection portion (30D) over the shortest distance.

[0125] [Appendix 4] 4. The nitride semiconductor device (10) according to any one of appendices 1 to 3, wherein an inclination angle (θ) of the oblique line portion (30E1) relative to the main gate portion (30C) is 40 degrees or more and 50 degrees or less.

[0126] [Appendix 5] 5. The nitride semiconductor device (10) according to any one of appendices 1 to 4, wherein a width (H3) of the oblique line portion (30E1) is 1.5 times or less the width (H1) of the main gate portion (30C).

[0127] [Appendix 6] The area of ​​each of the via connection portions (30D) is 4 μm 2 A nitride semiconductor device (10) according to any one of appendices 1 to 5, which is as follows:

[0128] [Appendix 7] The nitride semiconductor device (10) according to any one of Appendices 1 to 6, wherein a width (H5A) of the via connection portion (30D) in the first direction (X-axis direction) is three times or less the width (H1) of the main gate portion (30C).

[0129] [Appendix 8] In plan view, the area of ​​each of the connecting portions (30E) is 0.5 μm 2 A nitride semiconductor device (10) according to any one of appendices 1 to 7, which is as follows:

[0130] [Appendix 9] The nitride semiconductor device (10) according to any one of appendices 1 to 8, wherein an end of the main gate portion (30C) is located outside the active region (A1).

[0131] [Appendix 10] the gate via (72A) is located on the via connection portion (30D); 10. The nitride semiconductor device (10) according to any one of appendixes 1 to 9, wherein the gate via (72A) is located adjacent to the source opening (50A) in the second direction (Y-axis direction).

[0132] [Appendix 11] A nitride semiconductor device (10) according to any one of Appendices 1 to 10, wherein a first direction length (L3) of the gate via (72A) is shorter than a separation distance (L1) between adjacent main gate portions (30C) in the first direction (X-axis direction).

[0133] [Appendix 12] The nitride semiconductor device (10) according to any one of appendices 1 to 11, wherein a length (L3) in a first direction of the gate via (72A) is equal to or less than a length (L4) in a first direction of the source opening (50A).

[0134] [Appendix 13] a plurality of the active regions (A1) are arranged in the second direction (Y-axis direction) with the inactive regions (A2) sandwiched therebetween; One of the via connection portions (30D) is connected to four of the main gate portions (30C) through the linking portions (30E), The nitride semiconductor device (10) according to any one of Appendices 1 to 12, wherein the four main gate portions (30C) are two main gate portions (30C) aligned in the first direction (X-axis direction) and two main gate portions (30C) aligned in the second direction (Y-axis direction) with the inactive region (A2) sandwiched between the two main gate portions (30C). [Explanation of symbols]

[0135] θ…Inclination angle A1...active area A2…Inactive area H1,H3,H4…Width H2…electrode width H5A…1st direction width H5B…Second direction width L1,L2…separation distance L3, L4...Length in the first direction 10...Nitride semiconductor device 12...Chip body 13…Top surface 14...Gate pad 16...Sauce pad 18...Drain pad 20...Substrate 22...Buffer layer 24...Electron transit layer 26…electron supply layer 26A…Top surface 28...Two-dimensional electron gas 30...Gate layer 30A…Top surface 30B…Bottom surface 30C...Main gate area 30D...Via connection 30E…Connection part 30E1…Shaded area 32...Ridge 33...Extension part 34…Source side extension part 36...Drain side extension 40...Gate electrode 42...Source electrode 42A...Source contact part 44...Drain electrode 44A...Drain contact part 46...Field plate electrode 46A...end 46B...Opening for drain electrode 50...First passivation layer 50A...Source opening 50B...Drain opening 50C...Gate wiring opening 60...Second passivation layer 60A...Source wiring opening 60B...Opening for drain wiring 72...Gate wiring 72A...Gate via 74...Source wiring 76...Drain wiring 82...Semiconductor layer 84,86,88...electrode layer 100...Formation pattern

Claims

1. an electron transit layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a source opening and a drain opening spaced apart from each other in a first direction; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening; a gate wiring located on the passivation layer and electrically connected to the gate electrode through a gate via passing through the passivation layer; an active region including the source electrode and the drain electrode in a plan view; a non-active region in which the gate via and the gate wiring are disposed, the non-active region being disposed adjacent to the active region in a second direction perpendicular to the first direction; Including, The gate layer a plurality of main gate portions extending in the second direction and spaced apart from each other in the first direction, the main gate portions including portions located in the active region; a via connection portion located in a region between two of the main gate portions adjacent to each other in the first direction in the inactive region and connected to the gate via; a connecting portion that independently connects two ends of the main gate portions adjacent to each other in the first direction to the via connection portion, The coupling portion includes a diagonal line portion extending diagonally relative to the main gate portion.

2. the entire connecting portion is the diagonal line portion, a first end of the shaded portion is connected to an end of the main gate portion; The nitride semiconductor device according to claim 1 , wherein a second end of said shaded portion is connected to said via connection portion.

3. The nitride semiconductor device according to claim 2 , wherein, in a plan view, said oblique line portion connects an end of said main gate portion and said via connection portion over the shortest distance.

4. 2. The nitride semiconductor device according to claim 1, wherein an inclination angle of said oblique line portion with respect to said main gate portion is not less than 40 degrees and not more than 50 degrees.

5. 2. The nitride semiconductor device according to claim 1, wherein the width of said hatched portion is 1.5 times or less the width of said main gate portion.

6. The area of ​​each via connection portion is 4 μm ２ 2. The nitride semiconductor device according to claim 1, wherein:

7. The nitride semiconductor device according to claim 1 , wherein the width of said via connection portion in said first direction is equal to or less than three times the width of said main gate portion.

8. In a plan view, the area of ​​each of the connecting portions is 0.5 μm ２ 2. The nitride semiconductor device according to claim 1, wherein:

9. The nitride semiconductor device according to claim 1 , wherein an end of said main gate portion is located outside said active region.

10. the gate via is located on the via connection portion; The nitride semiconductor device according to claim 1 , wherein the gate via is located adjacent to the source opening in the second direction.

11. The nitride semiconductor device according to claim 1 , wherein a length of said gate via in the first direction is shorter than a separation distance between said main gate portions adjacent to each other in said first direction.

12. The nitride semiconductor device according to claim 1 , wherein the length of said gate via in the first direction is equal to or less than the length of said source opening in the first direction.

13. a plurality of the active regions are arranged in the second direction with the non-active regions sandwiched therebetween; one of the via connection portions is connected to four of the main gate portions via the coupling portions, The nitride semiconductor device according to any one of claims 1 to 12, wherein the four main gate portions are two main gate portions aligned in the first direction and two main gate portions aligned in the second direction with the inactive region sandwiched between the two main gate portions.

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