RC-igbt

Abstract

To provide an improved RC-IGBT for connection to an electrode.SOLUTION: The RC-IGBT10 includes an IGBT region 21 and a diode region 22 provided on a first surface 20S of a semiconductor layer 20 in a state of being separated in the X-axis direction, a boundary region 23 provided between the IGBT region 21 and the diode region 22, an insulating layer 30 that covers a portion corresponding to the IGBT region 21 and exposes portions corresponding to both the diode region 22 and the boundary region 23, a first electrode layer 40 including a first electrode portion 41 provided on the insulating layer 30, a second electrode portion 42 provided on the diode region 22, and a third electrode portion 43 provided on the boundary region 23, and an intermediate layer 60 disposed between the third electrode portion 43 and the first surface 20S of the semiconductor layer 20. The intermediate layer 60 is in contact with the insulating layer 30 in the X-axis direction, and the thickness T5 of the intermediate layer 60 is smaller than the thickness T4 of the insulating layer 30.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an RC-IGBT. [Background technology]

[0002] An RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) includes an IGBT and a freewheeling diode connected in antiparallel to the IGBT on a single chip. Patent Document 1 shows the active area of ​​an RC-IGBT, including an IGBT area and a diode area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 080476

[0004] [overview] There is room for improvement in the connection to the electrodes of the RC-IGBT.

[0005] an insulating layer that covers a portion of the first surface corresponding to the IGBT region while exposing portions corresponding to both the diode region and the boundary region; an electrode layer that includes a first electrode portion provided on the insulating layer in the IGBT region, a second electrode portion provided on the first surface in the diode region, and a third electrode portion provided on the first surface in the boundary region; and an intermediate layer that is arranged between the third electrode portion and the first surface, wherein the intermediate layer is in contact with the insulating layer in the first direction, and the thickness of the intermediate layer is thinner than the thickness of the insulating layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary RC-IGBT according to one embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the arrangement of the IGBT region and the diode region of the RC-IGBT shown in FIG. [Figure 3] FIG. 3 is a schematic enlarged view of a region F3 of the RC-IGBT shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the RC-IGBT taken along line F4-F4 shown in FIG. [Figure 5] FIG. 5 is a schematic plan view of a semiconductor device including the RC-IGBT of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an RC-IGBT according to a comparative example. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a modified RC-IGBT. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a modified RC-IGBT. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a modified RC-IGBT.

[0007] [Detailed explanation] Hereinafter, several embodiments of the RC-IGBT of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and not to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] <Embodiment> An RC-IGBT 10 according to an embodiment will be described with reference to FIGS. FIG. 1 is a schematic plan view of an exemplary RC-IGBT 10 according to one embodiment. FIG. 2 is a schematic plan view showing the arrangement of an IGBT region 21 and a diode region 22 of the RC-IGBT 10 shown in FIG. 1. In FIG. 2, the diode region 22 is dotted to aid in understanding. FIG. 3 is a schematic enlarged view of a region F3 of the RC-IGBT 10 shown in FIG. 2. FIG. 3 schematically shows the planar structure of the region F3. In FIG. 3, the intermediate layer 60 is dotted to aid in understanding. FIG. 4 is a schematic cross-sectional view of the RC-IGBT 10 taken along line F4-F4 shown in FIG. 3.

[0011] [Overall planar structure of RC-IGBT] 1 and 2, the RC-IGBT 10 has a flat plate shape. In Fig. 1, the RC-IGBT 10 is shown with the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1 as the thickness direction. The RC-IGBT 10 has a rectangular shape when viewed from the Z-axis direction.

[0012] The RC-IGBT 10 may include a cell region 11 and an outer periphery region 12 surrounding the cell region 11 when viewed from the Z-axis direction. The cell region 11 may have a rectangular shape when viewed from the Z-axis direction. The outer periphery region 12 may have a rectangular ring shape.

[0013] The cell region 11 includes an IGBT region 21 and a diode region 22. The IGBT region 21 is a region where the IGBT 21A shown in FIG. 4 is provided. The diode region 22 is a region where the diode 22A shown in FIG. 4 is provided. The diode 22A may be a freewheeling diode (FWD) connected in anti-parallel to the IGBT 21A. Both the IGBT 21A and the diode 22A are provided on the same chip.

[0014] The RC-IGBT 10 includes a semiconductor layer 20. The semiconductor layer 20 includes a first surface 20S and a second surface 20R (see FIG. 4) opposite the first surface 20S. Here, the term "plan view" used in this disclosure refers to viewing the RC-IGBT 10 from a direction perpendicular to the first surface 20S, unless explicitly stated otherwise. As shown in FIG. 1, the RC-IGBT 10 is shown with the Z-axis direction as the thickness direction. The Z-axis direction may be a direction perpendicular to the first surface 20S of the semiconductor layer 20. Therefore, "plan view" can also be referred to as viewing the RC-IGBT 10 from the Z-axis direction.

[0015] The semiconductor layer 20 may include a semiconductor substrate and an epitaxial layer. Therefore, the semiconductor layer 20 may be referred to as, for example, a "chip" or a "semiconductor chip." The semiconductor layer 20 may be made of a material containing Si. Therefore, a Si substrate may be used as the semiconductor substrate in the semiconductor layer 20. In this case, the epitaxial layer may be a Si epitaxial layer epitaxially grown on the Si substrate.

[0016] The RC-IGBT 10 includes an insulating layer 30 and a first electrode layer 40. The insulating layer 30 and the first electrode layer 40 are provided on the first surface 20S. The insulating layer 30 may be arranged so as to overlap the IGBT region 21 and expose the diode region 22 in a planar view. The first electrode layer 40 may be arranged so as to overlap at least both the IGBT region 21 and the diode region 22 in a planar view. Here, the first electrode layer 40 is an example of an "electrode layer."

[0017] The insulating layer 30 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al2O3). The insulating layer 30 may be composed of a single insulating layer or may have a stacked structure of multiple different insulating layers.

[0018] The first electrode layer 40 may include at least one of aluminum (Al), copper (Cu), an aluminum alloy, a copper alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The first electrode layer 40 may be composed of a single metal layer or may have a stacked structure of multiple different metal layers. In one example, the first electrode layer 40 is composed of a single metal layer. In one example, the first electrode layer 40 is composed of aluminum silicon copper (AlSiCu) as an aluminum alloy. In one example, the first electrode layer 40 may have a thickness of 3 μm or more and 6 μm or less. The thickness of the first electrode layer 40 can be changed as desired.

[0019] The first electrode layer 40 includes a first pad electrode 40E and a second pad electrode 40G. The first pad electrode 40E and the second pad electrode 40G are arranged spaced apart from each other in a plan view.

[0020] The first pad electrode 40E is arranged to overlap both the IGBT region 21 and the diode region 22 in a plan view. In one example, as shown in FIG. 1 , the first pad electrode 40E is provided to overlap the entire IGBT region 21 and the entire diode region 22. The first pad electrode 40E is provided on most of the first surface 20S of the semiconductor layer 20.

[0021] The second pad electrode 40G is arranged in a region, in plan view, that is different from both the IGBT region 21 and the diode region 22. The second pad electrode 40G is arranged at a position spaced apart from the first pad electrode 40E in the X-axis direction.

[0022] The RC-IGBT 10 may further include a gate wiring 51 electrically connected to the second pad electrode 40G. The gate wiring 51 is disposed above the semiconductor layer 20 and below the first pad electrode 40E. The gate wiring 51 may be insulated from both the semiconductor layer 20 and the first pad electrode 40E by the insulating layer 30. Therefore, the gate wiring 51 can be said to be embedded in the insulating layer 30. In one example, the gate wiring 51 may be made of conductive polysilicon. In another example, the gate wiring 51 may be made of another metallic material.

[0023] The gate wiring 51 may include multiple gate fingers 52. In one example, as shown in FIG. 1, the gate wiring 51 includes five gate fingers 52. Each gate finger 52 may extend in the X-axis direction. The number of gate fingers 52 may be set appropriately depending on the desired characteristics of the RC-IGBT 10.

[0024] As shown in FIG. 2, the RC-IGBT 10 may include multiple IGBT regions 21 and multiple diode regions 22. The multiple IGBT regions 21 and the multiple diode regions 22 may be arranged in an array without overlapping each other in a planar view. The multiple IGBT regions 21 may be arranged spaced apart from each other in the X-axis direction and the Y-axis direction. The multiple diode regions 22 may be arranged spaced apart from each other in the X-axis direction and the Y-axis direction. In one example, as shown in FIG. 2, both the IGBT regions 21 and the diode regions 22 are rectangular in a planar view. Here, in the present disclosure, the X-axis direction corresponds to the "first direction." In a planar view, the Y-axis direction orthogonal to the X-axis direction corresponds to the "second direction."

[0025] Each IGBT region 21 may be arranged adjacent to some of the multiple diode regions 22. For example, some of the multiple IGBT regions 21 may be arranged alternately with some of the multiple diode regions 22 in the X-axis direction. For example, as shown in FIG. 2, four IGBT regions 21 and three diode regions 22 are arranged alternately in the X-axis direction. A subregion 20A including such alternately arranged IGBT regions 21 and diode regions 22 may be arranged adjacent to the gate finger 52 shown in FIG. 1. The RC-IGBT 10 may include multiple subregions 20A arranged spaced apart from one another. For example, as shown in FIG. 2, the multiple subregions 20A are arranged spaced apart from one another in the Y-axis direction. The multiple subregions 20A and the multiple gate fingers 52 may be arranged alternately in the Y-axis direction. The number of IGBT regions 21 and diode regions 22 included in a subregion 20A and the number of subregions 20A are appropriately set according to the desired characteristics of the RC-IGBT 10.

[0026] 2, the area of ​​the IGBT region 21 in a plan view is larger than the area of ​​the diode region 22 in a plan view. The areas of the IGBT region 21 in a plan view and the diode region 22 in a plan view may be changed as appropriate. For example, the areas of the IGBT region 21 in a plan view and the diode region 22 in a plan view may be set as appropriate depending on the desired characteristics of the RC-IGBT 10.

[0027] The RC-IGBT 10 includes a boundary region 23 shown in Figures 3 and 4. The boundary region 23 is provided between the IGBT region 21 and the diode region 22 that are adjacent to each other. Note that the boundary region 23 is omitted in Figures 1 and 2 for simplification.

[0028] [Detailed structure of part of RC-IGBT] A detailed planar structure and cross-sectional structure of a portion of the RC-IGBT 10 will be described with reference to FIGS.

[0029] As shown in FIG. 3, the RC-IGBT 10 may include multiple trench structures 70 provided in the semiconductor layer 20. In one example, as shown in FIG. 3, each trench structure 70 extends in the Y-axis direction in a plan view. The multiple trench structures 70 are arranged spaced apart from each other in the X-axis direction across the IGBT region 21, the boundary region 23, and the diode region 22. In one example, the pitch PT of the multiple trench structures 70 in the X-axis direction may be constant. Note that the pitch PT of the multiple trench structures 70 can be changed as desired. In one example, the pitch PT of the multiple trench structures 70 may be different in the IGBT region 21, the boundary region 23, and the diode region 22.

[0030] As shown in FIG. 4, the RC-IGBT 10 includes a first region 20P containing n-type impurities and a second region 20Q containing p-type impurities. Therefore, the first region 20P is an n-type region, and the second region 20Q is a p-type region. The second region 20Q is provided on the first region 20P. The first region 20P includes a semiconductor substrate and a portion of the epitaxial layer of the semiconductor layer 20. The second region 20Q includes the epitaxial layer of the semiconductor layer 20. In this disclosure, the n-type is also referred to as the first conductivity type, and the p-type is also referred to as the second conductivity type. The n-type impurities may be, for example, phosphorus (P) or arsenic (As). The p-type impurities may be, for example, boron (B) or aluminum (Al).

[0031] (IGBT area) 4, in the IGBT region 21, the semiconductor layer 20 may further include an n-type emitter region 24 adjacent to the second region 20Q. The emitter region 24 includes a part of the first surface 20S of the semiconductor layer 20. That is, in the IGBT region 21, the emitter region 24 is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. In one example, the n-type impurity concentration of the emitter region 24 is 1×10 19 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0032] In the IGBT region 21, the second region 20Q may include a base region 25B. The base region 25B is adjacent to both the emitter region 24 and the first region 20P. In other words, the base region 25B is sandwiched between the emitter region 24 and the first region 20P in the Z-axis direction. In one example, the p-type impurity concentration of the base region 25B is 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0033] In the IGBT region 21, the semiconductor layer 20 may further include a p-type collector region 26C adjacent to the first region 20P. The collector region 26C includes a part of the second surface 20R of the semiconductor layer 20. That is, in the IGBT region 21, the collector region 26C is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. In one example, the p-type impurity concentration of the collector region 26C is 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0034] In the IGBT region 21, the first region 20P may include a buffer region 27 adjacent to the collector region 26C, a drift region 28 provided on the buffer region 27, and a carrier storage region 29 adjacent to the buffer region 27. The carrier storage region 29 is sandwiched between the base region 25B and the drift region 28 in the Z-axis direction. In one example, the n-type impurity concentration of the buffer region 27 is 1×10 15 cm -3 More than 1×10 17 cm -3 In one example, the n-type impurity concentration of the drift region 28 can be 1×10 13 cm -3 More than 1×10 15 cm -3 The drift region 28 has a lower n-type impurity concentration than the buffer region 27. The carrier storage region 29 has a higher n-type impurity concentration than the drift region 28. In one example, the n-type impurity concentration of the carrier storage region 29 is 1×10 15 cm -3 More than 1×10 17 cm -3 Preferably, the carrier storage region 29 has a lower n-type impurity concentration than the emitter region 24.

[0035] The provision of the carrier storage region 29 suppresses the discharge of carriers (holes) into the base region 25B, thereby promoting the accumulation of carriers (holes) in the region immediately below the trench structure 70 in the IGBT region 21. Therefore, the carrier storage region 29 can reduce the on-resistance and on-voltage of the IGBT 21A.

[0036] In the IGBT region 21, the multiple trench structures 70 may include multiple gate trench structures 70G and multiple emitter trench structures 70E. In one example, the gate trench structures 70G and the emitter trench structures 70E may be arranged alternately in the X-axis direction in the IGBT region 21. Note that the number and arrangement of the gate trench structures 70G and the emitter trench structures 70E may be changed as appropriate depending on the desired characteristics of the IGBT 21A.

[0037] Each gate trench structure 70G includes a gate trench 71G, a gate insulating layer 72G, and a gate electrode 73G. The gate trench 71G has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the base region 25B. Therefore, the gate trench 71G also penetrates the emitter region 24. The gate trench 71G penetrates the carrier storage region 29 and reaches the drift region 28.

[0038] The multiple gate trenches 71G may be arranged at intervals of 0.1 μm to 10 μm in the X-axis direction. Each gate trench 71G may have a width (dimension in the X-axis direction) of 0.5 μm to 3 μm inclusive. Each gate trench 71G may have a depth (dimension in the Z-axis direction) of 1 μm to 10 μm inclusive.

[0039] The gate trench 71G includes a sidewall and a bottom wall. The sidewall extends from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall forms an end of the gate trench 71G on the second surface 20R side of the semiconductor layer 20. In one example, as shown in FIG. 4, the sidewall extends along the Z-axis direction. The bottom wall has a curved shape that convexly extends toward the second surface 20R of the semiconductor layer 20.

[0040] The sidewalls may have a tapered shape in which the opening width (dimension in the X-axis direction) narrows from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall may be a flat surface perpendicular to the Z-axis direction. In this case, the corners between the bottom wall and the sidewalls may be curved and convex outward.

[0041] The gate insulating layer 72G is provided in the gate trench 71G. The gate insulating layer 72G may be formed by, for example, thermal oxidation. In this case, the boundary portion of the semiconductor layer 20 with the outer surface of the gate insulating layer 72G may form the sidewall and bottom wall of the gate trench 71G. The gate insulating layer 72G may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The gate insulating layer 72G is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the gate insulating layer 72G.

[0042] The gate insulating layer 72G is provided in a layered manner on the sidewalls and bottom wall of the gate trench 71G. As a result, a recess space is formed in the gate trench 71G by the gate insulating layer 72G. A gate electrode 73G is buried in this recess space. Therefore, it can be said that the gate electrode 73G is buried in the gate insulating layer 72G within the gate trench 71G.

[0043] The gate electrode 73G is configured to receive a gate potential. That is, the gate electrode 73G may be electrically connected to the second pad electrode 40G (see FIG. 1). In one example, although not shown, the gate electrode 73G is connected to a gate contact at one end of the gate trench 71G in the Y-axis direction. The gate contact is connected to the gate finger 52 (see FIG. 1). As a result, the gate electrode 73G is electrically connected to the second pad electrode 40G via the gate contact and the gate finger 52. An upper end surface of the gate electrode 73G may be located closer to the bottom wall of the gate trench 71G than the first surface 20S of the semiconductor layer 20. The gate electrode 73G is made of, for example, conductive polysilicon.

[0044] Each emitter trench structure 70E includes an emitter trench 71E, an emitter insulating layer 72E, and a field plate electrode 73E. Like the gate trench 71G, the emitter trench 71E penetrates the emitter region 24, the base region 25B, and the carrier storage region 29 and reaches the drift region .

[0045] The multiple emitter trenches 71E may be arranged at intervals of 0.1 μm or more and 10 μm or less in the X-axis direction. Each emitter trench 71E may have a width (dimension in the X-axis direction) of 0.5 μm or more and 3 μm or less. Each emitter trench 71E may have a depth (dimension in the Z-axis direction) of 1 μm or more and 10 μm or less. The shape of the emitter trench 71E shown in FIG. 4 may be the same as the shape of the gate trench 71G. In one example, the size and pitch of the emitter trench 71E may be the same as those of the gate trench 71G. In another example, the size and pitch of the emitter trench 71E may be different from those of the gate trench 71G.

[0046] The emitter insulating layer 72E is provided in the emitter trench 71E. When the emitter insulating layer 72E is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the emitter insulating layer 72E may form the sidewalls and bottom wall of the emitter trench 71E. The emitter insulating layer 72E may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the emitter insulating layer 72E may be made of the same material as the gate insulating layer 72G. The emitter insulating layer 72E is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the emitter insulating layer 72E.

[0047] The emitter insulating layer 72E is provided in a layered form on the sidewalls and bottom wall of the emitter trench 71E. This forms a recess space within the emitter trench 71E due to the emitter insulating layer 72E. A field plate electrode 73E is embedded in this recess space. Therefore, it can be said that the field plate electrode 73E is embedded in the emitter insulating layer 72E within the emitter trench 71E.

[0048] The field plate electrode 73E is configured to be applied with an emitter potential. That is, the field plate electrode 73E may be electrically connected to the first pad electrode 40E (see FIG. 1). In one example, although not shown, the field plate electrode 73E is connected to an emitter contact at one end of the emitter trench 71E in the Y-axis direction. The emitter contact is connected to the first pad electrode 40E. As a result, the field plate electrode 73E is electrically connected to the first pad electrode 40E via the emitter contact. The upper end surface of the field plate electrode 73E may be located closer to the bottom wall of the emitter trench 71E than the first surface 20S of the semiconductor layer 20. The field plate electrode 73E is made of, for example, conductive polysilicon. In this way, the field plate electrode 73E may be made of the same material as the gate electrode 73G.

[0049] The RC-IGBT 10 includes a plurality of contact structures 80 that electrically connect the first pad electrode 40E and the second region 20Q in the IGBT region 21. The contact structures 80 are arranged on both sides of the gate trench structure 70G in the X-axis direction and spaced apart from the gate trench structure 70G in the X-axis direction.

[0050] The contact structure 80 includes a contact hole 81 , an emitter contact 82 , and a p-type base contact region 83 . The contact hole 81 has an opening in the first surface 20S of the semiconductor layer 20 and extends in the Z-axis direction toward the second surface 20R. The contact hole 81 also penetrates the insulating layer 30 in the Z-axis direction. The contact hole 81 includes a sidewall and a bottom wall. The sidewall extends from the upper surface 30S of the insulating layer 30 toward the bottom wall. The sidewall includes a first sidewall formed by the insulating layer 30 and a second sidewall formed by the semiconductor layer 20. In one example, as shown in FIG. 4, the sidewall has a tapered shape in which the opening width (dimension in the X-axis direction) narrows from the upper surface 30S of the insulating layer 30 toward the bottom wall. The bottom wall has a curved shape that convexly curves toward the base region 25B.

[0051] The side walls may extend along the Z-axis direction. The bottom wall may be a flat surface perpendicular to the Z-axis direction. In this case, the corner between the bottom wall and the side walls may be curved and convex outward.

[0052] The emitter contact 82 is buried in the contact hole 81. The emitter contact 82 is in contact with the emitter region 24. The emitter contact 82 may have, for example, a stacked structure of a first conductive layer 82A and a second conductive layer 82B. The first conductive layer 82A may include at least one of titanium, titanium nitride, tantalum (Ta), and tantalum nitride (TaN). The second conductive layer 82B is provided on the first conductive layer 82A. The second conductive layer 82B may include at least one of tungsten (W), molybdenum, nickel, aluminum, copper, an aluminum alloy, and a copper alloy.

[0053] The base contact region 83 is provided in the base region 25B. The base contact region 83 is provided on the bottom wall of the contact hole 81. In other words, the base contact region 83 is exposed at the bottom wall of the contact hole 81. Therefore, the emitter contact 82 is in contact with the base contact region 83 at the bottom wall of the contact hole 81. The p-type impurity concentration of the base contact region 83 may be higher than the p-type impurity concentration of the base region 25B. In one example, the p-type impurity concentration of the base contact region 83 is 1×10 19 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0054] The RC-IGBT 10 may further include a second electrode layer 55 provided on the second surface 20R of the semiconductor layer 20. The second electrode layer 55 may be referred to as a second pad electrode. The second electrode layer 55 is electrically connected to the collector region 26C in the IGBT region 21. The second electrode layer 55 forms an ohmic contact with the collector region 26C. The second electrode layer 55 may include at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), and aluminum (Al).

[0055] In the IGBT region 21, the structure between the first pad electrode 40E and the second electrode layer 55 constitutes the IGBT 21A of the IGBT region 21. It can be said that the first pad electrode 40E constitutes the emitter of the IGBT 21A, and the second electrode layer 55 constitutes the collector of the IGBT 21A. The first pad electrode 40E can be said to be the emitter pad electrode of the RC-IGBT 10. The second pad electrode 40G can be said to be the gate pad electrode of the RC-IGBT 10. The second electrode layer 55 can be said to be the collector pad electrode of the RC-IGBT 10.

[0056] (diode region) In the diode region 22, the second region 20Q may include a p-type anode region 25A instead of the base region 25B of the IGBT region 21. The diode region 22 does not include the emitter region 24. Therefore, the anode region 25A includes a part of the first surface 20S of the semiconductor layer 20. That is, in the diode region 22, the anode region 25A is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. The anode region 25A is adjacent to the first region 20P. In one example, the p-type impurity concentration of the anode region 25A is 1×10 15 cm -3 More than 1×10 18 cm -3 In one example, the p-type impurity concentration of the anode region 25A may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the anode region 25A may be different from the p-type impurity concentration of the base region 25B.

[0057] In the diode region 22, the semiconductor layer 20 may further include an n-type cathode region 26K adjacent to the first region 20P, instead of the collector region 26C of the IGBT region 21. The cathode region 26K includes a part of the second surface 20R of the semiconductor layer 20. That is, in the diode region 22, the cathode region 26K is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. The cathode region 26K is adjacent to the collector region 26C in a direction perpendicular to the Z-axis direction. In one example, the n-type impurity concentration of the cathode region 26K is 1×10 19 cm -3 More than 1×10 20 cm -3 That is, the n-type impurity concentration of the cathode region 26K may be higher than the p-type impurity concentration of the collector region 26C.

[0058] In the diode region 22, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the diode region 22, the first region 20P does not include a carrier storage region 29. In the diode region 22, the buffer region 27 is adjacent to the cathode region 26K.

[0059] In the diode region 22, the plurality of trench structures 70 may include a plurality of diode trench structures 70D. Note that the number of diode trench structures 70D can be changed as appropriate depending on the desired characteristics of the diode 22A.

[0060] Each diode trench structure 70D includes a diode trench 71D, a diode insulating layer 72D, and a diode electrode 73D. The diode trench 71D has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the anode region 25A. The diode trench 71D reaches the drift region .

[0061] The multiple diode trenches 71D may be arranged at intervals of 0.1 μm to 10 μm in the X-axis direction. Each diode trench 71D may have a width (dimension in the X-axis direction) of 0.5 μm to 3 μm inclusive. Each diode trench 71D may have a depth (dimension in the Z-axis direction) of 1 μm to 10 μm inclusive. The shape of the diode trenches 71D shown in FIG. 4 may be the same as the shape of the gate trenches 71G. In one example, the size of the diode trenches 71D may be the same as the gate trenches 71G. The pitch of the diode trenches 71D is 1 / 2 the pitch of the gate trenches 71G. The size of the diode trenches 71D may be different from that of the gate trenches 71G. The pitch of the diode trenches 71D may be different from 1 / 2 the pitch of the gate trenches 71G.

[0062] The diode insulating layer 72D is provided in the diode trench 71D. When the diode insulating layer 72D is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the diode insulating layer 72D may form the sidewall and bottom wall of the diode trench 71D. The diode insulating layer 72D may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the diode insulating layer 72D may be made of the same material as the gate insulating layer 72G.

[0063] The diode insulating layer 72D is provided in a layered manner on the sidewalls and bottom wall of the diode trench 71D. As a result, a recess space is formed in the diode trench 71D by the diode insulating layer 72D. A diode electrode 73D is embedded in this recess space. Therefore, it can be said that the diode electrode 73D is embedded in the diode insulating layer 72D within the diode trench 71D.

[0064] The diode electrode 73D is configured to be applied with a potential different from the gate potential, for example, an anode potential. In one example, the anode potential is the same as the emitter potential. That is, the diode electrode 73D may be electrically connected to the first pad electrode 40E (see FIG. 1). The upper end surface of the diode electrode 73D may be located closer to the bottom wall of the diode trench 71D than the first surface 20S of the semiconductor layer 20. The diode electrode 73D is made of, for example, conductive polysilicon. In this way, the diode electrode 73D may be made of the same material as the gate electrode 73G.

[0065] The second electrode layer 55 is electrically connected to the cathode region 26K in the diode region 22. The second electrode layer 55 forms ohmic contact with the cathode region 26K. In this manner, a diode 22A can be configured in the diode region 22 by the structure between the first pad electrode 40E and the second electrode layer 55 in the diode region 22. For this reason, it can be said that the first pad electrode 40E configures the anode of the diode 22A, and the second electrode layer 55 configures the cathode of the diode 22A. In this manner, the first pad electrode 40E electrically connects the emitter of the IGBT 21A and the anode of the diode 22A. The second electrode layer 55 electrically connects the collector of the IGBT 21A and the cathode of the diode 22A.

[0066] (boundary area) In the boundary region 23, the second region 20Q may include a p-type boundary well region 25W. On the other hand, the emitter region 24 is not provided in the boundary region 23. Therefore, the boundary well region 25W includes a part of the first surface 20S of the semiconductor layer 20. That is, in the boundary region 23, the boundary well region 25W is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. Furthermore, the boundary well region 25W is adjacent to the first region 20P. In one example, the p-type impurity concentration of the boundary well region 25W is 1×10 15 cm -3 More than 1×10 18 cm -3 The following may be true: In one example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the boundary well region 25W may be different from the p-type impurity concentration of the base region 25B. In one example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the anode region 25A. In another example, the p-type impurity concentration of the boundary well region 25W may be different from the p-type impurity concentration of the anode region 25A.

[0067] Both the p-type cathode region 26K and the n-type collector region 26C adjacent to the first region 20P are arranged in the boundary region 23. That is, the boundary between the cathode region 26K and the collector region 26C is located in the boundary region 23.

[0068] In the boundary region 23, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the boundary region 23, the first region 20P does not include a carrier storage region 29. In the boundary region 23, the buffer region 27 is adjacent to both the cathode region 26K and the collector region 26C.

[0069] In the boundary region 23, the multiple trench structures 70 may include a boundary trench structure 70B. The boundary region 23 may include multiple boundary trench structures 70B. For example, the boundary region 23 may include two boundary trench structures 70B. The number of boundary trench structures 70B included in the boundary region 23 may be changed as appropriate. The width W3 of the boundary region 23 in the X-axis direction may be set so as to include multiple boundary trench structures 70B. For example, the width W3 of the boundary region 23 may be 5 μm or more and 10 μm or less.

[0070] Each boundary trench structure 70B includes a boundary trench 71B, a boundary insulating layer 72B, and a boundary electrode 73B. The boundary trench 71B has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the boundary well region 25W. The boundary trench 71B reaches the drift region .

[0071] The boundary trench 71B may have a width (dimension in the X-axis direction) of 0.5 μm or more and 3 μm or less. The boundary trench 71B may have a depth (dimension in the Z-axis direction) of 1 μm or more and 10 μm or less. The shape of the boundary trench 71B shown in FIG. 4 may be the same as the shape of the gate trench 71G. In one example, the size of the boundary trench 71B may be the same as the gate trench 71G. The size of the boundary trench 71B may be different from that of the gate trench 71G.

[0072] The boundary insulating layer 72B is provided in the boundary trench 71B. When the boundary insulating layer 72B is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the boundary insulating layer 72B may form the sidewall and bottom wall of the boundary trench 71B. The boundary insulating layer 72B may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the boundary insulating layer 72B may be made of the same material as the gate insulating layer 72G. The boundary insulating layer 72B is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the boundary insulating layer 72B.

[0073] The boundary insulating layer 72B is provided in a layered form on the sidewalls and bottom wall of the boundary trench 71B. As a result, a recess space is formed in the boundary trench 71B by the boundary insulating layer 72B. A boundary electrode 73B is embedded in this recess space. Therefore, it can be said that the boundary electrode 73B is embedded in the boundary insulating layer 72B within the boundary trench 71B.

[0074] The boundary electrode 73B is configured to be applied with an emitter potential. That is, the boundary electrode 73B may be electrically connected to the first pad electrode 40E (see FIG. 1). In one example, although not shown, the boundary electrode 73B is connected to a boundary contact at one end of the boundary trench 71B in the Y-axis direction. The boundary contact is connected to the first pad electrode 40E. As a result, the boundary electrode 73B is electrically connected to the first pad electrode 40E via the boundary contact. The upper end surface of the boundary electrode 73B may be located closer to the bottom wall of the boundary trench 71B than the first surface 20S of the semiconductor layer 20. The boundary electrode 73B is made of, for example, conductive polysilicon. In this way, the boundary electrode 73B may be made of the same material as the gate electrode 73G.

[0075] (LTC area) As shown in FIG. 4, the RC-IGBT 10 may include a lifetime control region 90 (hereinafter referred to as the "LTC region 90") provided within the semiconductor layer 20. The LTC region 90 is a region in which lifetime killers are intentionally provided, for example, by implanting impurities into the semiconductor layer 20. A lifetime killer is a carrier recombination center that shortens the lifetime. An example of a lifetime killer may be a crystal defect. The lifetime is the average time that excess carriers exist in a semiconductor material before recombining and reaching equilibrium. The LTC region 90 can be said to be a region in which crystal defects are provided within the semiconductor layer 20. The LTC region 90 is formed by implanting helium (He) into the semiconductor layer 20, for example. The lifetime killer is not limited to crystal defects, but may also be a vacancy, a divacancy, a complex defect of a vacancy or a divacancy with an element constituting the semiconductor layer 20, a dislocation, a rare gas element such as helium or neon (Ne), or a metal element such as platinum (Pt).

[0076] The LTC region 90 is provided so as to overlap with the diode region 22 in a planar view. The LTC region 90 may be provided over the entire diode region 22 in a planar view. On the other hand, the LTC region 90 is provided so as to be spaced apart from the IGBT region 21 in a planar view. An end 91 of the LTC region 90 is provided in the boundary region 23. It can be said that the LTC region 90 is provided so as to overlap with parts of the diode region 22 and the boundary region 23 in a planar view.

[0077] (insulating layer, first electrode layer, and intermediate member) The insulating layer 30 includes a first insulating layer 31 on the first surface 20S of the semiconductor layer 20 and a second insulating layer 32 on the first insulating layer 31. The first insulating layer 31 is in contact with the first surface 20S of the semiconductor layer 20. The second insulating layer 32 is in contact with the first insulating layer 31. The second insulating layer 32 may be stacked on the first insulating layer 31. In one example, the first insulating layer 31 and the second insulating layer 32 may be made of the same material. In another example, the first insulating layer 31 and the second insulating layer 32 may be made of different materials.

[0078] The first insulating layer 31 has a thickness thinner than the second insulating layer 32. The thickness of the first insulating layer 31 may be equal to the thickness of each of the gate insulating layer 72G, the emitter insulating layer 72E, the diode insulating layer 72D, and the boundary insulating layer 72B, for example. The first insulating layer 31 may be integrated with the gate insulating layer 72G and the emitter insulating layer 72E. The second insulating layer 32 covers the gate electrode 73G and the field plate electrode 73E.

[0079] The insulating layer 30 may include a diode opening 33. The diode opening 33 exposes the diode region 22. The diode opening 33 may also expose the boundary region 23. The insulating layer 30 is provided in the IGBT region 21. It can be said that the insulating layer 30 is provided so as to cover the IGBT region 21 while exposing the diode region 22 and the boundary region 23.

[0080] In one example, the side surface 33A of the insulating layer 30 constituting the diode opening 33 may be inclined toward the diode region 22 from the upper surface 30S of the insulating layer 30 toward the first surface 20S of the semiconductor layer 20. The diode opening 33 may expose the entire diode region 22 in the Y-axis direction. The diode opening 33 may expose the entire diode region 22 in the X-axis direction. The diode opening 33 may also expose the entire boundary region 23 in the Y-axis direction. The side surface 33A of the insulating layer 30 may be located in, for example, the boundary region 23. That is, a portion of the insulating layer 30 in the X-axis direction may be provided in the boundary region 23. In one example, the side surface 33A of the insulating layer 30 is located at an end of the boundary region 23 closer to the IGBT region 21. More specifically, the side surface 33A of the insulating layer 30 is located closer to the IGBT region 21 than the center in the X-axis direction of the boundary well region 25W adjacent to the IGBT region 21.

[0081] The first pad electrode 40E of the first electrode layer 40 may include electrode portions corresponding to the respective regions. For example, the first pad electrode 40E may include a first electrode portion 41, a second electrode portion 42, and a third electrode portion 43. The first electrode portion 41 is provided corresponding to the IGBT region 21. The first electrode portion 41 is provided on the insulating layer 30. The first electrode portion 41 is in contact with the upper surface 30S of the insulating layer 30. The second electrode portion 42 is provided corresponding to the diode region 22. The second electrode portion 42 is provided within the diode opening 33. For example, the second electrode portion 42 is in contact with the first surface 20S of the semiconductor layer 20 in the diode region 22. The third electrode portion 43 is provided corresponding to the boundary region 23. The third electrode portion 43 is provided within the diode opening 33. For example, the third electrode portion 43 is provided on the first surface 20S of the semiconductor layer 20 in the boundary region 23.

[0082] The RC-IGBT 10 includes an intermediate layer 60. The intermediate layer 60 is provided in the boundary region 23. The intermediate layer 60 is provided between the third electrode portion 43 of the first electrode layer 40 and the first surface 20S of the semiconductor layer 20.

[0083] The intermediate layer 60 includes a first surface 60S and a second surface 60R opposite to the first surface 60S. The first surface 60S and the second surface 60R face opposite each other in the Z-axis direction. The first surface 60S of the intermediate layer 60 is in contact with the third electrode portion 43 of the first electrode layer 40. The second surface 60R of the intermediate layer 60 is in contact with the first surface 20S of the semiconductor layer 20.

[0084] The intermediate layer 60 may be in contact with the insulating layer 30 in the X-axis direction. The insulating layer 30 may cover an end 61 of the intermediate layer 60 closer to the IGBT region 21. The insulating layer 30 includes a first insulating layer 31 covering the first surface 20S of the semiconductor layer 20 and a second insulating layer 32 on the first insulating layer 31. The first insulating layer 31 may be in contact with the end 61 of the intermediate layer 60 closer to the IGBT region 21. The second insulating layer 32 may cover the end 61 of the intermediate layer 60. In one example, the intermediate layer 60 may be provided so as to be in contact with the boundary well region 25W in the boundary region 23, which is closer to the IGBT region 21 than the boundary trench structure 70B. As a result, the intermediate layer 60 is in contact with the boundary well region 25W closer to the IGBT region 21 than the boundary trench structure 70B.

[0085] The intermediate layer 60 extends from the insulating layer 30 toward the diode region 22. The intermediate layer 60 extends across the entire boundary region 23 in the X-axis direction. In one example, the intermediate layer 60 may be provided so as to be in contact with the boundary well region 25W in the boundary region 23, which is closer to the diode region 22 than the boundary trench structure 70B. As a result, the intermediate layer 60 is in contact with the boundary well region 25W, which is closer to the diode region 22 than the boundary trench structure 70B.

[0086] 1 and 2, an IGBT region 21 and a diode region 22 are arranged in the X-axis direction. A boundary region 23 shown in FIGS. 3 and 4 is provided between the IGBT region 21 and the diode region 22 in the X-axis direction. The boundary region 23 extends in the Y-axis direction, which is perpendicular to the X-axis direction, between adjacent IGBT regions 21 and diode regions 22. The intermediate layer 60 may extend in the Y-axis direction along the boundary region 23. The intermediate layer 60 may extend across the entire boundary region 23 in the Y-axis direction.

[0087] The intermediate layer 60 may be conductive. The conductive intermediate layer 60 may electrically connect the third electrode portion 43 and the boundary well region 25W. The intermediate layer 60 may be provided along the first surface 20S of the semiconductor layer 20 and the boundary trench structure 70B. That is, the intermediate layer 60 includes a portion that extends from the first surface 20S toward the second surface 20R of the semiconductor layer 20 at a position corresponding to the boundary trench structure 70B. The intermediate layer 60 may include a recess 63 at a position corresponding to the boundary trench structure 70B. The intermediate layer 60 extends into the boundary trench 71B at a position corresponding to the boundary trench structure 70B, thereby contacting the boundary electrode 73B. Therefore, it can be said that the intermediate layer 60 is in contact with both the third electrode portion 43 and the boundary electrode 73B.

[0088] The thickness T5 of the intermediate layer 60 is thinner than the thickness T4 of the insulating layer 30. The thickness T4 of the insulating layer 30 may be 1 μm or more and 5 μm or less. The thickness T5 of the intermediate layer 60 may be thinner than the thickness of the second insulating layer 32. The thickness T5 of the intermediate layer 60 may be greater than or equal to the thickness of the first insulating layer 31. In one example, the thickness T5 of the intermediate layer 60 may be ½ of the thickness T4 of the insulating layer 30.

[0089] The intermediate layer 60 is made of conductive polysilicon. The intermediate layer 60 may be made of the same material as the boundary electrode 73B. In one example, the intermediate layer 60 may be provided integrally with the boundary electrode 73B. The intermediate layer 60 and the boundary electrode 73B may be one body. The intermediate layer 60 may be made of polysilicon doped with impurities. In one example, the impurity concentration of the intermediate layer 60 is 1×10 19 cm -3 More than 1×10 21 cm -3 It may be the following:

[0090] The first electrode portion 41, the second electrode portion 42, and the third electrode portion 43 each include a first surface 41S, 42S, and 43S on the side opposite to the semiconductor layer 20. The first surface 41S of the first electrode portion 41, the first surface 42S of the second electrode portion 42, and the first surface 43S of the third electrode portion 43 form a first surface 40S of the first pad electrode 40E of the first electrode layer 40.

[0091] The first electrode portion 41 has a first thickness T1 in the Z-axis direction. The first thickness T1 of the first electrode portion 41 may be expressed as the distance from the upper surface 30S of the insulating layer 30 to the first surface 41S of the first electrode portion 41. The second electrode portion 42 has a second thickness T2 in the Z-axis direction. The second thickness T2 of the second electrode portion 42 may be expressed as the distance from the first surface 20S of the semiconductor layer 20 to the first surface 42S of the second electrode portion 42. The third electrode portion 43 has a third thickness T3 in the Z-axis direction. The third thickness T3 of the third electrode portion 43 may be expressed as the distance from the first surface 60S of the intermediate layer 60 to the first surface 43S of the third electrode portion 43. In one example, the first thickness T1 of the first electrode portion 41, the second thickness T2 of the second electrode portion 42, and the third thickness T3 of the third electrode portion 43 are equal to one another. At least one of the first thickness T1 of the first electrode portion 41, the second thickness T2 of the second electrode portion 42, and the third thickness T3 of the third electrode portion 43 may be different from the others, or may be different from each other.

[0092] The first electrode portion 41, the second electrode portion 42, and the third electrode portion 43 may be an integrally formed one piece. The thickness of the first electrode layer 40 may be indicated by a first thickness T1 of the first electrode portion 41, for example. The first thickness T1 of the first electrode layer 40 may be greater than the thickness T4 of the insulating layer 30. The first thickness T1 of the first electrode layer 40 may be greater than or equal to 3 μm and less than or equal to 7 μm, for example.

[0093] The first pad electrode 40E includes a first step portion 44 provided between the first electrode portion 41 and the third electrode portion 43. The first step portion 44 includes a first curved portion 44A connected to the first electrode portion 41 and a second curved portion 44B connected to the third electrode portion 43. The first step portion 44 may include a first inclined surface 44C between the first curved portion 44A and the second curved portion 44B. The first inclined surface 44C may be inclined so that the second curved portion 44B is closer to the diode region 22 than the first curved portion 44A.

[0094] The first pad electrode 40E includes a second step portion 45 provided between the third electrode portion 43 and the second electrode portion 42. The second step portion 45 includes a third curved portion 45A connected to the third electrode portion 43 and a fourth curved portion 45B connected to the third electrode portion 43. The second step portion 45 may include a second inclined surface 45C between the third curved portion 45A and the fourth curved portion 45B. The second inclined surface 45C may be inclined so that the third curved portion 45A is closer to the IGBT region 21 than the fourth curved portion 45B.

[0095] The first step portion 44 has a first distance D1 between the first surface 41S of the first electrode portion 41 and the first surface 43S of the third electrode portion 43 in the Z-axis direction. The second step portion 45 has a second distance D2 between the first surface 43S of the third electrode portion 43 and the first surface 42S of the second electrode portion 42 in the Z-axis direction. In one example, the first distance D1 may be smaller than the second distance D2. That is, the first distance D1 between the first surface 41S of the first electrode portion 41 and the first surface 43S of the third electrode portion 43 in the Z-axis direction is smaller than the second distance D2 between the first surface 43S of the third electrode portion 43 and the first surface 42S of the second electrode portion 42 in the Z-axis direction. In this case, for example, the influence of stress on the diode region 22 can be reduced. Note that the first distance D1 may be equal to the second distance D2. Alternatively, the first distance D1 may be greater than the second distance D2.

[0096] <Operation of the embodiment> The operation of the RC-IGBT 10 of this embodiment will be described. Fig. 5 shows a schematic plan view of a semiconductor device 100 including an RC-IGBT 10 according to an embodiment. Fig. 6 is a schematic cross-sectional view of the semiconductor device 100 taken along line F6-F6 shown in Fig. 5. Figs. 5 and 6 show an example of mounting the RC-IGBT 10 according to an embodiment.

[0097] The semiconductor device 100 may be configured as a single semiconductor package or a single semiconductor module including the RC-IGBT 10. For example, the semiconductor device 100 may be a TO (Transistor Outline) type package including three terminals, for example, a TO-220 package. Note that the package structure of the semiconductor device 100 may be changed as desired.

[0098] The semiconductor device 100 includes a sealing resin 102. The sealing resin 102 is made of, for example, a mold resin. The material that makes up the sealing resin 102 may be, for example, a black epoxy resin. In one example, the sealing resin 102 has a rectangular parallelepiped shape with its thickness direction aligned in the Z-axis direction.

[0099] The semiconductor device 100 includes a metal plate 104 partially sealed in a sealing resin 102 , a first lead 120 , a second lead 122 , and a third lead 124 , and an RC-IGBT 10 sealed in the sealing resin 102 .

[0100] The metal plate 104 is flat and has a thickness in the Z-axis direction. The metal plate 104 is made of a material containing at least one of Cu, iron (Fe), and Al. The metal plate 104 includes a die pad 106. The die pad 106 includes a first portion 106A provided within the sealing resin 102 in a plan view, and a second portion 106B protruding from the sealing resin 102 in the Y-axis direction in a plan view. The first portion 106A and the second portion 106B are integrated. The sealing resin 102 may cover the entire die pad 106 when viewed from the Z-axis direction.

[0101] The first portion 106A has a rectangular shape in a plan view. The RC-IGBT 10 is mounted on the first portion 106A. The RC-IGBT 10 is bonded to the first portion 106A by a conductive bonding material SD1. It can also be said that the second electrode layer 55 of the RC-IGBT 10 is electrically connected to the first portion 106A by the conductive bonding material SD1. As a result, the second electrode layer 55 is electrically connected to the metal plate 104.

[0102] The second lead 122 includes a portion that protrudes in the Y-axis direction from the sealing resin 102 in a plan view. The second lead 122 is provided on the opposite side of the first portion 106A to the second portion 106B in the Y-axis direction.

[0103] In one example, the die pad 106 and the second lead 122 may be integrated into one piece. The second lead 122 may be bonded to the die pad 106. The second lead 122 protrudes from the center of the sealing resin 102 in the X-axis direction in a plan view.

[0104] The first lead 120 and the third lead 124 are arranged with the second lead 122 sandwiched between them in the X-axis direction in a plan view. Both the first lead 120 and the third lead 124 protrude from the sealing resin 102 in the Y-axis direction in a plan view. The first lead 120, the second lead 122, and the third lead 124 are made of a material containing at least one of Cu, Fe, and Al. In one example, the first lead 120, the second lead 122, and the third lead 124 may be made of the same material as the metal plate 104. A plating film made of a metal having high affinity (bonding strength) for solder may be provided on the outer surfaces of the second lead 122, the first lead 120, and the third lead 124. The plating film may include at least one of a Ni plating film, a Pd plating film, and an Au plating film.

[0105] The second pad electrode 40G is electrically connected to the first lead 120 by a wire 130. The first pad electrode 40E is electrically connected to the third lead 124 by a clip 132. The clip 132 may have any shape (outer shape) and thickness. The clip 132 is a conductive, plate-like connection plate. The clip 132 may be bent in accordance with the positional relationship between the first pad electrode 40E of the RC-IGBT 10 and the third lead 124. The clip 132 may be made of a material containing at least one of Cu and Al.

[0106] The clip 132 may include a first connection portion 132A and a second connection portion 132B. The first connection portion 132A and the second connection portion 132B are integrally formed. The first connection portion 132A includes a bonding surface that faces the first pad electrode 40E of the RC-IGBT 10.

[0107] 6, the first connection portion 132A of the clip 132 is electrically connected to the first pad electrode 40E by a conductive bonding material SD2. For example, the conductive bonding material SD2 may be solder. For example, the conductive bonding material SD2 may be disposed on the first pad electrode 40E of the RC-IGBT 10.

[0108] Here, a comparative example to the RC-IGBT 10 of the embodiment will be described. Fig. 7 shows a cross-sectional structure of an RC-IGBT 10X of a comparative example. Fig. 7 shows a cross section corresponding to the RC-IGBT 10 of the embodiment shown in Fig. 4. In the RC-IGBT 10X of the comparative example shown in Fig. 7, the same names and symbols are used for components corresponding to the RC-IGBT 10 of the embodiment shown in Fig. 4.

[0109] The RC-IGBT 10X of the comparative example does not include the intermediate layer 60, unlike the RC-IGBT 10 of the embodiment. Therefore, the RC-IGBT 10X of the comparative example includes a first step portion 44X between the first electrode portion 41 and the third electrode portion 43, but does not include the second step portion 45 of the embodiment. In other words, the RC-IGBT 10X of the comparative example does not include a step between the first surface 42S of the second electrode portion 42 and the first surface 43S of the third electrode portion 43.

[0110] In the first step portion 44X, the distance D1X between the first surface 41S of the first electrode portion 41 and the first surface 43S of the third electrode portion 43 is greater than the first distance D1 and the second distance D2 of the embodiment.

[0111] The conductive bonding material SD2 made of solder may be spread on the upper surface of the first pad electrode 40E. In one example, the conductive bonding material SD2 is disposed on a portion of the first surface 40S of the first pad electrode 40E. Then, the conductive bonding material SD2 melted by the reflow process is spread so as to cover the entire first pad electrode 40E.

[0112] In the case of the RC-IGBT10X of the comparative example, the conductive bonding material SD2 melted during the reflow process is unlikely to spread from the second electrode portion 42 in the diode region 22 and the third electrode portion 43 in the boundary region 23 to the first electrode portion 41 because the distance D1X of the first step portion 44X is large. This may make it difficult to join the clip 132 shown in FIGS. 5 and 6 .

[0113] In contrast, in the RC-IGBT 10 of the embodiment, the second distance D2 at the second step 45 between the second electrode portion 42 in the diode region 22 and the third electrode portion 43 in the boundary region 23 is smaller than the distance D1X in the comparative example. Furthermore, the first distance D1 at the first step 44 between the third electrode portion 43 in the boundary region 23 and the first electrode portion 41 in the IGBT region 21 is smaller than the distance D1X in the comparative example. Therefore, the conductive bonding material SD2 melted during the reflow process easily spreads from the diode region 22 through the boundary region 23 to the IGBT region 21. In other words, in the RC-IGBT 10 of the embodiment, the conductive bonding material SD2 can be spread to cover the entire first pad electrode 40E.

[0114] The intermediate layer 60 is made of a conductive material and electrically connects the first pad electrode 40E and the boundary electrode 73B. This allows the boundary electrode 73B to easily be at the emitter potential.

[0115] In one example, the intermediate layer 60 is made of conductive polysilicon. In one example, the boundary electrode 73B is made of conductive polysilicon. The intermediate layer 60 is connected to the boundary electrode 73B. Therefore, the intermediate layer 60 can be formed continuously with the boundary electrode 73B or in the same process. This makes it easy to arrange the intermediate layer 60.

[0116] <Effects of the embodiment> As described above, the RC-IGBT 10 of the embodiment provides the following effects. (1) The RC-IGBT 10 includes a semiconductor layer 20 including a first surface 20S, an IGBT region 21 and a diode region 22 provided on the first surface 20S while being spaced apart in the X-axis direction in a planar view seen from a thickness direction perpendicular to the first surface 20S, a boundary region 23 provided between the IGBT region 21 and the diode region 22 in the X-axis direction, an insulating layer 30 provided to cover a portion of the first surface 20S corresponding to the IGBT region 21 while exposing portions corresponding to both the diode region 22 and the boundary region 23, a first electrode layer 40 including a first electrode portion 41 provided on the insulating layer 30 in the IGBT region 21, a second electrode portion 42 provided on the first surface 20S in the diode region 22, and a third electrode portion 43 provided on the first surface 20S in the boundary region 23, and an intermediate layer 60 arranged between the third electrode portion 43 and the first surface 20S. The intermediate layer 60 is in contact with the insulating layer 30 in the X-axis direction, and the thickness T5 of the intermediate layer 60 is smaller than the thickness T4 of the insulating layer 30.

[0117] In the RC-IGBT 10 of the embodiment, the second distance D2 between the second electrode portion 42 in the diode region 22 and the third electrode portion 43 in the boundary region 23 is smaller than the distance D1X in a comparative example that does not include the intermediate layer 60. The first distance D1 between the third electrode portion 43 in the boundary region 23 and the first electrode portion 41 in the IGBT region 21 is smaller than the distance D1X in the RC-IGBT 10X of the comparative example that does not include the intermediate layer 60. Therefore, the conductive bonding material SD2 melted during the reflow process easily spreads from the diode region 22 through the boundary region 23 to the IGBT region 21. In other words, in the RC-IGBT 10 of the embodiment, the conductive bonding material SD2 can be spread so as to cover the entire first pad electrode 40E.

[0118] (2) The intermediate layer 60 may extend in the X-axis direction across the entire boundary region 23. Since the slope of the first surface 40S of the first electrode layer 40 is substantially gentle, the conductive bonding material SD2 can spread more easily.

[0119] (3) The thickness T5 of the intermediate layer 60 may be half the thickness T4 of the insulating layer 30. In the first electrode layer 40, the first distance D1 between the first electrode portion 41 and the third electrode portion 43 and the second distance D2 between the third electrode portion 43 and the second electrode portion 42 are approximately equal, which makes it easier for the conductive bonding material SD2 to spread.

[0120] (4) The first electrode layer 40 includes a first step portion 44 provided between the first electrode portion 41 and the third electrode portion 43. The first step portion 44 includes a first curved portion 44A connected to the first electrode portion 41 and a second curved portion 44B connected to the third electrode portion 43. Therefore, the conductive bonding material SD2 can be easily spread from the third electrode portion 43 toward the first electrode portion 41.

[0121] (5) The first electrode layer 40 includes a second step portion 45 provided between the third electrode portion 43 and the second electrode portion 42. The second step portion 45 includes a third curved portion 45A connected to the third electrode portion 43 and a fourth curved portion 45B connected to the second electrode portion 42. Therefore, the conductive bonding material SD2 can be easily spread from the second electrode portion 42 toward the third electrode portion 43.

[0122] (6) The intermediate layer 60 is made of a conductive material. The intermediate layer 60 electrically connects the first pad electrode 40E and the boundary electrode 73B. Therefore, the boundary electrode 73B can easily be set to the emitter potential.

[0123] (7) In one example, the intermediate layer 60 is made of conductive polysilicon. In one example, the boundary electrode 73B is made of conductive polysilicon. The intermediate layer 60 is connected to the boundary electrode 73B. Therefore, the intermediate layer 60 can be formed continuously with the boundary electrode 73B or in the same process. This makes it easy to arrange the intermediate layer 60.

[0124] (8) The intermediate layer 60 and the boundary electrode 73B are integrated. With this configuration, the intermediate layer 60 and the boundary electrode 73B can be formed in a common process. This simplifies the manufacturing process of the RC-IGBT 10.

[0125] <Example of change> The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0126] The configuration of the RC-IGBT 10 may be changed as appropriate. 8 to 10 show modifications to the RC-IGBT 10 of the embodiment. Figures 8 to 10 show cross sections at positions corresponding to the cross section of the RC-IGBT 10 shown in Figure 4.

[0127] The RC-IGBT 210 of the modified example shown in FIG. 8 includes an intermediate layer 260. Compared to the intermediate layer 60 of the embodiment, the intermediate layer 260 may include an inclined side surface 62A at an end 62 closer to the diode region 22. The side surface 62A is inclined so that its upper end is closer to the IGBT region 21 than its lower end. It can also be said that the side surface 62A is inclined so that it extends toward the diode region 22 as it extends from the first surface 60S of the intermediate layer 260 toward the first surface 20S of the semiconductor layer 20. The inclined side surface 62A of the intermediate layer 260 in this manner can make the inclination of the second inclined surface 45C of the second step portion 45 of the first pad electrode 40E in the first electrode layer 40 covering the intermediate layer 260 gentler. As a result, the conductive bonding material SD2 can more easily spread from the second electrode portion 42 in the diode region 22 to the third electrode portion 43 in the boundary region 23.

[0128] The RC-IGBT 310 of the modified example shown in FIG. 9 includes an intermediate layer 360. The intermediate layer 360 may include a first portion 361 and a second portion 362. The first portion 361 is a portion provided corresponding to the boundary region 23 and may have a configuration similar to that of the intermediate layer 60 of the embodiment. The second portion 362 can be considered to be a portion that protrudes from the boundary region 23 into the diode region 22. This second portion 362 allows the position of the second step portion 45 to be adjusted. The intermediate layer 360 may be connected to the diode electrode 73D in the diode region 22. Using the conductive intermediate layer 360 allows the potential of the boundary electrode 73B in the boundary region 23 to be the same as that of the diode electrode 73D. The intermediate layer 360 may be made of the same material as the boundary electrode 73B and the diode electrode 73D. The intermediate layer 360 may be formed integrally with the boundary electrode 73B and the diode electrode 73D.

[0129] 10 includes an insulating layer 430. In addition to the configuration of the insulating layer 30 of the embodiment, the insulating layer 430 can include a protruding portion 431 that protrudes from the IGBT region 21 into the boundary region 23. The first electrode layer 40 includes a first step portion 44 that corresponds to the protruding portion 431 of the insulating layer 430. Therefore, the position of the first step portion 44 can be adjusted by using this protruding portion 431.

[0130] The intermediate layer 60 may have insulating properties. The intermediate layer 60 may be made of the same material as the insulating layer 30. The intermediate layer 60 may be provided integrally with the insulating layer 30. The intermediate layer 60 may be made of a different material from the insulating layer 30. In one example, the insulating layer 30 is made of a first insulating layer 31 and a second insulating layer 32. When the first insulating layer 31 and the second insulating layer 32 are made of different materials, the intermediate layer 60 may be made of the same material as either the first insulating layer 31 or the second insulating layer 32. Alternatively, the intermediate layer 60 may be made of a different material from both the first insulating layer 31 and the second insulating layer 32.

[0131] The semiconductor device 100 shown in Figures 5 and 6 shows an example of a mounting of the RC-IGBT 10. The semiconductor device using the RC-IGBT 10 is not limited to a TO-type package and can be arbitrarily changed. The semiconductor device 100 may be configured in various packages, such as a small outline package (SOP), a quad for non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), or a small outline J-leaded package (SOJ), or similar packages.

[0132] The semiconductor device may also be configured as a semiconductor module including the RC-IGBT 10 and a support substrate on which the RC-IGBT 10 is mounted. The support substrate may be made of an insulating material such as ceramics or epoxy resin. The support substrate may also be a substrate including a metal plate as a core, the surface of which is covered with an insulating material.

[0133] The support substrate includes a first surface and a second surface opposite to the first surface, and the first surface includes a first electrode on which the RC-IGBT 10 is mounted and a second electrode serving as a terminal disposed apart from the RC-IGBT 10 mounted on the first electrode. A first pad electrode 40E of the RC-IGBT 10 is electrically connected to the second electrode by a clip 132.

[0134] The first surface of the support substrate may have mounted thereon elements other than the RC-IGBT 10. The second surface of the support substrate may have electrodes or elements mounted thereon for mounting the semiconductor module on another circuit board.

[0135] The end 61 of the intermediate layer 60 that is closer to the IGBT region 21 does not have to be covered with the insulating layer 30 . The lifetime control region 90 may be omitted.

[0136] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0137] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0138] [Appendix 1] a semiconductor layer including a first surface; an IGBT region and a diode region provided on the first surface so as to be spaced apart in a first direction in a plan view seen from a thickness direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; an insulating layer provided to cover a portion of the first surface corresponding to the IGBT region and to expose portions corresponding to both the diode region and the boundary region; an electrode layer including a first electrode portion provided on the insulating layer in the IGBT region, a second electrode portion provided on the first surface in the diode region, and a third electrode portion provided on the first surface in the boundary region; an intermediate layer disposed between the third electrode portion and the first surface; Including, the intermediate layer is in contact with the insulating layer in the first direction, The thickness of the intermediate layer is thinner than the thickness of the insulating layer. RC-IGBT.

[0139] [Appendix 2] the intermediate layer extends across the entire boundary region in the first direction; RC-IGBT as described in Appendix 1.

[0140] [Appendix 3] The thickness of the intermediate layer is half the thickness of the insulating layer. RC-IGBTs as described in Appendix 1 or Appendix 2.

[0141] [Appendix 4] The thickness of the electrode layer is equal to or greater than the thickness of the insulating layer. 1. An RC-IGBT according to any one of Supplementary Note 1 to Supplementary Note 3.

[0142] [Appendix 5] The electrode layer is a first step portion provided between the first electrode portion and the third electrode portion; a second step portion provided between the third electrode portion and the second electrode portion; Including, The first step portion is a first curved portion connected to the first electrode portion; a second curved portion connected to the third electrode portion; Including, The second step portion is a third curved portion connected to the third electrode portion; a fourth curved portion connected to the second electrode portion; Including, 1. The RC-IGBT according to any one of Supplementary Note 1 to Supplementary Note 4.

[0143] [Appendix 6] the first electrode portion, the second electrode portion, and the third electrode portion each include a first surface opposite to the semiconductor layer, In the thickness direction, a first distance between a first surface of the first electrode portion and a first surface of the third electrode portion is smaller than a second distance between the first surface of the third electrode portion and a first surface of the second electrode portion. RC-IGBT as described in Appendix 5.

[0144] [Appendix 7] The intermediate layer is made of a conductive material. 1. The RC-IGBT according to any one of Supplementary Note 1 to Supplementary Note 6.

[0145] [Appendix 8] The intermediate layer is made of conductive polysilicon. RC-IGBT as described in Appendix 7.

[0146] [Appendix 9] a boundary trench provided corresponding to the boundary region; a boundary insulating layer disposed in the boundary trench; a boundary electrode embedded in the boundary insulating layer in the boundary trench; Including, the intermediate layer is connected to the boundary electrode; An RC-IGBT as described in Appendix 7 or Appendix 8.

[0147] [Appendix 10] the intermediate layer is integral with the boundary electrode; RC-IGBT as described in Appendix 9.

[0148] [Appendix 11] The boundary trenches are provided in plurality and spaced apart from each other in the first direction. RC-IGBT as described in Appendix 9 or Appendix 10.

[0149] [Appendix 12] the intermediate layer extends across the boundary trenches in the first direction; RC-IGBT as described in Appendix 11.

[0150] [Appendix 13] The intermediate layer is made of an insulating material. 1. The RC-IGBT according to any one of Supplementary Note 1 to Supplementary Note 6.

[0151] [Appendix 14] The intermediate layer is integrated with the insulating layer. RC-IGBT as described in Appendix 13.

[0152] [Appendix 15] the intermediate layer includes a protruding portion that protrudes into the diode region in the first direction. 15. The RC-IGBT of any one of Supplementary Notes 1 to 14.

[0153] [Appendix 16] A direction perpendicular to the first direction in a plan view is defined as a second direction, the intermediate layer extends across the entire boundary region in the second direction. 16. The RC-IGBT of any one of Supplementary Notes 1 to 15.

[0154] [Appendix 17] The insulating layer covers an end portion of the intermediate layer that is closer to the IGBT region. 17. The RC-IGBT of any one of Supplementary Notes 1 to 16.

[0155] [Appendix 18] an end surface of the intermediate layer on the diode region side is inclined so as to extend toward the diode region as it approaches the first surface; 17. The RC-IGBT of any one of Supplementary Note 1 to Supplementary Note 17.

[0156] [Appendix 19] The thickness of the intermediate layer is 2 μm or less. 19. The RC-IGBT of any one of Supplementary Notes 1 to 18.

[0157] [Appendix 20] The width of the boundary region in the first direction is not less than 5 μm and not more than 10 μm. 19. The RC-IGBT of any one of Supplementary Note 1 to Supplementary Note 19.

[0158] [Appendix 21] the semiconductor layer includes a drift region of a first conductivity type; The IGBT region is a second conductivity type base region provided on the first surface; a gate trench having an opening in the first surface and extending through the base region; a gate insulating layer provided in the gate trench; a gate electrode embedded in the gate insulating layer in the gate trench; Including, The diode region is an anode region of a second conductivity type provided on the first surface; a diode trench having an opening in the first surface and extending through the anode region; a diode insulating layer disposed within the diode trench; a diode electrode embedded in the diode trench and in the diode insulating layer; Including, 21. The RC-IGBT of any one of Supplementary Note 1 to Supplementary Note 20.

[0159] [Appendix 22] The semiconductor layer is a second surface opposite the first surface; a collector region provided in a portion close to the second surface and at a position corresponding to the IGBT region; a cathode region provided in a portion close to the second surface and at a position corresponding to the diode region; Including, the boundary between the collector region and the cathode region is located in the boundary region; RC-IGBT as described in Appendix 21.

[0160] [Appendix 23] a second electrode layer provided on the second surface; RC-IGBT as described in Appendix 22.

[0161] [Appendix 24] a lifetime control region provided in the semiconductor layer and overlapping the diode region and the boundary region in a plan view; An end of the lifetime control region is located in the boundary region. 24. The RC-IGBT of any one of Supplementary Note 1 to Supplementary Note 23.

[0162] [Appendix 25] An RC-IGBT according to any one of Supplementary Note 1 to Supplementary Note 24; a terminal disposed apart from the RC-IGBT; a clip connecting the electrode layer and the terminal of the RC-IGBT; a conductive bonding material interposed between the electrode layer and the clip; 10. A semiconductor device comprising:

[0163] [Appendix 26] An RC-IGBT, a semiconductor layer including a first surface; an IGBT region and a diode region provided on the first surface so as to be spaced apart in a first direction in a plan view seen from a thickness direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; an insulating layer provided to cover a portion of the first surface corresponding to the IGBT region and to expose portions corresponding to both the diode region and the boundary region; an electrode layer including a first electrode portion provided on the insulating layer in the IGBT region, a second electrode portion provided on the first surface in the diode region, and a third electrode portion provided on the first surface in the boundary region; an intermediate layer disposed between the third electrode portion and the first surface; Including, the intermediate layer is in contact with the insulating layer in the first direction, The thickness of the intermediate layer is thinner than the thickness of the insulating layer. RC-IGBT and a terminal disposed apart from the RC-IGBT; a clip connecting the electrode layer and the terminal of the RC-IGBT; a conductive bonding material interposed between the electrode layer and the clip; 10. A semiconductor device comprising:

[0164] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0165] 10 Semiconductor device 11 Cell Area 12 Outer area 20 Semiconductor layer 20S 1st page 20R, Side 2 20A Sub-area 20P 1st area 20Q 2nd area 21 IGBT area 21A IGBT 22 Diode Region 22A diode 23 Boundary area 24 Emitter Area 25B Base area 25A anode area 25W Boundary Well Area 26C Collector Region 26K cathode area 27 Buffer Area 28 Drift Region 29 Carrier Storage Area 30 insulating layer 30S top surface 31 First insulating layer 32 Second insulating layer 33 Diode opening 33A side 40 1st electrode layer 40E First pad electrode (emitter pad electrode) 40G Second pad electrode (gate pad electrode) 40S 1st page 41 1st electrode part 41S Page 1 42 Second electrode part 42S 1st page 43 Third electrode part 43S 1st page 44 First step 44A First curved section 44B Second curved section 44C 1st slope 45 Second step 45A Third curved section 45B 4th curved section 45C 2nd slope 51 Gate wiring 52 Gate Finger 55 Second electrode layer 60 Middle Class 60S 1st page 60R 2nd side 61,62 End 62A Side 63 Recess 70 Trench structure 70G gate trench structure 71G Gate Trench 72G gate insulating layer 73G Gate electrode 70E Emitter trench structure 71E Emitter Trench 72E Emitter insulating layer 73E Field plate electrode 70D diode trench structure 71D Diode Trench 72D Diode insulating layer 73D Diode Electrode 70B Boundary Trench Structure 71B Boundary Trench 72B Boundary Insulation Layer 73B Boundary electrode 80 contact structure 81 Contact hole 82 Emitter contact 82A First conductive layer 82B Second conductive layer 83 Base contact region 90 LTC region (lifetime control region) 91 End 260 Middle Class 360 Middle Class 361 Part 1 362 Part 2 430 Insulation Layer 431 Protruding part D1 First distance D2 2nd distance T1~T3 1st~3rd thickness T4, T5 thickness W3 width

Claims

1. a semiconductor layer including a first surface; an IGBT region and a diode region provided on the first surface so as to be spaced apart in a first direction in a plan view seen from a thickness direction perpendicular to the first surface; a boundary region provided between the IGBT region and the diode region in the first direction; an insulating layer provided to cover a portion of the first surface corresponding to the IGBT region and to expose portions of the first surface corresponding to both the diode region and the boundary region; an electrode layer including a first electrode portion provided on the insulating layer in the IGBT region, a second electrode portion provided on the first surface in the diode region, and a third electrode portion provided on the first surface in the boundary region; an intermediate layer disposed between the third electrode portion and the first surface; Including, the intermediate layer is in contact with the insulating layer in the first direction, The thickness of the intermediate layer is thinner than the thickness of the insulating layer. RC-IGBT.

2. the intermediate layer extends across the entire boundary region in the first direction; The RC-IGBT according to claim 1.

3. The thickness of the intermediate layer is half the thickness of the insulating layer. The RC-IGBT according to claim 1.

4. The thickness of the electrode layer is equal to or greater than the thickness of the insulating layer. The RC-IGBT according to claim 1.

5. The electrode layer is a first step portion provided between the first electrode portion and the third electrode portion; a second step portion provided between the third electrode portion and the second electrode portion; Including, The first step portion is a first curved portion connected to the first electrode portion; a second curved portion connected to the third electrode portion; Including, The second step portion is a third curved portion connected to the third electrode portion; a fourth curved portion connected to the second electrode portion; Including, The RC-IGBT according to claim 1.

6. the first electrode portion, the second electrode portion, and the third electrode portion each include a first surface opposite to the semiconductor layer, a first distance between a first surface of the first electrode portion and a first surface of the third electrode portion in the thickness direction is smaller than a second distance between the first surface of the third electrode portion and a first surface of the second electrode portion; The RC-IGBT according to claim 5.

7. The intermediate layer is made of a conductive material. The RC-IGBT according to claim 1.

8. The intermediate layer is made of conductive polysilicon. The RC-IGBT according to claim 7.

9. a boundary trench provided corresponding to the boundary region; a boundary insulating layer disposed in the boundary trench; a boundary electrode embedded in the boundary insulating layer in the boundary trench; Including, the intermediate layer is connected to the boundary electrode; The RC-IGBT according to claim 7.

10. the intermediate layer is integral with the boundary electrode; The RC-IGBT according to claim 9.

11. The boundary trenches are provided in plurality and spaced apart from each other in the first direction. The RC-IGBT according to claim 9.

12. the intermediate layer extends across the boundary trenches in the first direction; The RC-IGBT according to claim 11.

13. The intermediate layer is made of an insulating material. The RC-IGBT according to claim 1.

14. The intermediate layer is integrated with the insulating layer. The RC-IGBT according to claim 13.

15. the intermediate layer includes a protruding portion that protrudes into the diode region in the first direction. The RC-IGBT according to claim 1.

16. A direction perpendicular to the first direction in a plan view is defined as a second direction, the intermediate layer extends across the entire boundary region in the second direction. The RC-IGBT according to claim 1.

17. The insulating layer covers an end portion of the intermediate layer that is closer to the IGBT region. The RC-IGBT according to claim 1.

18. an end surface of the intermediate layer on the diode region side is inclined so as to extend toward the diode region as it approaches the first surface; The RC-IGBT according to claim 1.

19. The thickness of the intermediate layer is 2 μm or less. The RC-IGBT according to claim 1.

20. The width of the boundary region in the first direction is 5 μm or more and 10 μm or less. The RC-IGBT according to claim 1.

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