Oscillators and Converters

Abstract

Create a suitable dead time. [Solution] The oscillator comprises: a first transistor which is a P-type semiconductor and has its source connected to a power supply terminal, its drain connected to a first connection point connected to one end of an inductor, and its gate connected to a second connection point connected to the other end of the inductor; a second transistor which is a P-type semiconductor and has its source connected to the power supply terminal, its drain connected to the second connection point, and its gate connected to the first connection point; a third transistor which is an N-type semiconductor and has its source connected to a reference voltage terminal and its drain connected to a third connection point through which current flows from the first connection point; a fourth transistor which is an N-type semiconductor and has its source connected to the reference voltage terminal and its drain connected to a fourth connection point through which current flows from the second connection point; a high-pass filter; a first buffer circuit; and a second buffer circuit.

Description

[Technical Field]

[0001] The present invention relates to oscillators and converters. [Background technology]

[0002] Conventionally, CMOS oscillators (class D oscillators) have been known. FIG. 13 is a diagram for explaining an example of a conventional CMOS oscillator 91. The CMOS oscillator 91 shown in FIG. 13(A) has two CMOS inverters (four transistors in total), and an inductor is connected between the gates of each transistor. According to the above-described configuration, only one inductor is required to configure the CMOS oscillator 91. Furthermore, the CMOS oscillator 91 has a structure in which the potential (V X91 and V X92 ) only becomes as large as the power supply voltage, so it can be constructed using elements with low voltage resistance.

[0003] However, as shown in the timing chart of FIG. 13(B), the CMOS oscillator 91 has a pair of left and right CMOS transistors (P-type transistors M P91 and N-type transistor M N91 , P-type transistor M P92 and N-type transistor M N92 ) are turned on at the same time, causing a shoot-through current. If a large amount of shoot-through current flows, it may lead to deterioration or destruction of the transistor.

[0004] Non-Patent Document 1 shows a first example of a CMOS oscillator that prevents shoot-through current. FIG. 14 is a diagram for explaining an example of a conventional CMOS oscillator 92 according to Countermeasure Example 1. A shoot-through current can be prevented by creating a dead time, which is the period from when one transistor turns off until the other transistor turns on. The CMOS oscillator 92 shown in FIG. 14(A) can be configured to generate a potential V X91 and potential V X92 potential V N91 and potential V N92This delays the on timing of the N-type transistor and creates dead time.

[0005] Furthermore, Non-Patent Document 2 discloses an example of a CMOS oscillator that creates a dead time using a method different from that of Non-Patent Document 1. FIG. 15 is a diagram for explaining an example of a conventional CMOS oscillator 93 relating to Countermeasure Example 2. The CMOS oscillator 93 shown in FIG. 15(A) detects reverse conduction of an N-type transistor using a comparator, and then turns on the N-type transistor. As a result, the CMOS oscillator 93 creates a dead time as shown in FIG. 15(B). [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard,” ISSCC, pp. 240-242, Feb. 2022 [Non-patent document 2] A 6.78-MHz 79.5%-Peak-Efficiency Wireless Power Transfer System using a Wireless Mode-Recognition Technique and a Fully-On / off Class-D Power Amplifier,” ISSCC, pp. 446-447, Feb. 2024 Summary of the Invention [Problem to be solved by the invention]

[0007] However, the technology described in Non-Patent Document 1 is N91 and potential V N92By lowering the level of N91 and N-type transistor M N92 The overdrive voltage of the N-type transistor becomes smaller, which increases the on-resistance of the N-type transistor. Also, the technology described in Non-Patent Document 2 has the problem that the dead time ends before sufficient charge transfer has occurred in the parasitic capacitance of the transistor, resulting in switching loss due to hard charging.

[0008] Furthermore, the technology described in Non-Patent Document 2 has difficulty in operating properly for signals of several hundred MHz or more because delays of several nanoseconds occur in the comparator, driver, and control block. Also, the technology described in Non-Patent Document 2 has a problem in that the control block is complex, making it difficult to create the control block.

[0009] The present invention has been made in view of the above-mentioned points, and has an object to provide a technique for creating a dead time in an appropriate manner. [Means for solving the problem]

[0010] One aspect of the present invention is a transistor including a first transistor which is a P-type semiconductor and has a source connected to a power supply terminal, a drain connected to a first connection point connected to one end of an inductor, and a gate connected to a second connection point connected to the other end of the inductor; a second transistor which is a P-type semiconductor and has a source connected to the power supply terminal, a drain connected to the second connection point, and a gate connected to the first connection point; a third transistor which is an N-type semiconductor and has a source connected to a reference voltage terminal and a drain connected to a third connection point through which a current flows from the first connection point; and a fourth transistor which is an N-type semiconductor and has a source connected to the reference voltage terminal and a drain connected to a fourth connection point through which a current flows from the second connection point. a fourth transistor that is an N-type semiconductor and has its drain connected to the second connection point; a first capacitor having one end connected to the second connection point; a first resistor connected between a bias voltage terminal and the first capacitor; a first buffer circuit in which the connection point between the first capacitor and the first resistor is connected to an input terminal and the gate of the third transistor is connected to an output terminal; a second capacitor having one end connected to the first connection point; a second resistor connected between a bias voltage terminal and the second capacitor; and a second buffer circuit in which the connection point between the second capacitor and the second resistor is connected to the input terminal and the gate of the fourth transistor is connected to the output terminal.

[0011] In one aspect of the present invention, the oscillator further includes a fifth transistor which is an N-type semiconductor and has a source connected to the third connection point, a drain connected to the first connection point, and a gate connected to the second connection point, and a sixth transistor which is an N-type semiconductor and has a source connected to the fourth connection point, a drain connected to the second connection point, and a gate connected to the first connection point.

[0012] In one aspect of the present invention, the oscillation frequency of the oscillator is 100 MHz or higher.

[0013] Another aspect of the present invention is a converter comprising a first oscillator which is the oscillator described above, a second oscillator, a third capacitor having one end connected to the first connection point of the first oscillator and the other end connected to the first connection point of the second oscillator, and a fourth capacitor having one end connected to the second connection point of the first oscillator and the other end connected to the second connection point of the second oscillator, wherein the reference voltage terminal of the first oscillator is connected to the power supply terminal of the second oscillator and a power supply output terminal which outputs a voltage. [Effects of the Invention]

[0014] According to the present invention, the dead time can be suitably created. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a circuit diagram illustrating an example of a configuration of an oscillator according to an embodiment. [Figure 2] 10A and 10B are diagrams for explaining a dead time creation method according to an embodiment. [Figure 3] 10 is a diagram for explaining the relationship between the voltage rise time, the buffer delay time, and the oscillation period of the oscillator. FIG. [Figure 4] FIG. 2 is a first diagram for explaining an example of the operation of an oscillator. [Figure 5] FIG. 2 is a second diagram for explaining an example of the operation of the oscillator. [Figure 6] FIG. 10 is a third diagram for explaining an example of the operation of the oscillator. [Figure 7] FIG. 10 is a circuit diagram showing an example of the configuration of an oscillator according to a modified example. [Figure 8] FIG. 1 is a circuit diagram illustrating an example of a configuration of a converter according to an embodiment. [Figure 9] FIG. 2 is a first diagram for explaining an example of the operation of a converter. [Figure 10] FIG. 2 is a second diagram for explaining an example of the operation of the converter. [Figure 11] FIG. 10 is a third diagram for explaining an example of the operation of the converter. [Figure 12]15 is a diagram showing the results of a performance simulation of a converter using the CMOS oscillator shown in FIG. 14 and a converter using the oscillator according to the embodiment. [Figure 13] FIG. 1 is a diagram illustrating an example of a conventional CMOS oscillator. [Figure 14] 10A and 10B are diagrams for explaining an example of a conventional CMOS oscillator according to a countermeasure example. [Figure 15] 10A and 10B are diagrams for explaining an example of a conventional CMOS oscillator according to a countermeasure example. DETAILED DESCRIPTION OF THE INVENTION

[0016] The oscillator and converter according to the present embodiment will be described in detail below with reference to the accompanying drawings, showing preferred embodiments. In the drawings, identical or similar parts are designated by identical or similar reference numerals. Note that the present embodiment is not limited to these embodiments and includes various modifications and improvements. In other words, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical, and the components described below can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components of the present embodiment may be made without departing from the spirit of the present invention.

[0017] [Oscillator] 1 is a circuit diagram showing an example of the configuration of an oscillator 1 according to an embodiment. The oscillator 1 includes a first transistor M P1 and the second transistor M P2 and the third transistor M C1 and the fourth transistor M C2 and the fifth transistor M N1 and the sixth transistor M N2 The oscillator 1 may include an inductor L, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first buffer circuit BC1, and a second buffer circuit BC2. The circuit configuration of the oscillator 1 is symmetrical. Therefore, the first transistor M P1 , third transistor M C1 , fifth transistor MN1 , the first capacitor C1, the first resistor R1, and the first buffer circuit BC1 are connected to the second transistor M P2 , the fourth transistor M C2 , the sixth transistor M N2 , the second capacitor C2, the second resistor R2, and the second buffer circuit BC2 operate symmetrically.

[0018] The oscillator 1 may be, for example, built into a semiconductor device (IC), or may not be built into the semiconductor device. Also, some of the components of the oscillator 1 may be built into the semiconductor device, and some may not be built into the semiconductor device. For example, the inductor L may not be provided within the oscillator 1, but may exist separately from the oscillator 1 and be connected to the oscillator 1.

[0019] First transistor M P1 is a P-type semiconductor having a source connected to the power supply terminal SV, a drain connected to the first connection point CP1, and a gate connected to the second connection point CP2. The power supply terminal SV is connected to the power supply voltage V IN and supplies voltage to oscillator 1.

[0020] Second transistor M P2 is a P-type semiconductor having a source connected to the power supply terminal SV, a drain connected to the second connection point CP2, and a gate connected to the first connection point CP1.

[0021] The first connection point CP1 is connected to one end of the inductor L and the second transistor M P2 and the gate of the fourth transistor M C2 and the gate of the sixth transistor M N2 The potential of the first connection point CP1 is V X1 In addition, the fourth transistor M C2 is connected to the first connection point CP1 via a second capacitor C2 and a second buffer circuit BC2.

[0022] The second connection point CP2 is connected to the other end of the inductor L and the first transistor M P1 and the gate of the third transistor MC1 and the gate of the fifth transistor M N1 The potential of the second connection point CP2 is V X2 In addition, the third transistor M C1 is connected to the second connection point CP2 via the first capacitor C1 and the first buffer circuit BC1.

[0023] Third transistor M C1 The third transistor M is an N-type semiconductor having a source connected to the reference voltage terminal RV, a drain connected to the third connection point CP3, and a gate connected to the first buffer circuit BC1. C1 The gate potential of C1 is.

[0024] Fourth transistor M C2 The fourth transistor M is an N-type semiconductor having a source connected to the reference voltage terminal RV, a drain connected to the fourth connection point CP4, and a gate connected to the second buffer circuit BC2. C2 The gate potential of C2 is.

[0025] The reference voltage terminal RV is connected to the reference voltage of the oscillator 1. The reference voltage may be, for example, 0 [V], a small voltage close to 0 [V], or any voltage set by the designer of the oscillator 1.

[0026] A current flows from the first connection point CP1 to the third connection point CP3. In FIG. 1, the third connection point CP3 is connected to the third transistor M C1 and the drain of the fifth transistor M N1 and the source of the fifth transistor M N1 A current flows through the drain and source of the third node CP3. A current may also flow from the third node CP3 to the first node CP1.

[0027] A current flows from the second connection point CP2 to the fourth connection point CP4. In FIG. 1, the fourth connection point CP4 is connected to the fourth transistor M C2and the drain of the sixth transistor M N2 and the source of the sixth transistor M N2 A current flows through the drain and source of the fourth node CP4. A current may also flow from the fourth node CP4 to the second node CP2.

[0028] Fifth transistor M N1 is an N-type semiconductor having a source connected to the third connection point CP3, a drain connected to the first connection point CP1, and a gate connected to the second connection point CP2.

[0029] 6th transistor M N2 is an N-type semiconductor having a source connected to the fourth connection point CP4, a drain connected to the second connection point CP2, and a gate connected to the first connection point CP1.

[0030] The first capacitor C1 has one end connected to the second connection point CP2 and the other end connected to the first resistor R1 and the first buffer circuit BC1. Hereinafter, the connection point between the first capacitor C1, the first resistor R1, and the first buffer circuit BC1 may be referred to as a fifth connection point CP5. The potential of the fifth connection point CP5 is V M1 When the oscillation frequency of the oscillator 1 is 100 [MHz], the capacitance value of the first capacitor C1 may be, for example, about 5 [pF].

[0031] The first resistor R1 has one end connected to the fifth connection point CP5 and the other end connected to the first bias voltage terminal BV1. The first bias voltage terminal BV1 is connected to the bias voltage V bias Connected to the bias voltage V bias The value of may be set by the designer of the oscillator 1, or may be set by a feedback device (not shown). A reference voltage may be connected to the first bias voltage terminal BV1. When the oscillation frequency of the oscillator 1 is 100 [MHz], the resistance value of the first resistor R1 may be, for example, about several hundred [Ω].

[0032] The first buffer circuit BC1 has a buffer delay, and the third transistor M C1The first buffer circuit BC1 has an input terminal connected to the fifth connection point CP5 and an output terminal connected to the third transistor M C1 The first buffer circuit BC1 may be, for example, an inverter chain with an even number of stages. The first buffer circuit BC1, which is an inverter chain with an even number of stages, can transfer a digital signal with a sharp change to the gate of the third transistor M C1 When the oscillation frequency of the oscillator 1 is 100 [MHz], the buffer delay time may be, for example, about several hundred [psec].

[0033] The second capacitor C2 has one end connected to the first connection point CP1 and the other end connected to the second resistor R2 and the second buffer circuit BC2. Hereinafter, the connection point between the second capacitor C2, the second resistor R2, and the second buffer circuit BC2 may be referred to as a sixth connection point CP6. The potential of the sixth connection point CP6 is V M2 is.

[0034] The second resistor R2 has one end connected to the sixth connection point CP6 and the other end connected to the second bias voltage terminal BV2. The second bias voltage terminal BV2 is connected to the bias voltage V bias The bias voltage V of the first bias voltage terminal BV1 is connected to bias and the bias voltage V of the second bias voltage terminal BV2. bias may be the same value or may be different values.

[0035] The second buffer circuit BC2 is a circuit similar to the first buffer circuit BC1, and includes a fourth transistor M C2 The second buffer circuit BC2 has an input terminal connected to the sixth connection point CP6 and an output terminal connected to the fourth transistor M C2 is connected to the gate of

[0036] 2A and 2B are diagrams for explaining a dead time generating method according to an embodiment. FIG. 2A is a diagram for explaining the roles of the first capacitance C1, the first resistor R1, and the first buffer circuit BC1. FIG. 2B is a diagram showing a voltage waveform output by the first capacitance C1, the first resistor R1, and the first buffer circuit BC1. The first capacitance C1, the first resistor R1, and the first buffer circuit BC1 are connected to the first transistor M. P1 The voltage input to the gate of the third transistor M C1 This delays the rise of the voltage input to the gate and accelerates the fall of the voltage.

[0037] The first capacitor C1 and the first resistor R1 form a high-pass filter (HPF). The high-pass filter receives a square wave (input voltage V X2 ), the output voltage V M1 is the input voltage V X2 Approximately 100% of the output voltage is output, and for a flat voltage with small fluctuations (low frequency components), the output voltage V M1 The output voltage V M1 As a result, the voltage V input to the first buffer circuit BC1 M1 is the first transistor M P1 BC1 falls below the buffer threshold voltage of the first buffer circuit BC1 before the voltage input to the gate of the third transistor M C1 The voltage input to the gate of the first transistor M P1 The voltage falls faster than the voltage input to the gate of

[0038] High-pass filter output voltage V M1 The time required for the output voltage V to fall varies depending on the time constant (τ=RC) of the high-pass filter. M1 The smaller the time constant, the faster the fall, and the larger the time constant, the slower the fall. The designer of the oscillator 1 may determine the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 according to the designed oscillation frequency.

[0039] Also, the output voltage of the high-pass filter, V M1 The time required for the fall of the bias voltage V bias The time required for the fall varies depending on the magnitude of the bias voltage V bias The larger the bias voltage V bias The designer of oscillator 1 must determine the bias voltage V according to the oscillation frequency to be designed. bias The bias voltage V bias is a voltage input to the oscillator 1, and can be easily changed after the oscillator 1 is designed. Therefore, in the oscillator 1 according to the first embodiment, the dead time determined by the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 is adjusted by the bias voltage V bias This can be adjusted by changing

[0040] The first buffer circuit BC1 is connected to the high-pass filter output voltage V M1 The delayed voltage V C1 the third transistor M C1 The voltage V C By delaying the third transistor M C1 The voltage V input to the gate of C1 is the first transistor M P1 The voltage V input to the gate of X Stand up slower than usual.

[0041] Figure 3 shows the voltage V C1 1 is a diagram illustrating the relationship between the rise time of the voltage V, the buffer delay time, and the oscillation period T of the oscillator 1. C1 The rise time of the voltage V can be determined by subtracting the dead time from half the oscillation period T of the oscillator 1. M1 The time it takes for the voltage V to rise above the buffer threshold voltage and fall below it can be set to be approximately the same as the time constant CR. M1 Since the buffer delay occurs both when V exceeds and when V falls below the buffer threshold voltage, C1The rise time of is about the same as the time constant RC. Also, the dead time created is about the same as the buffer delay time. Therefore, the voltage V C1 The rise time of can be determined by the formula set forth below.

[0042]

number

[0043] When the first resistor R1 and the first capacitor C1 are built into a semiconductor device, the area occupied by each element tends to be larger for the first capacitor C1, so it is desirable to make the capacitance value of the first capacitor C1 small and the resistance value of the first resistor R1 large.

[0044] The capacitance value of the first capacitor C1 is the same as that of the third transistor M C1 If the capacitance is small compared to the input capacitance of X2 ) is the first capacitor C1 and the third transistor M C1 The voltage is divided by the input capacitance of M1 is the input voltage V X1 Therefore, the capacitance value of the first capacitor C1 may not rise to the same extent as that of the third transistor M C1 It is desirable that the capacitance value of the first capacitor C1 is larger than the input capacitance of the third transistor M. C1 It is more desirable that the input capacitance be 10 times or more.

[0045] If the resistance value of the first resistor R1 is too large, the bias voltage V bias Therefore, the first resistor R1 is used to bias It is desirable to set the resistance value according to the speed at which the change is desired.

[0046] Third transistor M C1 On the other hand, if the dead time is too short, the voltage V X1 voltage VC1 Therefore, it is desirable that the dead time be about 30% of the half-cycle time of the oscillation period T. After designing the oscillator 1, the bias voltage V bias When adjusting the dead time, it is desirable that the dead time be about 10% of the half cycle of the oscillation cycle T.

[0047] In the above, a method for creating a dead time has been explained using the first capacitance C1, the first resistance R1, and the first buffer circuit BC1 as an example, but a dead time can also be created in a similar manner for the second capacitance C2, the second resistance R2, and the second buffer circuit BC2.

[0048] Next, the operation of the oscillator 1 will be specifically described with reference to FIGS.

[0049] 4 is a first diagram for explaining an example of the operation of the oscillator 1. FIG. 4(A) shows a state in which no current flows through each transistor. FIG. 4(B) shows a state in which the third transistor M C1 The gate potential V C1 and the fourth transistor M C2 The gate potential V C2 , the potential V of the first connection point CP1 X1 and the potential V of the second connection point CP2 X2 The time variations of the current I flowing through the inductor L and the time period A during which the dead time is created are shown. C1 and potential V C2 Since the third transistor M C1 and the fourth transistor M C2 Therefore, the first transistor M P1 , second transistor M P2 , fifth transistor M N1 , and the sixth transistor M N2 Regardless of whether the switch is on or off, no through current occurs.

[0050] 5 is a second diagram for explaining an example of the operation of the oscillator 1. In FIG. 5(A), the first transistor M P1 and the fourth transistor M C2 and the sixth transistor M N2 5B shows the state immediately after the first transistor M is turned on. FIG. 5B shows the period B during which the inductor L is discharged. P1 and the fourth transistor M C2 and the sixth transistor M N2 Immediately after the switch is turned on, the inertia of the inductor L causes a current I to flow in the direction from the second connection point CP2 to the first connection point CP1.

[0051] 6 is a third diagram for explaining an example of the operation of the oscillator 1. In FIG. 6(A), the fourth transistor M C2 6B shows the state until the conduction of inductor L ends. Figure 6B shows time period C during which inductor L charges. After the inertia of inductor L disappears, current I flows through inductor L in the direction from first connection point CP1 to second connection point CP2.

[0052] After the operation shown in FIG. 6, the oscillator 1 operates symmetrically to the operations shown in FIGS. 4 to 6, and performs operations during time periods A, B, and C. Specifically, after the operation shown in FIG. 6, a dead time (time period A) is inserted, and then the second transistor M P2 and the third transistor M C1 and the fifth transistor M N1 and are turned on (time period B and time period C). The oscillator 1 repeats the above-described symmetrical operations to oscillate.

[0053] FIG. 7 is a circuit diagram showing an example of the configuration of an oscillator 1A according to a modified example. In FIG. 1, the fifth transistor M N1 and the source of the third transistor M C1 The drains of the third transistor M C1 and the fifth transistor M N1 If both transistors M are not on, no current will flow. N1is the third transistor M C1 turns on earlier than the third transistor M C1 Therefore, the third transistor M C1 and the fifth transistor M N1 During the period when current flows through the third transistor M C1 Therefore, as shown in FIG. 7, the oscillator 1A has a fifth transistor M N1 and the sixth transistor M N2 It is not necessarily required to have the above.

[0054] The oscillator 1 includes a fifth transistor M N1 and the sixth transistor M N2 By providing this, oscillation can be easily initiated (start-up). An example of a specific startup method will be explained. At startup, the power supply voltage V IN and a bias voltage V bias and the third transistor M C1 and the fourth transistor M C2 The third transistor M C1 and the fourth transistor M C2 are simultaneously turned on, the potentials of the third and fourth connection points CP3 and CP4 become equal to the reference voltage. As a result, the oscillator 1 has the same configuration as the CMOS oscillator 91 shown in FIG. 13 and starts oscillating. After the oscillator 1 starts oscillating, the bias voltage V bias By gradually decreasing the voltage, the oscillator 1 can prevent a shoot-through current from occurring by creating a dead time while continuing to oscillate. Note that the oscillator 1A may start oscillation by performing cold start control or the like.

[0055] The oscillator 1 also includes a fifth transistor M N1 and the sixth transistor M N2 By providing the third transistor M C1 and the fourth transistor M C2 This reduces the voltage applied to the third transistor MC1 and the fourth transistor M C2 Therefore, a transistor with a low breakdown voltage can be used, and the on-resistance can be reduced.

[0056] [Oscillator Summary] According to the above-described embodiment, the oscillator 1 includes a first transistor M, which is a P-type semiconductor, having a source connected to a power supply terminal SV, a drain connected to a first connection point CP1 connected to one end of the inductor L, and a gate connected to a second connection point CP2 connected to the other end of the inductor L. P1 a second transistor MP2 which is a P-type semiconductor and has its source connected to the power supply terminal SV, its drain connected to the second connection point CP2, and its gate connected to the first connection point CP1; and a third transistor M which is an N-type semiconductor and has its source connected to the reference voltage terminal RV and its drain connected to the third connection point CP3 through which current flows from the first connection point CP1. C1 The source is connected to the reference voltage terminal RV, and the second connection point C P2 Current flows from the fourth connection point C P4 The fourth transistor M is an N-type semiconductor whose drain is connected to C2 a first capacitor C1 having one end connected to the second connection point CP2; a first resistor R1 connected between the first bias voltage terminal BV1 and the first capacitor C1; a first buffer circuit BC1 having a connection point (fifth connection point CP5) between the first capacitor C1 and the first resistor R1 connected to the input terminal and a gate of a third transistor MC1 connected to the output terminal; a second capacitor C2 having one end connected to the first connection point CP1; a second resistor R2 connected between the second bias voltage terminal BV2 and the second capacitor C2; a connection point (sixth connection point CP6) between the second capacitor C2 and the second resistor R2 connected to the input terminal; C2 The gate of the second buffer circuit B is connected to the output terminal. C2 The oscillator 1 according to the embodiment includes a first transistor M P1 and the second transistor M P2 On the other hand, the third transistor M C1 and the fourth transistor M C2By delaying the on-timing and advancing the off-timing, the generation of shoot-through current can be prevented. As a result, oscillator 1 can prevent the transistors from being destroyed or deteriorated, and extend the life of the transistors.

[0057] 14, the oscillator 1 can arbitrarily adjust the timing and length of the dead time, and therefore can avoid switching loss by performing ZVS (Zero Volt Switching). bias This makes it possible to prevent the overdrive voltage of the N-type transistor from becoming small, and consequently the on-resistance from becoming large.

[0058] 15, the oscillator 1 can create a dead time with a simple configuration without using a comparator, control block, etc. Furthermore, because the oscillator 1 does not use a comparator, control block, etc., the delay time is short and it can oscillate at a high frequency of 100 MHz or more.

[0059] Furthermore, according to the above-described embodiment, the oscillator 1 includes a fifth transistor M, which is an N-type semiconductor, having a source connected to the third connection point CP3, a drain connected to the first connection point CP1, and a gate connected to the second connection point CP2. N1 a sixth transistor M1, which is an N-type semiconductor, having a source connected to the fourth connection point CP4, a drain connected to the second connection point CP2, and a gate connected to the first connection point CP1; N2 The oscillator 1 further comprises a fifth transistor M N1 and the sixth transistor M N2 By providing the fifth transistor M, oscillation can be easily started. N1 and the sixth transistor M N2 By performing voltage division using the third transistor M C1 and the fourth transistor M C2This allows the use of transistors with low breakdown voltage, thereby reducing the on-resistance.

[0060] [Example of application to a converter] The oscillator 1 according to the embodiment can be used in a wide range of fields, such as an insulating converter, a device on the power receiving side of a contactless power supply system, etc. A converter 10, which is one application example of the oscillator 1, will be described with reference to Figs.

[0061] FIG. 8 is a circuit diagram showing an example of the configuration of a converter 10 according to an embodiment. FIG. 8(A) shows an example of the structure of the converter 10. FIG. 8(B) shows an example of the circuit configuration of the converter 10. The converter 10 includes two oscillators 1 or 1A (a first oscillator 11 and a second oscillator 12), a first flying capacitor C FRY1 and the second flying capacitor C FRY2 8 to 12 are the same as the symbols used in FIG. 1 with an H added. Also, the symbols used in FIG. 8 to 12 are the same as the symbols used in FIG. 1 with an L added. In the following explanation, explanations of components corresponding to the components already explained with reference to FIG. 1 may be omitted. Note that the first oscillator 11 and the second oscillator 12 may both be oscillator 1, or both may be oscillator 1A, or one may be oscillator 1 and the other may be oscillator 1A.

[0062] The first oscillator 11 is connected to the first connection point CP H1 is the first flying capacitor C FRY1 and the second connection point CP H2 is the second flying capacitor C FRY2 The second oscillator 12 is connected to the first connection point CP L1 is the first flying capacitor C FRY1 and the second connection point CP L2 is the second flying capacitor C FRY2 The reference voltage terminal RV of the first oscillator 11 is connected to Hand the power supply terminal SV of the second oscillator 12 L and power output terminal V OUT are connected to each other. Power supply output terminal V OUT is the power terminal SV H It outputs a part (half) of the power supplied from the first flying capacitor C FRY1 One end is the first connection point CP H1 and the other end is connected to the first connection point CP L1 The second flying capacitor C FRY2 One end is connected to the second connection point CP H2 and the other end is connected to the second connection point CP L2 The converter 10 is connected to the power supply terminal SV H to 2V IN The power supply voltage [V] is supplied and the power supply output terminal V OUT V, which has been halved from IN The converter 10 outputs a power supply voltage of [V]. In other words, the converter 10 is an SC converter that reduces the voltage to half. Note that the first flying capacitor C FRY1 is called the third capacitance, and the second flying capacitor C FRY2 may be referred to as the fourth capacitance.

[0063] 9A and 9B are diagrams illustrating an example of the operation of the converter 10. FIG. 9A shows a state in which no current flows through the transistors of the first oscillator 11 and the second oscillator 12. In FIG. 9A, the first flying capacitor C FRY1 discharges, and the second flying capacitor C FRY2 In FIG. 9B, the third transistor M CH1 The gate potential V CH1 and the fourth transistor M CH2 The gate potential V CH2 , first connection point CP H1 potential V XH1 and the second connection point CP H2 potential V XH2 , third transistor M CL1 The gate potential V CL1 and the fourth transistor M CL2 The gate potential V CL2, first connection point CP L1 potential V XL1 and the second connection point CP L2 potential V XL2 , inductor L H The current I H and inductor L L The current I L The time variations of each voltage and the time period A during which the dead time is created are shown. CH1 , potential V CH2 , potential V CL1 , and potential V CL2 Since the third transistor M CH1 , the fourth transistor M CH2 , third transistor M CL1 , and the fourth transistor M CL2 Therefore, no through current occurs.

[0064] 10 is a second diagram illustrating an example of the operation of the converter 10. In FIG. 10(A), the first transistor M PH1 , the fourth transistor M CH2 , the sixth transistor M NH2 , first transistor M PL1 , the fourth transistor M CL2 , and the sixth transistor M NL2 The state immediately after the inductor L is turned on is shown in FIG. H and inductor L L The first transistor M PH1 , the fourth transistor M CH2 , the sixth transistor M NH2 , first transistor M PL1 , the fourth transistor M CL2 , and the sixth transistor M NL2 Immediately after the inductor L H The second connection point CP H2 to the first connection point CP H1 Current I in the direction H Also, the inductor L L The second connection point CP L2to the first connection point CP L1 Current I in the direction L is playing.

[0065] 11 is a third diagram for explaining an example of the operation of the converter 10. In FIG. 11(A), the fourth transistor M CH2 and the fourth transistor M CL2 The state until the conduction of inductor L is completed is shown in FIG. 11(B). The period C during which inductor L is discharged is shown in FIG. H and inductor L L After the inertia of the inductor L H The first connection point CP H1 to the second connection point CP H2 Current I in the direction H Also, the inductor L L The first connection point CP L1 to the second connection point CP L2 Current I in the direction L After the operation shown in FIG. 11, the oscillator 1 operates in a manner symmetrical to that shown in FIG. 9 through FIG. 11. Specifically, the first flying capacitor C FRY1 charges the second flying capacitor CFRY2 discharges.

[0066] FIG. 12 shows the results of a performance simulation of a converter using the CMOS oscillator 92 (chip 1) shown in FIG. 14 and a converter 10 using the oscillator 1 (chip 2) according to the embodiment. FIG. 12(A) shows the results of a simulation of the relationship between current and power efficiency. The efficiency is calculated by the power supply output terminal V OUT Voltage output from power supply output terminal V OUT The current I output from out ) / (power terminal SV H Voltage supplied from (2VIN) × power supply terminal SV HThe on-resistance of oscillator 1 is smaller than that of CMOS oscillator 92, so converter 10 can reduce losses and improve the efficiency curve compared to converters using CMOS oscillator 92. Furthermore, because a sufficient overdrive voltage is applied to the N-type transistor of oscillator 1, converter 10 has a smaller on-resistance than converters using CMOS oscillator 92, and can improve power efficiency and maximum current density under heavy loads.

[0067] 12(B) shows the results of a simulation of the relationship between current and oscillation frequency. Compared to a converter using a CMOS oscillator 92, converter 10 has a smaller on-resistance, making it easier to oscillate and enabling it to stabilize the oscillation frequency.

[0068] Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to the above, and various design modifications can be made without departing from the spirit of the present invention. Furthermore, the configurations described in the above-described embodiments and examples can be combined. [Explanation of symbols]

[0069] 1...Oscillator, 10...Converter, M P1 …first transistor, M P2 …second transistor, M C1 ...third transistor, M C2 …fourth transistor, M N1 …fifth transistor, M N2 ...sixth transistor, C1...first capacitor, R1...first resistor, BC1...first buffer circuit, C2...second capacitor, R2...second resistor, BC2...second buffer circuit, SV...power supply terminal, RV...reference voltage terminal, BV1...first bias voltage terminal, BV2...second bias voltage terminal

Claims

1. a first transistor which is a P-type semiconductor, the first transistor having a source connected to a power supply terminal, a drain connected to a first connection point connected to one end of the inductor, and a gate connected to a second connection point connected to the other end of the inductor; a second transistor that is a P-type semiconductor and has a source connected to the power supply terminal, a drain connected to the second connection point, and a gate connected to the first connection point; a third transistor which is an N-type semiconductor and has a source connected to a reference voltage terminal and a drain connected to a third connection point through which a current flows from the first connection point; a fourth transistor which is an N-type semiconductor and has a source connected to the reference voltage terminal and a drain connected to a fourth connection point through which a current flows from the second connection point; a first capacitor having one end connected to the second connection point; a first resistor connected between a bias voltage terminal and the first capacitor; and a first buffer circuit having a connection point between the first capacitor and the first resistor connected to an input terminal and a gate of the third transistor connected to an output terminal; a second capacitor having one end connected to the first connection point; a second resistor connected between a bias voltage terminal and the second capacitor; and a second buffer circuit having a connection point between the second capacitor and the second resistor connected to an input terminal and a gate of the fourth transistor connected to an output terminal; An oscillator comprising:

2. a fifth transistor which is an N-type semiconductor and has a source connected to the third connection point, a drain connected to the first connection point, and a gate connected to the second connection point; a sixth transistor which is an N-type semiconductor and has a source connected to the fourth connection point, a drain connected to the second connection point, and a gate connected to the first connection point; The oscillator of claim 1 further comprising:

3. The oscillation frequency is 100 MHz or more.

3. The oscillator according to claim 1 or 2.

4. a first oscillator that is the oscillator according to claim 1 or 2; a second oscillator that is the oscillator according to claim 1 or 2; a third capacitor having one end connected to the first connection point of the first oscillator and the other end connected to the first connection point of the second oscillator; a fourth capacitor having one end connected to the second connection point of the first oscillator and the other end connected to the second connection point of the second oscillator; Equipped with the reference voltage terminal of the first oscillator is connected to the power supply terminal of the second oscillator and to a power supply output terminal that outputs a voltage; converter.

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