Semiconductor integrated circuit and memory system

Abstract

A semiconductor integrated circuit capable of appropriately adjusting the duty ratio of a clock signal is provided. [Solution] A semiconductor integrated circuit according to an embodiment includes a first pulse generation circuit that generates a first pulse signal and a second pulse signal that is an inverted signal of the first pulse signal; a second pulse generation circuit that generates a third pulse signal and a fourth pulse signal that is an inverted signal of the third pulse signal; a first inverting buffer that outputs the third signal based on inputs of the first and third pulse signals; and a second inverting buffer that outputs the fourth signal based on inputs of the second and fourth pulse signals, wherein the first inverting buffer lowers the logic level of the third signal when the logic level of the first pulse signal increases, and raises the logic level of the third signal when the logic level of the third pulse signal increases; and the second inverting buffer raises the logic level of the fourth signal when the logic level of the second pulse signal increases, and lowers the logic level of the fourth signal when the logic level of the fourth pulse signal increases.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor integrated circuit and a memory system. [Background technology]

[0002] In memory systems that perform high-speed communication using toggle DDR (Double Data Rate) or the like, a DCC (Duty Cycle Correction) circuit is used to correct deviations in the duty ratio of a clock signal. The DCC circuit includes a DCD (Duty Cycle Detector) circuit that detects the magnitude of deviation in the duty ratio, and a DCA (Duty Cycle Adjuster) circuit that adjusts the duty ratio based on the magnitude of the detected deviation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2017 / 0077915 [Patent Document 2] U.S. Patent No. 6,084,452 [Patent Document 3] US Patent Application Publication No. 2023 / 0216489 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor integrated circuit capable of appropriately adjusting the duty ratio of a clock signal is provided. [Means for solving the problem]

[0005] A semiconductor integrated circuit according to an embodiment includes a first pulse generating circuit that generates a first pulse signal and a second pulse signal that is an inverted signal of the first pulse signal based on a first signal, a second pulse generating circuit that generates a third pulse signal and a fourth pulse signal that is an inverted signal of the third pulse signal based on the second signal, a first inverting buffer that outputs a third signal from a first node based on inputs of the first pulse signal and the third pulse signal, and a second inverting buffer that outputs a fourth signal from a second node based on inputs of the second pulse signal and the fourth pulse signal, wherein the first inverting buffer outputs a fourth signal from a second node based on inputs of the second pulse signal and the fourth pulse signal, and the second inverting buffer changes the logic level of the third signal from the second logic level to the first logic level when the logic level of the third pulse signal changes from the second logic level to the first logic level, and changes the logic level of the third signal from the first logic level to the second logic level when the logic level of the second pulse signal changes from the second logic level to the first logic level; the second inverting buffer changes the logic level of the fourth signal from the first logic level to the second logic level when the logic level of the second pulse signal changes from the second logic level to the first logic level, and changes the logic level of the fourth signal from the second logic level to the first logic level when the logic level of the fourth pulse signal changes from the first logic level to the second logic level. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a DCC circuit according to the first embodiment. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a DCA circuit according to the first embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the DCA circuit according to the first embodiment. [Figure 5] FIG. 5 is a timing chart showing an example of the operation of the DCA circuit according to the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of a circuit configuration of a clock adjusting circuit according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the clock adjusting circuit according to the first embodiment. [Figure 8] FIG. 8 is a circuit diagram showing an example of a circuit configuration of a clock adjusting circuit according to a second embodiment. [Figure 9] FIG. 9 is a truth table of a pulse control circuit included in the clock adjustment circuit according to the second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of the circuit configuration of a pulse control circuit included in a clock adjusting circuit according to a second embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a clock adjusting circuit according to a third embodiment. [Figure 12] FIG. 12 is a timing chart showing an example of the operation of the clock adjusting circuit according to the third embodiment. [Figure 13] FIG. 13 is a block diagram showing an example of the configuration of a DCA circuit according to a fourth embodiment. [Figure 14] FIG. 14 is a circuit diagram showing an example of a circuit configuration of a clock adjusting circuit according to a fourth embodiment. [Figure 15] FIG. 15 is a timing chart showing an example of the operation of the clock adjusting circuit according to the fourth embodiment. [Figure 16] FIG. 16 is a timing chart showing an example of the operation of the clock adjusting circuit according to the fourth embodiment. [Figure 17] FIG. 17 is a circuit diagram showing an example of a circuit configuration of a clock adjusting circuit according to a first modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic, and the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element via an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] In the following explanation, a square wave signal is a signal that alternately supplies voltages corresponding to logic levels "0" and "1" at a fixed interval. The voltage corresponding to logic level "1" is higher than the voltage corresponding to logic level "0." The change in the logic level of a square wave signal from "0" to "1" is called a rise, and the change from "1" to "0" is called a fall. The time from a square wave signal's first rise to its next fall is called the signal's positive pulse width. The time from a square wave signal's first fall to its next rise is called the signal's negative pulse width. A square wave signal in which the positive and negative pulse widths are set to approximately the same length (a duty cycle of approximately 50%) is specifically called a clock signal. A square wave signal in which there is a large imbalance between the length of the positive pulse width and the length of the negative pulse width (a duty cycle that deviates significantly from 50%) is specifically called a pulse signal. Among pulse signals, a pulse signal whose positive pulse width is sufficiently shorter than its negative pulse width is particularly referred to as a positive pulse signal.A pulse signal whose negative pulse width is sufficiently shorter than its positive pulse width is particularly referred to as a negative pulse signal.

[0010] 1. First embodiment 1.1 Memory system configuration A memory system according to the first embodiment will be described. FIG. 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. The memory system 100 is a storage device configured to be connected to an external host device (not shown). The memory system 100 is, for example, a storage device such as an SD TM The memory system 100 may be a memory card, a Universal Flash Storage (UFS), or a Solid State Drive (SSD). The memory system 100 includes a memory controller 200 and a memory device 300.

[0011] The memory controller 200 is configured as an integrated circuit such as an SoC (System on a Chip). The memory controller 200 controls the memory device 300 based on a request from an external host device. Specifically, the memory controller 200 writes data requested to be written by the external host device to a nonvolatile memory included in the memory device 300. The memory controller 200 also reads data requested to be read by the external host device from the nonvolatile memory included in the memory device 300 and outputs the data to the external host device. Signals transmitted and received between the memory controller 200 and the memory device 300 include, for example, a chip enable signal BCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal BWE, read enable signals RE and BRE, input / output signals DQ<7:0>, a ready / busy signal RY / BY, and data strobe signals DQS and BDQS. The prefix "B" indicates the inverted logic of the signal without the prefix "B." The read enable signal BRE is an inverted signal of the read enable signal RE, and the two form a differential clock signal pair. The data strobe signal BDQS is an inverted signal of the data strobe signal DQS, and the two form a differential clock signal pair.

[0012] The chip enable signal BCE enables the memory device 300. The command latch enable signal CLE notifies the memory device 300 to send a command via the input / output signals DQ<7:0>. The address latch enable signal ALE notifies the memory device 300 to send address information via the input / output signals DQ<7:0>. The write enable signal BWE instructs the memory device 300 to write the input / output signals DQ. The read enable signals RE and BRE instruct the memory device 300 to output the input / output signals DQ. The ready / busy signal RY / BY indicates whether the memory device 300 sending the signal is ready (a state in which it can accept commands from the outside) or busy (a state in which it cannot accept commands from the outside). The input / output signals DQ<7:0> are 8 bits wide and include, for example, a command, write data or read data, address information, and status. The data strobe signals DQS and BDQS notify the memory controller 200 and the memory device 300 of the input / output timing of the input / output signals DQ<7:0>.

[0013] The memory device 300 includes an interface chip 310 and a plurality of memory chips 320. The plurality of memory chips 320 are connected to the interface chip 310 in parallel.

[0014] The interface chip 310 interfaces the chip enable signal BCE, command latch enable signal CLE, address latch enable signal ALE, write enable signal BWE, read enable signals RE and BRE, ready / busy signal RY / BY, input / output signals DQ<7:0>, and data strobe signals DQS and BDQS between the memory controller 200 and the multiple memory chips 320. For example, the interface chip 310 is configured to transmit the chip enable signal BCE to a memory chip that is to be operated among the multiple memory chips 320, thereby enabling the memory chip, and thereby transmit various signals only to the memory chip 320 that is to be operated.

[0015] The interface chip 310 has a function of transferring signals input from the memory controller 200 to the target memory chip 320 using, for example, a toggle DDR (Double Data Rate) method. By using the toggle DDR method, the signal input / output speed in each memory chip 320 is improved, enabling high-speed signal communication.

[0016] Each of the memory chips 320 is, for example, a NAND flash memory. Each memory chip 320 includes a memory cell array having a plurality of memory cells. Each memory chip 320 stores data in a nonvolatile manner.

[0017] The interface chip 310 and each memory chip 320 each include a DCC (Duty Cycle Correction) circuit 400. The DCC circuit 400 has the function of adjusting the duty ratio of an input clock signal to approximately 50% and outputting the clock signal. Specifically, the interface chip 310 includes DCC circuits 400a and 400b. Each memory chip 320 includes a DCC circuit 400c. The DCC circuit 400a corrects deviations in the duty ratio of the read enable signals RE and BRE output from the memory controller 200 and input to the memory chip 320. The DCC circuit 400b corrects deviations in the duty ratio of the data strobe signals DQS and BDQS output from the memory controller 200 and input to the memory chip 320, and the data strobe signals DQS and BDQS output from the memory chip 320 and input to the memory controller 200. The DCC circuit 400c corrects the deviation in the duty ratio of the read enable signals RE and BRE output from the interface chip 310 and converts them into data strobe signals DQS and BDQS. The DCC circuits 400a, 400b, and 400c have approximately the same configuration.

[0018] 1.2 DCC circuit configuration A DCC circuit according to a first embodiment will now be described. FIG. 2 is a block diagram showing an example of the configuration of the DCC circuit according to the first embodiment. The DCC circuit 400 receives, for example, differential clock signals CLKT and CLKB, corrects the deviation in the duty ratio of the clock signals CLKT and CLKB, and outputs the corrected differential clock signals C_CLKT and C_CLKB. In the memory system 100, the clock signals CLKT and CLKB and the corrected clock signals C_CLKT and C_CLKB correspond to the read enable signals RE and BRE, or the data strobe signals DQS and BDQS. In the following description, an index indicating how much the duty ratio of a clock signal deviates from 50% will be referred to as the "duty error."

[0019] 2, the DCC circuit 400 includes a DCA (Duty Cycle Adjuster) circuit 1, an input / output (IO: Input and Output) buffer 2, a DCD (Duty Cycle Detector) circuit 3, and a DCC logic circuit 4. The DCC circuit 400 detects a duty cycle error of the clock signals CLKT_IO and CLKB_IO output from the DCA circuit 1 using the DCD circuit 3, and performs feedback control in which the DCA circuit 1 makes a correction based on the detected duty cycle error, thereby correcting the duty cycle error.

[0020] The DCA circuit 1 receives the input differential clock signals CLKT and CLKB, as well as a control signal DCA_CODE, which will be described later. Based on the control signal DCA_CODE, the DCA circuit 1 performs correction so that the duty ratio of the differential correction clock signals C_CLKT and C_CLKB becomes approximately 50%. The DCA circuit 1 outputs the differential clock signals CLKT_IO and CLKB_IO whose duty ratios have been corrected.

[0021] The input / output buffer 2 receives the clock signals CLKT_IO and CLKB_IO output from the DCA circuit 1, controls amplification and the like, and outputs the corrected clock signals C_CLKT and C_CLKB.

[0022] The DCD circuit 3 measures the positive pulse widths of the clock signals CLKT_IO and CLKB_IO output from the DCA circuit 1 and detects a duty cycle error of the clock signals. The DCD circuit 3 outputs a signal DCD_CODE indicating the positive pulse widths of the clock signals CLKT_IO and CLKB_IO. The signal DCD_CODE has a plurality of bits (for example, 32 bits).

[0023] The DCC logic circuit 4 determines the delay setting value of the clock signal based on the signal DCD_CODE output from the DCD circuit 3. Specifically, the DCC logic circuit 4 compares the positive pulse width of the clock signal CLKT_IO with the positive pulse width of the clock signal CLKB_IO, and outputs a control signal DCA_CODE for correcting the duty error based on the comparison result.

[0024] 1.3 DCA circuit 1.3.1 Configuration Next, the DCA circuit according to the first embodiment will be described. Fig. 3 is a block diagram showing an example of the configuration of the DCA circuit according to the first embodiment. As shown in Fig. 3, the DCA circuit 1 includes two delay adjustment circuits 6a and 6b and a clock adjustment circuit 7.

[0025] The delay adjustment circuit 6a receives the clock signal CLKT and the control signal DCA_CODE as inputs, delays the clock signal CLKT based on the control signal DCA_CODE, and outputs the clock signal CLKIN_T. The delay adjustment circuit 6b receives the clock signal CLKB and the control signal DCA_CODE as inputs, delays the clock signal CLKB based on the control signal DCA_CODE, and outputs the clock signal CLKIN_B. The two delay adjustment circuits 6a and 6b have approximately the same configuration.

[0026] The clock adjustment circuit 7 receives the delayed clock signals CLKIN_T and CLKIN_B as input. The clock adjustment circuit 7 generates and outputs differential clock signals CLKOUT and CLKOUTB with the duty ratio corrected based on the phase difference between the clock signals CLKIN_T and CLKIN_B. The clock signals CLKOUT and CLKOUTB become the clock signals CLKT_IO and CLKB_IO, which are output from the DCA circuit 1, as is.

[0027] 1.3.2 Operation 4 and 5 are timing charts showing an example of the operation of the DCA circuit according to the first embodiment. Fig. 4 shows an example of the operation performed by the DCA circuit 1 when the positive pulse width of the input clock signal CLKT is longer than the positive pulse width of the clock signal CLKB. Fig. 5 shows an example of the operation performed by the DCA circuit 1 when the positive pulse width of the input clock signal CLKT is shorter than the positive pulse width of the clock signal CLKB.

[0028] As shown in FIG. 4, when the positive pulse width of the clock signal CLKT is long, the DCA circuit 1 drives the delay adjustment circuit 6a to delay the clock signal CLKT and generate the clock signal CLKIN_T. Meanwhile, the clock signal CLKB is output as is as the clock signal CLKIN_B. The clock adjustment circuit 7 causes the clock signal CLKOUT (i.e., the clock signal CLKT_IO) to rise and the clock signal CLKOUTB (i.e., the clock signal CLKB_IO) to fall in response to the rise of the input clock signal CLKIN_T. The clock adjustment circuit 7 causes the clock signal CLKOUT to fall and the clock signal CLKOUTB to rise in response to the rise of the input clock signal CLKIN_B. Therefore, the timing of the rise of the clock signal CLKOUT is delayed relative to the rise of the clock signal CLKT, while the timing of the fall of the clock signal CLKOUT remains unchanged, so the positive pulse width of the clock signal CLKOUT can be adjusted to be shorter. Similarly, the fall timing of the clock signal CLKOUTB is delayed relative to the fall timing of the clock signal CLKB, while the rise timing of the clock signal CLKOUTB remains unchanged, so the positive pulse width of the clock signal CLKOUTB can be adjusted to be longer. In this way, the DCA circuit 1 adjusts the duty ratio to approximately 50% and generates the differential clock signals CLKT_IO and CLKB_IO.

[0029] As shown in FIG. 5, when the positive pulse width of the clock signal CLKT is short, the DCA circuit 1 drives the delay adjustment circuit 6b to delay the clock signal CLKB and generate the clock signal CLKIN_B. Meanwhile, the clock signal CLKT is output as is as the clock signal CLKIN_T. The clock adjustment circuit 7 causes the clock signal CLKOUT to rise and the clock signal CLKOUTB to fall in accordance with the rise of the input clock signal CLKIN_T. The clock adjustment circuit 7 causes the clock signal CLKOUT to fall and the clock signal CLKOUTB to rise in accordance with the rise of the input clock signal CLKIN_B. Therefore, the fall timing of the clock signal CLKOUT is delayed from the fall timing of the original clock signal CLKT, while the rise timing of the clock signal CLKOUT remains unchanged, so the positive pulse width of the clock signal CLKOUT can be adjusted to be longer. Similarly, the rise timing of the clock signal CLKOUTB is delayed from the rise timing of the original clock signal CLKB, while the fall timing of the clock signal CLKOUTB remains unchanged, so the positive pulse width of the clock signal CLKOUTB can be adjusted to be shorter. In this way, the DCA circuit 1 adjusts the duty ratio to approximately 50% and generates the differential clock signals CLKT_IO and CLKB_IO.

[0030] In the above example and the example described below, the clock adjustment circuit 7 changes the logic levels of the output clock signals CLKOUT and CLKOUTB in accordance with the rise of the input clock signals CLKIN_T and CLKIN_B, but this is not limiting. For example, the clock adjustment circuit 7 may change the logic levels of the output clock signals CLKOUT and CLKOUTB in accordance with the fall of the input clock signals CLKIN_T and CLKIN_B. In this case, when the positive pulse width of the clock signal CLKT is long, the clock signal CLKB is delayed, and when the positive pulse width of the clock signal CLKT is short, the clock signal CLKT is delayed.

[0031] 1.4 Clock Adjustment Circuit 1.4.1 Configuration 6 is a circuit diagram showing an example of the circuit configuration of the clock adjustment circuit according to the first embodiment. As shown in FIG. 6, the clock adjustment circuit 7 includes two pulse generation circuits 10a and 10b, two inverting buffers 20a and 20b, an opposing inverter 30, and inverters 41 and 42.

[0032] The pulse generation circuits 10a and 10b output two pulse signals of opposite phases from an input clock signal and a feedback signal. The pulse generation circuit 10a includes a negative AND (NAND) circuit 11a and an inverter 12a. The pulse generation circuit 10b includes a negative AND circuit 11b and an inverter 12b. The pulse generation circuits 10a and 10b have approximately the same configuration.

[0033] The NAND circuits 11a and 11b are logic circuits that perform NAND operations, and each of the NAND circuits 11a and 11b has two input terminals and one output terminal.

[0034] The inverters 12a and 12b are logic circuits that perform a negation operation. Each of the inverters 12a and 12b has one input terminal and one output terminal.

[0035] The clock signal CLKIN_T is input to a first input terminal of the NAND circuit 11a, and a signal QB0T (described later) is input to a second input terminal as a feedback signal. The NAND circuit 11a performs a logical operation of NAND and outputs a pulse signal P0B. The pulse signal P0B is a negative pulse signal. The inverter 12a receives the pulse signal P0B as an input and outputs a pulse signal N0T. The pulse signal N0T is a positive pulse signal.

[0036] The clock signal CLKIN_B is input to a first input terminal of the NAND circuit 11b, and a signal QB0B (described later) is input to a second input terminal as a feedback signal. The NAND circuit 11b performs a logical operation of NAND and outputs a pulse signal P0T. The pulse signal P0T is a negative pulse signal. The inverter 12b receives the pulse signal P0T as an input and outputs a pulse signal N0B. The pulse signal N0B is a positive pulse signal.

[0037] Pulse signals N0T, P0T, N0B, and P0B are signals that control transistors included in inverting buffers 20a and 20b. Hereinafter, a voltage at a logic level corresponding to "0" will also be referred to as an "L" level, and a voltage at a logic level corresponding to "1" will also be referred to as an "H" level.

[0038] The inverting buffers 20a and 20b are circuits that output signals based on input pulse signals. The inverting buffer 20a outputs a signal QB0T based on the pulse signals N0T and P0T. The inverting buffer 20a includes transistors 21 and 22. The inverting buffer 20b outputs a signal QB0B based on the pulse signals N0B and P0B. The inverting buffer 20b includes transistors 23 and 24.

[0039] The transistors 21, 22, 23, and 24 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The transistors 21 and 23 are, for example, P-type MOSFETs. The transistors 21 and 23 conduct the drain and source terminals when the voltage applied to the gate terminal is at an "L" level, and insulate the drain and source terminals when the voltage applied to the gate terminal is at an "H" level. The threshold voltages of the transistors 21 and 23 are approximately equal. The transistors 22 and 24 are, for example, N-type MOSFETs. The transistors 22 and 24 conduct the drain and source terminals when the voltage applied to the gate terminal is at an "H" level, and insulate the drain and source terminals when the voltage applied to the gate terminal is at an "L" level. The threshold voltages of the transistors 22 and 24 are approximately equal.

[0040] In the inverting buffer 20a, the drain terminal of the transistor 21 and the drain terminal of the transistor 22 are connected via a node N1. The source terminal of the transistor 21 is connected to a power supply potential VDD. The source terminal of the transistor 22 is connected to a ground potential VSS. A pulse signal POT is input to the gate terminal of the transistor 21. A pulse signal NOT is input to the gate terminal of the transistor 22. The inverting buffer 20a varies the voltage of the node N1 by controlling the transistors 21 and 22 with the pulse signals POT and NOT, thereby generating a signal QBOT. The signal QBOT is input to the pulse generating circuit 10a (more specifically, the NAND circuit 11a) as a feedback signal.

[0041] In the inverting buffer 20b, the drain terminal of the transistor 23 and the drain terminal of the transistor 24 are connected via a node N2. The source terminal of the transistor 23 is connected to a power supply potential VDD. The source terminal of the transistor 24 is connected to a ground potential VSS. A pulse signal P0B is input to the gate terminal of the transistor 23. A pulse signal N0B is input to the gate terminal of the transistor 24. The inverting buffer 20b varies the voltage of the node N2 by controlling the transistors 23 and 24 with the pulse signals P0B and N0B, thereby generating a signal QB0B. The signal QB0B is input to the pulse generating circuit 10b (more specifically, the NAND circuit 11b) as a feedback signal.

[0042] The counter inverter 30 is provided to connect between nodes N1 and N2. The counter inverter 30 includes inverters 31 and 32. The inverters 31 and 32 are logic circuits that perform a NOT operation. The inverter 31 has an input terminal connected to node N2 and an output terminal connected to node N1. The inverter 32 has an input terminal connected to node N1 and an output terminal connected to node N2. That is, the inverters 31 and 32 are connected in parallel between nodes N1 and N2. The inverters 31 and 32 invert the logic level input to their input terminals and output the inverted signal. The threshold voltages of the inverters 31 and 32 are approximately equal.

[0043] The magnitude of the currents output by the inverters 31 and 32 included in the counter inverter 30 is set to be smaller than the magnitude of the currents output by the inverting buffers 20a and 20b. For example, if the inverters 31 and 32 are configured with multiple transistors (MOSFETs), the size of the transistors included in the inverters 31 and 32 is smaller than the size of the transistors 21, 22, 23, and 24 that configure the inverting buffers 20a and 20b. As a result, when the logic level of the output of the inverting buffer 20a differs from the logic level of the output of the inverter 31, the logic level of the output of the inverting buffer 20a takes precedence over the logic level of the node N1. When the logic level of the output of the inverting buffer 20b differs from the logic level of the output of the inverter 32, the logic level of the output of the inverting buffer 20b takes precedence over the logic level of the node N2.

[0044] The inverters 41 and 42 are logic circuits that perform a negation operation. The inverter 41 receives the signal QB0T, shapes the waveform into a substantially rectangular shape, inverts the logic level, and outputs the result as a clock signal CLKOUT. The inverter 42 receives the signal QB0B, shapes the waveform into a substantially rectangular shape, inverts the logic level, and outputs the result as a clock signal CLKOUTB. The clock signals CLKOUT and CLKOUTB are a differential signal pair. The threshold voltages of the inverters 41 and 42 are substantially equal.

[0045] 1.4.2 Operation 7 is a timing chart showing an example of the operation of the clock adjustment circuit according to the first embodiment. The operation of the clock adjustment circuit 7 will be described below with reference to FIG.

[0046] Clock signals CLKIN_T and CLKIN_B are input to the clock adjustment circuit 7. In the example shown in Fig. 7, the clock signal CLKIN_T rises at time t1, and the clock signal CLKIN_B rises at time t5. Note that the example shown in Fig. 7 shows a case where the clock signals CLKIN_T and CLKIN_B are not delayed by the delay adjustment circuits 6a and 6b. As long as the times at which the clock signals CLKIN_T and CLKIN_B fall are not included in the periods in which the transistors 21, 22, 23, and 24 are driven, the clock signals CLKIN_T and CLKIN_B may be delayed to correct the duty ratio.

[0047] When the clock signal CLKIN_T rises at time t1, a delay occurs due to the NAND circuit 11a, and the pulse signal N0T rises at time t2. This drives the transistor 22, and the voltage at the node N1 gradually decreases. Therefore, the signal QB0T gradually falls. Also, at time t2, the pulse signal P0B falls. This drives the transistor 23, and the voltage at the node N2 gradually increases. Therefore, the signal QB0B gradually rises.

[0048] At time t3, the clock signal CLKOUT rises when the voltage of the signal QB0T reaches the threshold voltage of the inverter 41. Furthermore, the clock signal CLKOUTB falls when the voltage of the signal QB0B reaches the threshold voltage of the inverter 42. The opposing inverter 30 adjusts the rise of the clock signal CLKOUT and the fall of the clock signal CLKOUTB to occur at the same time.

[0049] Furthermore, when the voltage of the signal QB0T reaches the threshold voltage of the NAND circuit 11a at time t3, the output of the NAND circuit 11a changes. As a result, after a delay corresponding to the NAND circuit 11a, the pulse signal N0T falls at time t4, and the pulse signal P0B rises.

[0050] When the clock signal CLKIN_B rises at time t5, a delay occurs due to the NAND circuit 11b, and the pulse signal N0B rises at time t6. This drives the transistor 24, and the voltage at the node N2 gradually decreases. Therefore, the signal QB0B gradually falls. Also, at time t6, the pulse signal P0T falls. This drives the transistor 21, and the voltage at the node N1 gradually increases. Therefore, the signal QB0T gradually rises.

[0051] At time t7, the clock signal CLKOUT falls when the voltage of the signal QB0T reaches the threshold voltage of the inverter 41. Furthermore, the clock signal CLKOUTB rises when the voltage of the signal QB0B reaches the threshold voltage of the inverter 42. The opposing inverter 30 adjusts the fall of the clock signal CLKOUT and the rise of the clock signal CLKOUTB to occur at the same time.

[0052] Furthermore, when the voltage of the signal QB0T reaches the threshold voltage of the NAND circuit 11b at time t7, the output of the NAND circuit 11b changes. As a result, after a delay equivalent to the NAND circuit 11b, the pulse signal N0B falls at time t8, and the pulse signal P0T rises.

[0053] The positive pulse widths of the pulse signals NOT and NOB are set to be longer than the response times of the output signals to the input signals of the first inverting buffer and the second inverting buffer, and shorter than the positive pulse widths of the output clock signals CLKOUT and CLKOUTB. Specifically, during the period from when the clock signal CLKIN_T rises to when the clock signal CLKIN_B rises, the pulse signal NOT rises and falls once. During the period from when the clock signal CLKIN_B rises to when the clock signal CLKIN_T rises, the pulse signal NOB rises and falls once. Furthermore, because the pulse signals POT and POB are inverted signals of the pulse signals NOB and NOT, respectively, the negative pulse widths of each signal are equal to the positive pulse widths of the pulse signals NOB and NOT, respectively.

[0054] The opposing inverter 30 serves to equalize the voltage transition speed at node N1 and the voltage transition speed at node N2. For example, if the transition speed of the output voltage of the inverting buffer 20a from time t2 to t3 is slower than the transition speed of the output voltage of the inverting buffer 20b from time t2 to t3, a high-level voltage is applied to node N1 via the inverter 31. This increases the rate at which the voltage at node N1 rises. Furthermore, if the transition speed of the output voltage of the inverting buffer 20b from time t2 to t3 is slower than the transition speed of the output voltage of the inverting buffer 20a from time t2 to t3, a low-level voltage is applied to node N2 via the inverter 32. This increases the rate at which the voltage at node N2 falls. Similarly, the voltage transition speeds at nodes N1 and N2 from time t6 to t7 can be adjusted. In this manner, the voltage transition speeds at nodes N1 and N2 can be equalized.

[0055] 1.5 Effects The DCA circuit according to the first embodiment can reduce the duty error of the output clock signal. This effect will be described in detail below.

[0056] The DCA circuit 1 according to the first embodiment includes two inverting buffers 20a and 20b. In the DCA circuit 1 according to the first embodiment, the inverting buffer 20a generates a clock signal CLKT_IO, and the inverting buffer 20b generates a clock signal CLKB_IO. The clock signals CLKT_IO and CLKB_IO are configured to form a differential clock signal pair. Therefore, a conversion circuit separate from the DCA circuit 1 for converting a single-phase clock signal into a differential clock signal pair can be omitted, thereby reducing factors that cause duty error and making it possible to reduce the duty error.

[0057] Furthermore, in the DCA circuit 1 according to the first embodiment, the pulse generating circuits 10a and 10b have substantially the same configuration. The inverting buffers 20a and 20b have substantially the same configuration. The configuration for generating the pulse signals P0T and N0T that control the inverting buffer 20a and the configuration for generating the pulse signals P0B and N0B that control the inverting buffer 20b are symmetrical to each other. Therefore, it can be said that the configurations for generating the output clock signals CLKT_IO and CLKB_IO are also symmetrical to each other. Specifically, for example, they do not include an inverter or the like for inverting the logic of only the input clock signal CLKIN_B. Therefore, it is possible to suppress duty cycle errors resulting from differences in the configurations for outputting clock signals.

[0058] Furthermore, the DCA circuit 1 according to the first embodiment is provided with an opposing inverter 30 at the output nodes of the two inverting buffers 20a and 20b that generate differential signals. This allows the voltage transition speeds of the inverting buffers 20a and 20b to be matched, averaging the difference between the time required to drive the P-type transistor and the time required to drive the N-type transistor. Therefore, it is possible to suppress duty cycle errors resulting from the difference between the time required to drive the P-type transistor and the time required to drive the N-type transistor.

[0059] As described above, the DCA circuit 1 according to the first embodiment can generate a differential clock signal pair with a small duty cycle error. This reduces the amount of duty cycle correction required for the entire DCC circuit 400, suppressing duty cycle fluctuations due to voltage and temperature fluctuations that accompany delay generation during duty cycle correction. Furthermore, the current required for duty cycle correction can be reduced, suppressing increases in power consumption and installation area required for the DCC circuit 400. Additionally, the frequency of duty cycle correction can be reduced, improving the performance of the entire memory system 100.

[0060] 2. Second embodiment Next, a second embodiment will be described. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

[0061] 2.1 Clock adjustment circuit configuration Fig. 8 is a circuit diagram showing an example of the circuit configuration of a clock adjustment circuit according to the second embodiment. The clock adjustment circuit 7 according to the second embodiment further includes pulse control circuits (PGCNT) 13a and 13b in the pulse generation circuits 10a and 10b, respectively. Fig. 9 is a truth table of the pulse control circuit included in the clock adjustment circuit according to the second embodiment.

[0062] The pulse control circuits 13a and 13b are circuits that receive two inputs IN and FB and return one output Q. The pulse control circuits 13a and 13b have a first input terminal corresponding to the input IN, a second input terminal corresponding to the input FB, and an output terminal corresponding to the output Q. The pulse control circuits 13a and 13b have substantially the same configuration. Hereinafter, when there is no need to distinguish between the pulse control circuits 13a and 13b, they will be referred to as pulse control circuits 13.

[0063] The clock signal CLKIN_T is input to a first input terminal of the pulse control circuit 13a, the signal QB0T is input to a second input terminal as a feedback signal, and the output terminal is connected to the second input terminal of the NAND circuit 11a.

[0064] The clock signal CLKIN_B is input to a first input terminal of the pulse control circuit 13b. The signal QB0B is input to a second input terminal as a feedback signal. The output terminal is connected to the second input terminal of the NAND circuit 11b.

[0065] The pulse control circuit 13 returns an output according to the input in accordance with the truth table shown in Fig. 9. Specifically, when the logic level of the input IN is "0" and the logic level of the input FB is "0", an output Q of logic level "0" is returned. When the logic level of the input IN is "0" and the logic level of the input FB is "1", an output Q of logic level "1" is returned. When the logic level of the input IN is "1" and the logic level of the input FB is "0", an output Q of logic level "0" is returned. When the logic level of the input IN is "1" and the logic level of the input FB is "1", the output Q returns a value that maintains the logic level that the output Q indicated immediately before.

[0066] 10 is a circuit diagram showing an example of the circuit configuration of a pulse control circuit included in the clock adjusting circuit according to the second embodiment. The pulse control circuit 13 includes an inverter 61, and NAND circuits 62, 63, and 64.

[0067] The inverter 61 is a logic circuit that performs a NOT operation. The inverter 61 has an input terminal and an output terminal. The NAND circuits 62, 63, and 64 are logic circuits that perform a NAND operation. The NAND circuits 62, 63, and 64 each have a first input terminal, a second input terminal, and an output terminal.

[0068] An input IN is input to the input terminal of the inverter 61. An output terminal of the inverter 61 is connected to a first input terminal of a NAND circuit 62. An input FB is input to a second input terminal of the NAND circuit 62. An output terminal of the NAND circuit 62 is connected to a first input terminal of a NAND circuit 63. An output of the NAND circuit 64 is input to a second input terminal of the NAND circuit 63. An output Q is output from the output terminal of the NAND circuit 63. The output Q is input to a first input terminal of the NAND circuit 64 as feedback. An input FB is input to a second input terminal of the NAND circuit 64.

[0069] With the circuit configuration shown above, it is possible to configure a logic circuit that performs logical operations such as those in the truth table shown in Fig. 9. Note that the above circuit configuration is just one example, and any configuration is acceptable as long as the logic circuit performs logical operations such as those in the truth table shown in Fig. 9.

[0070] 2.2 Effects The DCA circuit according to the second embodiment can reduce the duty error of the output clock signal, similar to the first embodiment.

[0071] Furthermore, the DCA circuit 1 according to the second embodiment can suppress oscillation of the clock signals CLKT_IO and CLKB_IO that are output. This effect will be described in detail below.

[0072] For example, consider a case where clock signal CLKIN_T indicates a logic level of "0" and clock signal CLKIN_B indicates a logic level of "1." In this case, signal QB0B indicates a logic level of "0." Since input IN of pulse control circuit 13b is "1" and input FB is "0," output Q indicates a logic level of "0."

[0073] Here, when the clock signal CLKIN_T rises and indicates a logic level of "1," the transistor 23 is driven, and the signal QB0B rises. At this time, the input IN of the pulse control circuit 13b is "1," and the input FB is "1," so the output Q indicates the previous logic level of "0." Therefore, the transistors 21 and 24 are not driven. In other words, oscillation of the clock signals CLKOUT and CLKOUTB can be suppressed.

[0074] Similarly, even if the clock signal CLKIN_B rises while the clock signal CLKIN_T indicates the logic level "1," oscillation of the clock signals CLKOUT and CLKOUTB can be suppressed.

[0075] 3. Third embodiment Next, a third embodiment will be described. In the following description, the description of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

[0076] 3.1 Clock adjustment circuit 3.1.1 Configuration 11 is a circuit diagram showing an example of the circuit configuration of a clock adjustment circuit according to the third embodiment. The clock adjustment circuit 7 according to the third embodiment further includes delay circuits 14a and 14b in the pulse generation circuits 10a and 10b, respectively.

[0077] The delay circuits 14a and 14b delay and output the input signal. The delay circuits 14a and 14b include, for example, an odd number of inverter stages connected in series. In FIG. 11, the delay circuits 14a and 14b include a configuration in which three inverters are connected in series, but this configuration is not limited as long as the delay time conditions described below are met. For example, the delay circuits 14a and 14b may include a configuration in which five or more odd number of inverter stages are connected in series. The delay circuits 14a and 14b have approximately the same configuration.

[0078] The clock signal CLKIN_T is input to the input terminal of the delay circuit 14a. The output terminal of the delay circuit 14a is connected to the second input terminal of the NAND circuit 11a and outputs a signal C0T. The signal C0T is a clock signal obtained by delaying the clock signal CLKIN_T.

[0079] The clock signal CLKIN_B is input to the input terminal of the delay circuit 14b. The output terminal of the delay circuit 14a is connected to the second input terminal of the NAND circuit 11b, and outputs a signal C0B. The signal C0B is a clock signal obtained by delaying the clock signal CLKIN_B.

[0080] The clock adjusting circuit 7 according to the third embodiment does not include feedback from the node N1 or N2 to the pulse generating circuit 10a or 10b. Therefore, the pulse generating circuits 10a and 10b generate pulse signals regardless of the output result of the inverting buffer 20a or 20b.

[0081] 3.1.2 Operation 12 is a timing chart showing an example of the operation of the clock adjustment circuit according to the third embodiment. The operation of the clock adjustment circuit 7 will be described below with reference to FIG.

[0082] The operation from when the clock signal CLKIN_T rises at time t1 until the clock signal CLKOUT rises at time t3 and the clock signal CLKOUTB falls is the same as in the first embodiment.

[0083] At time t4, the signal C0T falls after being delayed by the delay circuit 14a, which causes the pulse signal N0T to fall at time t5 after a delay by the NAND circuit 11a, and the pulse signal P0B to rise.

[0084] The operation from when the clock signal CLKIN_B rises at time t6 until the clock signal CLKOUT falls at time t8 and the clock signal CLKOUTB rises is the same as in the first embodiment.

[0085] At time t9, signal C0B falls after being delayed by delay circuit 14b. As a result, after a delay by NAND circuit 11b, pulse signal N0B falls at time t10 and pulse signal P0T rises. Thereafter, clock signal CLKIN_T rises at time t11, and the above operation is repeated thereafter.

[0086] The delay times provided by the delay circuits 14a and 14b are set to be longer than the response time of the output signal to the input signal in the inverters 31 and 32 included in the opposite inverter 30 and shorter than the positive pulse width of the output clock signals CLKOUT and CLKOUTB. Specifically, the delay circuit 14a delays the signal by a period longer than the time from time t1 when the clock signal CLKIN_T rises to time t3 when the opposite inverter 30 inverts the signal (time t1 to time t3) and shorter than the time from time t1 when the clock signal CLKIN_B rises to time t6 when the clock signal CLKIN_B rises (time t1 to time t8). The delay circuit 14b delays the signal by a period longer than the time from time t6 when the clock signal CLKIN_B rises to time t8 when the opposite inverter 30 inverts the signal (time t6 to time t8) and shorter than the time from time t6 when the clock signal CLKIN_B rises to time t11 when the clock signal CLKIN_T rises (time t6 to time t11).

[0087] 3.2 Effects The DCA circuit 1 according to the third embodiment can reduce the duty error of the output clock signal, similar to the first embodiment.

[0088] Additionally, the DCA circuit 1 according to the third embodiment does not provide feedback from the output of the inverting buffer 20a or 20b to the pulse generating circuits 10a and 10b. Therefore, compared to the second embodiment, a logic circuit that generates a signal based on a feedback signal is not required, which can suppress the occurrence of parasitic capacitance in the DCA circuit 1. Furthermore, oscillation of the output clock signals CLKT_IO and CLKB_IO can be suppressed.

[0089] 4. Fourth embodiment Next, a fourth embodiment will be described. The fourth embodiment is an embodiment derived from the third embodiment. In the following explanation, explanations of configurations equivalent to those of the first and third embodiments will be omitted, and configurations different from those of the first and third embodiments will be mainly explained.

[0090] 4.1 DCA circuit configuration The configuration of a DCA circuit according to the fourth embodiment will be described. Fig. 13 is a block diagram showing an example of the configuration of a DCA circuit according to the fourth embodiment. As shown in Fig. 13, a DCA circuit 1 receives inputs of a set signal SETB and a reset signal RSTB.

[0091] The set signal SETB and the reset signal RSTB are signals sent from, for example, an external control circuit (not shown) and are input to the clock adjustment circuit 7.

[0092] 4.2 Clock Adjustment Circuit 4.2.1 Configuration 14 is a circuit diagram showing an example of the circuit configuration of the clock adjustment circuit according to the third embodiment. The clock adjustment circuit 7 according to the fourth embodiment further includes a logical product (AND) circuit 50. In addition, the pulse generation circuits 10a and 10b include logical product circuits 15a and 15b instead of the NAND circuits 11a and 11b, respectively. The pulse generation circuits 10a and 10b include logical product circuits 16a and 16b instead of the inverters 12a and 12b, respectively.

[0093] The NAND circuits 15a and 15b are logic circuits that perform NAND operations, and each has three input terminals and one output terminal.

[0094] The clock signal CLKIN_T is input to a first input terminal of the NAND circuit 15a. The signal C0T, which is the output of the delay circuit 14a, is input to a second input terminal. The output signal of the AND circuit 50, which will be described later, is input to a third input terminal. The output terminal of the NAND circuit 15a is connected to the gate terminal of the transistor 23, and outputs a pulse signal P0B.

[0095] The clock signal CLKIN_B is input to a first input terminal of the NAND circuit 15b. The signal C0B, which is the output of the delay circuit 14b, is input to a second input terminal. The output signal of the AND circuit 50, which will be described later, is input to a third input terminal. The output terminal of the NAND circuit 15b is connected to the gate terminal of the transistor 21, and outputs a pulse signal P0T.

[0096] The NAND circuits 16a and 16b are logic circuits that perform NAND operations, and each of the NAND circuits 16a and 16b has two input terminals and one output terminal.

[0097] The pulse signal P0B is input to a first input terminal of the NAND circuit 16a. The set signal SETB is input to a second input terminal of the NAND circuit 16a. The output terminal of the NAND circuit 16a is connected to the gate terminal of the transistor 22 and outputs a pulse signal N0T.

[0098] The pulse signal POT is input to a first input terminal of the NAND circuit 16b. The reset signal RSTB is input to a second input terminal of the NAND circuit 16b. The output terminal of the NAND circuit 16b is connected to the gate terminal of the transistor 24 and outputs a pulse signal NOB.

[0099] The logical product circuit 50 is a logic circuit that performs logical product operations and has two input terminals and one output terminal.

[0100] A set signal SETB is input to a first input terminal of the AND circuit 50. A reset signal RSTB is input to a second input terminal of the AND circuit 50. An output terminal of the AND circuit 50 is connected to a third input terminal of the NAND circuit 15a and a third input terminal of the NAND circuit 15b.

[0101] 4.2.2 Operation 15 and 16 are timing charts showing an example of the operation of the clock adjustment circuit according to the fourth embodiment. The hatched portions in FIGS. 15 and 16 indicate an indeterminate state where the logic level is uncertain, and the signal in question takes on any voltage included in the hatched range. The operation of the clock adjustment circuit 7 will be described below with reference to FIGS. 15 and 16.

[0102] Immediately after powering on the DCA circuit 1, the inverting buffers 20a and 20b are not driven until either CLKIN_T or CLKIN_B input to the clock adjustment circuit 7 rises. Therefore, as shown in Figures 15 and 16, the output clock signals CLKOUT and CLKOUTB are in an undefined state. Even if the inverting buffers 20a and 20b are driven from this state, it may take some time for the output to stabilize because the initial states of the clock signals CLKOUT and CLKOUTB are undefined.

[0103] One possible solution to this problem is to fix the initial states of the clock signals CLKOUT and CLKOUTB. The operation of fixing the clock signal CLKOUT to logic level "1" is called a "set operation," and the operation of fixing the clock signal CLKOUT to logic level "0" is called a "reset operation." By performing a set operation or a reset operation, the initial states of the clock signals CLKOUT and CLKOUTB can be fixed, and the clock adjustment circuit 7 can be operated while avoiding an unstable state.

[0104] The set signal SETB and the reset signal RSTB are signals that exhibit a logic level of "1" in a steady state (when a set operation or a reset operation is not being performed). When a set operation is performed, the set signal SETB temporarily exhibits a logic level of "0" and then returns to a logic level of "1". When a reset operation is performed, the reset signal RSTB temporarily exhibits a logic level of "0" and then returns to a logic level of "1".

[0105] The operation shown in FIG. 15 corresponds to a set operation. When the set operation is executed, the set signal SETB falls at time t1. At this time, the output of the NAND circuit 16a becomes "1," and after a delay corresponding to the NAND circuit 16a, the pulse signal N0T rises at time t2. This drives the transistor 22, gradually decreasing the voltage at node N1. Therefore, the signal QB0T gradually falls. Furthermore, due to the effect of the inverter 32, the signal QB0B gradually rises.

[0106] At time t3, when the voltage of signal QB0T reaches the threshold voltage of inverter 41, the logic level of clock signal CLKOUT is fixed at "1." Furthermore, when the voltage of signal QB0B reaches the threshold voltage of inverter 42, the logic level of clock signal CLKOUTB is fixed at "0."

[0107] Thereafter, when the set signal SETB rises at time t4, after a delay corresponding to the NAND circuit 16a, the pulse signal N0T falls at time t5.

[0108] After all of these processes are completed, the input clock signal CLKIN_B rises at time t6. The input of the clock signal after the set operation begins with the rise of the clock signal CLKIN_B. Thereafter, the same operations as in the third embodiment are performed.

[0109] The operation shown in FIG. 16 corresponds to a reset operation. When the reset operation is performed, the reset signal RSTB falls at time t1. At this time, the output of the NAND circuit 16b becomes "1," and after a delay corresponding to the NAND circuit 16b, the pulse signal N0B rises at time t2. This drives the transistor 24, gradually decreasing the voltage at node N2. Therefore, the signal QB0B gradually falls. Furthermore, due to the effect of the inverter 31, the signal QB0T gradually rises.

[0110] At time t3, when the voltage of signal QB0T reaches the threshold voltage of inverter 41, the logic level of clock signal CLKOUT is fixed at "0." Furthermore, when the voltage of signal QB0B reaches the threshold voltage of inverter 42, the logic level of clock signal CLKOUTB is fixed at "1."

[0111] Thereafter, when the reset signal RSTB rises at time t4, after a delay corresponding to the NAND circuit 16b, the pulse signal N0B falls at time t5.

[0112] After all of these processes are completed, the input clock signal CLKIN_T rises at time t6. The input of the clock signal after the reset operation begins with the rise of the clock signal CLKIN_T. Thereafter, the same operations as in the third embodiment are performed.

[0113] 4.3 Effects The DCA circuit 1 according to the fourth embodiment can reduce the duty error of the output clock signal, as in the first embodiment, and can suppress the oscillation of the output clock signals CLKT_IO and CLKB_IO, as in the third embodiment.

[0114] Additionally, the DCA circuit 1 according to the fourth embodiment can prevent the clock signals CLKT_IO and CLKB_IO, which are output signals, from becoming unstable immediately after power-on, etc. This makes it possible to output stable clock signals CLKT_IO and CLKB_IO immediately after power-on.

[0115] 4.4 Variations In the fourth embodiment, circuits for performing set and reset operations are added to the configuration of the pulse generation circuits 10a and 10b shown in the third embodiment, which includes delay circuits 14a and 14b, respectively. However, this is not limiting. For example, circuits for performing set and reset operations may be added to the configuration of the first embodiment. For example, circuits for performing set and reset operations may be added to the configuration of the pulse generation circuits 10a and 10b shown in the second embodiment, which includes pulse control circuits 13a and 13b, respectively. Below, we will explain the differences from the fourth embodiment regarding a first modification in which circuits for performing set and reset operations are added to the configuration of the pulse generation circuits 10a and 10b, which includes pulse control circuits 13a and 13b, respectively.

[0116] Fig. 17 is a circuit diagram showing an example of the circuit configuration of a clock adjustment circuit according to a first modification of the fourth embodiment. As shown in Fig. 17, the clock adjustment circuit 7 according to the first modification of the fourth embodiment includes pulse control circuits 13a and 13b in the pulse generation circuits 10a and 10b, respectively, instead of the delay circuits 14a and 14b.

[0117] The pulse control circuits 13a and 13b are circuits that receive two inputs IN and FB and return one output Q. The pulse control circuits 13a and 13b have a first input terminal corresponding to the input IN, a second input terminal corresponding to the input FB, and an output terminal corresponding to the output Q. The pulse control circuits 13a and 13b return an output according to the input in accordance with the same truth table as the truth table shown in FIG.

[0118] The clock signal CLKIN_T is input to a first input terminal of the pulse control circuit 13a. The signal QB0T is input to a second input terminal as a feedback signal. The output terminal is connected to a second input terminal of the NAND circuit 15a.

[0119] The clock signal CLKIN_B is input to a first input terminal of the pulse control circuit 13b. The signal QB0B is input to a second input terminal as a feedback signal. The output terminal is connected to a second input terminal of the NAND circuit 15b.

[0120] The DCA circuit 1 according to the first modification of the fourth embodiment, like the fourth embodiment, can prevent the clock signals CLKT_IO and CLKB_IO, which are output signals, from being in an unstable state immediately after power-on, etc. This makes it possible to output stable clock signals CLKT_IO and CLKB_IO immediately after power-on.

[0121] 5. Other In the first to fourth embodiments introduced above, an example has been described in which the memory controller 200 is connected to each memory chip 320 via the interface chip 310, but the present invention is not limited to this configuration. For example, the memory controller 200 may be connected to each memory chip 320 without the interface chip 310. In this case, for example, the DCC circuit 400 is included in each memory chip 320.

[0122] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0123] 1...DCA circuit 2... Input / output buffer 3...DCD circuit 4...DCC logic circuit 6a, 6b...Delay adjustment circuit 7...Clock adjustment circuit 10a, 10b...Pulse generating circuit 11a, 11b, 15a, 15b, 16a, 16b, 62, 63, 64...NON-AND circuit 12a, 12b, 31, 32, 41, 42, 61... Inverter 13, 13a, 13b... Pulse control circuit 14a, 14b...Delay circuit 20a, 20b...inverting buffer 21, 22, 23, 24...Transistors 30... Opposing inverter 50...Logical product circuit 100...Memory system 200...Memory controller 300...Memory device 310...Interface chip 320...Memory chip 400, 400a, 400b, 400c...DCC circuit

Claims

1. a first pulse generating circuit that generates a first pulse signal and a second pulse signal that is an inverted signal of the first pulse signal based on a first signal; a second pulse generating circuit that generates a third pulse signal and a fourth pulse signal that is an inverted signal of the third pulse signal based on the second signal; a first inverting buffer that outputs a third signal from a first node based on the first pulse signal and the third pulse signal; a second inverting buffer that outputs a fourth signal from a second node based on the second pulse signal and the fourth pulse signal; Equipped with the first inverting buffer changes the logic level of the third signal from the second logic level to the first logic level when the logic level of the first pulse signal changes from the first logic level to a second logic level different from the first logic level, and changes the logic level of the third signal from the first logic level to the second logic level when the logic level of the third pulse signal changes from the second logic level to the first logic level; the second inverting buffer changes the logic level of the fourth signal from the first logic level to the second logic level when the logic level of the second pulse signal changes from the second logic level to the first logic level, and changes the logic level of the fourth signal from the second logic level to the first logic level when the logic level of the fourth pulse signal changes from the first logic level to the second logic level. Semiconductor integrated circuit.

2. a first inverter having an input connected to the first node and an output connected to the second node; a second inverter having an input connected to the second node and an output connected to the first node; The semiconductor integrated circuit according to claim 1 , further comprising:

3. a third inverter connected to the first node; a fourth inverter connected to the second node; The semiconductor integrated circuit according to claim 1 , further comprising:

4. the first pulse generating circuit, when the logic level of the first signal changes from the first logic level to the second logic level, changes the logic level of the first pulse signal from the first logic level to the second logic level and changes the logic level of the second pulse signal from the second logic level to the first logic level; the second pulse generating circuit changes the logic level of the third pulse signal from the second logic level to the first logic level and changes the logic level of the fourth pulse signal from the first logic level to the second logic level when the logic level of the second signal changes from the first logic level to the second logic level; 2. The semiconductor integrated circuit according to claim 1.

5. The first pulse generating circuit a first NAND circuit having a first input terminal to which the first signal is input, a second input terminal to which the third signal is input, and an output terminal to which the second pulse signal is output; a fifth inverter that receives the second pulse signal and outputs the first pulse signal; Including, The second pulse generating circuit a second NAND circuit having a third input terminal to which the second signal is input, a fourth input terminal to which the fourth signal is input, and an output terminal to which the third pulse signal is output; a sixth inverter that receives the third pulse signal and outputs the fourth pulse signal; Including, 5. The semiconductor integrated circuit according to claim 4.

6. The first inverting buffer comprises: a first transistor and a second transistor connected via the first node; the third pulse signal is input to the gate terminal of the first transistor; the first pulse signal is input to the gate terminal of the second transistor; outputting the third signal from an output terminal connected to the first node; The second inverting buffer comprises: a third transistor and a fourth transistor connected via the second node; the second pulse signal is input to the gate terminal of the third transistor; the fourth pulse signal is input to the gate terminal of the fourth transistor; outputting the fourth signal from an output terminal connected to the second node; 2. The semiconductor integrated circuit according to claim 1.

7. the first transistor, the second transistor, the third transistor, and the fourth transistor are MOS transistors; the first transistor and the third transistor have a first conductivity type; the second transistor and the fourth transistor have a second conductivity type different from the first conductivity type; 7. The semiconductor integrated circuit according to claim 6.

8. The magnitude of the current output by the first inverter and the second inverter is the magnitude of the current output from the first inverting buffer and the second inverting buffer is smaller than that of the current output from the first inverting buffer and the second inverting buffer; 3. The semiconductor integrated circuit according to claim 2.

9. the first pulse generating circuit further includes a first pulse control circuit; the first pulse control circuit includes a fifth input terminal to which the first signal is input, a sixth input terminal to which the third signal is input, and a first output terminal; an output of the first pulse control circuit is input to the second input terminal of the first NAND circuit in place of the third signal; The first pulse control circuit outputting a signal of the first logic level from the first output terminal when a signal of the first logic level is input to both the fifth input terminal and the sixth input terminal; outputting a signal of the second logic level from the first output terminal when the signal of the first logic level is input to the fifth input terminal and the signal of the second logic level is input to the sixth input terminal; outputting a signal of the first logic level from the first output terminal when the signal of the second logic level is input to the fifth input terminal and the signal of the first logic level is input to the sixth input terminal; when a signal of the second logic level is input to both the fifth input terminal and the sixth input terminal, a signal that maintains the logic level of the signal that was previously output from the first output terminal is output from the first output terminal; the second pulse generating circuit further includes a second pulse control circuit; the second pulse control circuit includes a seventh input terminal to which the second signal is input, an eighth input terminal to which the fourth signal is input, and a second output terminal; an output of the second pulse control circuit is input to the fourth input terminal of the first NAND circuit in place of the fourth signal; The second pulse control circuit outputting a signal of the first logic level from the second output terminal when a signal of the first logic level is input to both the seventh input terminal and the eighth input terminal; when a signal of the first logic level is input to the seventh input terminal and a signal of the second logic level is input to the eighth input terminal, a signal of the second logic level is output from the second output terminal; outputting a signal of the first logic level from the second output terminal when the signal of the second logic level is input to the seventh input terminal and the signal of the first logic level is input to the eighth input terminal; When a signal of the second logic level is input to both the seventh input terminal and the eighth input terminal, a signal that maintains the logic level of the signal that was previously output from the second output terminal is output from the second output terminal.

6. The semiconductor integrated circuit according to claim 5.

10. the first pulse generating circuit further includes a first delay circuit; the first delay circuit has an input terminal to which the first signal is input, a first delay element, and an output terminal; an output of the first delay circuit is input to the second input terminal of the first NAND circuit in place of the third signal; the second pulse generating circuit further includes a second delay circuit; the second delay circuit has an input terminal to which the second signal is input, a second delay element, and an output terminal; an output of the second delay circuit is input to the fourth input terminal of the second NAND circuit in place of the fourth signal; 6. The semiconductor integrated circuit according to claim 5.

11. pulse widths of the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal are longer than response times of output signals of the first inverting buffer and the second inverting buffer to input signals, and shorter than pulse widths of the third signal and the fourth signal; 2. The semiconductor integrated circuit according to claim 1.

12. a first inverter having an input connected to the first node and an output connected to the second node; a second inverter having an input connected to the second node and an output connected to the first node; Further provided with a delay time of the first delay element and a delay time of the second delay element are longer than a response time of an output signal of the first inverter and an output signal of the second inverter to an input signal, and shorter than a pulse width of the third signal and a pulse width of the fourth signal; The semiconductor integrated circuit according to claim 10.

13. the first pulse generating circuit generates the first pulse signal and the second pulse signal based on a fifth signal and a sixth signal in addition to the first signal; the second pulse generating circuit generates the third pulse signal and the fourth pulse signal based on the second signal, the fifth signal, and the sixth signal; When the logic level of the fifth signal changes from the second logic level to the first logic level, the first pulse generating circuit changes the logic levels of the first pulse signal and the second pulse signal to the second logic level; the second pulse generating circuit changes the logic level of the third pulse signal to the second logic level and changes the logic level of the fourth pulse signal to the first logic level; When the logic level of the sixth signal changes from the second logic level to the first logic level, the first pulse generating circuit changes the logic level of the first pulse signal to the first logic level and changes the logic level of the second pulse signal to the second logic level; the second pulse generating circuit changes the logic levels of the third pulse signal and the fourth pulse signal to the second logic level; 2. The semiconductor integrated circuit according to claim 1.

14. a logical product circuit including a ninth input terminal to which the fifth signal is input, a tenth input terminal to which the sixth signal is input, and a third output terminal; The first pulse generating circuit a first NAND circuit including a first input terminal to which the first signal is input, a second input terminal to which the third signal is input, an eleventh input terminal connected to a third output terminal of the AND circuit, and an output terminal to output the second pulse signal; a third NAND circuit having a twelfth input terminal to which the second pulse signal is input, a thirteenth input terminal to which the fifth signal is input, and an output terminal to which the first pulse signal is output; Including, The second pulse generating circuit a second NAND circuit including a third input terminal to which the second signal is input, a fourth input terminal to which the fourth signal is input, a fourteenth input terminal connected to the third output terminal of the AND circuit, and a fourth output terminal that outputs the third pulse signal; a fourth NAND circuit having a fifteenth input terminal to which the third pulse signal is input, a sixteenth input terminal to which the sixth signal is input, and an output terminal to which the fourth pulse signal is output; Including, 14. The semiconductor integrated circuit according to claim 13.

15. the first pulse generating circuit further includes a first pulse control circuit; the first pulse control circuit includes a fifth input terminal to which the first signal is input, a sixth input terminal to which the third signal is input, and a first output terminal; an output of the first pulse control circuit is input to the second input terminal of the first NAND circuit in place of the third signal; The first pulse control circuit outputting a signal of the first logic level from the first output terminal when a signal of the first logic level is input to both the fifth input terminal and the sixth input terminal; outputting a signal of the second logic level from the first output terminal when the signal of the first logic level is input to the fifth input terminal and the signal of the second logic level is input to the sixth input terminal; outputting a signal of the first logic level from the first output terminal when the signal of the second logic level is input to the fifth input terminal and the signal of the first logic level is input to the sixth input terminal; when a signal of the second logic level is input to both the fifth input terminal and the sixth input terminal, a signal that maintains the logic level of the signal that was previously output from the first output terminal is output from the first output terminal; the second pulse generating circuit further includes a second pulse control circuit; the second pulse control circuit includes a seventh input terminal to which the second signal is input, an eighth input terminal to which the fourth signal is input, and a second output terminal; an output of the second pulse control circuit is input to the fourth input terminal of the first NAND circuit in place of the fourth signal; The second pulse control circuit outputting a signal of the first logic level from the second output terminal when a signal of the first logic level is input to both the seventh input terminal and the eighth input terminal; when a signal of the first logic level is input to the seventh input terminal and a signal of the second logic level is input to the eighth input terminal, a signal of the second logic level is output from the second output terminal; outputting a signal of the first logic level from the second output terminal when the signal of the second logic level is input to the seventh input terminal and the signal of the first logic level is input to the eighth input terminal; When a signal of the second logic level is input to both the seventh input terminal and the eighth input terminal, a signal that maintains the logic level of the signal that was previously output from the second output terminal is output from the second output terminal.

15. The semiconductor integrated circuit according to claim 14.

16. the first pulse generating circuit further includes a first delay circuit; the first delay circuit has an input terminal to which the first signal is input, a first delay element, and an output terminal; an output of the first delay circuit is input to the second input terminal of the first NAND circuit in place of the third signal; the second pulse generating circuit further includes a second delay circuit; the second delay circuit has an input terminal to which the second signal is input, a second delay element, and an output terminal; an output of the second delay circuit is input to the fourth input terminal of the second NAND circuit in place of the fourth signal; 15. The semiconductor integrated circuit according to claim 14.

17. a first delay adjustment circuit that adds a delay to a seventh signal and outputs the first signal; a second delay adjustment circuit that adds a delay to the eighth signal and outputs the second signal; The semiconductor integrated circuit according to claim 1 , further comprising:

18. an input / output buffer that controls amplification or the like of the third signal and the fourth signal; a DCD circuit that measures pulse widths of the third signal and the fourth signal, detects a difference between the duty ratios of the third signal and the fourth signal, and outputs the difference; a DCC logic circuit that receives an output of the DCD circuit, determines a delay setting value, and controls the delay times in the first delay adjustment circuit and the second delay adjustment circuit; The semiconductor integrated circuit of claim 17 further comprising:

19. A memory controller; a memory chip including a memory cell array having a plurality of memory cells; an interface chip that interfaces the transmission and reception of signals exchanged between the memory controller and the memory chip; Equipped with the interface chip comprises the semiconductor integrated circuit according to claim 18 as a DCC circuit; the DCC circuit adjusts the duty ratio of a read enable signal or a data strobe signal transmitted and received between the memory controller and the memory chip; Memory system.

20. A memory controller; a memory chip including a memory cell array having a plurality of memory cells; Equipped with the memory chip comprises the semiconductor integrated circuit according to claim 18 as a DCC circuit; The DCC circuit adjusts a duty ratio of a read enable signal or a data strobe signal received from or transmitted to the memory controller. Memory system.

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