Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device that can be miniaturized is provided. [Solution] The semiconductor device comprises a first substrate on which a first circuit is provided, a second substrate stacked on the first substrate and on which a second circuit having a plurality of first wiring patterns periodically arranged at a constant first period is provided, and a plurality of first bridge wirings electrically connecting the first circuit and the plurality of first wiring patterns via a plurality of first contact holes penetrating the second substrate, wherein the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a first region is different from the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a second region.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A three-dimensional integration technology is known in which wafers or chips are bonded together and electrically connected to each other using through silicon vias (TSVs) (for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Ohba et al. "Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)", Electronics 2022, 11(2), 236 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the wafer or chip is distorted due to mechanical stress on the wafer or chip, misalignment may occur between the wiring pattern connecting the TSVs and the TSVs within the wafer or chip surface. If the TSVs and wiring pattern are made larger to absorb the misalignment, the semiconductor device will become larger.

[0005] An object of the present disclosure is to provide a semiconductor device that can be miniaturized and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a semiconductor device comprising: a first substrate having a first circuit; a second substrate having a second circuit stacked on the first substrate and having a plurality of first wiring patterns periodically arranged at a constant first period; and a plurality of first bridge wirings electrically connecting the first circuit and the plurality of first wiring patterns via a plurality of first contact holes penetrating the second substrate, wherein the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a first region is different from the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a second region.

[0007] An embodiment of the present disclosure is a method for manufacturing a semiconductor device, including the steps of stacking a second substrate having a second circuit on a first substrate having a first circuit; measuring a first in-plane distribution of misalignment between the first substrate and the second substrate; determining, based on the measured first distribution, a plurality of first positions on the second substrate at which to form a plurality of first contact holes that penetrate the second substrate and connect to the first circuit; forming the plurality of first contact holes at the plurality of first positions on the second substrate; and forming a plurality of first bridge wirings that electrically connect the first circuit and the second circuit via the plurality of first contact holes. [Effects of the Invention]

[0008] The disclosed technology allows for miniaturization. [Brief explanation of the drawings]

[0009] [Figure 1] 1A and 1B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 2] 2A to 2D are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4]FIG. 4 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5(A) to 5(C) are plan views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6(A) to 6(C) are plan views showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7A to 7D are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8(A) to 8(C) are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 9A and 9B are plan views of a semiconductor device according to a first modification of the first embodiment. [Figure 10] FIG. 10 is a plan view of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a circuit diagram of a pixel according to the second embodiment. [Figure 12] FIG. 12 is an enlarged view of the connection portion 42 in the second embodiment. [Figure 13] FIG. 13 is a plan view of the semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a memory cell according to the third embodiment. [Figure 15] 15(A) to 15(C) are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 16] 16A to 16C are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a block diagram of a semiconductor device according to a first modification of the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a semiconductor device according to a first modification of the third embodiment. [Figure 19] FIG. 19 is a schematic diagram of a semiconductor device according to a first modification of the third embodiment. [Figure 20]20(A) to 20(C) are cross-sectional views showing a method for manufacturing a semiconductor device according to Modification 1 of the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing another example of a semiconductor device according to the first modification of the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view of a semiconductor device according to Modification 2 of the third embodiment. [Figure 23] FIG. 23 is a schematic diagram of a semiconductor device according to Modification 2 of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0011] In this embodiment, a via-after method or via-last method is used, in which TSVs are formed after wafers or chips are bonded together. Instead of using a reticle to form the TSVs, a direct exposure method such as EB (Electron Beam) exposure is used to form the TSVs in accordance with the wiring pattern. This allows the TSVs to be formed in accordance with the wiring pattern even if the wafer or chip is distorted. Therefore, the TSVs and wiring patterns do not need to be large, allowing for the miniaturization of semiconductor devices.

[0012] (First embodiment) 1(A) to 2(D) are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 3 to 6(B) are plan views showing a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 1(A), a circuit 12B is formed on the upper surface of a substrate 10B. In the next step, as shown in FIG. 1(B), the lower surface of the substrate 10B is polished or ground to thin the substrate 10B.

[0013] As shown in FIG. 2(A), a circuit 12A is formed on the upper surface of the substrate 10A. In the next step, as shown in FIG. 2(B), an insulating film 14A is formed on the substrate 10A. This forms a first layer 15A having the substrate 10A and the insulating film 14A. The insulating film 14A is an inorganic insulating film such as a silicon oxide film or an organic insulating film. The upper surface of the first layer 15A is attached to the lower surface of the thinned substrate 10B in FIG. 1(B). The substrates 10A and 10B are, for example, semiconductor substrates such as silicon substrates or compound semiconductor substrates, or insulating substrates such as inorganic insulating substrates or organic insulating substrates.

[0014] Referring to FIG. 3, the bonding of wafers 11A and 11B will be described. In FIG. 3, alignment marks 20A and 20B are exaggerated. Wafer 11A is substrate 10A in FIG. 2A, and wafer 11B is substrate 10B in FIG. 1B. As shown in FIG. 3, wafer 11A has a plurality of regions 22A. Wafer 11B has a plurality of regions 22B. Regions 22A and 22B correspond to reticles. Circuit 12A in region 22A and circuit 12B in region 22B are patterned by photolithography using an exposure device such as a stepper. The patterns in the plurality of regions 22A are the same as each other, and the patterns in the plurality of regions 22B are the same as each other. Regions 22A and 22B have the same size. Alignment mark 20A is provided in region 22A. Alignment mark 20B is provided in region 22B. One or more alignment marks 20A are provided in one region 22A, and one or more alignment marks 20B are provided in one region 22B.

[0015] Alignment marks 20A and 20B are used within the wafer surface to measure the distribution of misalignment between wafers 11A and 11B. Because wafer 11B is thinned to a thickness of about several μm, alignment mark 20A is detected using reflected visible or infrared light. If the shape of alignment mark 20A is unclear, image processing may be performed.

[0016] As shown in FIG. 4, misalignment 21A is the misalignment of alignment mark 20A relative to alignment mark 20B. The magnitude and direction of misalignment 21A differ between substrates 10A and 10B. This is due to distortion between substrates 10A and 10B. Therefore, the distribution of misalignment 21A within the wafer surface is measured. Misalignment 21B represents the misalignment in locations where alignment marks 20A and 20B are not provided. Misalignment 21B can be estimated from misalignment 21A.

[0017] Figures 5(A) to 5(C) show areas where the misalignment is small, and Figures 6(A) to 6(C) show areas where the misalignment is large. As shown in Figures 5(A) and 6(A), wiring pattern 13A is provided on substrate 10A, and wiring pattern 13B is provided on substrate 10B. In Figure 5(A), alignment mark 20A almost overlaps alignment mark 20B, and the positions of wiring patterns 13A and 13B are also nearly as designed. In Figure 6(A), alignment mark 20A is significantly misaligned from alignment mark 20B, and the positions of wiring patterns 13A and 13B are significantly misaligned from the design.

[0018] As shown in FIGS. 5B and 6B, the position where the TSV 16B is formed is determined. The position of the TSV 16B is determined so that the TSV 16B overlaps the pad pattern of the wiring pattern 13A. The position of the TSV 16B is determined based on the distribution of the misalignment 21A within the wafer surface in FIG. 4. For example, based on the distribution of the misalignment 21A, the misalignment 21B may be estimated using deep learning or a fixed algorithm, and the position of the TSV 16B may be determined. Based on the distribution of the misalignment 21A, the position of the TSV 16B may be determined directly using deep learning or a fixed algorithm. Since the via 17B can be aligned with the wiring pattern 13B using a conventional stepper, there is almost no misalignment of the via 17B with respect to the wiring pattern 13B.

[0019] As shown in FIGS. 5(C) and 6(C), the planar shape of the bridge wiring 18B connecting the TSV 16B and the via 17B is determined. In addition to the planar shape, the position where the bridge wiring 18B is formed may also be determined. The planar shape of the bridge wiring 18B is determined so that it overlaps with the TSV 16B and the via 17B. The planar shape of the bridge wiring 18B is determined based on the positions of the TSV 16B and the via 17B in FIGS. 5(B) and 6(B). For example, the planar shape of the bridge wiring 18B may be determined using deep learning or a fixed algorithm based on the positions of the TSV 16B and the via 17B so as not to deviate from the design rules.

[0020] In a subsequent process, as shown in FIG. 2(C), an insulating film 14B is formed on the substrate 10B. This forms a second layer 15B having the substrate 10B and the insulating film 14B. TSVs 16B are formed at the positions of the TSVs 16B determined in FIGS. 5(B) and 6(B). As shown in FIG. 2(D), after vias 17B are formed, bridge wiring 18B having the planar shape determined in FIGS. 5(C) and 6(C) is formed.

[0021] 2(C) and 2(D) will be described in detail. FIGS. 7(A) to 8(C) are cross-sectional views showing a method for manufacturing a semiconductor device in the first embodiment. As shown in FIG. 7(A), a wiring pattern 13A is provided on a substrate 10A. An insulating film 14A is provided on the substrate 10A so as to cover the wiring pattern 13A. A substrate 10B is attached on the insulating film 14A. A wiring pattern 13B is provided on the substrate 10B. An insulating film 14B is provided on the substrate 10B so as to cover the wiring pattern 13B. A resist 30 is applied on the insulating film 14B.

[0022] In the next step, as shown in FIG. 7B, an opening 30A is formed in the resist 30 at the position of the TSV 16B determined in FIGS. 5B and 6B. An opening 30B is formed in the resist 30 at the position of the via 17B. The openings 30A and 30B are formed by exposing and developing the resist 30. For example, EB direct exposure is used to expose the resist 30.

[0023] 7C, the insulating film 14B, the substrate 10B, and the insulating film 14A are etched using the resist 30 as a mask to form a TSV 16B. Also, the insulating film 14B is etched using the resist 30 as a mask to form a via 17B.

[0024] In the next step, as shown in FIG. 7D, the resist 30 is removed. A resist 31 is applied to the inside of the TSV 16B and the via 17B and on the insulating film 14B. An opening 31A corresponding to the planar shape of the bridge wiring 18B determined in FIGS. 5C and 6C is formed in the resist 31. The opening 31A is formed by exposing and developing the resist 31. For example, EB direct exposure is used to expose the resist 31.

[0025] 8(A), in the next step, a portion of the upper part of the insulating film 14B is etched using a resist 31 as a mask to form a recess 19B. The insulating film 14B may be formed by stacking two insulating films, and the upper insulating film may be selectively etched relative to the lower insulating film.

[0026] In the next step, as shown in FIG. 8(B), the resist 31 is removed. A metal layer 32 is formed in the TSVs 16B, vias 17B, and recesses 19B, and on the insulating film 14B. In the next step, as shown in FIG. 8(C), the metal layer 32 on the insulating film 14B is polished to form the bridge wiring 18B embedded in the insulating film 14B. In this way, the semiconductor device 100 of FIG. 2(D) is completed. In this way, the bridge wiring 18B is formed using the damascene method. The bridge wiring 18B may also be formed using a method other than the damascene method.

[0027] (Modification 1 of the first embodiment) 9(A) and 9(B) are plan views of a semiconductor device according to Modification 1 of the first embodiment. As shown in FIGS. 9(A) and 9(B), the planar shape of the bridge wiring 18B is made large. This allows the bridge wiring 18B to connect the wiring patterns 13A and 13B via the TSV 16B and the via 17B, even if the position of the TSV 16B relative to the via 17B differs between FIGS. 9(A) and 9(B).

[0028] In the first modification of the first embodiment, the pattern of the bridge wiring 18B can be formed using a reticle, so that the exposure time can be reduced.

[0029] According to the first embodiment and its modifications, as shown in FIG. 2(B), a substrate 10B (second substrate) provided with a circuit 12B (second circuit) is stacked on a substrate 10A (first substrate) provided with a circuit 12A (first circuit). As shown in FIGS. 2 and 3, a first in-plane distribution of misalignment between the substrates 10A and 10B is measured. As shown in FIGS. 5(B) and 6(B), based on the measured first distribution, a plurality of first positions on the substrate 10B are determined for forming a plurality of TSVs 16B (a plurality of first contact holes) that penetrate the substrate 10B and connect to the circuit 12A. As shown in FIG. 2(C), a plurality of bridge wirings 18B (a plurality of first bridge wirings) are formed that electrically connect the circuits 12A and 12B via the plurality of TSVs 16B. 6(A) and 5(6), even if the substrate 10A is misaligned with the substrate 10B within the wafer surface, the size of the TSV 16B that can electrically connect the circuits 12A and 12B can be reduced, thereby enabling the semiconductor device 100 to be miniaturized.

[0030] As shown in FIGS. 5(C) and 6(C) of the first embodiment, the planar shapes of the plurality of bridge wirings 18B are determined based on the measured first distribution. In FIG. 2(C), the plurality of bridge wirings 18B having the determined planar shapes are formed. This allows the bridge wirings 18B to be smaller than when the bridge wirings 18B have the same planar shape, as shown in FIGS. 9(A) and 9(B) of Modification 1 of the first embodiment. This allows the semiconductor device 100 to be miniaturized.

[0031] As shown in FIG. 7B, an opening 30A is formed in the resist 30 using EB direct exposure. As shown in FIG. 7C, the opening 30A is used to form a TSV 16B. Furthermore, as shown in FIG. 7D, an opening 31A is formed in the resist 31 using EB direct exposure. As shown in FIGS. 8A to 8C, the opening 31A is used to form a bridge wiring 18B. In this manner, by using EB direct exposure, the TSV 16B and the bridge wiring 18B can be formed corresponding to the distortion between the substrates 10A and 10B. In addition to EB direct exposure, direct exposure methods using laser light, deflected ion beams, etc. may also be used to expose the resists 30 and 31. Furthermore, a liquid such as an acid that crosslinks or decomposes the resists 30 and 31 is charged as nanoparticles with a diameter of, for example, 1 nm to 10 nm. The openings in the resists 30 and 31 may also be formed using an inkjet method in which the charged nanoparticles are accelerated by an electric field to form a pattern.

[0032] In the first embodiment and its modifications, an example in which wafer 11B is stacked on wafer 11A has been described, but chips may also be stacked on chips. When wafers 11A and 11B are stacked, misalignment is likely to become large within the wafer surface. For example, when wafers 11A and 11B with a diameter of 300 mm are stacked, alignment accuracy of 100 nm or less is required across the entire wafer surface. Therefore, it is preferable to form TSVs 16B and bridge wiring 18B based on the distribution of misalignment within the surface.

[0033] (Second embodiment) The second embodiment is an example of a CMOS (Complementary Metal Oxide Semiconductor) image sensor. FIG. 10 is a plan view of a semiconductor device according to the second embodiment. The thickness direction of a substrate 10B is defined as the Z direction, and the side directions of the substrate 10B are defined as the X and Y directions. As shown in FIG. 10, in a semiconductor device 102 according to the second embodiment, a circuit 12B includes a plurality of pixels 40 and connection portions 41 and 42. The plurality of pixels 40 are arranged in a matrix on the substrate 10B in the X and Y directions. The plurality of pixels 40 are periodically arranged in the X direction with a constant period Px and periodically arranged in the Y direction with a constant period Py. The vertical signal line L1 is electrically connected to the pixels 40 arranged in the Y direction and extends in the Y direction. The horizontal signal line L2 is electrically connected to the pixels 40 arranged in the X direction and extends in the X direction. The connection portions 41 and 42 are provided on the periphery of the substrate 10B.

[0034] The vertical signal line L1 is electrically connected to the circuit 12A at a connection portion 41. The horizontal signal line L2 is electrically connected to the circuit 12A (see FIG. 2(D)) at a connection portion 42. The circuit 12A is, for example, an image processing circuit.

[0035] 11 is a circuit diagram of a pixel according to the second embodiment. A pixel 40 includes a photodiode PD and transistors Q1 to Q4. The photodiode PD is connected in the reverse direction between ground and the source of the transistor Q1. The transistor Q1 is a transfer gate, and the gate of the transistor Q1 is electrically connected to the horizontal readout line L2B. The drain of the transistor Q1 is electrically connected to the gate of the transistor Q2. The transistor Q2 is an amplifier transistor. The source of the transistor Q2 is electrically connected to the source of the transistor Q4. The drain of the transistor Q2 is connected to the power supply voltage VDD.

[0036] The transistor Q3 is a reset transistor. The source of the transistor Q3 is electrically connected to the gate of the transistor Q2. The drain of the transistor Q3 is electrically connected to the power supply voltage VDD. The gate of the transistor Q3 is electrically connected to the reset line L2C. The transistor Q4 is a select transistor. The drain of the transistor Q4 is electrically connected to the vertical signal line L1. The gate of the transistor Q4 is electrically connected to the horizontal selection line L2A. The horizontal signal line L2 in FIG. 10 includes the horizontal selection line L2A, the horizontal readout line L2B, and the reset line L2C.

[0037] The circuit 12A selects one vertical signal line L1 from the multiple vertical signal lines L1, selects one horizontal signal line L2 from the multiple horizontal signal lines L2, and reads out a signal from the selected pixel 40. A plurality of photodiodes PD and transistors Q1 may be provided in one pixel 40 so as to receive light of different wavelengths.

[0038] 12 is an enlarged view of a connection portion 42 in the second embodiment. As shown in FIG. 12, the connection portion 42 includes wiring patterns 13A and 13B, a TSV 16B, a via 17B, and a bridge wiring 18B. The wiring pattern 13B is a vertical signal line L1. The period of the wiring pattern 13B in the X direction is Px. The vias 17B at the ends of the wiring pattern 13B are provided alternately in the Y direction. As a result, the period of the vias 17B in the X direction is 2×Px.

[0039] The substrate 10A is distorted relative to the substrate 10B. As a result, the position of the wiring pattern 13A relative to the wiring pattern 13B differs between regions 42A and 42B in the connection portion 42. Therefore, as shown in FIGS. 5B and 6B, the position of the TSV 16B is determined depending on the misalignment between the wiring patterns 13A and 13B. As shown in FIGS. 7B and 7C, the TSV 16B is formed at the determined position. As a result, as shown in FIG. 12, the positional relationship 43A between the wiring pattern 13B and the TSV 16B in the region 42A differs from the positional relationship 43B between the wiring pattern 13B and the TSV 16B in the region 42B. Therefore, the TSV 16B can be aligned with the wiring pattern 13A in the regions 42A and 42B.

[0040] 5(C) and 6(C), the planar shape of the bridge wiring 18B is determined depending on the misalignment between the wiring patterns 13A and 13B. As shown in FIGS. 7(D) to 8(C), the bridge wiring 18B is formed with the determined planar shape. As a result, as shown in FIG. 12, the planar shape of the bridge wiring 18B in the region 42A differs from the planar shape of the bridge wiring 18B in the region 42B. Therefore, the bridge wiring 18B can be aligned with the TSV 16B in the regions 42A and 42B.

[0041] It is conceivable to enlarge the pads and TSVs 16B of the wiring pattern 13B to accommodate misalignment between the wiring patterns 13A and 13B. However, this would result in an increase in the size of the semiconductor device 102. Furthermore, the parasitic capacitance of the wiring would increase, reducing the speed at which the image processing circuit reads data from the pixels 40. In the second embodiment, the pads and TSVs 16B of the wiring pattern 13B can be made smaller. This allows the semiconductor device 102 to be miniaturized. Furthermore, the speed at which data is read from the pixels 40 can be improved.

[0042] In the second embodiment, a CMOS image sensor has been described as an example, but the sensor provided on the second layer 15B may be a sensor other than a photodiode.

[0043] (Third embodiment) The third embodiment is an example of a DRAM (Dynamic Random Access Memory). FIG. 13 is a plan view of a semiconductor device according to the third embodiment. The thickness direction of a substrate 10B is defined as the Z direction, and the side directions of the substrate 10B are defined as the X and Y directions. As shown in FIG. 13, in a semiconductor device 104 according to the third embodiment, a circuit 12B includes a plurality of memory cells 44 and connection portions 45 and 46. The memory cells 44 are arranged in a matrix in the X and Y directions on the substrate 10B. The memory cells 44 are periodically arranged in the X direction with a constant period Px and periodically arranged in the Y direction with a constant period Py. The bit lines BL are electrically connected to the memory cells 44 arranged in the Y direction and extend in the Y direction. The word lines WL are electrically connected to the memory cells 44 arranged in the X direction and extend in the X direction. The connection portions 45 and 46 are provided on the periphery of the substrate 10B.

[0044] At connection portions 45 and 46, the wiring pattern 13B is connected to the bit line BL and the word line WL, respectively. The wiring patterns 13A and 13B are electrically connected via a TSV 16B, a bridge wiring 18B, and a via 17B. As a result, the bit line BL and the word line WL are electrically connected to a circuit 12A (see FIG. 2(D)) provided on the substrate 10A. The circuit 12A is, for example, a peripheral circuit.

[0045] 14 is a cross-sectional view of a memory cell according to the third embodiment. As shown in FIG. 14, a transistor 23 and a word line WL are provided on a substrate 10B. The substrate 10B is, for example, a silicon substrate. The transistor 23 includes a source / drain 24, a channel 25, and a gate insulating film 26. The channel 25 is provided between the source / drain 24. The word line WL is embedded in the substrate 10B and is provided below the channel 25 with the gate insulating film 26 sandwiched therebetween. The word line WL functions as a gate. The word line WL extends in the X direction.

[0046] The capacitor 27, bit line BL, and wiring L3 are provided in the insulating film 14B. The capacitor 27 includes a cell plate 28A, a storage electrode 28B, and a dielectric film 29. The dielectric film 29 is provided between the cell plate 28A and the storage electrode 28B. The bit line BL extends in the Y direction. One of the source / drains 24 is electrically connected to the storage electrode 28B via wiring L3. The other of the source / drains 24 is electrically connected to the bit line BL. The insulating film 14B may be a two-layer structure consisting of an insulating film below the capacitor 27 and an insulating film surrounding the capacitor 27.

[0047] 15(A) to 16(C) are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment. As shown in FIG. 15(A), word lines WL are embedded in a substrate 10B. Bit lines BL are provided in an insulating film 14B. The bit lines BL are formed by wiring patterns 13B. The memory cells 44 of FIG. 14 are formed in the substrate 10B. The substrate 10B is, for example, a wafer 11A.

[0048] 15(B), in the next step, a support substrate 34 is attached to the upper surface of the insulating film 14B using an adhesive 33. The support substrate 34 is, for example, a wafer, and the adhesive 33 is, for example, an organic insulating film.

[0049] 15(C), the lower surface of the substrate 10B is polished, thereby thinning the substrate 10B. The thickness of the substrate 10B is, for example, 5 μm.

[0050] In the next step, as shown in FIG. 16(A), a circuit 12A is formed on a substrate 10A. A wiring pattern 13A is formed on the substrate 10A. The wiring pattern 13A is electrically connected to the circuit 12A. An insulating film 14A is formed on the substrate 10B so as to cover the wiring pattern 13A. The lower surface of the substrate 10B is attached to the upper surface of the insulating film 14A. The support substrate 34 is removed from the insulating film 14B. The adhesive 33 is removed from the insulating film 14B. As a result, a second layer 15B having the substrate 10B and the insulating film 14B is stacked on a first layer 15A having the substrate 10A and the insulating film 14A.

[0051] In the next step, the distribution of misalignment within the wafer surface of the substrates 10A and 10B is measured, as shown in Figures 3 and 4. The position of the TSV 16B is determined based on the distribution of misalignment, as shown in Figures 5(B) and 6(B). The pattern of the bridge wiring 18B is determined based on the distribution of misalignment, as shown in Figures 5(C) and 6(C).

[0052] 16B, in the next step, TSVs 16B are formed in the insulating film 14B, the substrate 10B, and the insulating film 14A at the positions determined in FIGS. 5B and 6B. Vias 17B are formed in the insulating film 14B.

[0053] 16(C), a recess 19B is formed in the insulating film 14B. A bridge wiring 18B is formed in the TSV 16B, the via 17B, and the recess 19B by, for example, a damascene method. In this way, the semiconductor device according to the third embodiment is manufactured.

[0054] 13, in the third embodiment, the bit lines BL are periodically arranged at a constant period Px in the X direction, and the word lines WL are periodically arranged at a constant period Py in the Y direction. The substrate 10A is distorted with respect to the substrate 10B. As a result, the position of the wiring pattern 13A relative to the wiring pattern 13B differs between regions 45A and 45B in the connection portion 45. The position of the wiring pattern 13A relative to the wiring pattern 13B differs between regions 46A and 46B in the connection portion 46.

[0055] Therefore, as shown in FIGS. 5B and 6B, the position of the TSV 16B is determined depending on the misalignment between the wiring patterns 13A and 13B. As shown in FIGS. 7B and 7C, the TSV 16B is formed at the determined position. As a result, as shown in FIG. 13, the positional relationship 47A between the wiring pattern 13B and the TSV 16B in the region 45A is different from the positional relationship 47B between the wiring pattern 13B and the TSV 16B in the region 45B. The positional relationship 47A between the wiring pattern 13B and the TSV 16B in the region 46A is different from the positional relationship 47B between the wiring pattern 13B and the TSV 16B in the region 46B. Therefore, the TSV 16B can be aligned with the wiring pattern 13A in the regions 45A, 45B, 46A, and 46B.

[0056] 5(C) and 6(C), the planar shape of the bridge wiring 18B is determined depending on the misalignment between the wiring patterns 13A and 13B. As shown in FIGS. 7(D) to 8(C), the bridge wiring 18B is formed with the determined planar shape. As a result, as shown in FIG. 13, the planar shape of the bridge wiring 18B in the region 45A is different from the planar shape of the bridge wiring 18B in the region 45B. The planar shape of the bridge wiring 18B in the region 46A is different from the planar shape of the bridge wiring 18B in the region 46B. Therefore, the bridge wiring 18B can overlap the TSV 16B in the regions 45A, 45B, 46A, and 46B.

[0057] (Modification 1 of the third embodiment) Modification 1 of the third embodiment is an example of a DRAM in which three or more layers are stacked. Fig. 17 is a block diagram of a semiconductor device according to Modification 1 of the third embodiment. As shown in Fig. 17, a semiconductor device 105 having a DRAM includes a memory cell array 50 and a peripheral circuit 51.

[0058] The memory cell array 50 has banks 50B to 50E. In each of the banks 50B to 50E, a plurality of memory cells 44 are arranged in a matrix. The memory cells 44 are, for example, the memory cells shown in FIG. 15. The memory cells 44 are connected to word lines WL and bit lines BL as shown in FIGS. 13 and 14.

[0059] The peripheral circuit 51 includes a read circuit 52, a column decoder 53, an input / output buffer 54, a row decoder 55, and an address buffer 56. Based on input address information, the address buffer 56 outputs a row address to the row decoder 55 and a column address to the column decoder 53. The row decoder 55 selects a word line WL corresponding to the row address. The column decoder 53 selects a bit line BL corresponding to the column address. The read circuit 52 includes, for example, a sense amplifier. When reading data, the read circuit 52 reads data from the selected memory cell 44 via the bit line BL. The input / output buffer 54 buffers the read data and sequentially outputs it to an external circuit. When writing data, the input / output buffer 54 sequentially acquires data from the external circuit. The acquired data is written to the selected memory cell 44.

[0060] 18 is a cross-sectional view of a semiconductor device according to Modification 1 of the third embodiment. As shown in FIG. 18, in a semiconductor device 105 of the third embodiment, first to fifth layers 15A to 15E are stacked. The second to fifth layers 15B to 15E include substrates 10B to 10E and insulating films 14B to 14D provided on the substrates 10B to 10E, respectively. Word lines WLB to WLE are buried in the substrates 10B to 10E, respectively. Bit lines BLB to BLE are provided in the insulating films 14B to 14E, respectively. The bit lines BLB to BLE include wiring patterns 13B to 13E, respectively.

[0061] The wiring pattern 13B on the second layer 15B is electrically connected to the wiring pattern 13A on the first layer 15A via a bridge wiring 18B and a TSV 16B. The wiring pattern 13C on the third layer 15C is electrically connected to the bridge wiring 18B on the second layer 15B via a bridge wiring 18C and a TSV 16C. The wiring pattern 13D on the fourth layer 15D is electrically connected to the bridge wiring 18C on the third layer 15C via a bridge wiring 18D and a TSV 16D. The wiring pattern 13E on the fifth layer 15E is electrically connected to the bridge wiring 18D on the fourth layer 15D via a bridge wiring 18E and a TSV 16E.

[0062] 19 is a schematic diagram of a semiconductor device according to Modification 1 of the third embodiment. As shown in FIG. 19, a peripheral circuit 51 is provided in a first layer 15A. Banks 50B to 50E are provided in second to fifth layers 15B to 15E, respectively. Each of the banks 50B to 50E has a plurality of memory cells 44. Each memory cell 44 has a transistor 23 and a capacitor 27. The memory cells 44 of the banks 50B to 50E are connected to bit lines BLB to BLE, respectively, and word lines WLB to WLE, respectively. The bit lines BLB to BLE are connected to a bit line BL. The bit line BL is connected to a read circuit 52 of the peripheral circuit 51.

[0063] 20(A) to 20(C) are cross-sectional views showing a method for manufacturing a semiconductor device according to Modification 1 of the third embodiment. As shown in FIG. 20(A), in a step subsequent to FIG. 2(C) of the first embodiment, a substrate 10C is attached onto an insulating film 14B. A circuit 12C is provided on the substrate 10C. In the next step, similar to FIGS. 3 and 4, the alignment distribution between the substrates 10B and 10C is measured. In the next step, similar to FIGS. 5(B) and 6(B), the position of the TSV 16C is determined based on the measured distribution of misalignment. In the next step, similar to FIGS. 5(C) and 6(C), the planar shape of the bridge wiring 18C is determined based on the measured distribution of misalignment.

[0064] In the next step, as shown in FIG. 20(B), an insulating film 14C is formed on the substrate 10C. This forms a third layer 15C having the substrate 10C and the insulating film 14C. The TSVs 16C are formed at the determined positions of the TSVs 16C. As shown in FIG. 19(C), after forming vias 17C, bridge wiring 18C having the determined planar shape is formed. This results in the third layer 15C being stacked on the second layer 15B. Similarly, the fourth layer 15D is stacked on the third layer 15C, and the fifth layer 15E is stacked on the fourth layer 15D. In this manner, the semiconductor device 105 according to the first modification of the third embodiment is manufactured.

[0065] 21 is a cross-sectional view showing another example of a semiconductor device according to Modification 1 of the third embodiment. As shown in FIG. 21, the first layer 15A to the fifth layer 15E are misaligned. Even in this case, the positions of the TSVs 16B to 16E are determined according to the misalignment, and the patterns of the bridge wirings 18B to 18E are determined. This allows electrical connection between the first layer 15A to the fifth layer 15E without increasing the size of the positions of the TSVs 16B to 16E. This allows the semiconductor device 105 to be miniaturized.

[0066] (Modification 2 of the third embodiment) Fig. 22 is a cross-sectional view of a semiconductor device according to Modification 2 of the third embodiment. Fig. 23 is a schematic diagram of a semiconductor device according to Modification 2 of the third embodiment. As shown in Figs. 22 and 23, in semiconductor device 106 according to Modification 2 of the third embodiment, bit line BLB is connected to read circuit 52 at its -Y end and to bit line BLC at its +Y end. Bit line BLC is connected to bit line BLB at its +Y end and to bit line BLD at its -Y end. Bit line BLD is connected to bit line BLC at its -Y end and to bit line BLE at its +Y end.

[0067] For example, 500 to 1000 memory cells 44 are connected to one bit line BL. The layout efficiency improves when the number of memory cells 44 connected to one bit line BL is large. However, as the bit line BL becomes longer and the resistance of the bit line BL increases, the operating speed decreases.

[0068] As in the first modification of the third embodiment, the bit lines BLB to BLE may branch off from the bit line BL. In this case, even if the bit lines BLB to BLE are made of a material with high resistivity, the resistance between the end memory cells 44 and the read circuit 52 does not increase. This improves the operating speed.

[0069] The bit lines BLB to BLE may be connected in series as in Modification 2 of the third embodiment. In this case, too, the bit lines BLB to BLE may be formed using a material with low resistivity, thereby preventing a decrease in operating speed.

[0070] In the third embodiment and its modifications, an example of a DRAM has been described as a semiconductor device, but the semiconductor device may also be a storage circuit such as an SRAM (Static RAM) or a nonvolatile memory.

[0071] The performance of transistors in high-speed logic circuits deteriorates when exposed to high temperatures. Meanwhile, some steps in the manufacturing process of memory cells 44 are performed at high temperatures. For this reason, it is difficult to form high-speed logic circuits and memory cells on the same substrate. In the second and third embodiments, high-speed logic circuits can be used as memory circuits.

[0072] 12 and 13, the circuit 12B has a plurality of wiring patterns 13B (a plurality of first wiring patterns) periodically arranged with a period of 2×Px in FIG. 12 and a period of Px and Py (a first period) in FIG. 13. On the other hand, in FIG. 12, the positional relationship between the plurality of TSVs 16B and the plurality of wiring patterns 13B in the region 42A (first region) is different from the positional relationship between the plurality of TSVs 16B and the plurality of wiring patterns 13B in the region 42B (second region). In FIG. 13, the positional relationship between the plurality of TSVs 16B and the plurality of wiring patterns 13B in the region 45A (and 46A) is different from the positional relationship between the plurality of TSVs 16B and the plurality of wiring patterns 13B in the region 45B (and 46B). This allows the size of the TSV 16B that can electrically connect the wiring patterns 13A and 13B to be reduced even if there is a misalignment of the wiring pattern 13A with respect to the wiring pattern 13B within the plane, thereby allowing the semiconductor devices 102, 104 to 106 to be miniaturized.

[0073] Note that the wiring patterns 13B being arranged periodically does not necessarily have to be arranged periodically at a strict interval, and allow for variations within the manufacturing tolerances. For example, the difference between the maximum and minimum values ​​of the periods of adjacent wiring patterns 13B may be, for example, 0.2 times or less, or even 0.15 times, the design period (e.g., the average period). The variation in period depends on the processing margin. The greater the difference between the maximum and minimum values, the greater the possibility that the minimum processing dimension limit may be exceeded on the minimum value side, resulting in a pattern short circuit or pattern loss, resulting in a defect. Furthermore, the difference in the positional relationship between the TSVs 16B and the wiring patterns 13B in the first and second regions may be greater than the manufacturing tolerance. For example, the difference in the positional relationship between the TSVs 16B and the wiring patterns 13B in the first and second regions may be 0.2 times or more the average diameter of the TSVs 16B, and in some cases, may be 0.5 times or more.

[0074] Because the vias 17B are formed using, for example, a reticle, the positions within the wiring pattern 13B where the bridge wirings 18B are connected to the wiring patterns 13B in the region 42A (45A and 46A; first region) are the same as the positions within the wiring pattern 13B where the bridge wirings 18B are connected to the wiring patterns 13B in the region 42B (45B and 46B; second region). The positions within the wiring pattern 13B where the bridge wirings 18B are connected to the wiring patterns 13B (i.e., the positions of the vias 17B) do not have to be exactly the same in the first and second regions; differences within the order of manufacturing error are allowed. For example, the positions of the vias 17B within the wiring pattern 13B in the first and second regions may be, for example, 0.2 times or less, or 0.15 times or less, the average diameter of the vias 17B.

[0075] 12 and 13, the planar shape of the plurality of bridge wirings 18B in the region 42A (45A and 46A; first region) is different from the planar shape of the plurality of bridge wirings 18B in the region 42B (45B and 46B: second region). This allows the bridge wirings 18B to be overlapped with the TSVs 16B even if the positional relationship between the TSVs 16B and the wiring pattern 13B is different between the first region and the second region. The planar shapes of the bridge wirings 18B in the first region and the second region may be different by an amount equal to or greater than a manufacturing error. For example, when the bridge wirings 18B in the first region and the second region are overlapped, the maximum difference in the periphery of the planar shape is, for example, 0.2 times or more the average diameter of the TSVs 16B, and may be 0.25 times or more.

[0076] In the second embodiment, as shown in FIG. 10, the circuit 12B has a plurality of pixels 40 (a plurality of unit circuits) arranged in a matrix. As shown in FIG. 12, the period Px of the wiring pattern 13B is twice the period at which the pixels 40 are arranged. In the third embodiment, as shown in FIG. 13, the circuit 12B has a plurality of memory cells 44 (a plurality of unit circuits) arranged in a matrix. The period Px of the wiring pattern 13B is one time the period at which the memory cells 44 are arranged. In this way, in the circuit 12B in which the unit circuits are arranged in a matrix, the period of the wiring pattern 13B can be an integer multiple of the period of the unit circuits.

[0077] 10 and 13, each of the wiring patterns 13B is connected to the pixels 40 or memory cells 44 arranged in rows or columns.

[0078] In the second and third embodiments, an example has been described in which the circuit 12B is connected to the circuit 12A via the bridge wiring 18B and the TSV 16B at the periphery of the circuit 12B. The circuit 12B may be connected to the circuit 12A via the bridge wiring 18B and the TSV 16B at the center of the circuit 12B. Each pixel 40 or memory cell 44 may be connected to the circuit 12A via the bridge wiring 18B and the TSV 16B.

[0079] As shown in FIG. 20(A), a substrate 10C (third substrate) provided with a circuit 12C (third circuit) is stacked on a substrate 10B. As shown in FIGS. 3 and 4, a second distribution of in-plane misalignment between the substrates 10B and 10C is measured. As shown in FIGS. 5(B) and 6(B), based on the measured second distribution, a plurality of second positions on the substrate 10C are determined where a plurality of TSVs (a plurality of second contact holes) that penetrate the substrate 10C and connect to the circuit 12C are formed. As shown in FIG. 20(B), a plurality of TSVs 16C are formed at a plurality of second positions on the substrate 10C. As shown in FIG. 20(C), a plurality of bridge wirings 18C (a plurality of second bridge wirings) that electrically connect the circuits 12B and 13C are formed via the TSVs 16C. This allows a third layer 15C to be stacked on the second layer 15B. In this manner, three or more substrates 10A to 10C can also be stacked. Stacking a plurality of banks 50B to 50C can increase memory capacity.

[0080] 12 and 13, the plurality of wiring patterns 13C (the plurality of second wiring patterns) are periodically arranged at a constant second period. Meanwhile, the positional relationship between the plurality of TSVs 16C and the plurality of wiring patterns 13C in the third region is different from the positional relationship between the plurality of TSVs 16C and the plurality of wiring patterns 13C in the fourth region. This allows the size of the TSVs 16C that can electrically connect the wiring patterns 13B and 13C to be reduced even if there is a misalignment of the wiring pattern 13B with respect to the wiring pattern 13C within the plane. This allows the semiconductor device to be miniaturized.

[0081] In the first to third embodiments and their modifications, the substrates 10A to 10E are made of the same material. However, the material of at least one of the substrates 10A to 10E may be different from the material of the other substrates. For example, in the second embodiment, the circuit 12B on the second layer 15B may have a sensor using a compound semiconductor, and the circuit 12A on the first layer 15A may be a CMOS circuit. This allows a material optimal for sensing (e.g., a compound semiconductor) to be selected for the substrate 10B on the second layer 15B, and a material optimal for processing sensed signals (e.g., silicon) to be selected for the substrate 10B on the first layer 15A. The substrate 10A may also be an interposer, such as an insulating substrate. In this way, when the materials of the substrates 10A and 10B are different, the difference in thermal expansion coefficients will cause significant distortion between the substrates 10A and 10B. In the second embodiment, the circuits 12A and 12B can be electrically connected even when the distortion between the substrates 10A and 10B is significant.

[0082] Although the present disclosure has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present disclosure, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0083] 10A, 10B, 10C, 10D, 10E board 11A, 11B wafers 12A, 12B, 12C circuits 13A, 13B, 13C, 13D, 13E wiring patterns 14A, 14B, 14C, 14D, 14E Insulating film 15A 1st layer 15B 2nd layer 15C 3rd layer 15D 4th layer 15E 5th layer 17B, ​​17C vias 18B, 18C, 18D, 18E Bridge wiring 20A, 20B marks 22A, 22B area 23 Transistor 27 Capacitor 40 pixels 44 memory cells

Claims

1. a first substrate on which a first circuit is provided; a second substrate laminated on the first substrate and provided with a second circuit having a plurality of first wiring patterns periodically arranged at a constant first period; a plurality of first bridge wirings that electrically connect the first circuit and the plurality of first wiring patterns via a plurality of first contact holes that penetrate the second substrate; Equipped with A semiconductor device, wherein the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a first region is different from the positional relationship between the plurality of first contact holes and the plurality of first wiring patterns in a second region.

2. 2. The semiconductor device according to claim 1, wherein in the first region, positions within the first wiring pattern where the plurality of first bridge wirings are connected to the plurality of first wiring patterns respectively are the same as positions within the first wiring pattern where the plurality of first bridge wirings are connected to the plurality of first wiring patterns respectively in the second region.

3. 3 . The semiconductor device according to claim 1 , wherein a planar shape of the plurality of first bridge wirings in the first region is different from a planar shape of the plurality of first bridge wirings in the second region.

4. the second circuit has a plurality of unit circuits arranged in a matrix, 3. The semiconductor device according to claim 1, wherein the first period is an integer multiple of the period in which the plurality of unit circuits are arranged.

5. 5. The semiconductor device according to claim 4, wherein each of said plurality of first wiring patterns is connected to unit circuits arranged in rows or columns.

6. a third substrate laminated on the second substrate and provided with a third circuit having a plurality of second wiring patterns periodically arranged at a constant second period; a plurality of second bridge wirings that electrically connect the second circuit and the plurality of second wiring patterns via a plurality of second contact holes that penetrate the third substrate; The semiconductor device according to claim 1 or 2, comprising:

7. The semiconductor device according to claim 1 , wherein the first substrate and the second substrate are made of different materials.

8. a step of stacking a second substrate provided with a second circuit on a first substrate provided with a first circuit; measuring a first distribution of in-plane misalignment between the first substrate and the second substrate; determining a plurality of first positions on the second substrate at which a plurality of first contact holes that penetrate the second substrate and connect to the first circuit are to be formed, based on the measured first distribution; forming the first contact holes at the first locations in the second substrate; forming a plurality of first bridge wirings that electrically connect the first circuit and the second circuit through the plurality of first contact holes; A method for manufacturing a semiconductor device, comprising:

9. the second circuit has a plurality of wiring patterns periodically arranged at a constant period; a plurality of first bridge wirings electrically connect the first circuit and the plurality of wiring patterns via the plurality of first contact holes; 9. The method for manufacturing a semiconductor device according to claim 8, wherein a positional relationship between the first contact holes and the wiring patterns in the first region is different from a positional relationship between the first contact holes and the wiring patterns in the second region.

10. determining a planar shape of the plurality of first bridge wirings based on the measured first distribution; the step of forming the plurality of first bridge wirings includes forming the plurality of first bridge wirings having the determined planar shape; 10. The method for manufacturing a semiconductor device according to claim 8.

11. laminating a third substrate, on which a third circuit is provided, on the second substrate; measuring a second in-plane distribution of misalignment between the second substrate and the third substrate; determining a plurality of second positions on the third substrate at which a plurality of second contact holes that penetrate the third substrate and connect to the second circuit are to be formed, based on the measured second distribution; forming the second contact holes at the second locations in the third substrate; forming a plurality of second bridge wirings that electrically connect the second circuit and the third circuit through the plurality of second contact holes; The method for manufacturing a semiconductor device according to claim 8 or 9, comprising:

12. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the plurality of first contact holes uses an EB direct exposure method.

13. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the first substrate and the second substrate are wafers.

Images