Loop device

Abstract

A circuit device or the like capable of outputting an appropriate output voltage in a circuit that outputs an output voltage based on a power supply voltage. [Solution] The circuit device 100 includes a bias voltage generation circuit 210 that generates a first bias voltage VR1 and a second bias voltage VR2 based on a power supply voltage VPS, outputs the first bias voltage VR1 to a first bias node NR1, and outputs the second bias voltage VR2 to a second bias node NR2, a first follower circuit 251 that outputs a first output voltage VOUT1 that follows the first bias voltage VR1, a second follower circuit 252 that outputs a second output voltage VOUT2 that follows the second bias voltage VR2, and a first potential fixing circuit 231 that fixes the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises.

Description

[Technical Field]

[0001] The present invention relates to a circuit device and the like. [Background technology]

[0002] Patent Document 1 discloses a voltage regulation system including a voltage regulation means and a plurality of stages connected in parallel to the output of the voltage regulation means. The voltage regulation means generates a voltage using an amplifier circuit. The generated voltage is input to the gate of the source follower of each stage, and the source follower of each stage outputs an output voltage. In this way, the plurality of stages outputs a plurality of output voltages. These multiple output voltages are generated with respect to a ground voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-301087 Summary of the Invention [Problem to be solved by the invention]

[0004] In a circuit that generates an output voltage with a given potential difference from the power supply voltage, that is, that outputs an output voltage based on the power supply voltage, it is necessary to output an appropriate output voltage in response to changes in the power supply voltage when the power supply is started. Patent Document 1 outputs an output voltage based on the ground voltage, and does not describe a case where the output voltage is output based on the power supply voltage. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, the circuit device including: a bias voltage generation circuit that generates a first bias voltage and a second bias voltage based on the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage to a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; a second follower circuit that outputs the second output voltage that follows the second bias voltage to a second output node; and a first potential fixing circuit that fixes the potential of the first bias node to the potential of the power supply node when the power supply voltage rises.

[0006] Another aspect of the present disclosure relates to a circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, the circuit device including: a bias voltage generation circuit that generates a first bias voltage and a second bias voltage using the power supply voltage as a reference, outputs the first bias voltage to a first bias node, and outputs the second bias voltage as the second output voltage to a second output node that is a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; and a first potential fixing circuit that fixes the potential of the first bias node to the potential of the power supply node when the power supply voltage rises. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a first configuration example of a voltage generating circuit included in a circuit device. [Figure 2] 1 shows an example of the configuration of a circuit device including a voltage generating circuit and a subsequent circuit. [Figure 3] 10 shows a first detailed configuration example of a voltage generating circuit. [Figure 4] 10 shows a second detailed configuration example of a voltage generation circuit. [Figure 5] 10 shows example signal waveforms illustrating the operation of the second detailed configuration example of the voltage generating circuit. [Figure 6]10 is a configuration example of a comparative example. [Figure 7] 10 shows an example of a signal waveform in a comparative example. [Figure 8] 10 shows a first alternative configuration example of the first potential fixing circuit. [Figure 9] 10 shows another example of the configuration of the second reference voltage setting circuit. [Figure 10] 10 shows another example of the configuration of the second potential fixing circuit. [Figure 11] 10 shows a second alternative configuration example of the first potential fixing circuit. [Figure 12] 10 shows a first alternative configuration example of a bias voltage generating circuit. [Figure 13] 10 shows a second alternative configuration example of the bias voltage generating circuit. [Figure 14] 10 shows a second configuration example of a voltage generating circuit included in a circuit device. [Figure 15] 10 shows a more detailed configuration example of the second configuration example of the voltage generating circuit. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the content of the claims, and not all of the configurations described in the embodiments are necessarily essential components. Note that connection in the embodiments includes electrical connection. Electrical connection means a connection that allows the transmission of an electrical signal, voltage, or current, and includes a connection that allows the transmission of information by an electrical signal. The electrical connection may be a connection via a passive element, an active element, or the like.

[0009] 1. First configuration example 1 shows a first configuration example of a voltage generation circuit 200 included in the circuit device of this embodiment. The voltage generation circuit 200 includes a bias voltage generation circuit 210, a first potential clamp circuit 231, a second potential clamp circuit 232, a first follower circuit 251, and a second follower circuit 252. Note that the second potential clamp circuit 232 may be omitted. The circuit device may include only the voltage generation circuit 200, or may further include other circuits. The circuit device is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate.

[0010] The power supply node NPS is a node to which a power supply voltage VPS is supplied from the power supply. The ground node NGND is a node to which a ground voltage GND is supplied from the power supply. The power supply voltage VPS refers to a power supply voltage including transient voltage fluctuations, such as the power supply voltage before, during, and after power supply startup. The power supply voltage after the power supply has started up and stabilized is referred to as a given power supply voltage VBB. The power supply may be provided externally to the circuit device or may be built into the circuit device.

[0011] The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on a power supply voltage VPS, outputs the first bias voltage VR1 to a first bias node NR1, and outputs the second bias voltage VR2 to a second bias node NR2. Here, the power supply voltage VPS is assumed to be a given power supply voltage VBB. A voltage based on a given power supply voltage VBB refers to a voltage generated to have a given voltage difference from the given power supply voltage VBB. The first bias voltage VR1 and the second bias voltage VR2 are set so that a second output voltage VOUT2 (described below) is lower than the first output voltage VOUT1. For example, the second bias voltage VR2 is lower than the first bias voltage VR1.

[0012] The first follower circuit 251 outputs a first output voltage VOUT1 that follows the first bias voltage VR1 to a first output node NOUT1. That is, the first follower circuit 251 outputs a first output voltage VOUT1 that maintains a given voltage difference with respect to the first bias voltage VR1, or outputs a first output voltage VOUT1 that has the same voltage value as the first bias voltage VR1. The first follower circuit 251 is, for example, a source follower circuit as described in FIG. 3 etc., but is not limited to this and may be a voltage follower circuit or the like. A voltage follower circuit is a circuit in which the negative input terminal and output terminal of an operational amplifier are connected, with the positive input terminal of the operational amplifier being the input of the voltage follower circuit and the output terminal of the operational amplifier being the output of the voltage follower circuit.

[0013] The second follower circuit 252 outputs a second output voltage VOUT2 that follows the second bias voltage VR2 to a second output node NOUT2. That is, the second follower circuit 252 outputs a second output voltage VOUT2 that maintains a given voltage difference with respect to the second bias voltage VR2, or outputs a second output voltage VOUT2 that has the same voltage value as the second bias voltage VR2. The second follower circuit 252 is, for example, a source follower circuit as described in FIG. 3 etc., but is not limited to this and may be a voltage follower circuit or the like.

[0014] The first potential clamping circuit 231 clamps the potential of the first bias node NR1 to the potential of the power supply node NPS during the rise of the power supply voltage VPS. That is, when the power supply is started and the power supply voltage VPS is raised from near the ground voltage GND to a given power supply voltage VBB, the first potential clamping circuit 231 clamps the potential of the first bias node NR1 so that the first bias voltage VR1 is equal to the power supply voltage VPS during the rise. The rise of the power supply voltage VPS includes at least the period until the power supply voltage VPS reaches the given power supply voltage VBB. For example, as described with reference to FIG. 3 and other figures, the bias voltage generation circuit 210 is enabled and begins generating a bias voltage after the power supply voltage VPS reaches the given power supply voltage VBB. In this case, the rise of the power supply voltage VPS may be the period until the bias voltage generation circuit 210 is enabled.

[0015] The second potential clamping circuit 232 clamps the potential of the second bias node NR2 to the potential of the power supply node NPS when the power supply voltage VPS rises. That is, when the power supply is started and the power supply voltage VPS is raised from a low voltage such as near 0 V to a given power supply voltage VBB, the second potential clamping circuit 232 clamps the potential of the second bias node NR2 so that the second bias voltage VR2 and the power supply voltage VPS in the middle of rising are equal to each other.

[0016] According to this embodiment, when the power supply voltage VPS rises, the first bias voltage VR1 is fixed to the power supply voltage VPS, and the first output voltage VOUT1 that follows it is also fixed to the power supply voltage VPS. This reduces the impact on downstream circuits that use the first output voltage VOUT1. Possible impacts include malfunctions or failures of downstream circuits. Similarly, the second bias voltage VR2 is fixed to the power supply voltage VPS, and the second output voltage VOUT2 that follows it is also fixed to the power supply voltage VPS. This reduces the impact on downstream circuits that use the second output voltage VOUT2.

[0017] 2 shows an example of the configuration of a circuit device 100 including a voltage generating circuit 200 and a subsequent circuit 300. Here, a bridge circuit and its driver circuit will be described as an example of the circuit 300 that uses a first output voltage VOUT1 and a second output voltage VOUT2, but the circuit 300 is not limited to this. The circuit 300 includes a level shifter 310, a first pre-driver circuit 321, a second pre-driver circuit 322, and a driver circuit 330.

[0018] The driver circuit 330 is a bridge circuit. That is, the driver circuit 330 includes a high-side first drive transistor 331 connected between a power supply node NPS and a drive voltage output node, and a low-side second drive transistor 332 connected between the drive voltage output node and a ground node NGND. The first drive transistor 331 is a P-type MOS transistor, and the second drive transistor 332 is an N-type MOS transistor. The first drive transistor 331 and the second drive transistor 332 are alternately turned on and off to drive a load such as a motor. Note that, although an example in which the driver circuit 330 is a half-bridge circuit has been shown, the driver circuit 330 may also be an H-bridge circuit.

[0019] The level shifter 310 includes an inverter circuit INV, P-type MOS transistors TL1 to TL4, and N-type MOS transistors TL5 and TL6. The connections are as shown in the figure. The operation will be described below.

[0020] The level shifter 310 level-shifts a control signal HCK from a control circuit (not shown) and outputs the result as a signal LSQ. The control signal HCK controls the first drive transistor 331 of the driver circuit 330 to turn on or off. Assume that the power supply voltage VPS is a given power supply voltage VBB. The high level of the control signal HCK is a logic power supply voltage lower than the given power supply voltage VBB, and the low level is ground voltage GND. The high level of the signal LSQ is the given power supply voltage VBB, and the low level is a voltage higher than the second output voltage VOUT2 by approximately the threshold voltage of the P-type MOS transistor TL4. The second output voltage VOUT2 is, for example, a voltage lower than the first output voltage VOUT1 by approximately the threshold voltage of the P-type MOS transistor TL4. In this case, the low level of the signal LSQ is approximately the same as the first output voltage VOUT1.

[0021] The first pre-driver circuit 321 is configured with one or more stages of inverter circuits or the like, and drives the gate of the first drive transistor 331 of the driver circuit 330 by buffering the signal LSQ. A high-potential side power supply node of the first pre-driver circuit 321 is connected to the power supply node NPS, and a low-potential side power supply node is connected to the first output node NOUT1 of the voltage generation circuit 200.

[0022] The second pre-driver circuit 322 is configured with one or more inverter circuits or the like, and drives the gate of the second drive transistor 332 of the driver circuit 330 by buffering a control signal LCK from a control circuit (not shown). The control signal LCK is a signal for controlling the second drive transistor 332 to be on or off. A power supply voltage VREG is supplied to the high-potential power supply node of the second pre-driver circuit 322, and a low-potential power supply node is connected to a ground node NGND. The power supply voltage VREG is supplied, for example, from a regulator or the like that steps down a given power supply voltage VBB. The power supply voltage VREG is a voltage higher than the ground voltage GND and lower than the first output voltage VOUT1.

[0023] When the power supply voltage VPS is rising, assume that VOUT1 < VPS. Then, the output of the first pre-driver circuit 321 becomes indeterminate, and there is a possibility of an incorrect operation in which the first driving transistor 331 of the driver circuit 330 turns on. When the first driving transistor 331 turns on, current flows from the power supply node NPS through the first driving transistor 331 to the load, and there is a possibility that the first driving transistor 331 or the load fails. According to the present embodiment, when the power supply voltage VPS is rising, the first output voltage VOUT1 is fixed to the power supply voltage VPS by the first potential fixing circuit 231 of the voltage generation circuit 200. As a result, the output of the first pre-driver circuit 321 is determined to be the power supply voltage VPS, and the off state of the first driving transistor 331 of the driver circuit 330 is maintained, so that incorrect operation or failure can be prevented.

[0024] Also, when the power supply voltage VPS is rising, assume that VOUT2 < VPS. Then, the signal LSQ output from the level shifter 310 to the first pre-driver circuit 321 becomes indeterminate, and there is a possibility of the same incorrect operation or failure as described above. According to the present embodiment, when the power supply voltage VPS is rising, the second output voltage VOUT2 is fixed to the power supply voltage VPS by the second potential fixing circuit 232 of the voltage generation circuit 200. As a result, the signal LSQ output from the level shifter 310 is determined to be the power supply voltage VPS, and incorrect operation or failure can be prevented. These problems and solution methods will be described again in more specific configuration examples of FIGS. 4 to 7.

[0025] FIG. 3 is a first detailed configuration example of the voltage generation circuit 200. Note that descriptions of parts similar to the configuration example of FIG. 1 will be omitted as appropriate.

[0026] The bias voltage generation circuit 210 includes a first reference voltage setting circuit 211, a second reference voltage setting circuit 212, and a bias circuit 215.

[0027] The first reference voltage setting circuit 211 is connected between the power supply node NPS and the first bias node NR1 and sets the potential difference between a given power supply voltage VBB and the first bias voltage VR1 as the first reference voltage when a bias current flows. The first reference voltage setting circuit 211 is, for example, a reverse Zener diode or multiple reverse Zener diodes connected in series. The reverse direction means that the anode is connected to a node on the low potential side and the cathode is connected to a node on the high potential side. In this case, the first reference voltage is set by the Zener voltage of the Zener diode. Alternatively, the first reference voltage setting circuit 211 may be one or more reverse Zener diodes and one or more forward diodes connected in series. The forward direction means that the anode is connected to a node on the high potential side and the cathode is connected to a node on the low potential side. In this case, the first reference voltage is set by the Zener voltage of the Zener diode and the forward voltage of the diode.

[0028] The second reference voltage setting circuit 212 is connected between the first bias node NR1 and the second bias node NR2, and sets the potential difference between the first bias voltage VR1 and the second bias voltage VR2 as the second reference voltage when a bias current flows. The second reference voltage setting circuit 212 is, for example, a forward diode or multiple forward diodes connected in series. Alternatively, the second reference voltage setting circuit 212 may be one or more forward diodes and one or more reverse Zener diodes connected in series.

[0029] The bias circuit 215 supplies a bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. Specifically, the bias circuit 215 includes a current source IB that flows a bias current from a second bias node NR2 to a ground node NGND. When the current source IB flows a bias current, the bias current flows from the power supply node NPS through the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 to the second bias node NR2. This generates a first bias voltage VR1 and a second bias voltage VR2. The bias circuit 215 supplies a bias current when an enable signal EN from a control circuit (not shown) is enabled.

[0030] The first follower circuit 251 is a source follower circuit and includes a resistor RF1 and a P-type MOS transistor TF1. The resistor RF1 is connected between the power supply node NPS and the first output node NOUT1. The source of the P-type MOS transistor TF1 is connected to the first output node NOUT1, the drain is connected to the ground node NGND, and the gate is connected to the first bias node NR1. The first output voltage VOUT1 is a voltage higher than the first bias voltage VR1 by approximately the threshold voltage of the P-type MOS transistor TF1. In other words, the potential difference between a given power supply voltage VBB and the first output voltage VOUT1 is lower than the first reference voltage set by the first reference voltage setting circuit 211 by approximately the threshold voltage of the P-type MOS transistor TF1.

[0031] The second follower circuit 252 is a source follower circuit and includes a resistor RF2 and a P-type MOS transistor TF2. The resistor RF2 is connected between the power supply node NPS and the second output node NOUT2. The source of the P-type MOS transistor TF2 is connected to the second output node NOUT2, the drain is connected to the ground node NGND, and the gate is connected to the second bias node NR2. The second output voltage VOUT2 is a voltage higher than the second bias voltage VR2 by approximately the threshold voltage of the P-type MOS transistor TF2. If the threshold values ​​of the P-type MOS transistors TF1 and TF2 are the same, the potential difference between the first output voltage VOUT1 and the second output voltage VOUT2 is the first reference voltage set by the second reference voltage setting circuit 212.

[0032] Fig. 4 shows a second detailed configuration example of the voltage generating circuit 200. Note that descriptions of parts similar to those in the configuration examples of Fig. 1 or 3 will be omitted where appropriate.

[0033] The first reference voltage setting circuit 211 includes a Zener diode ZD1. The anode of the Zener diode ZD1 is connected to the first bias node NR1, and the cathode is connected to the power supply node NPS.

[0034] The second reference voltage setting circuit 212 includes a diode-connected NPN bipolar transistor BP2, whose collector and base are connected to the first bias node NR1 and whose emitter is connected to the second bias node NR2.

[0035] The bias circuit 215 includes resistors R1, R2, and an N-type MOS transistor M1. One end of the resistor R1 is connected to a power supply node NPS, and the other end is connected to the drain of the N-type MOS transistor M1. One end of the resistor R2 is connected to a second bias node NR2, and the other end is connected to the drain of the N-type MOS transistor M1. The source of the N-type MOS transistor M1 is connected to a ground node NGND. An enable signal EN is input to the gate of the N-type MOS transistor M1. When the enable signal EN is at a low level, the N-type MOS transistor M1 is off, the bias circuit 215 is disabled, and no bias current is supplied. When the enable signal EN is at a high level, the N-type MOS transistor M1 is on, and the bias circuit 215 is enabled and supplies a bias current.

[0036] The first potential fixing circuit 231 includes a resistor RK1 provided between the power supply node NPS and the first bias node NR1. One end of the resistor RK1 is connected to the power supply node NPS, and the other end is connected to the first bias node NR1. The resistance value of the resistor RK1 is set so that the Zener diode ZD1 turns on when the bias circuit 215 passes a bias current. In other words, the resistance value of the resistor RK1 is set so that the voltage drop when the bias current flows through the resistor RK1 exceeds the Zener voltage.

[0037] The second potential fixing circuit 232 includes a capacitor CK2 provided between the power supply node NPS and the second bias node NR2. One end of the capacitor CK2 is connected to the power supply node NPS, and the other end is connected to the second bias node NR2.

[0038] Fig. 5 shows example signal waveforms for explaining the operation of the second detailed configuration example of the voltage generating circuit 200. First, a configuration example and example signal waveforms of a comparative example will be explained using Fig. 6 and Fig. 7, and then the waveform example of Fig. 5 will be explained in comparison with that.

[0039] 6 shows a configuration example of a comparative example. In the comparative example, the first potential clamp circuit 231 and the second potential clamp circuit 232 are omitted from the configuration example of FIG. 4. A parasitic capacitance CP1 exists between the first bias node NR1 and the ground node NGND, and a parasitic capacitance CP2 exists between the second bias node NR2 and the ground node NGND. These parasitic capacitances are generated by the wiring parasitic capacitance of each bias node, the parasitic capacitance of a circuit element connected to each bias node, or the like.

[0040] 7 shows an example of signal waveforms in a comparative example. The enable signal EN changes from low to high after the power supply is started and the power supply voltage VPS reaches a given power supply voltage VBB. The bias circuit 215 is disabled while the enable signal EN is low, and does not supply bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. Hereinafter, the ground voltage GND is assumed to be 0V.

[0041] Before the power supply is started up, the power supply voltage VPS is 0 V. Therefore, the first bias voltage VR1, the second bias voltage VR2, the first output voltage VOUT1, and the second output voltage VOUT2 are all 0 V. At this time, the potential difference across the parasitic capacitances CP1 and CP2 is 0 V.

[0042] When the power supply starts up, the power supply voltage VPS rises from 0V to a given power supply voltage VBB. The waveform of the bias voltage IDA represents the waveform when the first bias voltage VR1 and the second bias voltage VR2 ideally track the power supply voltage VPS. In reality, the first bias voltage VR1 is maintained near 0V due to parasitic capacitance CP1 until the power supply voltage VPS exceeds the Zener voltage of the Zener diode ZD1. After the power supply voltage VPS rises and the Zener diode ZD1 turns on, the parasitic capacitance CP1 charges and the first bias voltage VR1 rises. Similarly, the parasitic capacitance CP2 maintains the second bias voltage VR2 near 0V due to parasitic capacitance CP2 until the power supply voltage VPS exceeds the voltage obtained by adding the Zener voltage and the forward voltage of the diode formed by the NPN bipolar transistor BP2. Note that resistor R1 is a high resistance, and the charging of the parasitic capacitance CP2 via resistors R1 and R2 is negligible. After the power supply voltage VPS rises and the Zener diode ZD1 and the diode are turned on, the parasitic capacitance CP2 is charged and the second bias voltage VR2 rises.

[0043] The waveform of the output voltage IDB represents the waveform when the first output voltage VOUT1 and the second output voltage VOUT2 ideally track the power supply voltage VPS. In reality, as described above, when the power supply voltage VPS rises, a potential difference occurs between the power supply voltage VPS and the first bias voltage VR1, and a potential difference occurs between the power supply voltage VPS and the second bias voltage VR2. If these potential differences are higher than the threshold voltages of the N-type transistors TF1 and TF2, the N-type transistors TF1 and TF2 turn on. Therefore, when the power supply voltage VPS rises, the first output voltage VOUT1 and the second output voltage VOUT2 are lower than the power supply voltage VPS. Considering the power supply voltage VPS as the reference, VPS-VOUT1 and VPS-VOUT2 temporarily drop below 0 V when the power supply voltage VPS rises. In this way, if the first output voltage VOUT1 and the second output voltage VOUT2 drop below the power supply voltage VPS when the power supply voltage VPS rises, there is a possibility that the downstream circuit 300 that uses the first output voltage VOUT1 and the second output voltage VOUT2 may malfunction or fail, as described in FIG. 2 etc.

[0044] Returning to the example of signal waveforms in this embodiment shown in Fig. 5, as explained in Fig. 4, in this embodiment, the resistor RK1 of the first potential clamp circuit 231 and the capacitor CK2 of the second potential clamp circuit 232 are provided.

[0045] When the power supply voltage VPS rises, the enable signal EN is at a low level. The bias circuit 215 does not supply a bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 while the enable signal EN is at a low level. At this time, the power supply node NPS and the first bias node NR1 are connected via a resistor RK1, so that the first bias voltage VR1 follows the power supply voltage VPS at approximately the same voltage. The resistance value of the resistor RK1 is set to a value that can charge the parasitic capacitance CP1 shown in FIG. 6. Furthermore, the power supply node NPS and the second bias node NR2 are connected via a capacitor CK2, so that the second bias voltage VR2 follows the power supply voltage VPS at approximately the same voltage. The capacitance value of the capacitor CK2 is sufficiently larger than the parasitic capacitance CP2 shown in FIG. 6.

[0046] When the power supply voltage VPS rises, there is almost no potential difference between the power supply voltage VPS and the first bias voltage VR1, so the P-type MOS transistor TF1 does not turn on. As a result, the first output voltage VOUT1 follows the power supply voltage VPS at approximately the same voltage. Similarly, there is almost no potential difference between the power supply voltage VPS and the second bias voltage VR2, so the P-type MOS transistor TF2 does not turn on. As a result, the second output voltage VOUT2 follows the power supply voltage VPS at approximately the same voltage. When the power supply voltage VPS rises, the first output voltage VOUT1 and the second output voltage VOUT2 do not decrease relative to the power supply voltage VPS, so malfunction or failure of the subsequent circuit 300 as described with reference to FIG. 2 etc. can be prevented.

[0047] When the enable signal EN changes from low to high, the bias circuit 215 supplies a bias current. As a result, the potential difference between a given power supply voltage VBB and the first bias voltage VR1 is set by the Zener voltage of the Zener diode ZD1. Furthermore, the potential difference between the first bias voltage VR1 and the second bias voltage VR2 is set by the forward voltage of the diode formed by the NPN bipolar transistor BP2. Then, the first follower circuit 251 outputs a first output voltage VOUT1 that follows the first bias voltage VR1, and the second follower circuit 252 outputs a second output voltage VOUT2 that follows the second bias voltage VR2.

[0048] 8 shows a first alternative configuration example of the first potential clamp circuit 231. The first potential clamp circuit 231 includes a resistor RK1 and a capacitor CK1 connected in parallel between a power supply node NPS and a first bias node NR1. Specifically, one end of the resistor RK1 and one end of the capacitor CK1 are connected to the power supply node NPS, and the other ends are connected to the first bias node NR1.

[0049] 9 shows another example of the configuration of the second reference voltage setting circuit 212. The second reference voltage setting circuit 212 includes an NPN bipolar transistor BP2 and a P-type MOS transistor TP2 connected in series between a first bias node NR1 and a second bias node NR2. Each transistor is diode-connected. Specifically, the collector and base of the NPN bipolar transistor BP2 are connected to the first bias node NR1, and the emitter is connected to the second bias node NR2. The source of the P-type MOS transistor TP2 is connected to the emitter of the NPN bipolar transistor BP2, and the drain and gate are connected to the second bias node NR2.

[0050] In this configuration example, the second reference voltage, which is the potential difference between the first bias voltage VR1 and the second bias voltage VR2, is the sum of the forward voltage of the diode formed by the NPN bipolar transistor BP2 and the forward voltage of the diode formed by the P-type MOS transistor TP2.

[0051] 10 shows another example of the configuration of the second potential clamping circuit 232. The second potential clamping circuit 232 includes a P-type MOS transistor TK2 provided between the power supply node NPS and the second bias node NR2. Specifically, the source of the P-type MOS transistor TK2 is connected to the power supply node NPS, and the drain is connected to the second bias node NR2. An enable signal EN is input to the gate of the P-type MOS transistor TK2. When the enable signal EN is at a low level, the P-type MOS transistor TK2 is on and clamps the second bias voltage VR2 to the power supply voltage VPS, and when the enable signal EN is at a high level, the P-type MOS transistor TK2 is off.

[0052] 11 shows a second alternative configuration example of the first potential clamping circuit 231. The first potential clamping circuit 231 includes a P-type MOS transistor TK1 provided between the power supply node NPS and the first bias node NR1. Specifically, the source of the P-type MOS transistor TK1 is connected to the power supply node NPS, and the drain is connected to the first bias node NR1. An enable signal EN is input to the gate of the P-type MOS transistor TK1. When the enable signal EN is at a low level, the P-type MOS transistor TK1 is on and clamps the first bias voltage VR1 to the power supply voltage VPS, and when the enable signal EN is at a high level, the P-type MOS transistor TK1 is off.

[0053] 12 shows a first alternative configuration example of the bias voltage generating circuit 210. The bias voltage generating circuit 210 includes a first reference voltage setting circuit 211b, a second reference voltage setting circuit 212b, and a bias circuit 215b.

[0054] The bias circuit 215b supplies a first bias current to the first reference voltage setting circuit 211b and a second bias current to the second reference voltage setting circuit 212b. The bias circuit 215b includes a first bias circuit 217 and a second bias circuit 218.

[0055] The first bias circuit 217 supplies a first bias current to the first reference voltage setting circuit 211b. Specifically, the first bias circuit 217 includes a current source IB1 that causes the first bias current to flow from the first bias node NR1 to the ground node NGND. When the current source IB1 causes the first bias current to flow, the bias current flows from the power supply node NPS through the first reference voltage setting circuit 211b to the first bias node NR1.

[0056] The second bias circuit 218 supplies a second bias current to the second reference voltage setting circuit 212b. Specifically, the second bias circuit 218 includes a second current source IB2 that supplies the second bias current from the second bias node NR2 to the ground node NGND. When the second current source IB2 supplies the second bias current, the bias current flows from the power supply node NPS through the second reference voltage setting circuit 212b to the second bias node NR2.

[0057] Each of the first bias circuit 217 and the second bias circuit 218 is configured similarly to the bias circuit 215 described with reference to FIG. 1, FIG. 3, or FIG. 4, etc.

[0058] The first reference voltage setting circuit 211b is connected between the power supply node NPS and the first bias node NR1, and sets the potential difference between a given power supply voltage VBB and the first bias voltage VR1 as the first reference voltage when the first bias current flows.

[0059] The second reference voltage setting circuit 212b is connected between the power supply node NPS and the second bias node NR2, and sets the potential difference between a given power supply voltage VBB and the second bias voltage VR2 as the second reference voltage when the second bias current flows. In this configuration example, the second reference voltage is greater than the first reference voltage.

[0060] The first reference voltage setting circuit 211b is configured similarly to the first reference voltage setting circuit 211 described with reference to Figure 3 or 4. The second reference voltage setting circuit 212b is configured, for example, by including the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 described with reference to Figure 3 or 4.

[0061] 13 shows a second alternative configuration example of the bias voltage generating circuit 210. The bias voltage generating circuit 210 includes a first reference voltage setting circuit 211c, a second reference voltage setting circuit 212b, and a bias circuit 215.

[0062] The first reference voltage setting circuit 211c is a voltage divider circuit. The voltage divider circuit divides the voltage between the power supply voltage VPS and the second output voltage VOUT2, and outputs the result as a first bias voltage VR1 to a first bias node NR1. The first reference voltage setting circuit 211c includes resistors RD1 and RD2 connected in series between the power supply node NPS and a second output node NOUT2. A node between the resistors RD1 and RD2 is connected to the first bias node NR1.

[0063] In this configuration example, the first bias voltage VR1 is higher than the second output voltage VOUT2. Therefore, the first output voltage VOUT1 that follows the first bias voltage VR1 is higher than the second output voltage VOUT2.

[0064] In this embodiment, the circuit device 100 generates a first output voltage VOUT1 and a second output voltage VOUT2 lower than the first output voltage VOUT1 from a power supply voltage VPS supplied to a power supply node NPS. The circuit device 100 includes a bias voltage generation circuit 210, a first follower circuit 251, a second follower circuit 252, and a first potential fixing circuit 231. The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on the power supply voltage VPS, and outputs the first bias voltage VR1 to a first bias node NR1 and the second bias voltage VR2 to a second bias node NR2. The first follower circuit 251 outputs a first output voltage VOUT1 that follows the first bias voltage VR1 to a first output node NOUT1. The second follower circuit 252 outputs a second output voltage VOUT2 that follows the second bias voltage VR2 to a second output node NOUT2. The first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises.

[0065] In this embodiment, the first bias voltage VR1 is generated based on the power supply voltage VPS, and the first output voltage VOUT1 is generated based on the first bias voltage VR1. That is, the first output voltage VOUT1 is generated based on the power supply voltage VPS. In such a case, as described with reference to FIGS. 6 and 7, the first output voltage VOUT1 may be lower than the power supply voltage VPS when the power supply voltage VPS rises. This may cause the downstream circuit 300 using the first output voltage VOUT1 to malfunction or fail when the power supply voltage VPS rises. According to this embodiment, the first potential clamp circuit 231 clamps the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises. The first output voltage VOUT1 follows the first bias voltage VR1, which is clamped to the power supply voltage VPS, and therefore follows the power supply voltage VPS. As a result, no difference occurs between the first output voltage VOUT1 and the power supply voltage VPS when the power supply voltage VPS rises, and the subsequent circuit 300 that uses the first output voltage VOUT1 does not malfunction or fail.

[0066] In this embodiment, the circuit device 100 may also include a second potential clamping circuit 232. The second potential clamping circuit 232 may clamp the potential of the second bias node NR2 to the potential of the power supply node NPS when the power supply voltage VPS rises.

[0067] According to this embodiment, the second output voltage VOUT2 follows the second bias voltage VR2, which is fixed to the power supply voltage VPS, and therefore follows the power supply voltage VPS. As a result, no difference occurs between the second output voltage VOUT2 and the power supply voltage VPS when the power supply voltage VPS rises, and the downstream circuit 300 that uses the second output voltage VOUT2 does not malfunction or fail.

[0068] 3 and other embodiments, the bias voltage generation circuit 210 may include a first reference voltage setting circuit 211 and a second reference voltage setting circuit 212. The first reference voltage setting circuit 211 may be provided between a power supply node NPS and a first bias node NR1, and may set the potential difference between the power supply node NPS and the first bias node NR1 to a first reference voltage. The second reference voltage setting circuit 212 may be provided between the first bias node NR1 and a second bias node NR2, and may set the potential difference between the first bias node NR1 and the second bias node NR2 to a second reference voltage.

[0069] According to this embodiment, the first reference voltage setting circuit 211 sets the potential difference between the power supply node NPS and the first bias node NR1 as the first reference voltage, thereby generating a first bias voltage VR1 based on the power supply voltage VPS. As a result, a first output voltage VOUT1 that follows the first bias voltage VR1 is generated based on the power supply voltage VPS. Also, according to this embodiment, the second reference voltage setting circuit 212 sets the potential difference between the first bias node NR1 and the second bias node NR2 as the second reference voltage, thereby generating a second bias voltage VR2 based on the first bias voltage VR1 that is based on the power supply voltage VPS. As a result, a second output voltage VOUT2 that follows the second bias voltage VR2 is generated based on the power supply voltage VPS.

[0070] 4 and other embodiments, the first reference voltage setting circuit 211 may generate the first reference voltage from the Zener voltage of Zener diode ZD1. The second reference voltage setting circuit 212 may generate the second reference voltage from the forward voltage of the diode. Note that in FIG. 4, the base-emitter voltage of diode-connected NPN bipolar transistor BP2 corresponds to the forward voltage of the diode.

[0071] According to this embodiment, a first bias voltage VR1 can be generated that is lower than the power supply voltage VPS by the Zener voltage, and a second bias voltage VR2 can be generated that is lower than the power supply voltage VPS by the sum of the Zener voltage and the forward voltage of the diode, using the power supply voltage VPS as a reference.

[0072] In the embodiment of FIG. 3 etc., the bias voltage generating circuit 210 may include a bias circuit 215 that supplies a bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212.

[0073] According to this embodiment, the bias circuit 215 supplies a bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212, so that the first reference voltage setting circuit 211 sets the first reference voltage and the second reference voltage setting circuit 212 sets the second reference voltage. For example, a bias current is supplied to the Zener diode ZD1, so that the Zener diode ZD1 generates a Zener voltage as the first reference voltage. Furthermore, a bias current is supplied to the diode, so that the diode generates a forward voltage as the second reference voltage.

[0074] In the embodiment of FIG. 3 etc., the bias circuit 215 does not need to supply bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 when the power supply voltage VPS rises.

[0075] According to this embodiment, the first reference voltage and the second reference voltage are not set when the power supply voltage VPS rises, which allows the first potential clamp circuit 231 to clamp the first bias voltage VR1 to the power supply voltage VPS, and the second potential clamp circuit 232 to clamp the second bias voltage VR2 to the power supply voltage VPS.

[0076] 12, the bias voltage generating circuit 210 may include a first reference voltage setting circuit 211b and a second reference voltage setting circuit 212b. The first reference voltage setting circuit 211b may be provided between the power supply node NPS and the first bias node NR1 and set the potential difference between the power supply node NPS and the first bias node NR1 to a first reference voltage. The second reference voltage setting circuit 212b may be provided between the power supply node NPS and the second bias node NR2 and set the potential difference between the power supply node NPS and the second bias node NR2 to a second reference voltage.

[0077] 12, the bias voltage generating circuit 210 may include a bias circuit 215b that supplies bias currents to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. In the embodiment of FIG.

[0078] According to this embodiment, a first bias voltage VR1 is generated with reference to the power supply voltage VPS, thereby generating a first output voltage VOUT1 that follows the first bias voltage VR1 with reference to the power supply voltage VPS. Similarly, a second bias voltage VR2 is generated with reference to the power supply voltage VPS, thereby generating a second output voltage VOUT2 that follows the second bias voltage VR2 with reference to the power supply voltage VPS.

[0079] In the embodiment of FIG. 12, the bias circuit 215b does not need to supply a bias current to the first reference voltage setting circuit 211b and the second reference voltage setting circuit 212b when the power supply voltage VPS rises.

[0080] According to this embodiment, the first reference voltage and the second reference voltage are not set when the power supply voltage VPS rises, which allows the first potential clamp circuit 231 to clamp the first bias voltage VR1 to the power supply voltage VPS, and the second potential clamp circuit 232 to clamp the second bias voltage VR2 to the power supply voltage VPS.

[0081] 4, 8, or 11, the first potential clamp circuit 231 may be configured with at least one of a resistor, a capacitor, or a transistor. When a transistor is used, the transistor is on when the power supply voltage VPS rises.

[0082] According to this embodiment, the power supply node NPS and the first bias node NR1 are connected by at least one of a resistor, a capacitor, or a transistor, so that the first bias voltage VR1 is fixed to the power supply voltage VPS when the power supply voltage VPS rises.

[0083] In the embodiment of FIG. 4 or FIG. 10, the second potential clamp circuit 232 may be configured by at least one of a capacitor or a transistor.

[0084] According to this embodiment, the power supply node NPS and the second bias node NR2 are connected by at least one of a capacitor and a transistor, so that the second bias voltage VR2 is fixed to the power supply voltage VPS when the power supply voltage VPS rises.

[0085] 2 and other embodiments, the circuit device 100 may include a circuit that operates with the power supply voltage VPS as the high-potential power supply voltage and the first output voltage VOUT1 as the low-potential power supply voltage. In the example of Fig. 2, the first pre-driver circuit 321 is a circuit that operates with the power supply voltage VPS as the high-potential power supply voltage and the first output voltage VOUT1 as the low-potential power supply voltage.

[0086] If the first output voltage VOUT1 becomes lower than the power supply voltage VPS when the power supply voltage VPS rises, a circuit that operates using the first output voltage VOUT1 as a low-potential power supply voltage may malfunction. This malfunction may also cause failure of circuit elements within the circuit device 100, external circuits, or external components. According to this embodiment, the first output voltage VOUT1 is fixed to the power supply voltage VPS when the power supply voltage VPS rises, so that malfunction or failure does not occur.

[0087] 2, the circuit device 100 may also include a first pre-driver circuit 321 that drives a first drive transistor 331 of the driver circuit 330, and a level shifter 310 that level-shifts a control signal HCK of the first pre-driver circuit 321 and outputs the signal to the first pre-driver circuit 321. The first drive transistor 331 may be provided between a power supply node NPS and an output node for a drive voltage. The first pre-driver circuit 321 may operate using the power supply voltage VPS as a high-potential power supply voltage and the first output voltage VOUT1 as a low-potential power supply voltage. The level shifter 310 may output a voltage based on the power supply voltage VPS as a high level and the second output voltage VOUT2 as a low level.

[0088] When the power supply voltage VPS rises, if the first output voltage VOUT1 falls below the power supply voltage VPS, the first pre-driver circuit 321 operates, turning on the first drive transistor 331, causing a malfunction or failure. Alternatively, when the power supply voltage VPS rises, if the second output voltage VOUT2 falls below the power supply voltage VPS, the low level of the output of the level shifter 310 falls below the power supply voltage VPS, and this low level is input to the first pre-driver circuit 321, causing a malfunction or failure. According to this embodiment, when the power supply voltage VPS rises, the first output voltage VOUT1 is fixed to the power supply voltage VPS, so the output of the first pre-driver circuit 321, which uses the first output voltage VOUT1 as the low-potential power supply voltage, is fixed to the power supply voltage VPS. Furthermore, when the power supply voltage VPS rises, the second output voltage VOUT2 is fixed to the power supply voltage VPS, so the output of the level shifter 310, which outputs a low-level voltage based on the second output voltage VOUT2, is fixed to the power supply voltage VPS. As a result, malfunctions or failures do not occur when the power supply voltage VPS rises.

[0089] 2. Second configuration example 14 shows a second configuration example of the voltage generating circuit 200 included in the circuit device 100 of this embodiment. Below, the description of the same parts as in the first configuration example described in FIGS. 1 to 13 will be omitted as appropriate, and the following mainly describes the parts that are different from the first configuration example.

[0090] The voltage generating circuit 200 includes a bias voltage generating circuit 210, a first potential clamping circuit 231, a second potential clamping circuit 232, and a first follower circuit 251. In the second configuration example, the second follower circuit 252 is omitted from the first configuration example, and the second bias node NR2 serves as the second output node NOUT2. That is, the bias voltage generating circuit 210 outputs the second bias voltage VR2 as the second output voltage VOUT2 to the second output node NOUT2.

[0091] 15 shows a more detailed configuration example of the second configuration example of the voltage generating circuit 200. The bias voltage generating circuit 210 includes a first reference voltage setting circuit 211, a second reference voltage setting circuit 212, and a bias circuit 215c.

[0092] The bias circuit 215c includes a resistor R2 and an N-type MOS transistor M1. One end of the resistor R2 is connected to a second bias node NR2, and the other end is connected to the drain of the N-type MOS transistor M1. The source of the N-type MOS transistor M1 is connected to a ground node NGND. An enable signal EN is input to the gate of the N-type MOS transistor M1.

[0093] In this embodiment, the circuit device 100 generates a first output voltage VOUT1 and a second output voltage VOUT2 lower than the first output voltage VOUT1 from a power supply voltage VPS supplied to a power supply node NPS. The circuit device 100 includes a bias voltage generation circuit 210, a first follower circuit 251, and a first potential clamping circuit 231. The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on the power supply voltage VPS, outputs the first bias voltage VR1 to a first bias node NR1, and outputs the second bias voltage VR2 as a second output voltage VOUT2 to a second output node NOUT2, which is the second bias node NR2. The first follower circuit 251 outputs the first output voltage VOUT1, which follows the first bias voltage VR1, to the first output node NOUT1. The first potential clamping circuit 231 clamps the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises.

[0094] According to this embodiment, the first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises. The first output voltage VOUT1 follows the first bias voltage VR1 fixed to the power supply voltage VPS, and therefore follows the power supply voltage VPS. As a result, no difference occurs between the first output voltage VOUT1 and the power supply voltage VPS when the power supply voltage VPS rises, and the downstream circuit 300 that uses the first output voltage VOUT1 does not malfunction or fail.

[0095] In this embodiment, the second bias voltage VR2 is output to the second output node NOUT2 without passing through a follower circuit. At this time, the second potential fixing circuit 232 may fix the potential of the second output node NOUT2 to the potential of the power supply node NPS when the power supply voltage VPS rises. This eliminates a difference between the second output voltage VOUT2 and the power supply voltage VPS when the power supply voltage VPS rises, preventing malfunction or failure of the downstream circuit 300 that uses the second output voltage VOUT2.

[0096] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be within the scope of the present disclosure. For example, a term described at least once in the specification or drawings with a different, broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device, voltage generating circuit, subsequent circuit, bias voltage generating circuit, first follower circuit, second follower circuit, first potential clamping circuit, and second potential clamping circuit are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0097] 100...circuit device, 200...voltage generation circuit, 210...bias voltage generation circuit, 211, 211b, 211c...first reference voltage setting circuit, 212, 212b...second reference voltage setting circuit, 215, 215b, 215c...bias circuit, 231...first potential fixing circuit, 232...second potential fixing circuit, 251...first follower circuit, 252...second follower circuit, 300...circuit, 310...level shifter, 321...first pre-driver circuit, 322...second pre-driver circuit, 330...driver circuit, 331...first driving circuit Transistor, 332...second drive transistor, BP2...NPN bipolar transistor, CK1...capacitor, GND...ground voltage, NGND...ground node, NOUT1...first output node, NOUT2...second output node, NPS...power supply node, NR1...first bias node, NR2...second bias node, RK1...resistor, VOUT1...first output voltage, VOUT2...second output voltage, VPS...power supply voltage, VR1...first bias voltage, VR2...second bias voltage, ZD1...Zener diode

Claims

1. 1. A circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, a bias voltage generating circuit that generates a first bias voltage and a second bias voltage based on the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage to a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; a second follower circuit that outputs the second output voltage that follows the second bias voltage to a second output node; a first potential fixing circuit that fixes the potential of the first bias node to the potential of the power supply node when the power supply voltage rises; A circuit device comprising:

2. 1. A circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, a bias voltage generating circuit that generates a first bias voltage and a second bias voltage using the power supply voltage as a reference, outputs the first bias voltage to a first bias node, and outputs the second bias voltage as the second output voltage to a second output node that is a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; a first potential fixing circuit that fixes the potential of the first bias node to the potential of the power supply node when the power supply voltage rises; A circuit device comprising:

3. 3. The circuit device according to claim 1, a second potential fixing circuit for fixing the potential of the second bias node to the potential of the power supply node when the power supply voltage rises;

4. 3. The circuit device according to claim 1, The bias voltage generating circuit includes: a first reference voltage setting circuit provided between the power supply node and the first bias node, the first reference voltage setting circuit setting a potential difference between the power supply node and the first bias node to a first reference voltage; a second reference voltage setting circuit provided between the first bias node and the second bias node, the second reference voltage setting circuit setting a potential difference between the first bias node and the second bias node to a second reference voltage; A circuit device comprising:

5. 5. The circuit device according to claim 4, The first reference voltage setting circuit generating the first reference voltage by a Zener voltage of a Zener diode; The second reference voltage setting circuit A circuit device, characterized in that the second reference voltage is generated by a forward voltage of a diode.

6. 5. The circuit device according to claim 4, The bias voltage generating circuit includes: a bias circuit for supplying a bias current to the first reference voltage setting circuit and the second reference voltage setting circuit;

7. 7. The circuit device according to claim 6, The bias circuit a first reference voltage setting circuit that supplies a first bias current to the second reference voltage setting circuit and a second reference voltage setting circuit when the power supply voltage rises;

8. 3. The circuit device according to claim 1, The bias voltage generating circuit includes: a first reference voltage setting circuit provided between the power supply node and the first bias node, the first reference voltage setting circuit setting a potential difference between the power supply node and the first bias node to a first reference voltage; a second reference voltage setting circuit provided between the power supply node and the second bias node, the second reference voltage setting circuit setting a potential difference between the power supply node and the second bias node to a second reference voltage; A circuit device comprising:

9. 9. The circuit device according to claim 8, The bias voltage generating circuit includes: a bias circuit for supplying a bias current to the first reference voltage setting circuit and the second reference voltage setting circuit;

10. 10. The circuit device according to claim 9, The bias circuit a first reference voltage setting circuit that supplies a first bias current to the second reference voltage setting circuit and a second reference voltage setting circuit when the power supply voltage rises;

11. 3. The circuit device according to claim 1, The first potential fixing circuit A circuit device comprising at least one of a resistor, a capacitor, and a transistor.

12. 4. The circuit device according to claim 3, The second potential fixing circuit A circuit device comprising at least one of a capacitor and a transistor.

13. 3. The circuit device according to claim 1, A circuit device comprising: a circuit that operates using the power supply voltage as a high-potential power supply voltage and the first output voltage as a low-potential power supply voltage.

14. 3. The circuit device according to claim 1, a first pre-driver circuit for driving a first drive transistor of a driver circuit provided between the power supply node and an output node of a drive voltage; a level shifter that level-shifts a control signal of the first pre-driver circuit; Including, The first pre-driver circuit The power supply voltage is a high-potential power supply voltage, and the first output voltage is a low-potential power supply voltage; The level shifter is a circuit device configured to output the power supply voltage at a high level and a voltage based on the second output voltage at a low level;

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