Semiconductor Devices

Abstract

To provide a semiconductor device that enables high integration. [Solution] The semiconductor device has a diffusion resistor R as a plurality of first resistive elements. DIFF , insulating layer STI and multiple GC resistors R as second resistive elements GC The device comprises a plurality of first resistive elements, which are provided on the main surface side of the semiconductor substrate, extending in a first direction X parallel to the main surface of the semiconductor substrate 200, and arranged in a second direction Y parallel to the main surface of the semiconductor substrate and intersecting the first direction, with a first connection terminal portion T on the end side in the first direction. DIFF The insulating layer is disposed between the first resistor elements of the semiconductor substrate, and has an electrode mounting surface in contact with the electrode layer. The second resistor elements are disposed on the electrode mounting surface of the insulating layer between the first resistor elements, extend in the first direction, are aligned in the second direction, and have second connection terminal portions T GC The conductive layer has a plurality of conductive layers.

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor device is known in which a first resistive element made of a diffusion layer and a second resistive element made of a conductive layer are provided on a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 0300912 [Patent Document 2] U.S. Patent Application Publication No. 2011 / 0092042 [Patent Document 3] U.S. Patent No. 6172389 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a semiconductor device that enables high integration. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment comprises a semiconductor substrate and an electrode layer provided on the side of the semiconductor substrate facing the main surface. The semiconductor device comprises a plurality of first resistive elements made of a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, and arranged in a second direction parallel to the main surface of the semiconductor substrate and intersecting the first direction, with a first connection terminal portion at the end in the first direction; an insulating layer disposed between each of the plurality of first resistive elements of the semiconductor substrate and having an electrode mounting surface in contact with the electrode layer; and a plurality of second resistive elements made of a plurality of conductive layers provided on the electrode mounting surface of the insulating layer between the plurality of first resistive elements, extending in a first direction, arranged in a second direction, and having a second connection terminal portion at the end in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment. [Figure 2] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 3] 1 is a schematic exploded perspective view showing an example of the configuration of a memory die MD. FIG. [Figure 4] FIG. 2 is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 5] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 6] 2 is a schematic cross-sectional view showing the configuration of a portion of a memory die MD. FIG. [Figure 7] FIG. 2 is a schematic plan view showing a configuration example of a chip CP. [Figure 8] 8 is a schematic plan view showing an enlarged circuit region A in the peripheral circuit region RPC shown in FIG. 7. [Figure 9] 1 is a plan view showing a diffused resistor RDIFF and a GC resistor RGC according to the first embodiment. FIG. [Figure 10] 1 is a cross-sectional view showing a diffusion resistor RDIFF and a GC resistor RGC according to the first embodiment. [Figure 11]This is a cross-sectional view corresponding to Figure 10, showing a modified example of the first embodiment. [Figure 12] This is a cross-sectional view illustrating the manufacturing method for diffusion resistor RDIFF and GC resistor RGC according to this embodiment. [Figure 13] This is a cross-sectional view illustrating the manufacturing method for diffusion resistor RDIFF and GC resistor RGC according to this embodiment. [Figure 14] 10A and 10B are cross-sectional views for explaining a method for manufacturing the diffused resistor RDIFF and the GC resistor RGC according to the embodiment. [Figure 15] This is a cross-sectional view illustrating the manufacturing method for diffusion resistor RDIFF and GC resistor RGC according to this embodiment. [Figure 16] This is a cross-sectional view illustrating the manufacturing method for diffusion resistor RDIFF and GC resistor RGC according to this embodiment. [Figure 17] This is a cross-sectional view illustrating the manufacturing method for diffusion resistor RDIFF and GC resistor RGC according to this embodiment. [Figure 18] This is a plan view showing the diffusion resistor RDIFF and GC resistor RGC according to the second embodiment. [Figure 19] This is a cross-sectional view showing the diffusion resistor RDIFF and GC resistor RGC according to the second embodiment. [Figure 20] This is a plan view showing the diffusion resistance RDIFF and GC resistance RGC according to the third embodiment. [Figure 21] This is a cross-sectional view showing the diffusion resistor RDIFF and GC resistor RGC according to the third embodiment. [Figure 22] This is a plan view showing the diffusion resistance RDIFF and GC resistance RGC according to the fourth embodiment. [Figure 23] This is a cross-sectional view showing the diffusion resistor RDIFF and GC resistor RGC according to the fourth embodiment. [Figure 24] This is a plan view showing the diffusion resistance RDIFF and GC resistance RGC according to the fifth embodiment. [Figure 25] This is a plan view showing the diffusion resistance RDIFF and GC resistance RGC according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor devices according to embodiments will be described in detail with reference to the drawings. In the following embodiments, a "semiconductor memory device" will be described as an example of a semiconductor device. However, the following embodiments are merely examples and are not intended to limit the present invention. In addition, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. In addition, parts common to multiple embodiments will be assigned the same reference numerals, and explanations thereof may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0015] Furthermore, in this specification, when referring to a configuration, component, etc., "width," "length," or "thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed using SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy), or the like.

[0016] In addition, in this specification, the term "wiring" may include wiring, via contact electrodes, connection portions for connecting wiring and via contact electrodes, adhesive electrodes, and the like.

[0017] [First embodiment] [Circuit configuration of memory die MD] Figure 1 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 2 is a schematic circuit diagram showing a part of the configuration of the memory die MD.

[0018] 1, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuit PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. The peripheral circuit PC also includes an input / output control circuit I / O and a logic circuit CTR.

[0019] [Circuit configuration of memory cell array MCA] As shown in FIG. 2, the memory cell array MCA includes the above-mentioned multiple memory blocks BLK. Each of the multiple memory blocks BLK includes multiple string units SU. Each of the multiple string units SU includes multiple memory strings MS. One end of each of the multiple memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of the multiple memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0020] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS. The drain-side select transistor STD, the plurality of memory cells MC, and the source-side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0021] The memory cells MC are field-effect transistors. Each memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. Each memory cell MC stores one or more bits of data. A word line WL is connected to the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all memory strings MS in one memory block BLK.

[0022] The select transistors (STD, STS) are field-effect transistors. The select transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. A select gate line (SGD, SGS) is connected to the gate electrode of each of the select transistors (STD, STS). One drain-side select gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side select gate line SGS is commonly connected to all memory strings MS in one memory block BLK. The drain-side select gate line SGD and the source-side select gate line SGS may be referred to as select gate lines SG, respectively.

[0023] [Memory die MD structure] 3 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment. As shown in FIG. 3, the memory die MD includes a chip C on the memory cell array MCA side. M and peripheral circuit PC side chip C P And, it is equipped with.

[0024] Chip C M On the upper surface are multiple external pad electrodes P (not shown) that can be connected to bonding wires. X Also, chip C M On the underside of I1Also, chip C P On the upper surface, there are multiple bonded electrodes P I2 A chip C is provided below. M Regarding the multiple bonded electrodes P I1 The surface on which the external pad electrodes P are provided is called the front surface. X The surface on which the chip C is provided is called the back surface. P Regarding the multiple bonded electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite to the front surface is called the back surface. P The surface of the chip C P and the chip C M The back side is chip C M The surface of the casing is provided above the surface of the casing.

[0025] Chip C M and Chip C P This is chip C M Surface and chip C P The surfaces of the plurality of laminated electrodes P are arranged to face each other. I1 is a plurality of laminated electrodes P I2 are provided corresponding to the plurality of bonded electrodes P I2 The electrode P is placed in a position where it can be attached to the I1 and laminated electrode P I2 That is, Chip C M and chip C P and functions as a bonding electrode for electrically connecting them.

[0026] Furthermore, in the example shown in Figure 3, chip C M The corners a1, a2, a3, and a4 are the chip C P These correspond to corners b1, b2, b3, and b4.

[0027] Figure 4 shows chip C M 4 is a schematic bottom view showing a configuration example of the laminated electrode P I1 5 and 6 are schematic cross-sectional views showing the configuration of a part of the memory die MD. P7 is a schematic plan view showing a configuration example of the laminated electrode P I2 Some of the components have been omitted.

[0028] [Chip C M [Structure] In the example in Figure 4, chip C M The memory device 100 includes four memory planes MP0 to MP3 aligned in the X direction. Note that the four memory planes MP0 to MP3 may be simply referred to as memory planes MP. Each of the four memory planes MP0 to MP3 includes a plurality of memory blocks BLK aligned in the Y direction. In the example of FIG. 4, each of the four memory planes MP0 to MP3 includes a hookup region R HU And the memory hole region R provided between these MH It includes (memory area) and . In addition, in the example in Figure 4, the memory hole area R MH There are four regions R in the X direction MHU It is divided into these four regions R MHU The widths of the chips C in the X direction may or may not be the same. M This is a peripheral region R located on one end in the Y direction of the four memory planes MP0 to MP3. P Equipped with.

[0029] In the illustrated example, the hook-up region R HU These are provided at both ends of the memory plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the hookup region R HU The hook-up region R may be provided at one end in the X direction of the memory plane MP, not at both ends in the X direction. HU may be provided at the center position or near the center in the X direction of the memory plane MP.

[0030] Chip C M For example, as shown in Figure 5, the substrate layer L SB and the base layer L SB The memory cell array layer LMCA and memory cell array layer L MCA It comprises a via contact electrode layer CH provided below, a plurality of wiring layers M0, M1 provided below the via contact electrode layer CH, and a chip bonding electrode layer MB provided below the wiring layers M0, M1.

[0031] [Chip C M The base layer L SB [Structure] For example, as shown in Figure 5, the substrate layer L SB The memory cell array layer L MCA It comprises a conductive layer 100 provided on the upper surface, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back wiring layer MA.

[0032] The conductive layer 100 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0033] The conductive layer 100 functions as part of the source line SL (Figure 2). Four conductive layers 100 are provided, corresponding to the four memory planes MP0 to MP3 (Figure 4). Regions VZ, which do not include the conductive layer 100, are provided at the X and Y ends of the memory plane MP.

[0034] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0035] The back wiring layer MA includes a plurality of wirings ma, which may include, for example, aluminum (Al).

[0036] Some of the multiple wirings ma function as part of the source line SL (Figure 2). There are, for example, four of these wirings ma, corresponding to four memory planes. Each of these wirings ma is electrically connected to the conductive layer 100.

[0037] Furthermore, some of the multiple wirings ma are external pad electrodes P X This function is achieved by this wiring ma in the surrounding region R. P It is provided in the region VZ that does not include the conductive layer 100, and the memory cell array layer L MCA It is connected to the via contact electrode CC inside. In addition, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0038] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0039] [Chip C M The memory cell array layer L MCA Hookup Area R HU Structure in As shown in Figure 6, the hook-up area R HU Multiple via contact electrodes CC are provided in the device. Each of these multiple via contact electrodes CC extends in the Z direction and is connected to the conductive layer 110 (WL, SGD, SGS) at its upper end.

[0040] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in Surrounding area R P For example, as shown in Figure 5, the external pad electrode P X In response, multiple via contact electrodes CC are provided. These multiple via contact electrodes CC have an external pad electrode P at their upper end. X is connected to.

[0041] [Structure of via contact electrode layer CH] Multiple via contact electrodes ch included in the via contact electrode layer CH are, for example, in the memory cell array layer L MCA Internal configuration and chip C P It is electrically connected to at least one of the internal components.

[0042] The via contact electrode layer CH includes multiple via contact electrodes ch as multiple wirings. These multiple via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to multiple semiconductor layers 120 and are connected to the lower ends of the multiple semiconductor layers 120.

[0043] [Chip C M [Structure of wiring layers M0 and M1] The wirings included in the wiring layers M0 and M1 are, for example, the memory cell array layer L MCA Internal configuration and chip C P It is electrically connected to at least one of the internal components.

[0044] The wiring layer M0 includes multiple wirings m0. These multiple wirings m0 may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminate of tantalum nitride (TaN) and tantalum (Ta), and a laminate of metal films such as copper (Cu). Some of the multiple wirings m0 function as bit lines BL. The bit lines BL are, for example, aligned in the X direction and extended in the Y direction.

[0045] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 5. These wirings m1 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0046] [Chip bonding electrode layer MB structure] The plurality of wirings included in the chip bonding electrode layer MB are, for example, MCA Internal configuration and chip C P It is electrically connected to at least one of the internal components.

[0047] The chip bonding electrode layer MB is made up of a plurality of bonding electrodes P I1 (adhesive pad). These plural adhesive electrodes P I1is a barrier conductive film p such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I1B and metal films such as copper (Cu) I1M The film may include a laminated film of the above.

[0048] [Chip C P [Structure] Chip C P As shown in Figure 7, for example, it includes regions MP0' to MP3' that overlap with four memory planes MP0 to MP3 aligned in the X direction. At both ends of these four regions MP0' to MP3' in the X direction are the low control circuit regions R RC In addition, these two row control circuit regions R RC Between them, there are two block decoder regions R aligned in the X direction. BD In addition, these two block decoder regions R BD Between them is the peripheral circuit region R PC The peripheral circuit region R PC In the figure, four column control circuit regions R are arranged in the X and Y directions. CC Although not shown, a peripheral circuit region R PC Other areas of the chip also contain circuits. M The surrounding area R P (Fig. 4) P In the area of, the circuit area R C is provided.

[0049] Also, Chip C P As shown in Figure 5, for example, the device comprises a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 provided above the electrode layer GC, and a chip-bonded electrode layer DB provided above the wiring layers D0, D1, D2, D3, D4.

[0050] [Chip C P Structure of semiconductor substrate 200] The semiconductor substrate 200 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). The semiconductor substrate 200 has a main surface S on the electrode layer GC and wiring layers D0, D1, D2, D3, D4 side. M The main surface S of the semiconductor substrate 200 M On the surface on the side of the semiconductor substrate 200, there are provided an N-type diffusion layer 200N containing an N-type impurity such as phosphorus (P), a P-type diffusion layer 200P containing a P-type impurity such as boron (B), a semiconductor substrate region 200S in which the N-type diffusion layer 200N and the P-type diffusion layer 200P are not provided, and an insulating layer STI. A portion of the P-type diffusion layer 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type diffusion layer 200P is provided in the N-type diffusion layer 200N. The N-type diffusion layer 200N, the P-type diffusion layer 200P provided in the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors that constitute the peripheral circuit PC. Note that some of the plurality of transistors Tr function as word line switches WLSW and select gate line switches SGSW.

[0051] [Chip C P Electrode layer GC structure] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CS.

[0052] The N-type diffusion layer 200N of the semiconductor substrate 200, the P-type diffusion layer 200P provided in the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC, one electrode of a plurality of capacitors, etc. Also, as shown in FIG. 6, a part of the P-type diffusion layer 200P of the semiconductor substrate 200 forms a diffusion resistor R DIFF It functions as:

[0053] The plurality of electrodes gc included in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, the other electrodes of the plurality of capacitors, etc. Also, as shown in FIG. 6, some of the plurality of electrodes gc included in the electrode layer GC function as GC resistors R GC It functions as:

[0054] The via contact electrode CS extends in the Z direction, and its lower end is connected to the semiconductor substrate 200 or the upper surface of the electrode g. The via contact electrode CS may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0055] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in Figure 7, the multiple connections and multiple wirings included in D0, D1, D2, D3, and D4 are, for example, in the memory cell array layer L MCA Internal configuration and chip C P It is electrically connected to at least one of the internal components.

[0056] The wiring layers D0, D1, and D2 each include a plurality of connection portions d0, d1, and d2 and a plurality of wirings. These connection portions d0, d1, and d2 and the plurality of wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0057] The wiring layers D3 and D4 each include a plurality of connecting portions d3 and d4 and a plurality of wirings, which may include a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0058] [Structure of the chip-bonded electrode layer DB] Multiple wirings included in the chip bonding electrode layer DB are, for example, in the memory cell array layer L MCA Internal configuration and chip C PIt is electrically connected to at least one of the internal components.

[0059] The chip bonding electrode layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I2 is a barrier conductive film p such as titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) I2M The film may include a laminated film of the above.

[0060] In addition, the bonded electrode P I1 and laminated electrode P I2 In particular, metal films such as copper (Cu) I1M ,p I2M When using the metal film p I1M and metal film p I2M However, the bonded electrode P due to the misalignment of the bonding position is I1 and laminated electrode P I2 Distortion of the bonded shape, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous areas on the side). I1 and adhesive electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and laminated electrode P I2 The cross section of the bonded electrode P along the Z direction has a non-rectangular shape, with the side walls not being linear. I1 and laminated electrode P I2 When these are bonded together, the barrier metal covers the bottom, sides, and top surfaces of each Cu component forming them. In contrast, in a typical Cu wiring layer, an insulating layer (such as SiN or SiCN) with an oxidation prevention function for Cu is provided on the top surface of the Cu, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0061] [Diffusion resistance R DIFF and GC resistance RGC Pattern] FIG. 8 shows the peripheral circuit region R PC 1 is an enlarged plan view of a circuit region A in the peripheral region R. P It may be provided in other areas such as the above.

[0062] The circuit area A includes three circuit modules MDA, MDB, and MDC, and a resistor element area RES provided around them. The resistor element area RES includes a diffused resistor R DIFF and the GC resistor R as the second resistive element. GC The diffusion resistor R DIFF and GC resistance R GC are connected to three circuit modules MDA, MDB, and MDC as some of the circuit elements. Note that the number and arrangement of circuit modules are not limited to those illustrated.

[0063] 9 and 10 show the diffused resistor R DIFF and GC resistance R GC Fig. 9 is an enlarged plan view of a circuit region B in the resistive element region RES of Fig. 8. Fig. 10 is a cross-sectional view taken along line CC' in Fig. 9 and seen from the direction of the arrow.

[0064] The resistor circuit of this embodiment is formed by a semiconductor substrate 200 and a main surface S of the semiconductor substrate 200. M and an electrode layer GC disposed on the opposite side. M On the side, multiple diffused resistors R DIFF There are multiple diffused resistors R DIFF In this example, the P-type diffusion layer 200P is formed in an N-type diffusion layer 200N (N-well). DIFF are the main surface S of the semiconductor substrate 200. M , and extends in the Y direction parallel to the main surface S of the semiconductor substrate 200. M are parallel to each other and are arranged at a predetermined pitch P1 in the X direction, which intersects with the Y direction. DIFF The first connection terminal portion T is provided at the end portion in the Y direction, for example, at both ends.DIFF It has.

[0065] Multiple diffusion resistors R of the semiconductor substrate 200 DIFF The insulating layer STI is provided between the plurality of diffusion resistors R DIFF The side surfaces of the respective electrodes in the X and Y directions are surrounded by a plurality of diffused resistors R DIFF The surface of the insulating layer STI on the electrode layer GC side is insulated from the electrode installation surface S. G It functions as follows: Electrode mounting surface S G is the diffusion resistance R DIFF Top surface (main surface S) M ) to a position where it contacts the lower surface of the electrode layer GC.

[0066] The electrode layer GC has multiple diffusion resistances R DIFF Electrode mounting surface S of the insulating layer STI between them G , and multiple GC resistors R consisting of electrodes gc GC In FIG. 9, the GC resistor R GC and diffusion resistance R DIFF To distinguish between the GC resistor R GC The same applies to Figures 18, 20, 22, 24 and 25. GC are the electrode placement surfaces S of the insulating layer STI, respectively. G It extends in the Y direction above the DIFF The GC resistors R GC The second connection terminal portion T is provided at the end portion in the Y direction, for example, at both ends. GC It has.

[0067] In this embodiment, a plurality of diffusion resistors R DIFF and multiple GC resistors R GC are arranged alternately in the X direction.

[0068] In this embodiment, the diffusion resistance R DIFF The width W1 in the X direction is the GC resistance R GC The width W3 of the insulating layer STI in the X direction is larger than the width W2 of the GC resistor R GCHowever, the widths W1 and W2 may be substantially equal.

[0069] [Effects of this embodiment] On the surface of the semiconductor substrate 200, in order to prevent variations in the planarization process, it is necessary to ensure that the area covered by electrode gc in a given area (hereinafter referred to as "GC coverage rate") and the area not covered by electrode gc in the same given area (hereinafter referred to as "AA coverage rate") are each 15% to 30% or more. If the resistive element region RES contains a diffusion resistor R DIFF When only a pattern is formed, the diffusion resistance R DIFF Similarly, if the GC resistor R is formed in the resistive element region RES, GC When only the AA pattern is formed, the GC resistor R GC It is necessary to form a fill pattern around the area where the electrode gc does not exist. In either case, an extra fill area other than the resistance element is required, which poses the problem of increasing the cell size accordingly.

[0070] In contrast, in this embodiment, the diffusion resistor R DIFF and GC resistor R GC , and AA are alternately arranged one by one, so that the GC coverage and the AA coverage can be satisfied simultaneously without providing a fill area, and therefore the area of ​​the resistor region RES can be reduced.

[0071] [Modified version of the first embodiment] FIG. 11 is a cross-sectional view corresponding to FIG. 10, showing a modification of the first embodiment. In this modification, the electrode installation surface S of the insulating layer STI G The width W2 in the X direction is the GC resistor R GC In this case, the width W2 of the insulating layer STI in the X direction is substantially equal to the width W1 of the insulating layer STI. G is the diffusion resistance R DIFF Top surface (main surface S) M) protrudes a distance D toward the electrode layer GC, so the GC resistance R GC and diffusion resistance R DIFF can be arranged apart from each other, ensuring mutual insulation. GC and diffusion resistance R DIFF The pitch P1' in the X direction can be made smaller than the pitch P1 in the first embodiment, and the chip area can be further reduced.

[0072] [Diffusion resistance R DIFF and GC resistance R GC [Manufacturing method] 12 to 17 show the diffusion resistor R DIFF and GC resistance R GC 12 to 17 are cross-sectional views for explaining the manufacturing method of the peripheral circuit region R PC In the resistive element region RES and other regions, for example, the memory hole region R MH 1 illustrates a region in which the transistor Tr is formed.

[0073] Diffusion resistance R DIFF and GC resistance R GC In the manufacturing process, for example, as shown in Figure 12, an insulating layer 200G is formed on the surface of a semiconductor substrate 200 on which an N-type diffusion layer 200N (N wells) has been selectively formed in advance. This process is carried out, for example, by thermal oxidation.

[0074] Next, as shown in FIG. 13, an opening 200A is formed at a position corresponding to the insulating layer STI described with reference to FIG. 10. The opening 200A extends in the Z direction and the Y direction, and extends in the X direction at both ends in the Y direction. The opening 200A penetrates the insulating layer 200G and the N-type diffusion layer 200N in the Z direction, and divides a portion of the surface of the semiconductor substrate 200. This step is performed by a method such as RIE.

[0075] Next, as shown in Figure 14, for example, an insulating layer 200H is formed on the semiconductor substrate 200. This process is carried out, for example, by CVD. Here, the opening 200A is filled with the insulating layer 200H.

[0076] Next, as shown in FIG. 15, a part of the insulating layer 200H is removed until the surface of the insulating layer 200G is exposed, and the electrode installation surface S G This step is performed by a method such as CMP.

[0077] Next, as shown in Figure 16, for example, a conductive layer gcA containing polysilicon or tungsten (W), or a two-layer conductive layer gcA of polysilicon and tungsten (W), is formed on the surfaces of the insulating layer STI and the insulating layer 200G. This process is carried out by, for example, CVD, thermal oxidation, or sputtering.

[0078] Next, as shown in Figure 17, for example, a portion of the conductive layer gcA is removed to expose the surface of the semiconductor substrate 200 and form multiple electrodes gc. This process is carried out, for example, by RIE.

[0079] As a result, in the resistive element region RES, the electrode mounting surface S G On top of that, a GC resistor R consisting of electrodes gc GC In addition, the memory hole region R MH In the region where the transistor Tr is formed, a gate made of an electrode gc is formed on the insulating layer 200G.

[0080] Next, P-type impurities such as boron (B) are implanted into the surface of the N-type diffusion layer 200N of the exposed semiconductor substrate 200. This process is carried out, for example, by a method such as ion implantation.

[0081] As a result, in the resistor element region RES, a diffusion resistor R DIFF In addition, the memory hole region R MH In the region where the transistor Tr is formed, P-type diffusion layers that serve as the drain and source are formed on both sides in the Y direction of the electrode gc that serves as the gate.

[0082] [Second embodiment] 18 and 19 show the diffusion resistor R DIFF and GC resistance R GC Fig. 18 is an enlarged plan view of a region corresponding to the region shown in Fig. 9. Fig. 19 is a cross-sectional view taken along line DD' in Fig. 18 and seen from the direction of the arrow.

[0083] In this embodiment, the diffusion resistor R DIFF and GC resistor R GC The diffused resistors R and R are arranged alternately in multiple units (six units in this example) in the X direction. DIFF The width W4 in the X direction of the insulating layer STI between the GC The width W2 in the X direction of the diffused resistor R DIFF The GC resistor R is set to the minimum width that allows insulation between the GC The insulating layer STI on which the six GC resistors R are placed is wider than the width W4. GC The width W5 is set to allow for placement.

[0084] Diffusion resistance R DIFF These are arranged in the X direction at a predetermined pitch P2, and the GC resistor R GC are arranged in the X direction at a pitch of P3. GC The width W2 in the X direction is the diffusion resistance R DIFF If the width W2 in the X direction is smaller than the DIFF and GC resistance R GC If the space in the X direction is constant, the pitch P3 can be made smaller than the pitch P2. DIFF The pitch P2 and the GC resistance R GC The pitch P3 may be the same. Since the other configurations are the same as in the first embodiment, a detailed explanation of the overlapping parts will be omitted.

[0085] In this embodiment, in addition to the same effects as in the first embodiment, the multiple diffusion resistors R DIFF and multiple GC resistors R GCSince multiple units are arranged alternately, the connection pattern can be simplified depending on the configuration of the connection wiring pattern to the connected circuit unit. DIFF and multiple GC resistors R GC The number of these is not limited to six, and can be arbitrarily determined within the range that satisfies the AA coverage and GC coverage.

[0086] [Third embodiment] Figures 20 and 21 show the diffusion resistance R according to the third embodiment. DIFF and GC resistance R GC This figure shows the pattern. Figure 20 is an enlarged plan view of the region corresponding to the region shown in Figure 9. Figure 21 is a cross-sectional view taken along the EE' line in Figure 20, viewed from the direction of the arrow.

[0087] In this embodiment, there are three diffusion resistors R DIFF and one GC resistor R GC and are arranged alternately in the X direction. Adjacent diffusion resistance R in the X direction DIFF The width W4 in the X direction of the insulating layer STI between the GC The width W2 in the X direction of the diffused resistor R DIFF The GC resistor R is set to the minimum width that allows insulation between the GC The insulating layer STI on which the resistor R is placed is wider than the width W4. GC The width W3 is set to allow for placement. Since the other configurations are the same as in the first embodiment, detailed explanations of the overlapping parts are omitted.

[0088] As in this embodiment, the diffusion resistance R DIFF and GC resistor R GC This means that the same number of resistors do not necessarily have to be arranged alternately. GC The diffusion resistance R is greater than DIFF This is a useful pattern when using more. Even in this case, there is no need to provide a fill area, so the area of ​​the resistive element region RES can be reduced.

[0089] [Fourth embodiment] Figures 22 and 23 show the diffusion resistance R according to the fourth embodiment. DIFF and GC resistance R GC Fig. 22 is an enlarged plan view of a region corresponding to the region shown in Fig. 9. Fig. 23 is a cross-sectional view taken along line FF' in Fig. 22 and seen from the direction of the arrow.

[0090] In this embodiment, one diffused resistor R DIFF and three GC resistors R GC The and are arranged alternately in the X direction. GC resistor R GC The insulating layer STI that is placed there has three GC resistors R GC The width W6 is set to allow for placement. Since the other configurations are the same as in the first embodiment, a detailed explanation of the overlapping parts will be omitted.

[0091] As in this embodiment, the diffusion resistance R DIFF and GC resistor R GC This means that the same number of elements do not necessarily have to be arranged alternately. In this embodiment, the diffusion resistance R DIFF than GC resistance R GC This is a useful pattern when using more. Even in this case, there is no need to provide a fill area, so the area of ​​the resistive element region RES can be reduced.

[0092] [Fifth embodiment] Figure 24 shows the diffusion resistance R according to the fifth embodiment. DIFF and GC resistance R GC This figure shows the pattern. Figure 24 is an enlarged plan view of the region corresponding to the region shown in Figure 9.

[0093] In this embodiment, a plurality of diffusion resistors R DIFF and multiple GC resistors R GC These are arranged alternately, one by one, in the X direction. Diffusion resistance R DIFF The length L1 in the Y direction is the GC resistance R GC It is shorter than the length L2 in the Y direction. Multiple diffusion resistances R DIFF At one end in the Y direction, the odd-numbered first connection terminal section T DIFFand the first connection terminal portion T adjacent to one side in the X direction DIFF Wiring W extending in the X direction connecting DIFF Through this, at the other end in the Y direction, the even-numbered first connection terminal section T DIFF and the first connection terminal portion T adjacent to one side in the X direction DIFF Wiring W extending in the X direction connecting DIFF Multiple GC resistors R are connected in series via this. GC At one end in the Y direction, the odd-numbered second connection terminal T GC and a second connection terminal portion T adjacent to one side in the X direction GC Wiring W extending in the X direction connecting GC Through this, at the other end in the Y direction, the even-numbered second connection terminal section T GC and a second connection terminal portion T adjacent to one side in the X direction GC Wiring W extending in the X direction connecting GC They are connected in series via [a specific component]. The other configurations are the same as in the first embodiment, so a detailed explanation of the overlapping parts will be omitted.

[0094] As in this embodiment, the diffusion resistance R DIFF and GC resistor R GC The lengths do not have to be the same. For example, the diffusion resistance R DIFF The length L1 in the Y direction is the GC resistance R GC It may be longer than the length L2 in the Y direction. Also, the diffusion resistance R DIFF and GC resistance R GC By connecting these elements in series with each other, a resistive element having a desired resistance value can be provided.

[0095] [Sixth embodiment] Figure 25 shows the diffusion resistance R according to the sixth embodiment. DIFF and GC resistance R GC This figure shows the pattern. Figure 25 is an enlarged plan view of the region corresponding to the region shown in Figure 9.

[0096] In this embodiment, a plurality of diffusion resistors R DIFF and multiple GC resistors R GCThe diffused resistors R are arranged alternately in the X direction when viewed from the Z direction. DIFF and multiple GC resistors R GC At one end in the Y direction, the second connection terminal portion T is adjacent to the first connection terminal portion T and is arranged at one end in the X direction. GC and the first connection terminal portion T DIFF Wiring W extending in the X direction to connect to DG At the other end in the Y direction, the first connection terminal portion T DIFF and the second connection terminal portion T arranged on the other side of the X direction. GC Wiring W extending in the X direction to connect to DG The other configurations are the same as those in the first embodiment, so detailed explanations of overlapping parts will be omitted.

[0097] According to this embodiment, the diffusion resistance R DIFF and GC resistance R GC By alternately connecting these in series, a resistor element having a desired resistance value can be provided.

[0098] [Other embodiments] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, the configurations described above are merely examples, and the specific configurations can be adjusted as appropriate.

[0099] For example, in each of the above embodiments, the diffusion resistor R DIFF The P-type diffusion layer 200P formed in the N-type diffusion layer 200N (N-well) was used as the diffusion resistor R DIFF Alternatively, an N-type diffusion layer 200N formed in a P-type diffusion layer 200P (P-well) can be used as the N-type diffusion layer 200N.

[0100] In addition, the diffusion resistor R DIFF and GC resistance R GC Some of them may be used as dummy resistors that are not connected to any circuit.

[0101] In the above embodiments, examples of application to NAND flash memories have been described. However, the technology described in this specification can also be applied to configurations other than NAND flash memories, such as three-dimensional NOR flash memories. The technology described in this specification can also be applied to semiconductor memory devices other than flash memories, such as three-dimensional DRAMs, and semiconductor devices other than semiconductor memory devices.

[0102] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0103] 110...conductive layer, 120...semiconductor layer (semiconductor column), 200, 500...semiconductor substrate, C M ...Chip (1st chip), C P ...chip (second chip), BL...bit line, WL...word line, SG...select gate line, CC...via contact electrode, MC...memory cell, M0, M1, D0, D1, D2, D3, D4, D100, D101, D102, D103...wiring layer, GC...electrode layer, gc...electrode, MB, DB...chip bonding electrode layer, RES...resistance element area, MDA, MDB, MDC...circuit module area, R DIFF ...diffusion resistance, R GC ...GC resistance, STI...insulating layer, T DIFF ...first connection terminal part, T GC ...Second connection terminal section.

Claims

1. a semiconductor substrate; an electrode layer provided on a side opposite to the main surface of the semiconductor substrate; In a semiconductor device comprising: a plurality of first resistance elements each including a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, aligned in a second direction parallel to the main surface of the semiconductor substrate and intersecting the first direction, and having a first connection terminal portion at an end side in the first direction; an insulating layer disposed between the plurality of first resistor elements on the semiconductor substrate and having an electrode placement surface in contact with the electrode layer; a plurality of second resistance elements each including a plurality of conductive layers provided on the electrode installation surface of the insulating layer between the plurality of first resistance elements, extending in the first direction, aligned in the second direction, and having a second connection terminal portion on an end side in the first direction; A semiconductor device comprising:

2. The plurality of first resistance elements and the plurality of second resistance elements are alternately arranged one by one in the second direction. The semiconductor device according to claim 1.

3. The plurality of first resistance elements and the plurality of second resistance elements are alternately arranged in the second direction in units of a plurality of elements. The semiconductor device according to claim 1.

4. One second resistance element of the plurality of second resistance elements is disposed between some of the plurality of first resistance elements and another part of the plurality of first resistance elements. The semiconductor device according to claim 1.

5. One first resistance element of the plurality of first resistance elements is disposed between some of the plurality of second resistance elements and another part of the plurality of second resistance elements. The semiconductor device according to claim 1.

6. The plurality of diffusion layers are P-type diffusion layers. The semiconductor device according to claim 1.

7. The plurality of diffusion layers are N-type diffusion layers. The semiconductor device according to claim 1.

8. the plurality of first resistance elements are connected in series via the first connection terminal portion, The plurality of second resistance elements are connected in series via the second connection terminal portion. The semiconductor device according to claim 1.

9. The plurality of first resistance elements and the plurality of second resistance elements are alternately connected in series via the first connection terminal portion and the second connection terminal portion. The semiconductor device according to claim 1.

10. a transistor having a gate electrode; The gate electrode of the transistor and the second resistive element are formed in the same electrode layer. The semiconductor device according to claim 1.

11. No other conductive layer is disposed at a position of the electrode layer that overlaps with the plurality of first resistance elements in a third direction that intersects with the first direction and the second direction. The semiconductor device according to claim 1.

12. The electrode mounting surface of the insulating layer protrudes toward the electrode layer side from the main surface of the semiconductor substrate. The semiconductor device according to claim 1.

13. The width of the electrode mounting surface of the insulating layer in the second direction is substantially equal to the width of the second resistive element in the second direction.

13. The semiconductor device according to claim 12.

14. The width of the first resistive element in the second direction is greater than the width of the second resistive element in the second direction. The semiconductor device according to claim 1.

15. The pitch of the plurality of first resistive elements in the second direction is greater than the pitch of the plurality of second resistive elements in the second direction.

4. The semiconductor device according to claim 3.

16. The length of the first resistive element in the first direction is different from the length of the second resistive element in the first direction. The semiconductor device according to claim 1.

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