Redistribution layer and method for manufacturing the same

Abstract

The present invention provides a redistribution layer and a method for manufacturing the same that suppress the increase in dielectric loss. [Solution] In the wiring board group, the rewiring layer comprises at least one wiring layer 20A, 20B including a plurality of wirings 27 including a bottom surface, an upper surface and two side surfaces, an inorganic layer 23 including at least a plurality of upper surface portions located on the upper surface of each wiring, and an organic layer 22 located on the inorganic layer. The plurality of wirings include at least a first wiring 27A and a second wiring 27B adjacent to the first wiring. The inorganic layer includes an upper surface portion 231 located on the upper surface of the first wiring and an upper surface portion 232 connecting the upper surface portion located on the upper surface of the second wiring.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a redistribution layer and a method for manufacturing the same.

Background Art

[0002] Packaging technologies for densely mounting a plurality of semiconductor elements with different functions, such as CPUs and memories, on a single substrate have attracted attention. A structure for electrically connecting a plurality of semiconductor elements is also referred to as an interposer. The interposer includes, for example, a wiring layer including a conductive layer and an insulating layer. The wiring layer serves, for example, to relocate pads or terminals of semiconductor elements to another location. A structure in which a plurality of wiring layers are stacked is also referred to as a redistribution layer.

[0003] Each wiring layer includes a plurality of wirings and an insulating layer that at least partially covers the plurality of wirings. Patent Document 1 discloses a structure in which the insulating layer includes an inorganic layer that at least partially covers the plurality of wirings and an organic layer that covers the inorganic layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As the frequency of an electrical signal transmitted by a wiring increases, transmission loss is more likely to occur between two adjacent wirings. An example of transmission loss is dielectric loss. Dielectric loss is a phenomenon in which part of the energy of an electric field generated due to an electrical signal transmitted by a wiring is converted into heat and lost inside a dielectric. The higher the dielectric tangent of the organic layer disposed between two adjacent wirings, the greater the dielectric loss.

[0006] The embodiments of this disclosure aim to provide a redistribution layer and a method for manufacturing the same that can effectively solve the aforementioned problems. [Means for solving the problem]

[0007] Embodiments of this disclosure relate to the following [1] to

[18] . [1] A redistribution layer, The wiring comprises at least one wiring layer including a plurality of wirings including a bottom surface, a top surface and two side surfaces, an inorganic layer including at least a plurality of top surface portions located on the top surface of each wiring, and an organic layer located on the inorganic layer, Each of the aforementioned wirings includes at least a first wiring and a second wiring adjacent to the first wiring, The inorganic layer is a rewiring layer that includes an upper surface connecting portion that connects the upper surface portion located on the upper surface of the first wiring and the upper surface portion located on the upper surface of the second wiring.

[0008] [2] In the rewiring layer described in [1], the at least one wiring layer may include a void located below the upper connection portion.

[0009] [3] In the redistribution layer described in [2], the inorganic layer may include a plurality of side portions located on the two sides of each wiring and connected to each of a plurality of upper portions located on the upper surface of each wiring.

[0010] In the redistribution layer described in [4] [3], each of the multiple side portions may include a portion in which the thickness of the side portion decreases as it extends downward from the upper portion.

[0011] In the redistribution layer described in [5] [3] or [4], the two sides of the first wiring may include an inner side facing the side of the second wiring and an outer side, and one of the two sides of the second wiring may be an inner side facing the inner side of the first wiring, and the inorganic layer may include a bottom connection portion connecting the side portion located on the inner side of the first wiring and the side portion located on the inner side of the second wiring, and the void may be located between the top connection portion and the bottom connection portion.

[0012] In the redistribution layer described in [6] [5], each of the multiple side portions may include a portion in which the thickness of the side portion decreases as it extends upward from the bottom connection portion.

[0013] In the redistribution layer described in [7] [3] or [4], the two sides of the first wiring may include an inner side facing the side of the second wiring and an outer side, and one of the two sides of the second wiring may be an inner side facing the inner side of the first wiring, and the inner side of the first wiring and the inner side of the second wiring may each include a portion in contact with the void.

[0014] In the rewiring layer described in [8] [7], the entire area of ​​the outer side surface of the first wiring may be covered by the side portion.

[0015] In the rewiring layer described in any one of [9] [2] to [8], the ratio of the width of the gap to the spacing between the wirings may be 0.40 or more.

[0016] In the rewiring layer described in any one of

[10] [2] to [9], the ratio of the thickness of the void to the height of the wiring may be 0.50 or more.

[0017]

[11] In the rewiring layer according to any one of [1] to

[10] , the ratio of the height of the wiring to the interval between the wirings may be 1.50 or more and 5.00 or less.

[0018]

[12] In the rewiring layer according to [1], the inorganic layer may be filled without a gap between the first wiring and the second wiring.

[0019]

[13] A method for manufacturing a rewiring layer, comprising a rewiring step of forming a rewiring layer including at least one wiring layer on a substrate, wherein the at least one wiring layer includes a plurality of wirings including a lower surface, an upper surface, and two side surfaces, an inorganic layer including at least a plurality of upper surface portions located on the upper surface of each wiring, and an organic layer located on the inorganic layer, the rewiring step includes a step of forming the plurality of wirings, an inorganic layer forming step of forming the inorganic layer on the plurality of wirings, and an organic layer forming step of forming the organic layer on the inorganic layer, the inorganic layer forming step is performed such that the upper surface portions located on the upper surfaces of two adjacent wirings are connected to each other, a method for manufacturing a rewiring layer.

[0020]

[14] In the method for manufacturing a rewiring layer according to

[13] , the inorganic layer forming step may include a step of forming the inorganic layer by physical vapor deposition.

[0021]

[15] In the method for manufacturing a rewiring layer according to

[14] , the inorganic layer forming step may include a first step of performing physical vapor deposition along a direction inclined with respect to the thickness direction of the substrate, and a second step of performing physical vapor deposition along a direction inclined with respect to the thickness direction on the opposite side to the first step.

[0022]

[16] In the method for manufacturing a rewiring layer according to

[13] , the inorganic layer forming step may include a step of forming the inorganic layer by chemical vapor deposition.

[0023]

[17] In the method for manufacturing a rewiring layer described in

[13] , the inorganic layer forming step may include a step of forming the inorganic layer by an atomic layer deposition method and a step of forming the inorganic layer by a physical vapor deposition method or a chemical vapor deposition method.

[0024]

[18] In the method for manufacturing a rewiring layer according to any one of

[13] to

[17] , the ratio of the height of the wiring to the interval between the wirings may be 1.50 or more and 5.00 or less.

Advantages of the Invention

[0025] According to an embodiment of the present disclosure, dielectric loss between two adjacent wirings is reduced.

Brief Description of the Drawings

[0026] [Figure 1] It is a plan view showing a wiring board group according to an embodiment. [Figure 2] It is a cross-sectional view of the wiring board group along the line II-II of FIG. 1. [Figure 3] It is a cross-sectional view showing an example of a rewiring layer. [Figure 4] It is a cross-sectional view showing an example of a second wiring layer. [Figure 5] It is a cross-sectional view showing an example of a wiring and an inorganic layer. [Figure 6] It is a plan view showing an example of a wiring and an inorganic layer. [Figure 7] It is a cross-sectional view showing a step of forming a first wiring layer. [Figure 8] It is a cross-sectional view showing a step of forming a second opening in an organic layer of a first wiring layer. [Figure 9] It is a cross-sectional view showing a step of forming an adhesion layer and a seed layer of a second wiring layer. [Figure 10] It is a cross-sectional view showing a step of forming a plating layer of a second wiring layer. [Figure 11] It is a cross-sectional view showing a step of removing a part of an adhesion layer and a seed layer of a second wiring layer. [Figure 12]This is a cross-sectional view showing the process of forming the inorganic layer of the second wiring layer. [Figure 13] This is a cross-sectional view showing the process of forming a first opening in the inorganic layer of the second wiring layer. [Figure 14] This is a cross-sectional view showing the process of forming the organic layer of the second wiring layer. [Figure 15] This is a cross-sectional view showing the process of forming a conductive layer on the second wiring layer. [Figure 16] This is a cross-sectional view showing an example of the process for forming an inorganic layer. [Figure 17] This is a cross-sectional view showing an example of the process for forming an inorganic layer. [Figure 18] This is a cross-sectional view showing the process of bonding the upper surface of the redistribution layer to the substrate. [Figure 19] This is a cross-sectional view showing the process of irradiating the peeling layer with light. [Figure 20] This is a cross-sectional view showing the process of separating the redistribution layer from the carrier substrate. [Figure 21] This is a cross-sectional view showing the process of forming the organic layer of the second wiring layer in the first modified example. [Figure 22] This is a cross-sectional view showing the process of forming the organic layer of the second wiring layer in the second modified example. [Figure 23] This is a cross-sectional view showing the process of forming a second opening in the inorganic layer of the second wiring layer in the second modified example. [Figure 24] This is a cross-sectional view showing an example of an inorganic layer in the third modified example. [Figure 25] The third modified example is a cross-sectional view showing an example of the process for forming an inorganic layer. [Figure 26] The third modified example is a cross-sectional view showing an example of the process for forming an inorganic layer. [Figure 27] This is a cross-sectional view showing an example of an inorganic layer in the fourth modified example. [Figure 28] The fourth modified example is a cross-sectional view showing an example of the process for forming the inorganic layer. [Figure 29] The fourth modified example is a cross-sectional view showing an example of the process for forming the inorganic layer. [Figure 30]This is a cross-sectional view showing an example of an inorganic layer in the fifth modified example. [Figure 31] This is a cross-sectional view showing an example of the process for forming the inorganic layer in the fifth modified example. [Figure 32] This is a cross-sectional view showing an example of the process for forming the inorganic layer in the sixth modified example. [Figure 33] This is a cross-sectional view showing an example of the process for forming the inorganic layer in the sixth modified example. [Figure 34] This is a cross-sectional view showing an example of the process for forming the inorganic layer in the sixth modified example. [Figure 35] This is a cross-sectional view showing an example of the process for forming the inorganic layer in the sixth modified example. [Figure 36] This figure shows an example of a product that incorporates a redistribution layer. [Modes for carrying out the invention]

[0027] In this specification, unless otherwise specified, terms meaning base materials such as "substrate," "base material," "board," "sheet," and "film" are not distinguished from each other solely on the basis of differences in name. For example, "substrate" is a concept that includes materials that may be called sheets or films.

[0028] In this specification, unless otherwise specified, the term "plane" refers to the plane of a plate-like member in question that coincides with the planar direction of the member when viewed as a whole and in a broad sense. The term "normal direction" as used with respect to a plate-like member refers to the direction normal to the plane of the member.

[0029] In this specification, unless otherwise specified, terms relating to shape and geometric conditions, as well as values ​​that specify the degree of shape and geometric conditions, may be interpreted based on the function they achieve, without being bound by their strict meaning. Examples of terms relating to shape and geometric conditions include "parallel" and "orthogonal." Examples of values ​​that specify the degree of shape and geometric conditions include length values ​​and angle values.

[0030] In this specification and these drawings, unless otherwise specified, when the positional relationship of a second component to a first component is described using terms such as "above," "below," "upper side," "lower side," "upward," or "downward," the second component may or may not be in contact with the first component. In this specification and these drawings, unless otherwise specified, when the positional relationship of a second component to a first component is described using terms such as "above," "upper side," or "upward," depending on the usage conditions of the product, the second component may be located "below," "downward," or "downward" of the first component.

[0031] In this specification, if multiple candidate upper limits and multiple candidate lower limits are given for a certain parameter, the numerical range of that parameter may be constructed by combining any one candidate upper limit and any one candidate lower limit. For example, consider the case where it is stated that "Parameter B is, for example, A1 or greater, and may be A2 or greater, and may be A3 or greater. Parameter B is, for example, A4 or less, and may be A5 or less, and may be A6 or less." In this case, the numerical range of parameter B may be A1 or greater and A4 or less, A1 or greater and A5 or less, A1 or greater and A6 or less, A2 or greater and A4 or less, A2 or greater and A5 or less, A2 or greater and A6 or less, A3 or greater and A4 or less, A3 or greater and A5 or less, and A3 or greater and A6 or less.

[0032] In this specification and these drawings, unless otherwise specified, identical parts or components having similar functions are denoted by the same or similar reference numerals. Dimensional ratios in the drawings may differ from actual ratios for illustrative purposes. In this specification and these drawings, some components may be omitted from the drawings.

[0033] In this specification and these drawings, unless otherwise specified, one embodiment of this specification may be combined with other embodiments or modifications, to the extent that it does not contradict. Other embodiments or modifications may also be combined with each other, to the extent that it does not contradict.

[0034] In this specification and these drawings, unless otherwise specified, when multiple steps are disclosed regarding a method such as a manufacturing method, other steps not disclosed may be performed between the disclosed steps. The order of the disclosed steps may be changed to the extent that it does not create a contradiction.

[0035] The configuration of the redistribution layer and its manufacturing method will be described in detail with reference to the drawings. However, the technical concept of the embodiments of this disclosure shall not be construed as being limited only to the following specific embodiments.

[0036] Figure 1 is a plan view showing an example of a wiring board group 10. Figure 2 is a cross-sectional view of the wiring board group 10 in Figure 1 along line II-II. The wiring board group 10 includes multiple wiring boards having the same structure. As will be described later, multiple wiring boards can be obtained by dividing the wiring board group 10. Each of the multiple wiring boards has a redistribution layer. That is, the wiring board group 10 has multiple redistribution layers 20.

[0037] The wiring board group 10 has a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 are included in the planar direction of the wiring board group 10. The first direction D1 is perpendicular to the second direction D2. The third direction D3 is the thickness direction of the wiring board group 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0038] The wiring board group 10 comprises a carrier substrate 12, a release layer 13, and a plurality of redistribution layers 20. The release layer 13 is located between the carrier substrate 12 and the redistribution layers 20 in the thickness direction of the wiring board group 10. The release layer 13 is located on the carrier substrate 12.

[0039] Although not shown in the diagram, the member supporting the redistribution layer 20 is not limited to the carrier substrate 12. For example, instead of the carrier substrate 12, the redistribution layer 20 may be placed on an electrode substrate having an opening that penetrates its upper and lower surfaces, with metal wiring formed in the opening. The electrode located in the opening may be connected to the conductive layer of the redistribution layer 20.

[0040] The redistribution layer 20 may be provided on either the front or back surface of a substrate such as a carrier substrate 12 or an electrode substrate, or on both the front and back surfaces. The conductive layer pattern of the redistribution layer 20 located on the back surface may be the same as or different from the conductive layer pattern of the redistribution layer 20 located on the front surface.

[0041] The individual components of the wiring board group 10 will now be described.

[0042] (Rewiring layer) Multiple redistribution layers 20 have the same structure as each other. For example, as shown in Figure 1, multiple redistribution layers 20 may have the same structure in a plan view. As shown in Figure 1, multiple redistribution layers 20 may be regularly arranged in the planar direction of the wiring board group 10. For example, multiple redistribution layers 20 may be regularly arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be directions parallel to the edges of the carrier substrate 12. "Planar view" means viewing the object along a third direction D3.

[0043] Figure 2 is a cross-sectional view of the wiring board group 10 along line II-II in Figure 1. The redistribution layer 20 includes a bottom surface 201 and an top surface 202. The bottom surface 201 faces the carrier substrate 12. The top surface 202 is located on the opposite side of the bottom surface 201. The redistribution layer 20 includes an insulating layer 21 and a plurality of conductive layers 25. The insulating layer 21 at least partially covers the conductive layers 25.

[0044] In this specification, "bottom surface" such as bottom surface 201 means the surface facing the carrier substrate 12 in the state of the wiring board group 10. "Top surface" means the surface located on the opposite side of the "bottom surface" in the thickness direction.

[0045] Some of the multiple conductive layers 25 may be pads 26. A pad 26 may have an upper or lower surface that includes a portion that is not in contact with an insulating material such as an insulating layer 21. For example, if a pad 26 is located on the lower surface 201 of the rewiring layer 20, the lower surface of the pad 26 is not in contact with an insulating material. For example, if a pad 26 is located on the upper surface 202 of the rewiring layer 20, the upper surface of the pad 26 is not in contact with an insulating material. For example, if a portion of the upper surface of the pad 26 is connected to a through electrode described later, the upper surface of the pad 26 can be said to include a portion that is not in contact with an insulating material. In a plan view, the pad 26 has dimensions that are larger than the dimensions of the wiring and the through electrode described later.

[0046] Some of the multiple conductive layers 25 may be wiring 27. The wiring 27 extends at least partially in a first direction D1 or a second direction D2. Both the upper and lower surfaces of the wiring 27 may be in contact with an insulating material such as an insulating layer 21. The insulating material has insulating properties. The insulating material may be an organic material or an inorganic material.

[0047] Some of the multiple conductive layers 25 may be through electrodes 28. These through electrodes 28 are also referred to as vias. The through electrodes 28 extend in a third direction D3. For example, the through electrodes 28 are located in openings formed in the insulating layer 21. The through electrodes 28 can electrically connect the conductive layers 25 of two adjacent wiring layers in the third direction D3, for example. The through electrodes 28 may be connected to pads 26.

[0048] The redistribution layer 20 may include a plurality of stacked wiring layers. In the example shown in Figure 2, the redistribution layer 20 includes a first wiring layer 20A and a second wiring layer 20B. Each of the plurality of wiring layers may include an insulating layer 21 and a plurality of conductive layers 25. In each of the plurality of wiring layers, the insulating layer 21 at least partially covers the conductive layer 25.

[0049] The first wiring layer 20A may constitute the lower surface 201 of the rewiring layer 20. The insulating layer 21 of the second wiring layer 20B may constitute the upper surface 202 of the rewiring layer 20. The wiring board group 10 may include a conductive layer 25 located on the insulating layer 21 of the second wiring layer 20B that constitutes a pad 26.

[0050] The redistribution layer 20 has a thickness T1. The thickness T1 is, for example, 6 μm or more, may be 12 μm or more, or 18 μm or more. The thickness T1 is, for example, 100 μm or less, may be 90 μm or less, or 80 μm or less. The thickness T1 is the distance in the third direction D3 from the bottom surface 201 to the top surface 202. The dimensions of the components of the wiring board group 10, such as the thickness T1, are calculated based on a cross-sectional image of the wiring board group 10 taken by a scanning electron microscope.

[0051] The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 may be, for example, 3.0 μm or more, or 6.0 μm or more. The thickness T2 of each of the multiple wiring layers in the redistribution layer 20 may be, for example, 26.0 μm or less, or 10.0 μm or less. The thicknesses T2 of the multiple wiring layers may be the same or different.

[0052] Figure 3 is a cross-sectional view showing an example of a rewiring layer 20. In multiple wiring layers, the insulating layer 21 includes an organic layer 22. In at least one wiring layer, the insulating layer 21 may include an organic layer 22 and an inorganic layer 23.

[0053] In the example shown in Figure 3, the insulating layer 21 of the first wiring layer 20A includes an organic layer 22. The organic layer 22 of the first wiring layer 20A may be in contact with the conductive layer 25 such that it at least partially covers the conductive layer 25. "Covering" means that when the rewiring layer 20 is viewed along the direction normal to the lower surface 201, the organic layer 22 and the conductive layer 25 overlap at least partially.

[0054] In the example shown in Figure 3, the insulating layer 21 of the second wiring layer 20B includes an organic layer 22 and an inorganic layer 23. The inorganic layer 23 of the second wiring layer 20B may be in contact with the conductive layer 25 so as to at least partially cover it. The organic layer 22 of the first wiring layer 20A may be located on the inorganic layer 23. The portion of the inorganic layer 23 of the second wiring layer 20B that does not overlap with the conductive layer 25 may be in contact with the organic layer 22 of the first wiring layer 20A.

[0055] At least one of the multiple wiring layers of the redistribution layer 20 includes multiple wirings 27, an inorganic layer 23 located on the multiple wirings 27, and an organic layer 22 located on the inorganic layer 23. In the example shown in Figure 3, the second wiring layer 20B includes multiple wirings 27, an inorganic layer 23 located on the multiple wirings 27, and an organic layer 22 located on the inorganic layer 23.

[0056] As shown in Figure 3, the inorganic layer 23 may be configured such that the organic layer 22 is not placed between two adjacent wirings 27. In the example shown in Figure 3, the space between two adjacent wirings 27 is covered by the inorganic layer 23 located above the space. As will be described later, in each wiring layer, the organic layer 22 is formed after the inorganic layer 23 is formed on the conductive layer 25 such as the wiring 27. Since the space between two adjacent wirings 27 is covered by the inorganic layer 23, the organic layer 22 is not formed between the two adjacent wirings 27. As a result, a void 29 may be formed between two adjacent wirings 27. A "void" means a space surrounded by a solid, where no solid or liquid exists.

[0057] Since the organic layer 22 is not placed between two adjacent wirings 27, the dielectric loss tangent in the space between the two adjacent wirings 27 is reduced. As a result, the dielectric loss between the two adjacent wirings is reduced.

[0058] Since no organic layer 22 is placed between two adjacent wirings 27, the relative permittivity in the space between the two adjacent wirings 27 may be reduced. As a result, the dielectric loss between the two adjacent wirings may be reduced.

[0059] The organic layer 22 contains an insulating organic material. Examples of organic materials include polyimide, epoxy, and acrylic.

[0060] The organic layer 22 may contain multiple fillers distributed within the organic material. By mixing multiple fillers into the organic material, the mechanical properties, thermal properties, etc., of the organic layer 22 are adjusted. The fillers may contain inorganic materials or organic materials. An example of a filler material is silicon dioxide.

[0061] The inorganic layer 23 contains an inorganic material. Examples of inorganic materials include metallic materials, inorganic oxides, and inorganic nitrides. The inorganic material may also be insulating. For example, the inorganic material may be an insulating inorganic oxide or inorganic nitride. An inorganic oxide is, for example, silicon oxide such as SiO2. An inorganic nitride is, for example, silicon nitride such as SiN. The inorganic material may also be SiOC, SiC, SiFO, SiON, SiCN, etc.

[0062] The inorganic layer 23 may consist of a single layer made of the inorganic material described above. Alternatively, the inorganic layer 23 may include multiple layers. For example, the inorganic layer 23 may include a first inorganic layer in contact with the conductive layer 25 and a second inorganic layer located on the first inorganic layer. The first inorganic layer may have higher adhesion to the conductive layer 25 than the second inorganic layer. The second inorganic layer may have a lower dielectric constant than the first inorganic layer. For example, the first inorganic layer may contain a silicon nitride such as SiN, and the second inorganic layer may contain a silicon oxide such as SiO2.

[0063] The thermal expansion coefficient of the inorganic material in the inorganic layer 23 is smaller than that of the organic material in the organic layer 22. The thermal expansion coefficient of the inorganic layer 23 is, for example, 10.0 ppm / °C or less, but may also be 8.0 ppm / °C or less, or 5.0 ppm / °C or less.

[0064] The thickness of the inorganic layer 23 is, for example, 0.10 μm or more, may be 0.30 μm or more, or 0.50 μm or more. The thickness of the inorganic layer 23 is, for example, 5.0 μm or less, may be 3.0 μm or less, or 1.0 μm or less.

[0065] The process for forming the redistribution layer 20 may include steps performed at high temperatures, such as a heating step for the organic layer 22. The thermal expansion coefficient of the organic material in the organic layer 22 is greater than that of the other components of the redistribution layer 20. For example, the thermal expansion coefficient of the organic material in the organic layer 22 is greater than that of the substrate, such as the carrier substrate 12. For example, the thermal expansion coefficient of the organic material in the organic layer 22 is greater than that of the conductive layer 25. After the heating step, when the temperature of the components of the redistribution layer 20 decreases, stress may be generated due to the difference between the thermal expansion coefficient of the organic layer 22 and that of the other components. For example, stress may be generated in the substrate, the conductive layer 25, etc.

[0066] According to this embodiment, since the redistribution layer 20 includes an inorganic layer 23, the stress caused by the organic layer 22 is suppressed from affecting components other than the inorganic layer 23. For this reason, for example, warping of the redistribution layer 20, the wiring board group 10, or the wiring board 11 is suppressed. By suppressing the occurrence of stress in the conductive layer 25, the occurrence of defects such as deformation and damage in the conductive layer 25 may also be suppressed.

[0067] The conductive layer 25 contains a conductive material. The conductive layer 25 may contain metals such as copper, gold, silver, platinum, palladium, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these metals. The thickness T3 of the conductive layer 25 is, for example, 0.1 μm or more, may be 0.5 μm or more, or may be 1.0 μm or more. The thickness T3 of the conductive layer 25 is, for example, 15.0 μm or less, may be 10.0 μm or less, or may be 6.0 μm or less.

[0068] As described later, the conductive layer 25 may include a seed layer and a plating layer. The seed layer is a conductive layer formed by a physical vapor deposition method such as sputtering. The plating layer is a conductive layer formed on the seed layer by an electroplating process. The conductive layer 25 may also include an adhesion layer located between the insulating layer 21 and the seed layer. The adhesion layer may be a conductive layer, and may be a layer of metal oxide or metal nitride. It may also be a laminate of these.

[0069] The material of the adhesion layer is different from the material of the seed layer and the material of the plating layer. Examples of adhesion layer materials include titanium, molybdenum, tungsten, tantalum, nickel, chromium, aluminum, compounds thereof, alloys thereof, or oxides and nitrides thereof. The adhesion layer may have higher adhesion to the insulating layer 21 than the seed layer.

[0070] The seed layer may contain metallic materials such as copper, nickel, titanium, chromium, zinc, and gold. The seed layer may also contain compounds of these metallic materials. The seed layer may consist of multiple layers. The plating layer may contain metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these materials.

[0071] The structure of the wiring 27 and inorganic layer 23 of the second wiring layer 20B will be described in detail. Figure 4 is a cross-sectional view showing an example of the second wiring layer 20B.

[0072] (wiring) The structure of the wiring 27 will now be described in detail. As shown in Figure 4, each of the multiple wirings 27 includes an upper surface 271, a lower surface 272, and two side surfaces 273. The upper surface 271 is covered by an inorganic layer 23. The lower surface 272 is located opposite the upper surface 271 in the third direction D3. The lower surface 272 of the wiring 27 of the second wiring layer 20B faces the insulating layer 21 of the first wiring layer 20A. The lower surface 272 of the wiring 27 of the second wiring layer 20B may also be in contact with the organic layer 22 of the first wiring layer 20A. The side surfaces 273 are located between the upper surface 271 and the lower surface 272.

[0073] The multiple wirings 27 arranged in the planar direction of the redistribution layer 20 include, for example, a first wiring 27A, a second wiring 27B, and a third wiring 27C. The second wiring 27B is located between the first wiring 27A and the third wiring 27C. The first wiring 27A and the second wiring 27B are adjacent. The second wiring 27B and the third wiring 27C are adjacent.

[0074] Each of the multiple wires 27 may be a signal wire or a ground wire. A signal wire is a wire that transmits an electrical signal. A ground wire is a wire that is connected to ground potential. For example, the second wire 27B may be a signal wire, and the first wire 27A and the third wire 27C may be ground wires.

[0075] The two sides 273 of each wiring 27 may be classified as either an inner side 2731 or an outer side 2732. An inner side 2731 is the side facing the side 273 of another adjacent wiring 27. An outer side 2732 is the wiring 27 that does not face any other wiring. In the example shown in Figure 4, both sides 273 of the second wiring 27B are inner sides 2731. The first wiring 27A includes an inner side 2731 facing the inner side 2731 of the second wiring 27B and an outer side 2732. The third wiring 27C includes an inner side 2731 facing the inner side 2731 of the second wiring 27B and an outer side 2732.

[0076] The wiring 27 has a width W1 and a height H1. The width W1 is the dimension of the wiring 27 in a direction perpendicular to the direction in which the wiring 27 extends and which is included in the in-plane direction of the lower surface 201 of the rewiring layer 20. In the example shown in Figure 4, the width W1 is the dimension of the wiring 27 in the first direction D1. The width W1 is measured at an intermediate position of the wiring 27 in the third direction D3. The height H1 is the dimension of the wiring 27 in the third direction D3. The height H1 is measured at an intermediate position of the wiring 27 in the direction in which the width W1 is measured.

[0077] The width W1 of the wiring 27 is, for example, 1.0 μm or more, may be 2.0 μm or more, or may be 3.0 μm or more. The width W1 is, for example, 10.0 μm or less, may be 8.0 μm or less, or may be 6.0 μm or less.

[0078] The smaller the width W1, the more wires 27 can be placed per unit area of ​​the rewiring layer 20. On the other hand, the smaller the width W1, the greater the electrical resistance of the wires 27. When the width W1 is small, it is preferable to have a large height H1 for the wires 27. By increasing the height H1, the electrical resistance of the wires 27 is kept low.

[0079] The ratio of height H1 to width W1, H1 / W1, is also called the aspect ratio of the wiring 27. The aspect ratio of the wiring 27 is, for example, 1.0 or greater, may be 1.5 or greater, or may be 2.0 or greater. The aspect ratio of the wiring 27 is, for example, 5.0 or less, may be 4.0 or less, or may be 3.0 or less.

[0080] The symbol K1 represents the spacing between two adjacent wires 27. The spacing K1 is measured at the midpoint in the third direction D3 of the wire 27 having the lower height H1 of the two adjacent wires 27.

[0081] The spacing K1 is, for example, 2.0 μm or less, may be 1.7 μm or less, or 1.5 μm or less. By reducing the spacing K1, the space between two adjacent wirings 27 is more easily covered by the inorganic layer 23. The spacing K1 is, for example, 0.5 μm or more, may be 0.7 μm or more, or 1.0 μm or more.

[0082] The ratio of height H1 to spacing K1, H1 / K1, is also called the spatial aspect ratio. Height H1 is the smaller of the heights H1 of two adjacent wirings 27. The spatial aspect ratio is, for example, 1.0 or greater, may be 1.5 or greater, or 2.0 or greater. The spatial aspect ratio is, for example, 5.0 or less, may be 4.0 or less, or 3.0 or less.

[0083] Each of the multiple wirings 27 includes two corners 274. Each of the two corners 274 is located between the top surface 271 and the two sides 273.

[0084] Figure 5 is a cross-sectional view showing an example of wiring 27 and inorganic layer 23. One of the two corners 274 is determined based on the position where wiring 27 is tangent to a hypothetical straight line M1 inclined at an angle of +θ with respect to the third direction D3 in the cross-sectional view of wiring 27. The other of the two corners 274 is determined based on the position where wiring 27 is tangent to a hypothetical straight line M2 inclined at an angle of -θ with respect to the third direction D3 in the cross-sectional view of wiring 27. θ is 30°.

[0085] (Inorganic layer) The structure of the inorganic layer 23 will now be described in detail. As shown in Figure 4, the inorganic layer 23 includes multiple upper surface portions 231 located on the upper surface 271 of multiple wirings 27, and upper surface connecting portions 232 that connect two adjacent upper surface portions 231. For example, the upper surface portion 231 located on the upper surface 271 of the first wiring 27A and the upper surface portion 231 located on the upper surface 271 of the second wiring 27B are connected by one upper surface connecting portion 232. For example, the upper surface portion 231 located on the upper surface 271 of the second wiring 27B and the upper surface portion 231 located on the upper surface 271 of the third wiring 27C are connected by another upper surface connecting portion 232.

[0086] The combination of multiple upper surface portions 231 and multiple upper surface connection portions 232 covers the space between multiple wirings 27 arranged in the in-plane direction on the lower surface 201 of the redistribution layer 20. As a result, as shown in Figure 4, gaps 29 are formed in the space between the multiple wirings 27. Each of the multiple gaps 29 is located below the upper surface connection portion 232. "Downward" means the direction toward the lower surface 201 of the redistribution layer 20 in the third direction D3. "Upward," which will be described later, means the direction toward the upper surface 202 of the redistribution layer 20 in the third direction D3.

[0087] The upper portion 231 has a thickness T3. Thickness T3 is the dimension of the upper portion 231 in the third direction D3. Thickness T3 is measured at the midpoint of the wiring 27 in the measurement direction of the width W1.

[0088] The thickness T3 may be more than half of the spacing K1. Having a thickness T3 that is more than half of the spacing K1 facilitates connection between the upper portions 231 of two adjacent wirings 27. The ratio of thickness T3 to spacing K1, T3 / K1, is, for example, 0.50 or more, may be 0.60 or more, or 0.70 or more. T3 / K1 is, for example, 1.00 or less, may be 0.90 or less, or 0.80 or less.

[0089] As shown in Figure 4, the inorganic layer 23 may include a plurality of side portions 233. Each of the plurality of side portions 233 is located on the side 273 of the wiring 27. Each of the plurality of side portions 233 is connected to the corresponding top portion 231.

[0090] The side portion 233 and the top portion 231 may be distinguished based on the position of the corners 274 of the wiring 27. For example, as shown in Figure 5, the side portion 233 and the top portion 231 may be distinguished by a first boundary line BL1. The first boundary line BL1 is a hypothetical straight line that passes through the corners 274 and is parallel to the in-plane direction of the lower surface 201 of the rewiring layer 20. If the positions of the two corners 274 in the third direction D3 are different, the first boundary line BL1 passes through the lower of the two corners 274. As shown in Figure 5, the top connection portion 232 may overlap the first boundary line BL1.

[0091] The side portion 233 has a thickness T4. The thickness T4 is the dimension of the side portion 233 in a direction perpendicular to the direction in which the wiring 27 extends and which is included in the in-plane direction of the lower surface 201 of the rewiring layer 20.

[0092] Each of the multiple side portions 233 may include a portion where the thickness T4 decreases as it extends downward from the top portion 231.

[0093] The side portion 233 may have an intermediate thickness T40. The intermediate thickness T40 is the thickness T4 of the side portion 233 at the intermediate position of the wiring 27 in the third direction D3. The intermediate thickness T40 may be smaller than the thickness T3 of the top portion 231. The ratio T40 / T3, which is the ratio of T40 to the thickness T3, is, for example, 0.60 or less, may be 0.50 or less, may be 0.40 or less, or may be 0.30 or less.

[0094] The inorganic layer 23 may include bottom connecting portions 234 that connect the side portions 233 provided on two adjacent wirings 27 to each other. For example, the inorganic layer 23 may include one bottom connecting portion 234 that connects a side portion 233 located on the inner side 2731 of the first wiring 27A to a side portion 233 located on the inner side 2731 of the second wiring 27B. For example, the inorganic layer 23 may include another bottom connecting portion 234 that connects a side portion 233 located on the inner side 2731 of the second wiring 27B to a side portion 233 located on the inner side 2731 of the third wiring 27C.

[0095] The lower surface of the lower connection portion 234 of the second wiring layer 20B faces the insulating layer 21 of the first wiring layer 20A. The lower surface of the lower connection portion 234 of the second wiring layer 20B may also be in contact with the organic layer 22 of the first wiring layer 20A.

[0096] The gap 29 may be located between the upper connection portion 232 and the lower connection portion 234 in the third direction D3. The gap 29 includes an upper end 291 and a lower end 292. The upper end 291 is the uppermost part of the gap 29. The lower end 292 is the lowermost part of the gap 29.

[0097] As shown in Figure 5, the upper end 291 may be located below the corner 274 of the wiring 27. Although not shown, the upper end 291 may also be located above the corner 274.

[0098] The side portion 233 and the bottom connection portion 234 may be distinguished based on the position of the lower end 292 of the gap 29. For example, as shown in Figure 5, the side portion 233 and the bottom connection portion 234 may be distinguished with the second boundary line BL2 as the boundary. The second boundary line BL2 is a hypothetical straight line that passes through the lower end 292 and is parallel to the in-plane direction of the lower surface 201 of the redistribution layer 20.

[0099] The gap 29 has a thickness H2. Thickness H2 is the distance in the third direction D3 between the upper end 291 and the lower end 292. The larger the thickness H2, the lower the dielectric loss tangent in the space between two adjacent wirings 27. The larger the thickness H2, the lower the relative permittivity in the space between two adjacent wirings 27.

[0100] The ratio H2 / H1, which is the ratio of the thickness H2 of the gap 29 to the height H1 of the wiring 27, is, for example, 0.30 or more, may be 0.40 or more, or may be 0.50 or more. H2 / H1 is, for example, 0.90 or less, may be 0.80 or less, or may be 0.70 or less.

[0101] The gap 29 has a width W2. The width W2 is the dimension of the gap 29 in a direction perpendicular to the direction in which the wiring 27 extends and which is included in the in-plane direction of the lower surface 201 of the rewiring layer 20. The width W2 is measured at a position midway between the upper end 291 and the lower end 292 in the third direction D3. The larger the width W2, the lower the dielectric loss tangent in the space between two adjacent wirings 27. The larger the width W2, the lower the relative permittivity in the space between two adjacent wirings 27.

[0102] The ratio W2 / K1, which is the ratio of the width W2 of the gap 29 to the distance K1 between two adjacent wirings 27, is, for example, 0.20 or more, may be 0.30 or more, or may be 0.40 or more. W2 / K1 is, for example, 0.90 or less, may be 0.80 or less, or may be 0.70 or less.

[0103] Each of the multiple side portions 233 may include a portion in which the thickness T4 decreases as it extends upward from the bottom connection portion 234.

[0104] Figure 6 is a plan view showing an example of multiple wirings 27 and an inorganic layer 23. The multiple wirings 27 may extend parallel to each other over a length U1 in the in-plane direction of the lower surface 201 of the rewiring layer 20. The length U1 is, for example, 100 μm or more, may be 300 μm or more, or may be 500 μm or more.

[0105] (Carrier substrate) The carrier substrate 12 is a component that supports the redistribution layer 20. The carrier substrate 12 may include, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a metal substrate, a silicon carbide substrate, an alumina (Al2O3) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO2) substrate, a lithium niobate substrate, a tantalum niobate substrate, and the like. The resin substrate may contain organic materials. For example, the resin substrate may contain epoxy resin, polyethylene, polypropylene, and the like. The metal substrate may consist only of conductive metals such as copper, aluminum, and nickel, or it may consist of multiple metals such as stainless steel. The thickness of the carrier substrate 12 is, for example, 100 μm or more, may be 200 μm or more, or may be 500 μm or more. The thickness of the carrier substrate 12 is, for example, 2 mm or less, may be 1.5 mm or less, or may be 1 mm or less.

[0106] (Exfoliation layer) The release layer 13 is a layer that facilitates the process of peeling the redistribution layer 20 from the carrier substrate 12. The release layer 13 includes a first lower surface 131 facing the carrier substrate 12 and a first upper surface located on the opposite side of the first lower surface 131. The release layer 13 contains, for example, a resin.

[0107] The release layer 13 may be configured such that its adhesion to the redistribution layer 20 is reduced by some trigger. The trigger may be irradiating the release layer 13 with light of a specific wavelength. For example, the release layer 13 may be decomposed by irradiating it with light of a specific wavelength. The trigger may also be heating the release layer 13. For example, the release layer 13 may contain a thermoplastic resin. Furthermore, if the release layer 13 is configured such that it does not break or cause problems to the redistribution layer 20 even when an external force greater than the force required to bond the release layer 13 to the redistribution layer 20 is applied, the release layer 13 may be peeled off without applying a trigger.

[0108] The thickness of the release layer 13 is, for example, 0.1 μm or more, may be 0.2 μm or more, or 0.3 μm or more. The thickness of the release layer 13 is, for example, 1.0 μm or less, may be 0.8 μm or less, or 0.5 μm or less.

[0109] (Manufacturing method for wiring boards) A method for manufacturing the wiring board group 10 will be described.

[0110] As shown in Figure 7, a carrier substrate 12 is prepared. Subsequently, as shown in Figure 7, a release layer 13 is formed on the carrier substrate 12. The process of forming the release layer 13 includes, for example, a coating step of applying a solution containing a resin and a solvent, and a drying step of evaporating the solvent after the coating step. Examples of solvents include propylene glycol monomethyl ether, 2-methoxy-1-methylethyl acetate, N-methyl-2-pyrrolidone, γ-butyrolactone, ethyl lactate, and toluene. The drying step includes, for example, a step of heating the carrier substrate 12.

[0111] Next, a rewiring process is performed to form a rewiring layer 20 having multiple wiring layers on the carrier substrate 12. The rewiring process includes, for example, a first wiring process to form a first wiring layer 20A, and a second wiring process to form a second wiring layer 20B on the first wiring layer 20A.

[0112] Figure 7 is a cross-sectional view showing the first wiring process for forming the first wiring layer 20A. The first wiring layer 20A may be formed on the release layer 13. The first wiring process includes the steps of forming a conductive layer 25 and forming an organic layer 22. The steps of forming the conductive layer 25 and forming the organic layer 22 will be described in detail in the second wiring process described later.

[0113] Although not shown in the diagram, a step of forming an intermediate layer on the peeling layer 13 may be performed before the first wiring step. The intermediate layer may be, for example, a layer that shields the light irradiated onto the peeling layer 13.

[0114] After the first wiring process, a second wiring process is carried out to form a second wiring layer 20B on the first wiring layer 20A. The second wiring process may include a step of forming a second opening 227 in the organic layer 22 of the first wiring layer 20A, as shown in Figure 8.

[0115] The second wiring step includes forming a conductive layer 25 on the insulating layer 21 of the first wiring layer 20A. For example, as shown in Figure 9, an adhesion layer 251 and a seed layer 252 are formed on the organic layer 22 of the insulating layer 21 of the first wiring layer 20A. The adhesion layer 251 and the seed layer 252 are formed, for example, by sputtering. The adhesion layer 251 and the seed layer 252 are also formed on the bottom and side surfaces of the second opening 227 of the organic layer 22 of the first wiring layer 20A.

[0116] Next, as shown in Figure 10, a first resist layer 71 is formed on the seed layer 252. The first resist layer 71 has an opening 711 that penetrates the first resist layer 71 in the thickness direction. In a plan view, the opening 711 has a shape corresponding to the plating layer 253. Next, a plating process is carried out. In the plating process, as shown in Figure 10, a plating layer 253 is formed in the opening 711 by electroplating.

[0117] Next, as shown in Figure 11, a step is performed to remove the first resist layer 71. Subsequently, as shown in Figure 11, a step is performed to remove the adhesion layer 251 and seed layer 252 that were overlapping the first resist layer 71. In this way, a conductive layer 25 including the adhesion layer 251, seed layer 252, and plating layer 253 is formed.

[0118] Next, as shown in Figure 12, an inorganic layer formation process is carried out to form the inorganic layer 23. For example, the inorganic layer 23 is formed by a physical vapor deposition method. Examples of physical vapor deposition methods include vacuum deposition and sputtering. The inorganic layer 23 covers multiple conductive layers 25 of the second wiring layer 20B and the organic layer 22 of the first wiring layer 20A. The inorganic layer 23 may also be formed to cover the space between two adjacent wirings 27. As a result, a gap 29 may be formed between two adjacent wirings 27, as shown in Figure 12.

[0119] Next, as shown in Figure 13, a step is performed to form a first opening 237 in the inorganic layer 23. The first opening 237 is formed in the inorganic layer 23 at a position that overlaps with the pad 26 of the conductive layer 25 in a plan view. The first opening 237 is formed in the inorganic layer 23 by, for example, dry etching, wet etching, blasting, etc.

[0120] Next, as shown in Figure 14, an organic layer formation step is performed to form an organic layer 22 that covers the inorganic layer 23. For example, the organic layer 22 is formed by applying an organic material onto the inorganic layer 23 by a spin coating method or the like. Alternatively, the organic layer formation step may include a step of attaching a film containing a layer of organic material onto the inorganic layer 23. The organic layer 22 may also be formed by transferring a layer of organic material onto the inorganic layer 23. Next, as shown in Figure 14, a step is performed to form a second opening 227 in the organic layer 22 at a position that overlaps with the first opening 237 of the inorganic layer 23 in a plan view. If the organic material is photosensitive, the second opening 227 may be formed in the organic layer 22 by an exposure step and a development step. Next, a heating step may be performed to heat the organic layer 22. The heating step hardens the organic layer 22. The heating temperature is, for example, 200°C or higher.

[0121] The reference numeral L2 represents the dimension of the first opening 237 in the planar direction of the lower surface 201. The reference numeral L4 represents the dimension of the second opening 227 in the planar direction of the lower surface 201. As shown in Figure 14, the dimension L4 of the second opening 227 may be smaller than the dimension L2 of the first opening 237. In this case, as shown in Figure 14, a portion of the organic layer 22 can contact the upper surface of the pad 26.

[0122] After the second wiring layer 20B, which includes an organic layer 22, an inorganic layer 23, and a conductive layer 25, is formed, conductive layers 25 such as pads 26, wiring 27, and through electrodes 28 may be formed on the second wiring layer 20B, as shown in Figure 15.

[0123] A group of wiring boards 10 is obtained by forming multiple redistribution layers 20 on the carrier substrate 12.

[0124] The inorganic layer formation process will be explained in detail. Figures 16 and 17 are cross-sectional views showing an example of the inorganic layer formation process.

[0125] In the physical vapor deposition method, the inorganic layer 23 is preferentially formed on the portion of the redistribution layer 20 that faces the vapor deposition source 60 in the third direction D3. Therefore, as shown in Figure 16, the upper surface portion 231 formed on the upper surface 271 can grow faster than the side surface portion 233 formed on the side surface 273.

[0126] As shown in Figure 17, when the upper surface portion 231 grows until it touches the upper surface portions 231 of two adjacent wirings 27, an upper surface connection portion 232 is formed between the two upper surface portions 231. In other words, the two upper surface portions 231 are connected to each other. As a result, the space between the two adjacent wirings 27 is covered by the inorganic layer 23.

[0127] In the example shown in Figure 17, when the space between two adjacent wirings 27 is covered by the inorganic layer 23, the side portions 233 located on the inner sides 2731 of the two adjacent wirings 27 are not yet in contact with each other. Therefore, a gap 29 is formed below the upper connection portion 232.

[0128] According to this embodiment, since the organic layer 22 is not placed between two adjacent wirings 27, the dielectric loss tangent, relative permittivity, etc., in the space between the two adjacent wirings 27 are reduced. In particular, since an air gap 29 is formed between the two adjacent wirings 27, the dielectric loss tangent, relative permittivity, etc., are further reduced. As a result, dielectric loss between the two adjacent wirings can be reduced.

[0129] In this embodiment, as shown in Figure 17, the upper surface 271 and side surface 273 of the wiring 27 are covered by the inorganic layer 23, and the upper surface portions 231 located on the upper surface 271 of two adjacent wirings 27 are connected to each other. Therefore, the structural stability of the multiple wirings 27 is ensured.

[0130] (Manufacturing method for wiring boards) A method for manufacturing the wiring board 11 will be described.

[0131] A group of wiring boards 10 is prepared. Next, a separation process is performed to separate the wiring boards 11. Multiple wiring boards 11 are obtained through the separation process. Each wiring board 11 comprises a carrier substrate 12, a release layer 13 located on the carrier substrate 12, and a redistribution layer 20 located on the release layer 13.

[0132] As shown in Figures 18 and 19, after the separation process, a bonding process may be performed to bond the wiring board 11 to the substrate 81. The substrate 81 may include a base material 811 and a plurality of terminals 812 located on the base material 811. The substrate 81 may include an adhesive layer 813 covering the plurality of terminals. The adhesive layer 813 may be provided on the wiring board 11. In the bonding process, as shown in Figure 19, a conductive layer 25 located on the upper surface 202 of the rewiring layer 20 and constituting the pad 26 may be electrically connected to the terminals 812 of the substrate 81.

[0133] Next, as shown in Figures 19 and 20, a peeling step may be performed to peel the redistribution layer 20 from the carrier substrate 12. The peeling step may include an irradiation step in which light L is irradiated onto the peeling layer 13, as shown in Figure 19. In the irradiation step, the light L may reach the peeling layer 13 after passing through the carrier substrate 12. The peeling layer 13 may be decomposed by the heat generated due to the irradiation of light L. Due to the decomposition, the adhesion between the carrier substrate 12 and the redistribution layer 20 decreases. Therefore, as shown in Figure 20, the redistribution layer 20 is transferred from the carrier substrate 12 to the substrate 81.

[0134] The structure comprising the transferred redistribution layer 20 includes a substrate 81 and the redistribution layer 20 located on the substrate 81. This structure may also be referred to as a wiring board. In the wiring board shown in Figure 20, the upper surface 202 of the redistribution layer 20 faces the substrate 81.

[0135] Although not shown in the diagram, the method of use and distribution of the redistribution layer 20 are not particularly limited. For example, a semiconductor element may be mounted on the lower surface 201 of the redistribution layer 20. The semiconductor element includes a transistor formed from a semiconductor such as silicon. Examples of semiconductor elements include a CPU, GPU, FPGA, sensor, and memory. The semiconductor element may also be a chiplet in which semiconductor elements such as a CPU, GPU, FPGA, sensor, and memory are divided according to their function.

[0136] Although not shown in the figures, the redistribution layer 20 may be manufactured on a substrate 81 or other material that includes a conductive layer such as terminals 812. In this case, the redistribution layer 20 is used with its lower surface 201 facing the substrate 81. In this case, a semiconductor element may be mounted on the upper surface 202 of the redistribution layer 20.

[0137] The redistribution layer 20 may be distributed in the form of a group of wiring boards 10. The redistribution layer 20 may be distributed in the form of a wiring board 11. The redistribution layer 20 may be distributed after being transferred from the carrier substrate 12 to the substrate 81.

[0138] The above-described embodiment can be modified in various ways. Hereinafter, modifications will be described with reference to the drawings as necessary. In the following description and the drawings used therein, parts that can be configured similarly to the above-described embodiment will be given the same reference numerals as those used for the corresponding parts in the above-described embodiment. Duplicate explanations will be omitted. Furthermore, if it is clear that the effects and advantages obtained in the above-described embodiment can also be obtained in the modifications, the explanation may be omitted.

[0139] (First variation) Figure 21 is a cross-sectional view showing the process of forming the organic layer 22 of the second wiring layer 20B in the first modified example. As shown in Figure 21, the dimension L4 of the second opening 227 of the organic layer 22 may be larger than the dimension L2 of the first opening 237 of the inorganic layer 23. According to the first modified example, the process of forming the second opening 227 in the organic layer 22 is simplified compared to the case where dimension L4 is smaller than dimension L2. For example, the requirement for precision in the exposure process performed to form the second opening 227 in the organic layer 22 is relaxed.

[0140] (Second variation) Figure 22 is a cross-sectional view showing the organic layer formation process in a second modified example. As shown in Figure 22, the organic layer 22 may be formed on the inorganic layer 23 in a state where the first opening has not yet been formed. After the organic layer formation process, as shown in Figure 22, a second opening 227 is formed in the organic layer 22 at a position that overlaps with the pad 26 of the conductive layer 25 in a plan view.

[0141] Next, as shown in Figure 23, a step is performed to form the first aperture 237 in the inorganic layer 23 at a position overlapping the second aperture 227 in a plan view. For example, the first aperture 237 is formed in the inorganic layer 23 by plasma etching. For example, the first aperture 237 is formed in the inorganic layer 23 by the action of plasma gas on the inorganic layer 23 exposed to the second aperture 227. In this case, the dimension L2 of the first aperture 237 is equal to the dimension L4 of the second aperture 227. "Equal" means that at the interface between the organic layer 22 and the inorganic layer 23 in the third direction D3, the difference between the dimension L2 of the first aperture 237 and the dimension L4 of the second aperture 227 is 0.10 μm or less.

[0142] (Third variation) Figure 24 is a cross-sectional view showing an example of the inorganic layer 23 in the third modified example. The side portion 233 of the inorganic layer 23 does not have to cover the entire side portion 273 of the wiring 27. For example, the side portion 233 may cover only a portion of the side portion 273 adjacent to the corner 274. The side portion 273 adjacent to the bottom surface 272 does not have to be covered by the inorganic layer 23.

[0143] As shown in Figure 24, in the third modified example, the inner surfaces 2731 of two adjacent wirings 27 each include a portion in contact with the gap 29. For example, the inner surfaces 2731 of the first wiring 27A and the second wiring 27B each include a portion in contact with the gap 29. In this case, the width W2 of the gap 29 may be equal to the distance K1 between two adjacent wirings 27.

[0144] The side portions 233 provided on two adjacent wirings 27 do not have to be connected to each other. For example, as shown in Figure 24, the inorganic layer 23 does not have to include the bottom connection portion described above. For example, the inorganic layer 23 does not have to be placed on the organic layer 22 of the first wiring layer 20A in the space between two adjacent wirings 27 of the second wiring layer 20B. In this case, a gap 29 is formed between the top connection portion 232 of the second wiring layer 20B and the organic layer 22 of the first wiring layer 20A.

[0145] As shown in Figure 24, the thickness H2 of the gap 29 may be greater than the height H1 of the wiring 27.

[0146] Figures 25 and 26 are cross-sectional views showing an example of the inorganic layer formation process in the third modified example. In the third modified example, the physical vapor deposition method is controlled so that almost no inorganic layer 23 is formed in the space between two adjacent wirings 27. As a result, as shown in Figure 26, a void 29 with a larger volume is obtained compared to the embodiment described above.

[0147] (Fourth variation) Figure 27 is a cross-sectional view showing an example of the inorganic layer 23 in the fourth modified example. The side portion 233 of the inorganic layer 23 does not have to cover the entire side portion 273 of the wiring 27. For example, as in the third modified example, the inner side portions 2731 of two adjacent wirings 27 may each include portions that are in contact with the gap 29. On the other hand, the entire outer side portion 2732 of the wiring 27 may be covered by the side portion 233 of the inorganic layer 23.

[0148] Figures 28 and 29 are cross-sectional views showing an example of the inorganic layer formation process in the fourth modified example. In the fourth modified example, the inorganic layer formation process includes a first step and a second step.

[0149] In the first step, as shown by the arrow in Figure 28, a physical vapor deposition method is performed along a direction inclined with respect to the third direction D3. For example, physical vapor deposition along a direction inclined with respect to the third direction D3 is achieved by adjusting the relative positions of the multiple wirings 27 with respect to the vapor deposition source. In the first step, a side portion 233 of the inorganic layer 23 is formed on the outer side surface 2732 of the third wiring 27C, but an inorganic layer does not need to be formed on the outer side surface 2732 of the first wiring 27A. In the first step, a side portion 233 may be formed on only one of the inner side surfaces 2731 of two adjacent wirings 27.

[0150] In the second step, as indicated by the arrow in Figure 29, physical vapor deposition is performed on the opposite side from the first step, along a direction inclined with respect to the third direction D3. In the second step, a side portion 233 of the inorganic layer 23 is formed on the outer side surface 2732 of the first wiring 27A, but an inorganic layer does not necessarily have to be formed on the outer side surface 2732 of the third wiring 27C. In the second step, a side portion 233 may be formed only on the other of the two adjacent inner side surfaces 2731 of the wirings 27.

[0151] By adjusting the duration of the first and second processes, the inorganic layer 23 shown in Figure 27 can be obtained. In the fourth modified example, as in the third modified example, the physical vapor deposition method is controlled so that almost no inorganic layer 23 is formed in the space between two adjacent wirings 27. As a result, a void 29 with a larger volume than in the above-described embodiment can be obtained.

[0152] In the fourth modified example, the entire outer surface 2732 of the wiring 27 is covered by the side portion 233 of the inorganic layer 23, thereby increasing the structural stability of the wiring 27.

[0153] (Fifth variation) Figure 30 is a cross-sectional view showing an example of the inorganic layer 23 in the fifth modified example. In the fifth modified example as well, the inorganic layer 23 includes a plurality of upper surface portions 231 located on the upper surface 271 of a plurality of wirings 27, and an upper surface connecting portion 232 connecting two adjacent upper surface portions 231.

[0154] As shown in Figure 30, the inorganic layer 23 may be filled without gaps in the space between two adjacent wirings 27. For example, the inorganic layer 23 may be filled without gaps between the first wiring 27A and the second wiring 27B.

[0155] In the fifth modified example, the organic layer 22 is not placed between two adjacent wirings 27. The dielectric loss tangent of the inorganic material constituting the inorganic layer 23 is lower than that of the organic material constituting the organic layer 22. In the fifth modified example, the dielectric loss tangent in the space between two adjacent wirings 27 is reduced. As a result, the dielectric loss between two adjacent wirings can be reduced.

[0156] Figure 31 is a cross-sectional view showing an example of the inorganic layer formation process in the fifth modified example. In the fifth modified example, the inorganic layer formation process includes a step of forming an inorganic layer 23 by chemical vapor deposition.

[0157] In chemical vapor deposition, the growth pattern of the inorganic layer 23 differs depending on the free path of the molecules of the material constituting the inorganic layer 23. Free path refers to the distance that particles such as molecules can travel without colliding with other particles and being scattered.

[0158] In the example shown in Figure 31, the free process is set to be long. In this case, the inorganic layer 23 is easily formed in the space between two adjacent wirings 27. For example, the thickness T4 of the side portion 233 increases from the top surface 271 downwards. By performing chemical vapor deposition with the free process set to be long, the inorganic layer 23 can be filled without gaps in the space between two adjacent wirings 27, as shown in Figure 30.

[0159] If the inorganic layer formation process includes a step of forming the inorganic layer 23 by chemical vapor deposition, the composition of the inorganic layer 23 may be adjusted by adjusting the free step. For example, by setting the free step shorter than in the example shown in Figure 31, the inorganic layer 23 shown in Figure 4 can be obtained. For example, by setting the free step even shorter, the inorganic layer 23 shown in Figure 24 can be obtained.

[0160] (Sixth variation) In the sixth modified example, the inorganic layer formation step includes a step of forming an inorganic layer 23 by atomic layer deposition. Figure 32 is a cross-sectional view showing an example of the step of forming an inorganic layer 23 by atomic layer deposition.

[0161] In atomic layer deposition, layers of uniform thickness are formed regardless of the shape of the object. For example, as shown in Figure 32, an inorganic layer 23 with a uniform thickness can be formed on the upper surface 271 and side surface 273 of the wiring 27, and on the organic layer 22 of the first wiring layer 20A.

[0162] Figure 33 is a cross-sectional view showing an example of the inorganic layer 23 formed in the sixth modified example. The inorganic layer 23 may be filled without gaps in the space between two adjacent wirings 27. The inorganic layer 23 shown in Figure 33 may be obtained by continuing the atomic layer deposition method.

[0163] Alternatively, the inorganic layer 23 shown in Figure 33 may be obtained by performing another method after atomic layer deposition. For example, the inorganic layer formation step may include a step of forming the inorganic layer 23 by atomic layer deposition and a step of forming the inorganic layer 23 by physical vapor deposition or chemical vapor deposition. The inorganic layer 23 shown in Figure 33 can be obtained by adjusting the conditions of the physical vapor deposition or chemical vapor deposition. For example, the inorganic layer 23 shown in Figure 33 can be obtained by performing a chemical vapor deposition method with a long free process after atomic layer deposition.

[0164] Figure 34 is a cross-sectional view showing an example of the inorganic layer 23 formed in the sixth modified example. The inorganic layer 23 shown in Figure 34 is obtained by performing a step of forming the inorganic layer 23 by atomic layer deposition, followed by a step of forming the inorganic layer 23 by physical vapor deposition or chemical vapor deposition. For example, the inorganic layer 23 shown in Figure 34 can be obtained by performing chemical vapor deposition, in which the free process is set to be short, after atomic layer deposition.

[0165] Figure 35 is a cross-sectional view showing an example of the inorganic layer 23 formed in the sixth modified example. The inorganic layer 23 shown in Figure 35 is obtained by performing a step of forming the inorganic layer 23 by atomic layer deposition, followed by a step of forming the inorganic layer 23 by physical vapor deposition or chemical vapor deposition. For example, the inorganic layer 23 shown in Figure 35 can be obtained by performing chemical vapor deposition, in which the free process is set to be even shorter, after atomic layer deposition.

[0166] Figure 36 shows an example of a product on which the redistribution layer 20 is installed. The redistribution layer 20 can be used in a variety of products. For example, it can be installed in notebook personal computers 110, tablet terminals 120, mobile phones 130, smartphones 140, digital video cameras 150, digital cameras 160, digital clocks 170, servers 180, etc.

[0167] Although several modifications of the above-described embodiment have been explained, it is naturally possible to combine multiple modifications as appropriate and apply them to the above-described embodiment. [Explanation of symbols]

[0168] 10 Wiring board group 11 Wiring board 12 Carrier board 20 Redistribution layer 20A First wiring layer 20B 2nd wiring layer 20C 3rd wiring layer 21 Insulating layer 22 Organic layer 227 Second opening 23 Inorganic layer 231 Top part 232 Top connection section 233 Side part 234 Bottom connection part 237 First opening 25 Conductive layer 26 pads 27 Wiring 27A 1st wiring 27B 2nd wiring 27C 3rd wiring 271 Top surface 272 Bottom surface 273 Side view 274 Corner 28 Through electrode 29 void 71. First Resist Layer 81 circuit boards

Claims

1. It is a redistribution layer, The wiring comprises at least one wiring layer including a plurality of wirings including a bottom surface, a top surface and two side surfaces, an inorganic layer including at least a plurality of top surface portions located on the top surface of each wiring, and an organic layer located on the inorganic layer. Each of the aforementioned wirings includes at least a first wiring and a second wiring adjacent to the first wiring, The inorganic layer is a rewiring layer that includes an upper surface connecting portion that connects the upper surface portion located on the upper surface of the first wiring and the upper surface portion located on the upper surface of the second wiring.

2. The rewiring layer according to claim 1, wherein the at least one wiring layer includes a gap located below the upper connection portion.

3. The rewiring layer according to claim 2, wherein the inorganic layer is located on two of the sides of each wiring and includes a plurality of side portions connected to each of a plurality of upper portions located on the upper surface of each wiring.

4. The redistribution layer according to claim 3, wherein each of the multiple side portions includes a portion in which the thickness of the side portion decreases as it extends downward from the upper portion.

5. The two sides of the first wiring include an inner side facing the side of the second wiring and an outer side, One of the two sides of the second wiring is the inner side facing the inner side of the first wiring, The inorganic layer includes a bottom connecting portion that connects the side portion located on the inner side of the first wiring and the side portion located on the inner side of the second wiring. The rewiring layer according to claim 3, wherein the gap is located between the upper connection portion and the lower connection portion.

6. The rewiring layer according to claim 5, wherein each of the multiple side portions includes a portion in which the thickness of the side portion decreases as it extends upward from the bottom connection portion.

7. The two sides of the first wiring include an inner side facing the side of the second wiring and an outer side, One of the two sides of the second wiring is the inner side facing the inner side of the first wiring, The rewiring layer according to claim 3, wherein the inner surface of the first wiring and the inner surface of the second wiring each include a portion in contact with the void.

8. The rewiring layer according to claim 7, wherein the entire area of ​​the outer side surface of the first wiring is covered by the side portion.

9. The rewiring layer according to any one of claims 2 to 8, wherein the ratio of the width of the gap to the spacing between the wirings is 0.40 or more.

10. The rewiring layer according to any one of claims 2 to 8, wherein the ratio of the thickness of the void to the height of the wiring is 0.50 or more.

11. The rewiring layer according to any one of claims 1 to 8, wherein the ratio of the height of the wiring to the spacing between the wirings is 1.50 or more and 5.00 or less.

12. The rewiring layer according to claim 1, wherein the inorganic layer is filled without any gaps between the first wiring and the second wiring.

13. A method for manufacturing a redistribution layer, The redistribution process includes forming a redistribution layer on a substrate that includes at least one wiring layer, The at least one wiring layer includes a plurality of wires including a bottom surface, an upper surface and two side surfaces, an inorganic layer including at least a plurality of upper surface portions located on the upper surface of each wire, and an organic layer located on the inorganic layer. The rewiring step includes a step of forming a plurality of the wirings, an inorganic layer forming step of forming the inorganic layer on the plurality of the wirings, and an organic layer forming step of forming the organic layer on the inorganic layer. A method for manufacturing a rewiring layer, wherein the inorganic layer formation step is carried out such that the upper surface portions located on the upper surfaces of two adjacent wirings are connected to each other.

14. The manufacturing method according to claim 13, wherein the inorganic layer formation step includes a step of forming the inorganic layer by a physical vapor deposition method.

15. The manufacturing method according to claim 14, wherein the inorganic layer formation step includes a first step of performing a physical vapor deposition method along a direction inclined with respect to the thickness direction of the substrate, and a second step of performing a physical vapor deposition method along a direction inclined with respect to the thickness direction on the opposite side from the first step.

16. The manufacturing method according to claim 13, wherein the inorganic layer formation step includes a step of forming the inorganic layer by chemical vapor deposition.

17. The manufacturing method according to claim 13, wherein the inorganic layer formation step includes a step of forming the inorganic layer by atomic layer deposition and a step of forming the inorganic layer by physical vapor deposition or chemical vapor deposition.

18. The manufacturing method according to any one of claims 13 to 17, wherein the ratio of the height of the wiring to the spacing between the wirings is 1.50 or more and 5.00 or less.

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