Nitride semiconductor light-emitting device and method for manufacturing nitride semiconductor light-emitting device

Abstract

The present invention provides a nitride semiconductor light-emitting element and a method for manufacturing a nitride semiconductor light-emitting element that can improve light output. [Solution] The nitride semiconductor light-emitting element 1 comprises a substrate 2, a first buffer layer 3 formed on the substrate 2 containing Al and N, a second buffer layer 4 formed on the first buffer layer 3 containing Al, Ga and N and having a smaller Al composition ratio than the first buffer layer 3, an n-type semiconductor layer 5 formed on the second buffer layer 4, an active layer 7 formed on the n-type semiconductor layer 5 that emits ultraviolet light with a central wavelength of 365 nm or less, and a p-type semiconductor layer 9 formed on the active layer 7. The silicon concentration at the center of the stacking direction of the first buffer layer 3 is 1.02 × 10⁻¹⁶. 18 [atoms / cm 3 The following applies:

Description

[Technical Field]

[0001] The present invention relates to a nitride semiconductor light-emitting device and a method for manufacturing a nitride semiconductor light-emitting device. [Background technology]

[0002] Patent Document 1 discloses a group III nitride semiconductor epitaxial substrate comprising a sapphire substrate, an undoped AlN layer formed on the sapphire substrate, and an AlN buffer layer formed on the undoped AlN layer. In the group III nitride semiconductor epitaxial substrate described in Patent Document 1, the silicon concentration in the AlN buffer layer is 1.0 × 10⁻⁶. 19 / cm 3 It is considered to be larger than that. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-35535 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, when the Group III nitride semiconductor epitaxial substrate described in Patent Document 1 is used to manufacture a nitride semiconductor light-emitting element that emits ultraviolet light, the high silicon concentration in the buffer layer makes it easier for ultraviolet light to be absorbed, resulting in a decrease in light output.

[0005] This invention has been made in view of the above circumstances, and aims to provide a nitride semiconductor light-emitting element and a method for manufacturing a nitride semiconductor light-emitting element that can improve the light output. [Means for solving the problem]

[0006] To achieve the above objective, the present invention comprises a substrate, a first buffer layer containing Al and N formed on the substrate, a second buffer layer formed on the first buffer layer containing Al, Ga and N and having a smaller Al composition ratio than the first buffer layer, an n-type semiconductor layer formed on the second buffer layer, an active layer formed on the n-type semiconductor layer that emits ultraviolet light with a central wavelength of 365 nm or less, and a p-type semiconductor layer formed on the active layer, wherein the silicon concentration at the center of the stacking direction of the first buffer layer is 1.02 × 10⁻¹⁶. 18 [atoms / cm 3 The present invention provides a nitride semiconductor light-emitting element that is as follows:

[0007] Furthermore, in order to achieve the above objective, the present invention forms a first buffer layer containing Al and N on a substrate, forms a second buffer layer containing Al, Ga and N on the first buffer layer, having a smaller Al composition ratio than the first buffer layer, forms an n-type semiconductor layer on the second buffer layer, forms an active layer emitting ultraviolet light with a central wavelength of 365 nm or less on the n-type semiconductor layer, forms a p-type semiconductor layer on the active layer, and the silicon concentration at the center of the stacking direction of the first buffer layer is 1.02 × 10⁻¹⁶. 18 [atoms / cm 3 The present invention provides a method for manufacturing a nitride semiconductor light-emitting element, as described below. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a nitride semiconductor light-emitting element and a method for manufacturing a nitride semiconductor light-emitting element that can improve the light output. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram illustrating the configuration of a nitride semiconductor light-emitting element in an embodiment. [Figure 2] This graph shows the silicon concentration distribution of wafers for samples 1 to 5 in the experimental example. [Figure 3] This is a magnified view of a portion of Figure 2. [Figure 4] This graph shows the relationship between the central silicon concentration in the first buffer layer and the optical output in an experimental example. [Modes for carrying out the invention]

[0010] [Embodiment] Embodiments of the present invention will be described with reference to Figures 1 to 3. The embodiments described below are presented as preferred specific examples for carrying out the present invention, and while some parts specifically illustrate various technically preferable technical matters, the technical scope of the present invention is not limited to these specific embodiments.

[0011] (Nitride semiconductor light-emitting element 1) Figure 1 is a schematic diagram illustrating the configuration of the nitride semiconductor light-emitting element 1. Note that in Figure 1, the dimensional ratios of the stacking directions of each semiconductor layer of the nitride semiconductor light-emitting element 1 (hereinafter also simply referred to as "light-emitting element 1") do not necessarily correspond to the actual dimensions. Hereafter, the stacking direction of each semiconductor layer of the light-emitting element 1 will be referred to as the vertical direction. Furthermore, one side of the vertical direction where each semiconductor layer on the substrate 2 is grown (for example, the upper side in Figure 1) will be referred to as the upper side, and the opposite side (for example, the lower side in Figure 1) will be referred to as the lower side. Note that the terms "upper" and "lower" are for convenience only and do not limit the orientation of the light-emitting element 1 relative to the vertical direction when it is in use.

[0012] The light-emitting element 1 is, for example, a light-emitting diode (LED) or a semiconductor laser (LD). In this embodiment, the light-emitting element 1 is a light-emitting diode that emits light with wavelengths in the ultraviolet region. In particular, the light-emitting element 1 in this embodiment emits ultraviolet light with a central wavelength of 240 nm to 365 nm. The light-emitting element 1 can be used in fields such as sterilization (e.g., air purification, water purification, etc.), medical applications (e.g., phototherapy, measurement and analysis, etc.), and UV curing.

[0013] The light-emitting element 1 sequentially includes a first buffer layer 3, a second buffer layer 4, an n-type semiconductor layer 5, a composition gradient layer 6, an active layer 7, an electron blocking layer 8, and a p-type semiconductor layer 9 on a substrate 2. Further, the light-emitting element 1 includes an n-side electrode 11 provided on the n-type semiconductor layer 5 and a p-side electrode 12 provided on the p-type semiconductor layer 9.

[0014] As the semiconductor constituting the light-emitting element 1, for example, Al a Ga b In 1-a-b A binary to quaternary group III nitride semiconductor represented by N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1) can be used. In this embodiment, as the semiconductor constituting the light-emitting element 1, Al c Ga 1-c A binary or ternary group III nitride semiconductor represented by N (0 ≦ c ≦ 1) is used. A part of these group III elements may be replaced with boron (B), thallium (Tl), etc. Also, a part of nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0015] The substrate 2 is made of a material that transmits the light emitted by the active layer 7. In this embodiment, the substrate 2 is a sapphire (Al2O3) substrate. The growth surface 21 formed on the upper surface of the substrate 2 is a c-plane. This c-plane may have an off-angle. Also, as the substrate 2, for example, an aluminum nitride (AlN) substrate, an aluminum gallium nitride (AlGaN) substrate, etc. may be used.

[0016] The first buffer layer 3 is formed on the substrate 2. The first buffer layer 3 is formed of Al p Ga 1-p N (0.7 ≦ p ≦ 1) having a higher Al composition ratio than the second buffer layer 4. The Al composition ratio is also referred to as the AlN mole fraction. In this embodiment, the first buffer layer 3 is formed of aluminum nitride. The film thickness of the first buffer layer 3 is larger than the film thickness of the second buffer layer 4. For example, the film thickness of the first buffer layer 3 is 1800 nm or more and 2200 nm or less.

[0017] Figure 2 is a graph showing the silicon concentration distribution in the stacking direction for wafers relating to samples 1 to 3, which have the configuration of this embodiment, and wafers relating to samples 4 and 5, which do not have the configuration of this embodiment. Hereafter, when simply referring to the silicon concentration distribution, it means the silicon concentration distribution in the stacking direction. In Figure 2, the silicon concentration distribution in the stacking direction region around the first buffer layer 3 of the light-emitting element 1 is shown. In Figure 2, the boundaries of each semiconductor layer are represented by thin solid lines in the vertical direction. Figure 2 shows the silicon concentration obtained by secondary ion mass spectrometry (SIMS) after ions were incident on the wafer from above (i.e., the side opposite the substrate). Figure 3 is an enlarged view of the vicinity of the second buffer layer 4 in Figure 2. Details of samples 1 to 5 will be explained in the experimental examples described later.

[0018] As shown in Figure 2, the first buffer layer 3 contains silicon concentration that can be measured using methods such as secondary ion mass spectrometry (SIMS) at a limit of (e.g., 5.00 × 10⁻¹⁰). 15 [atoms / cm 3 It contains silicon at a concentration of ]) or higher. As mentioned above, the first buffer layer 3 is a semiconductor layer with a high Al composition ratio, so silicon (Si) in the first buffer layer 3 has difficulty entering the lattice positions of the aluminum nitride that constitutes the first buffer layer 3, and is more likely to exist in the interstitial positions of the aluminum nitride. At least a portion of the silicon present in the interstitial positions of the aluminum nitride exists in a precipitated state of compounds such as silicon nitride. The silicon present in the first buffer layer 3 without doping absorbs ultraviolet light with a central wavelength of 365 nm or less emitted by the active layer 7, and is therefore presumed to be a factor that reduces the light output of the light-emitting element 1. For this reason, as will be explained below, in the light-emitting element 1 of this embodiment, the silicon concentration of the first buffer layer 3 is kept low.

[0019] Here, the interface between the first buffer layer 3 and the substrate 2 is defined as the first interface 31, and the interface between the first buffer layer 3 and the second buffer layer 4 is defined as the second interface 32. In the silicon concentration distribution of the light-emitting element 1, the region of the first buffer layer 3 from the first interface 31 upwards at a predetermined distance (e.g., 500 nm) is a region where accurate measurement of the silicon concentration is difficult due to the influence of the substrate 2. Also, in the silicon concentration distribution, the range of the first buffer layer 3 from the second interface 32 downwards at a predetermined distance (e.g., 250 nm) is a region where the silicon concentration is locally high due to the influence of silicon contained near the second interface 32 of the first buffer layer 3. Furthermore, in the first buffer layer 3, from the position a predetermined distance (e.g., 500 nm) upwards from the first interface 31 to the position a predetermined distance (e.g., 250 nm) downwards from the second interface 32, the change in the silicon concentration of the first buffer layer 3 in the stacking direction is gradual (e.g., the change is 2.00 × 10⁻¹⁰). 17 [atoms / cm 3 This is the area (within the following range).

[0020] In this embodiment, the light-emitting element 1 has a silicon concentration at the center C in the stacking direction of the first buffer layer 3 (see the dashed line in Figure 2) (hereinafter referred to as "central silicon concentration Si center It is also called ''. ) However, 1.02 × 10 18 [atoms / cm 3 The following is true. This suppresses the absorption of ultraviolet light emitted by the active layer 7 in the first buffer layer 3, thereby improving the light output of the light-emitting element 1. Also, the central silicon concentration of the first buffer layer 3 is Si center is 0.91 × 10 18 [atoms / cm 3 The following is preferable: 0.83 × 10 18 [atoms / cm 3 The following values ​​are more preferable. These values ​​will be supported by the experimental examples described later. Furthermore, the central silicon concentration Si of the first buffer layer 3. center The lower limit is 0 [atoms / cm 3 ]This is the case, and considering feasibility, for example, 1.00 × 10 16 [atoms / cm 3It can be set to ] or higher. Also, the central silicon concentration of the first buffer layer 3 is Si center For example, this was defined as the average silicon concentration in the range between a position 30 nm away from the center C in the stacking direction on one side of the stacking direction and a position 30 nm away from the center C in the stacking direction on the other side of the stacking direction.

[0021] Furthermore, as shown in Figures 2 and 3, a positive peak P1 appears in the silicon concentration distribution of the light-emitting element 1 in the stacking direction range including the position of the second interface 32. A positive peak refers to a peak that is convex towards the higher silicon concentration side (upper side in the graphs of Figures 2 and 3) in the silicon concentration distribution of the light-emitting element 1, and a negative peak refers to a peak that is convex towards the lower silicon concentration side (lower side in the graphs of Figures 2 and 3). The silicon concentration of this positive peak P1 (i.e., the peak top value Si) top ) is 1.15 × 10 18 [atoms / cm 3 ] Preferably 2.22 × 10 18 [atoms / cm 3 The above is more preferable. In this way, by including a certain amount or more of silicon near the second interface 32 of the first buffer layer 3, dislocations extending upward from the substrate 2 are suppressed from extending further above the second interface 32. Peak top value Si top This can be, for example, less than the silicon concentration of the n-type semiconductor layer 5.

[0022] As shown in Figure 1, the second buffer layer 4 is formed on the first buffer layer 3. The second buffer layer 4 is an undoped Al q Ga 1-qIt is formed by N (0 ≤ q < 1). An undoped semiconductor layer refers to a semiconductor layer in which impurities have not been intentionally added during its formation, and a semiconductor layer containing trace amounts of impurities that are inevitably present is also considered an undoped semiconductor layer. The Al composition ratio q of the second buffer layer 4 can be, for example, greater than or equal to the Al composition ratio r of the n-type semiconductor layer 5 and less than the Al composition ratio p of the first buffer layer 3. The Al composition ratio q of the second buffer layer 4 is, for example, 45% or more and 65% or less. The film thickness of the second buffer layer 4 is, for example, 80 nm or more and 120 nm or less.

[0023] As shown in Figure 2, the second buffer layer 4 contains silicon at a concentration exceeding, for example, the silicon concentration measurement limit in SIMS. A negative peak P2 appears in the silicon concentration distribution of the second buffer layer 4. This can be formed, for example, because the upper end of the second buffer layer 4 is adjacent to the n-type semiconductor layer 5 with a high silicon concentration, the lower end of the second buffer layer 4 is adjacent to the end of the first buffer layer 3 on the second interface 32 side where the silicon concentration is locally high, and no silicon source is supplied (or only a very small amount is supplied) during the deposition of the second buffer layer 4. The silicon concentration of the negative peak P2 (i.e., the peak bottom value Si bottom ) is the central silicon concentration Si of the first buffer layer 3. center The above is preferable (i.e., only sample 1 out of samples 1 to 5 in Figure 2). In the second buffer layer 4, compared to the first buffer layer 3, the Al composition ratio is lower and silicon doping is easier, and the peak bottom value of the negative peak P2 is Si bottom The central silicon concentration Si of the first buffer layer 3 center As a result, silicon is doped into the second buffer layer 4, causing appropriate strain in the crystal lattice constituting the second buffer layer 4. Consequently, lattice relaxation is less likely to occur during the deposition of the n-type semiconductor layer 5 on the second buffer layer 4, and it is presumed that the crystallinity of the n-type semiconductor layer 5 is improved. Negative peak P2 peak-bottom value Si bottom is 2.00 × 10 17 [atoms / cm 3The above is preferable. Also, if the silicon concentration of the second buffer layer 4 is too high, cracks may occur in the second buffer layer 4, making it difficult to deposit the second buffer layer 4, so the peak bottom value of the negative peak P2 is Si bottom is 1.00 × 10 18 [atoms / cm 3 The following are preferable.

[0024] As shown in Figure 1, the n-type semiconductor layer 5 is formed on the second buffer layer 4. The n-type semiconductor layer 5 is made of, for example, Al doped with n-type impurities. r Ga 1-r This is an n-type cladding layer formed by N(0≦r≦1). In this embodiment, silicon (Si) was used as the n-type impurity. The same applies to semiconductor layers containing n-type impurities other than the n-type semiconductor layer 5. Germanium (Ge), selenium (Se), or tellurium (Te) may also be used as the n-type impurity. The Al composition ratio r of the n-type semiconductor layer 5 is, for example, 45% to 65%. The n-type semiconductor layer 5 may be a single-layer structure or a multilayer structure.

[0025] The composition gradient layer 6 is formed on the n-type semiconductor layer 5. The composition gradient layer 6 is Al s Ga 1-s It consists of N(0≦s≦1). The Al composition ratio at each position in the vertical direction of the composition gradient layer 6 increases as the position gets higher. The composition gradient layer 6 may also include, for example, a very small area in the vertical direction (for example, less than 5% of the entire vertical region of the composition gradient layer 6) in which the Al composition ratio does not increase as you move upwards.

[0026] Preferably, the Al composition ratio at the lower end of the composition gradient layer 6 is approximately the same as (for example, a difference of 5% or less) the Al composition ratio at the upper end of the n-type semiconductor layer 5 adjacent to the lower side of the composition gradient layer 6. Furthermore, it is preferable that the Al composition ratio at the upper end of the composition gradient layer 6 is approximately the same as (for example, a difference of 5% or less) the Al composition ratio at the lower end of the barrier layer 71 adjacent to the upper side of the composition gradient layer 6.

[0027] The active layer 7 is formed on the composition gradient layer 6. The active layer 7 of this embodiment has a multiple quantum well structure having a plurality of well layers 721 and 722. The bandgap of the active layer 7 is adjusted so that it can emit ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. When the active layer 7 is a multiple quantum well structure as in this embodiment, from the viewpoint of improving the light output, the central wavelength of the ultraviolet light emitted by the active layer 7 is preferably 250 nm or more and 320 nm or less, and more preferably 260 nm or more and 290 nm or less. In this embodiment, the active layer 7 has three barrier layers 71 and three well layers 721 and 722, and the barrier layers 71 and the well layers 721 and 722 are alternately laminated. In the active layer 7, the barrier layer 71 is located at the lower end and the well layer 722 is located at the upper end.

[0028] Each barrier layer 71 is formed of Al t Ga 1-t N (0 < t ≦ ۱). The Al composition ratio t of each barrier layer 71 is, for example, 75% or more and 95% or less. Also, the film thickness of each barrier layer 71 is, for example, 2 nm or more and 50 nm or less.

[0029] The well layers 721 and 722 are formed of Al u Ga 1-u N (0 < u < ۱). The Al composition ratio u of each well layer 721 and 722 is smaller than the Al composition ratio t of the barrier layer 71 (that is, u < t).

[0030] The three well layers 721 and 722 have different compositions: the lowest well layer 721, which is located at the bottom, and the two upper well layers 722, which are the other two well layers. For example, the film thickness of the lowest well layer 721 is 1 nm or more greater than the film thickness of each of the two upper well layers 722, and the Al composition ratio of the lowest well layer 721 is 2% or more greater than the Al composition ratio of each of the two upper well layers 722. In this embodiment, the upper well layers 722 have a film thickness of 2 nm to 4 nm and an Al composition ratio of 25% to 45%, while the lowest well layer 721 has a film thickness of 4 nm to 6 nm and an Al composition ratio of 35% to 55%. The difference in film thickness between the lowest well layer 721 and each of the upper well layers 722 can be 2 nm to 4 nm.

[0031] By making the Al composition ratio of the bottom well layer 721 greater than that of the upper well layer 722, the crystallinity of the bottom well layer 721 is improved. This is because the difference in Al composition ratio between the bottom well layer 721 and the n-type semiconductor layer 5 becomes smaller. As the crystallinity of the bottom well layer 721 improves, the crystallinity of each semiconductor layer of the active layer 7 formed above the bottom well layer 721 also improves. This improves the carrier mobility in the active layer 7 and increases the optical output. This effect becomes more pronounced as the film thickness of the bottom well layer 721 increases, but from the viewpoint of suppressing an increase in the overall electrical resistance of the light-emitting element 1, the film thickness of the bottom well layer 721 is designed to be below a predetermined value.

[0032] In this embodiment, the active layer is shown as a multiple quantum well structure with three well layers, but it is not limited to this, and may also be a multiple quantum well structure with two or four or more well layers. Furthermore, the active layer may be a single quantum well structure having only one well layer.

[0033] The electron blocking layer 8 is formed on the active layer 7. The electron blocking layer 8 has the role of improving the electron injection efficiency into the active layer 7 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 7 to the p-type semiconductor layer 9 side (hereinafter also referred to as the electron blocking effect). The electron blocking layer 8 has a stacked structure in which a first layer 81 and a second layer 82 are stacked in order from the bottom side.

[0034] The first layer 81 is provided on the active layer 7. The first layer 81 is made of, for example, Al v Ga 1-v N (0 < v ≤ 1). The Al composition ratio v of the first layer 81 is, for example, 90% or more, and in this embodiment, it is made of aluminum nitride. The film thickness of the first layer 81 is, for example, 0.5 nm or more and 5.0 nm or less.

[0035] The second layer 82 is made of, for example, Al w Ga 1-w N (0 < w < 1). The Al composition ratio w of the second layer 82 is smaller than the Al composition ratio v of the first layer 81 (that is, w < v), and is, for example, 70% or more and 90% or less. The film thickness of the second layer 82 is larger than the film thickness of the first layer 81, and is, for example, 15 nm or more and 100 nm or less.

[0036] Since a semiconductor layer with a larger Al composition ratio has a larger electrical resistance value, if the film thickness of the first layer 81 with a relatively high Al composition ratio is made too large, an excessive increase in the overall electrical resistance value of the light-emitting device 1 will occur. Therefore, it is preferable to make the film thickness of the first layer 81 somewhat smaller. On the other hand, if the film thickness of the first layer 81 is made small, the probability that electrons tunnel through the first layer 81 from the bottom side to the top side can increase. Therefore, in the light-emitting device 1 of this embodiment, by forming the second layer 82 on the first layer 81, the electrons are suppressed from tunneling through the entire electron blocking layer 8.

[0037] The first layer 81 and the second layer 82 can each be an undoped layer, a layer containing n-type impurities, a layer containing p-type impurities, or a layer containing both n-type and p-type impurities. Magnesium (Mg) can be used as the p-type impurity, but other materials such as zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), or carbon (C) may also be used. The same applies to semiconductor layers containing other p-type impurities. When each electron block layer 8 contains impurities, the impurities contained in each electron block layer 8 may be contained in the entire electron block layer 8 or in a part of each electron block layer 8.

[0038] Silicon is present between the electron block layer 8 and the p-type semiconductor layer 9. Magnesium is easily attracted to silicon, and hydrogen easily combines with magnesium. The presence of silicon between the electron block layer 8 and the p-type semiconductor layer 9 suppresses the diffusion of magnesium and hydrogen from the p-type semiconductor layer 9 to the active layer 7, thereby extending the lifespan of the light-emitting element 1. Furthermore, the presence of silicon between the electron block layer 8 and the p-type semiconductor layer 9 allows for the formation of a layer with pits (for example, so-called V-pits) between the electron block layer 8 and the p-type semiconductor layer 9. Since pits are formed when a silicon source is supplied to the location where dislocations exist, the formation of pits suppresses the propagation of dislocations above the pits, thereby extending the lifespan of the light-emitting element 1.

[0039] The p-type semiconductor layer 9 is formed on the electron block layer 8. The p-type semiconductor layer 9 has a lower Al composition ratio than the electron block layer 8 and is doped with p-type impurities. x Ga 1-x It is formed by N(0≦x<1). In this embodiment, the p-type semiconductor layer 9 has a stacked structure in which a first p-type cladding layer 91, a second p-type cladding layer 92, and a p-type contact layer 93 are stacked in order from the bottom.

[0040] The first p-type clad layer 91 is provided so as to be in contact with the second layer 82. The first p-type clad layer 91 is made of Al y Ga 1-y N (0 < y < 1). The Al composition ratio y of the first p-type clad layer 91 is, for example, 45% or more and 65% or less. The film thickness of the first p-type clad layer 91 is, for example, 15 nm or more and 35 nm or less.

[0041] The second p-type clad layer 92 is made of Al z Ga 1-z N (0 < z < 1). The Al composition ratio at each position in the vertical direction of the second p-type clad layer 92 becomes smaller as the position is higher. Note that the second p-type clad layer 92 may include a region where the Al composition ratio does not decrease as it goes upward in a very small part of the stacking direction (for example, a region within 5% of the entire stacking direction of the second p-type clad layer 92).

[0042] It is preferable that the Al composition ratio of the lower end portion of the second p-type clad layer 92 is substantially the same as the Al composition ratio of the first p-type clad layer 91 (for example, the difference is within 5%), and the Al composition ratio of the upper end portion of the second p-type clad layer 92 is substantially the same as the Al composition ratio of the p-type contact layer 93 (for example, the difference is within 5%). The film thickness of the second p-type clad layer 92 can be, for example, 2 nm or more and 4 nm or less.

[0043] The p-type contact layer 93 is a layer to which the p-side electrode 12 described later is connected, and is doped with a high concentration of p-type impurities. The p-type contact layer 93 is configured such that the Al composition ratio is low (for example, 10% or less) in order to achieve an ohmic contact with the p-side electrode 12, and from this perspective, it is preferably formed of p-type gallium nitride (GaN). The film thickness of the p-type contact layer 93 is, for example, 10 nm or more and 25 nm or less. Note that the p-type semiconductor layer 9 may be a single layer or a plurality of layers.

[0044] The n-side electrode 11 is formed on the exposed surface 51 of the n-type semiconductor layer 5 that is exposed above the active layer 7. The n-side electrode 11 can be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and titanium nitride (TiN) are sequentially stacked on the n-type semiconductor layer 5.

[0045] The p-side electrode 12 is formed on the upper surface of the p-type semiconductor layer 9. The p-side electrode 12 can be made of, for example, rhodium (Rh). In this embodiment, the p-side electrode 12 is a reflective electrode having a reflectance of 50% or more, preferably 60% or more, at the central wavelength of light emitted by the active layer 7, but is not limited to this.

[0046] The light-emitting element 1 is used by being flip-chip mounted on a package substrate (not shown). Specifically, the light-emitting element 1 is mounted with the side where the n-side electrode 11 and p-side electrode 12 are provided facing the package substrate, and each of the n-side electrode 11 and p-side electrode 12 is mounted on the package substrate via connecting members such as gold bumps. Light is extracted from the substrate 2 side (i.e., the bottom side) of the flip-chip mounted light-emitting element 1.

[0047] (Method for manufacturing nitride semiconductor light-emitting element 1) Next, an example of a method for manufacturing the light-emitting element 1 of this embodiment will be described. In this embodiment, a first buffer layer 3, a second buffer layer 4, an n-type semiconductor layer 5, a composition gradient layer 6, an active layer 7, an electron blocking layer 8, and a p-type semiconductor layer 9 are sequentially epitaxially grown on a disc-shaped substrate 2 by metal-organic chemical vapor deposition (MOCVD). That is, in this embodiment, the disc-shaped substrate 2 is placed in a chamber, and each semiconductor layer is formed on the substrate 2 by introducing the source gas for each semiconductor layer into the chamber. As source gases for epitaxial growth of each semiconductor layer, trimethylaluminum (TMA) can be used as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH3) as a nitrogen source, tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (Cp2Mg) as a magnesium source.

[0048] The MOCVD method is sometimes also called Metal Organic Vapor Phase Epitaxy (MOVPE). Furthermore, other epitaxial growth methods such as Molecular Beam Epitaxy (MBE) and Hydride Vapor Phase Epitaxy (HVPE) can also be used to epitaxially grow each semiconductor layer on substrate 2.

[0049] In the manufacturing method of the light-emitting element 1 of this embodiment, when the first buffer layer 3 is formed, the central silicon concentration Si of the first buffer layer 3 centerAs mentioned above, measures are taken to keep this low. For example, the chamber used for depositing each semiconductor layer of the light-emitting element 1 should contain as little silicon as possible. If a material containing silicon as a constituent element is used in the chamber, there is a concern that silicon will be released from the material constituting the chamber during wafer deposition, resulting in a high silicon content in the first buffer layer 3. For example, in the HVPE method, quartz (SiO2) is often used in the chamber, so it is preferable to deposit each semiconductor layer of the light-emitting element 1 using the MOCVD method. In addition, in this embodiment, the amount of TMSi supplied during the deposition of the first buffer layer 3 is set to 3.0 sccm or less (including zero). This also reduces the central silicon concentration Si in the first buffer layer 3. center As mentioned above, this will decrease.

[0050] Furthermore, in the manufacturing method of the light-emitting element 1 of this embodiment, the intermediate consisting of the substrate 2 and the first buffer layer 3 obtained after the deposition of the first buffer layer 3 is exposed to an atmosphere containing silicon. For example, the intermediate is temporarily removed from the chamber into the atmosphere containing silicon. As a result, silicon is incorporated into the first buffer layer 3 from the side of the first buffer layer 3 opposite to the substrate 2, and the aforementioned positive peak P1 appears in the silicon concentration distribution of the light-emitting element 1.

[0051] After the intermediate is returned to the chamber, the second buffer layer 4, n-type semiconductor layer 5, composition gradient layer 6, active layer 7, electron blocking layer 8, and p-type semiconductor layer 9 are sequentially epitaxially grown. In this embodiment, when the second buffer layer 4 is deposited, TMSi, which is the silicon source, is not supplied, and as a result, the second buffer layer 4 is deposited as an undoped semiconductor layer. Furthermore, the manufacturing conditions such as growth temperature, growth pressure, and growth time for epitaxial growth of each semiconductor layer on the wafer can be general conditions according to the configuration of each semiconductor layer.

[0052] After forming each semiconductor layer on a disc-shaped substrate 2, a mask is formed on a portion of the p-type semiconductor layer 9, i.e., the portion other than the exposed surface 51 of the n-type semiconductor layer 5. Then, the area where the mask is not formed is etched away from the top surface of the p-type semiconductor layer 9 up to partway down the n-type semiconductor layer 5 in the vertical direction. This creates an exposed surface 51 on the n-type semiconductor layer 5 that is exposed upwards. After the exposed surface 51 is formed, the mask is removed.

[0053] Next, an n-side electrode 11 is formed on the exposed surface 51 of the n-type semiconductor layer 5, and a p-side electrode 12 is formed on the p-type semiconductor layer 9. The n-side electrode 11 and the p-side electrode 12 may be formed by well-known methods such as electron beam deposition or sputtering. By cutting the completed material into desired dimensions, multiple light-emitting elements 1 as shown in Figure 1 can be manufactured from a single wafer.

[0054] (Operation and Effects of the Embodiment) In this embodiment, the light-emitting element 1 has a silicon concentration Si at the center C in the stacking direction of the first buffer layer 3. center However, 1.02 × 10 18 [atoms / cm 3 The result is as follows. Therefore, the light output of light-emitting element 1 is improved. This value will be supported by the experimental example described later.

[0055] Furthermore, in the silicon concentration distribution of the second buffer layer 4, a negative peak P2 appears, and the silicon concentration of the negative peak P2 (i.e., the peak-bottom value Si) bottom ) is the silicon concentration Si at the center C in the stacking direction of the first buffer layer 3. center That concludes the explanation. In the second buffer layer 4, compared to the first buffer layer 3, the Al composition ratio is lower and silicon doping is more easily performed, and the peak bottom value of the negative peak P2 is Si bottom The silicon concentration Si at the center C in the stacking direction of the first buffer layer 3 centerAs a result, silicon is doped into the second buffer layer 4, causing appropriate strain in the crystal lattice constituting the second buffer layer 4. Consequently, lattice relaxation is less likely to occur during the deposition of the n-type semiconductor layer 5 on the second buffer layer 4, and it is presumed that the crystallinity of the n-type semiconductor layer 5 will improve. Furthermore, the silicon concentration of the first buffer layer 3 is lower, which also improves the optical output of the light-emitting element 1.

[0056] Furthermore, in the silicon concentration distribution of the light-emitting element 1, a positive peak P1 appears in the stacking direction range that includes the position of the second interface 32. In this way, the presence of a certain amount or more of silicon near the second interface 32 of the first buffer layer 3 suppresses the extension of dislocations extending upward from the substrate 2 beyond the second interface 32.

[0057] Also, the silicon concentration at the positive peak P1 (i.e., the peak top value Si) top ) is 2.22 × 10 18 [atoms / cm 3 This completes the explanation. As a result, dislocations extending upward from the substrate 2 are further suppressed from extending beyond the second interface 32.

[0058] Furthermore, the Al composition ratio of the second buffer layer 4 is greater than or equal to that of the n-type semiconductor layer 5. Therefore, abrupt changes in the Al composition ratio between the second buffer layer 4 and the adjacent buffer layer 5 are suppressed, and the generation of dislocations in the n-type semiconductor layer 5 due to lattice mismatch is suppressed.

[0059] Furthermore, the intermediate, in which the first buffer layer 3 is formed on the substrate 2, is exposed to a silicon-containing atmosphere before the second buffer layer 4 is formed. This makes it possible to easily manufacture a light-emitting element 1 in which the aforementioned positive peak P1 appears in the silicon concentration distribution.

[0060] As described above, this embodiment provides a nitride semiconductor light-emitting element and a method for manufacturing a nitride semiconductor light-emitting element that can improve the optical output.

[0061] [Example of experiment] In this experimental example, the central silicon concentration Si of the first buffer layer 3 is center This is an example of evaluating the change in the optical output of a wafer when a certain factor is changed. Note that, unless otherwise specified, any component names used in this experimental example that are the same as those used in previously described configurations represent the same components as those in the previously described configurations.

[0062] In this experimental example, as shown in Figure 2, the central silicon concentration of the first buffer layer 3 is Si center Wafers for samples 1 to 5 with different properties were prepared. Unless otherwise specified below, samples 1 to 5 are wafers having the same basic configuration as the light-emitting element 1 in the embodiment, and were manufactured using the same manufacturing method as the light-emitting element 1 in the embodiment. Central silicon concentration Si of the first buffer layer 3 center The adjustment was made by changing the amount of TMSi, the silicon source, supplied when depositing the first buffer layer 3 for each of the samples 1 to 5. The amount of TMSi supplied when depositing the first buffer layer 3 was 0.0 sccm for sample 1, 2.5 sccm for sample 2, 3.0 sccm for sample 3, 3.5 sccm for sample 4, and 4.0 sccm for sample 5 (see Table 2 below). In addition, the central silicon concentration of the first buffer layer 3 in samples 1 to 5 was Si center As a result of this change, the peak-bottom value of the negative peak P2 in the silicon concentration distribution of the second buffer layer 4, Si, changes as shown in Figures 2 and 3. bottom , and the peak top value Si of the positive peak P1 near the second interface 32 of the first buffer layer 3. top This has also changed. Table 1 will be used to explain the wafers of samples 1 to 5.

[0063] [Table 1]

[0064] The film thickness of each semiconductor layer listed in Table 1 was measured by transmission electron microscopy. The Al composition ratio of each layer listed in Table 1 is an estimated value from the secondary ion intensity of Al measured by SIMS. In addition, the column for composition gradient layer 6 in Table 1 indicates that the Al composition ratio at each position in the vertical direction of composition gradient layer 6 gradually increases from 55% to 85% from the bottom end to the top end of composition gradient layer 6. In addition, the column for the second p-type cladding layer 92 in Table 1 indicates that the Al composition ratio at each position in the vertical direction of the second p-type cladding layer 92 gradually decreases from 55% to 0% from the bottom end to the top end of the second p-type cladding layer 92.

[0065] Furthermore, the Si and Mg concentrations listed in Table 1 are those obtained when the wafer was measured from above using SIMS. In Table 1, the silicon concentration of the bottom well layer 721 represents the peak silicon concentration at each vertical position of the bottom well layer 721. In Table 1, the * marks in the Si concentration column indicate that accurate measurement of silicon and magnesium concentrations is difficult due to the thin film thickness of the semiconductor layer. Also, in the Si concentration and Mg concentration columns in Table 1, the notation "BG" stands for background level. The background level is the silicon or magnesium concentration detected when silicon or magnesium is not doped. Furthermore, in Table 1, for the silicon concentration in the second layer 82 of the electron block layer 8 and the first p-type cladding layer 91 of the p-type semiconductor layer 9, the peak silicon concentration at the interface between the second layer 82 and the first p-type cladding layer 91 is (2.00±1.00)×10 19 [atoms / cm 3 This means that the peak is at a background level at all other stacking directions except for this peak.

[0066] In Table 1, for the components common to Samples 1 to 5, Samples 1 to 5 are shown without distinction, and for the components that are different from each other in Samples 1 to 5, that is, the silicon concentration of the first buffer layer 3 and the silicon concentration of the second buffer layer 4, they are shown individually for each of Samples 1 to 5. In the column of the silicon concentration of the first buffer layer 3 in Table 1, the central silicon concentration Si center of each sample is described. In the column of the silicon concentration of the second buffer layer 4 in Table 1, the peak bottom value Si bottom of the negative peak P2 of the second buffer layer 4 of each sample is described.

[0067] And in each of Samples 1 to 5, the emission output (arbitrary unit) can be measured by various known methods. In this experimental example, as an example, In (indium) electrodes are attached to the center and edge of one wafer respectively, a predetermined current is passed through this electrode to cause the center of the wafer to emit light, and a method of measuring this emission with a photodetector installed at a predetermined position is used. The magnitude of the current passed during measurement was 20 mA. The results are shown in Table 2 and FIG. 4. FIG. 4 is a graph showing the relationship between the central silicon concentration Si center of the first buffer layer 3 and the light output.

[0068]

Table 2

[0069] As can be seen from Table 2 and FIG. 4, Samples 1 to 3 that satisfy the central silicon concentration Si center of the first buffer layer 3 being 1.02×10 18 [atoms / cm 3 or less have a higher light output than Samples 4 and 5 in which the central silicon concentration Si center of the first buffer layer 3 exceeds 1.02×10 18 [atoms / cm 3 . Therefore, the central silicon concentration Si center of the first buffer layer 3 is 1.02×10 18 [atoms / cm 3It can be seen that the optical output can be improved by setting it to the following. Also, the central silicon concentration Si of the first buffer layer 3 center 0.91 × 10 18 [atoms / cm 3 High light output was obtained in samples 1 and 2 that satisfy the following conditions, therefore the central silicon concentration Si of the first buffer layer 3 center is 0.91 × 10 18 [atoms / cm 3 The following is preferable. Furthermore, the central silicon concentration Si of the first buffer layer 3. center 0.83 × 10 18 [atoms / cm 3 Since sample 1 satisfying the following conditions yielded the highest light output, the central silicon concentration of the first buffer layer 3 is Si center is 0.83 × 10 18 [atoms / cm 3 The following is more preferable. From a similar viewpoint, the central silicon concentration Si of the first buffer layer 3 center 9.12 × 10 17 [atoms / cm 3 The following is preferable: 8.39 × 10 17 [atoms / cm 3 The following is preferable: 3.10 × 10 16 [atoms / cm 3 The following are preferable.

[0070] Furthermore, it can be seen that sample 1, in which TMSi was not supplied during the deposition of the first buffer layer 3, has a higher optical output than any of samples 2 to 5, in which TMSi was supplied during the deposition of the first buffer layer 3. Therefore, it is preferable to form the first buffer layer 3 as an undoped semiconductor layer. Note that when the TMSi flow rate during the deposition of the first buffer layer 3 was increased compared to that of sample 5, the first buffer layer 3 cracked, making deposition difficult.

[0071] Also, from Table 2, the peak-bottom values ​​Si bottom The central silicon concentration Si of the first buffer layer 3 center For sample 1, which is as described above, the peak-bottom value Si bottomThe central silicon concentration Si of the first buffer layer 3 center Compared to samples 2-5, which have values ​​less than Si, the light output is higher. In other words, the peak-bottom value is Si bottom This is the central silicon concentration Si of the first buffer layer 3. center The above is preferable.

[0072] (Summary of the embodiments) Next, the technical concept understood from the embodiments described above will be described using the reference numerals and other symbols from the embodiments. However, the reference numerals and other symbols in the following description are not limited to the components in the claims that are specifically shown in the embodiments.

[0073] [1] A first embodiment of the present invention comprises a substrate 2, a first buffer layer 3 formed on the substrate 2 containing Al and N, a second buffer layer 4 formed on the first buffer layer 3 containing Al, Ga and N and having a smaller Al composition ratio than the first buffer layer 3, an n-type semiconductor layer 5 formed on the second buffer layer 4, an active layer 7 formed on the n-type semiconductor layer 5 that emits ultraviolet light with a central wavelength of 365 nm or less, and a p-type semiconductor layer 9 formed on the active layer 7, wherein the silicon concentration at the center of the stacking direction of the first buffer layer 3 is 1.02 × 10 18 [atoms / cm 3 The following is a nitride semiconductor light-emitting element 1. This makes it possible to improve the optical output of the nitride semiconductor light-emitting element 1.

[0074] [2] A second embodiment of the present invention is that, in the first embodiment, a negative peak P2 appears in the silicon concentration distribution of the second buffer layer 4 in the stacking direction, and the silicon concentration of the negative peak P2 is equal to or greater than the silicon concentration at the center of the first buffer layer 3 in the stacking direction. This is expected to improve the crystallinity of the n-type semiconductor layer 5.

[0075] [3] A third embodiment of the present invention is that, in the first or second embodiment, a positive peak P1 appears in the distribution of silicon concentration in the stacking direction in a range in the stacking direction that includes the location of the interface 32 on the second buffer layer 4 side of the first buffer layer 3. This suppresses the extension of dislocations from the substrate 2 to the p-type semiconductor layer 9.

[0076] [4] A fourth embodiment of the present invention is the third embodiment in which the silicon concentration of the positive peak P1 is 2.22 × 10 18 [atoms / cm 3 It must be at least [the above]. This further suppresses the extension of dislocations from substrate 2 to the p-type semiconductor layer 9.

[0077] [5] A fifth embodiment of the present invention is that, in any one of the first to fourth embodiments, the Al composition ratio of the second buffer layer 4 is equal to or greater than the Al composition ratio of the n-type semiconductor layer 5. This suppresses the occurrence of dislocations in the n-type semiconductor layer 55 that are caused by lattice mismatch.

[0078] [6] In a sixth embodiment of the present invention, a first buffer layer 3 containing Al and N is formed on a substrate 2, a second buffer layer 4 containing Al, Ga and N and having a smaller Al composition ratio than the first buffer layer 3 is formed on the first buffer layer 3, an n-type semiconductor layer 5 is formed on the second buffer layer 4, an active layer 7 emitting ultraviolet light with a center wavelength of 365 nm or less is formed on the n-type semiconductor layer 5, a p-type semiconductor layer 9 is formed on the active layer 7, and the silicon concentration at the center of the stacking direction of the first buffer layer 3 is 1.02 × 10 18 [atoms / cm 3 The following is a method for manufacturing a nitride semiconductor light-emitting element 1. This makes it possible to manufacture nitride semiconductor light-emitting element 1 with improved light output.

[0079] [7] A seventh embodiment of the present invention is, in the sixth embodiment, an intermediate having the first buffer layer 3 formed on the substrate 2 is exposed to a silicon-containing atmosphere before the second buffer layer 4 is formed, thereby causing a positive peak P1 to appear in the silicon concentration distribution in the stacking direction in a range in the stacking direction that includes the position of the interface 32 of the first buffer layer 3 on the second buffer layer 4 side. This makes it possible to easily manufacture a nitride semiconductor light-emitting element 1 in which the extension of dislocations from the substrate 2 to the p-type semiconductor layer 9 side is suppressed.

[0080] (Note) Although embodiments of the present invention have been described above, the embodiments described herein do not limit the invention as defined in the claims. Furthermore, it should be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention. Moreover, the present invention can be implemented with appropriate modifications without departing from its spirit. [Explanation of symbols]

[0081] 1…Nitride semiconductor light-emitting element 2… Circuit board 3…First buffer layer 31...1st interface 32…Second interface 4…Second buffer layer 5...n-type semiconductor layer 55...n-type semiconductor layer 7…Active layer 9...p-type semiconductor layer P1…Positive peak P2…Negative peak

Claims

1. circuit board and A first buffer layer containing Al and N is formed on the substrate, A second buffer layer is formed on the first buffer layer, contains Al, Ga, and N, and has a lower Al composition ratio than the first buffer layer, An n-type semiconductor layer formed on the second buffer layer, An active layer formed on the aforementioned n-type semiconductor layer, which emits ultraviolet light with a central wavelength of 365 nm or less, The active layer comprises a p-type semiconductor layer formed on the active layer, The silicon concentration at the center of the stacking direction of the first buffer layer is 1.02 × 10⁻¹⁶. １８ [atoms / cm ３ The following is true: Nitride semiconductor light-emitting element.

2. In the distribution of silicon concentration in the second buffer layer in the stacking direction, a negative peak appears. The silicon concentration of the negative peak is greater than or equal to the silicon concentration at the center of the stacking direction of the first buffer layer. The nitride semiconductor light-emitting device according to claim 1.

3. In the silicon concentration distribution in the stacking direction, a positive peak appears in the range of the stacking direction that includes the position of the interface of the first buffer layer on the second buffer layer side. The nitride semiconductor light-emitting element according to claim 1 or 2.

4. The silicon concentration of the aforementioned positive peak is 2.22 × 10⁻⁶. １８ [atoms / cm ３ That's all. The nitride semiconductor light-emitting device according to claim 3.

5. The Al composition ratio of the second buffer layer is equal to or greater than the Al composition ratio of the n-type semiconductor layer. The nitride semiconductor light-emitting element according to claim 1 or 2.

6. A first buffer layer containing Al and N is formed on the substrate. A second buffer layer containing Al, Ga, and N, with a lower Al composition ratio than that of the first buffer layer, is formed on the first buffer layer. An n-type semiconductor layer is formed on the second buffer layer. An active layer emitting ultraviolet light with a central wavelength of 365 nm or less is formed on the aforementioned n-type semiconductor layer. A p-type semiconductor layer is formed on the active layer, The silicon concentration at the center of the stacking direction of the first buffer layer is 1.02 × 10⁻¹⁶. １８ [atoms / cm ３ The following is true: A method for manufacturing a nitride semiconductor light-emitting element.

7. The intermediate on which the first buffer layer is formed on the substrate is exposed to a silicon-containing atmosphere before the second buffer layer is formed, thereby causing a positive peak to appear in the silicon concentration distribution in the stacking direction, within the range of the stacking direction including the interface of the first buffer layer on the second buffer layer side. The method for manufacturing a nitride semiconductor light-emitting element according to claim 6.

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