Semiconductor light-emitting element, semiconductor light-emitting device, and method for manufacturing the same

Abstract

It allows for easy and stable electrical connection. [Solution] The semiconductor light-emitting device has a laminate in which a plurality of light-emitting unit layers, each consisting of a p-type layer, an emissive layer, and an n-type layer, are stacked in a predetermined stacking direction, and a tunnel junction layer is provided between the p-type and n-type layers of adjacent light-emitting unit layers in the stacking direction. The laminate is partitioned by partition grooves and constitutes a plurality of pixels having a plurality of subpixels. The subpixels are divided into an emissive portion and a non-emissive portion by a partition groove that divides the emissive layer of a predetermined light-emitting unit layer, electrodes are provided on the mounting surfaces of the emissive portion and the non-emissive portion, and conductive vias are provided from the electrodes to a predetermined n-type layer for circuit configuration to the emissive layer of the predetermined light-emitting unit layer. The side surface of the conductive via is a surface that is inclined at an angle with respect to the stacking direction from the side surface of the partition groove. In the plurality of subpixels, the electrodes on the emissive portion side are formed on the same plane, and the electrodes on the non-emissive portion side are formed on the same plane.

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting element, a semiconductor light-emitting device, and a method for manufacturing the same.

Background Art

[0002] As a high-resolution color display, several p-n junction LEDs are grown in the same epitaxial wafer, and a multi-level mesa etching process is performed to form independent electrical contacts for each p-n junction, and a semiconductor light-emitting element capable of independently controlling the wavelength and emission luminance is known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the semiconductor light-emitting element described in Patent Document 1, independent electrical contacts for each p-n junction are formed at different heights. Therefore, when mounted on a mounting substrate, there is a problem that electrical connection failure is likely to occur. Alternatively, in order to achieve good electrical connection, it is necessary to use a mounting substrate with a complex structure that can accommodate electrical contacts with different heights.

[0005] The present invention has been made in view of the above conventional circumstances, and an object thereof is to provide a semiconductor light-emitting element, a semiconductor light-emitting device, and a method for manufacturing the same that can easily and stably achieve electrical connection.

Means for Solving the Problems

[0006] (1) The semiconductor light-emitting element according to the first aspect of the present invention is Multiple light-emitting unit layers (30R, 30G, 30B), each consisting of a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310), are stacked in a predetermined stacking direction. A laminate (30) is provided in which tunnel junction layers (305, 309) are provided between the p-type layer and the n-type layer of the light-emitting unit layer adjacent to each other in the stacking direction. Multiple pixels (70) are partitioned by partition grooves (80) and each pixel (70) has multiple subpixels (71), The sub-pixel is divided into an emitting portion (72) and a non-emitting portion (73) by a dividing groove (801) that divides the emitting layer of a predetermined emitting unit layer. An electrode (31) is provided on the mounting surface of the light-emitting portion and the non-light-emitting portion, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, The side surface of the conductive via is a surface that is inclined at an angle with respect to the stacking direction from the side surface of the partition groove. In the plurality of subpixels, the electrodes on the light-emitting side are formed on the same plane, and the electrodes on the non-light-emitting side are formed on the same plane. This resolved the above issues. (2) The semiconductor light-emitting element according to the second aspect of the present invention is Multiple light-emitting unit layers (30R, 30G, 30B), each consisting of a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310), are stacked in a predetermined stacking direction. A laminate (30) is provided in which tunnel junction layers (305, 309) are provided between the p-type layer and the n-type layer of the light-emitting unit layer adjacent to each other in the stacking direction. Multiple pixels (70) are partitioned by partition grooves (80) and each pixel (70) has multiple subpixels (71), The sub-pixel is divided into an emitting portion (72) and a non-emitting portion (73) by a dividing groove (801) that divides the emitting layer of a predetermined emitting unit layer. An electrode (31) is provided on the mounting surface of the light-emitting portion and the non-light-emitting portion, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, The conductive via includes a plurality of conductive vias of different depths, and the conductive via that is deeper than the other conductive vias has a continuous shape without steps on the side surface of the portion corresponding to the depth of the other conductive vias. In the plurality of subpixels, the electrodes on the light-emitting side are formed on the same plane, and the electrodes on the non-light-emitting side are formed on the same plane. This resolved the above issues. (3) The semiconductor light-emitting device of the present invention is as described in (2) above, The side surface of the conductive via is formed perpendicular to the mounting surface. It is possible. (4) The semiconductor light-emitting device of the present invention is one of the above (1) to (3), The electrode on the light-emitting side and the electrode on the non-light-emitting side are formed on the same plane. It is possible. (5) The semiconductor light-emitting device of the present invention is one of the above (1) to (3), The dividing groove of the sub-pixel is a groove that is shallower than the conductive via of the light-emitting portion of a sub-pixel other than the sub-pixel, and has the same depth as the dividing groove to the n-type layer. It is possible. (6) The semiconductor light-emitting element of the present invention is one of the above (1) to (3), In the sub-pixel, the conductive via on the non-emitting portion side is a groove deeper than the dividing groove. It is possible. (7) The semiconductor light-emitting device of the present invention is one of the above (1) to (3), The division groove has a bottom portion (801x) which has a flat surface (801y), and a recess (801z) which is deeper than the flat surface. It can be done this way. (8) A semiconductor light-emitting device according to another aspect of the present invention is A semiconductor light-emitting element (1) described in any one of (1) to (3) is mounted on a mounting substrate (90), It is possible. (9) A method for manufacturing a semiconductor light-emitting element according to another aspect of the present invention is: A light-emitting unit layer (30R, 30G, 30B) in which a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310) are stacked is stacked on a device substrate (10) in a plurality in a predetermined stacking direction. A stacked body (30) provided with tunnel junction layers (305, 309) between the p-type layer and the n-type layer of the light-emitting unit layers adjacent in the stacking direction. It is partitioned by a partition groove (80) and constitutes a plurality of pixels (70) having a plurality of sub-pixels (71). The sub-pixel is divided into a light-emitting part (72) and a non-light-emitting part (73) by a division groove (801) that divides the light-emitting layer of a predetermined light-emitting unit layer. An electrode (31) is provided on the mounting surfaces of the light-emitting part and the non-light-emitting part, and has a conductive via (32) leading to a predetermined n-type layer for a circuit configuration from the electrode to the light-emitting layer of the predetermined light-emitting unit layer. A method for manufacturing a semiconductor light-emitting device, in which, in the plurality of sub-pixels, the electrodes on the light-emitting part side are formed on the same plane, and the electrodes on the non-light-emitting part side are formed on the same plane. An epitaxial stacking step (S00) in which each layer of the stacked body is formed on the device substrate by epitaxial film formation. A pixel partition groove forming step (S01) in which the partition groove is formed by etching in the stacking direction of the stacked body. A pixel shape processing step (S02) in which at least the groove of the conductive via of the light-emitting part among the division groove and the conductive via is formed by multiple etching. An electrode forming step (S05) in which the electrode and the conductive via are formed. Having It can be. (10) The method for manufacturing a semiconductor light-emitting device of the present invention is as described in (9) above. In the multiple etching of the pixel shape processing step. The division groove and the groove of the conductive via are formed from a shallower portion, and a difference is additionally formed in a deeper portion. It can be. (11) The method for manufacturing a semiconductor light-emitting device of the present invention is as described in (9) above. In multiple etchings in the pixel shape processing step, the dividing grooves and the grooves of the conductive vias are formed for grooves of the same depth. This is possible. (12) The grooves of the conductive vias in the non-light-emitting portion are formed in the pixel division groove forming step (S01). This is possible. (13) A method for manufacturing a semiconductor light-emitting device according to another aspect of the present invention is The semiconductor light-emitting element manufactured by the manufacturing method described in (9) above is mounted on a mounting substrate (90). This is possible. (14) The method for manufacturing a semiconductor light-emitting device of the present invention is, in (13) above, after the semiconductor light-emitting element is mounted on the mounting substrate, It can have a lift-off step of lifting off the element substrate. This is possible. (15) The method for manufacturing a semiconductor light-emitting device of the present invention is, in (13) above, The pixels of the semiconductor light-emitting element can be such that the plurality of sub-pixels are integrated. This is possible.

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a semiconductor light-emitting element, a semiconductor light-emitting device, and a manufacturing method thereof that can easily achieve stable electrical connection.

Brief Description of the Drawings

[0008] [Figure 1] It is a schematic diagram showing a VR goggle which is an example of a display device including a first embodiment of a semiconductor light-emitting device according to the present invention. [Figure 2] It is a schematic plan view showing a mounting substrate used in the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 3] It is a partial plan view showing the arrangement of pixels and the like in the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 4] This is a plan view showing a pixel in a first embodiment of a semiconductor light-emitting device according to the present invention. [Figure 5] This is a cross-sectional view showing a pixel in a first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 6] This is a cross-sectional view in a direction that intersects with Figure 5. [Figure 7] This is a schematic cross-sectional view illustrating the principle of current flow in the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 8] This is a cross-sectional view showing the bottom of a divided groove in the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 9] This is a flowchart showing a first embodiment of a method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 10] This is an explanatory diagram illustrating a first embodiment of the method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 11] This is an explanatory diagram illustrating a first embodiment of the method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 12] This is an explanatory diagram illustrating a first embodiment of the method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 13] This is an explanatory diagram of a process showing a modified example 1 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 14] This is an explanatory diagram of a process showing a modified example 2 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 15] This is an explanatory diagram of a process showing a modified example 3 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 16] This is an explanatory diagram of a process showing a modified example 4 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 17] This is an explanatory diagram of a process showing a modified example 5 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 18] This is a cross-sectional view showing a first embodiment of a semiconductor light-emitting device according to the present invention. [Figure 19] This is a cross-sectional view showing a first embodiment of a semiconductor light-emitting device according to the present invention. [Figure 20] This is a schematic partial cross-sectional view showing a modified example 1 of the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 21] This is a schematic partial cross-sectional view showing a modified example 2 of the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 22] This is a cross-sectional view showing each pixel in a modified example 6 of the first embodiment of the semiconductor light-emitting element according to the present invention. [Figure 23] This is a schematic partial cross-sectional view showing a modified example 3 of the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 24] This is a schematic cross-sectional view showing another modification of the first embodiment of the semiconductor light-emitting device according to the present invention. [Figure 25] This is an explanatory diagram of a process showing a second embodiment of the method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 26] This is an explanatory diagram of a process showing a second embodiment of the method for manufacturing a semiconductor light-emitting element according to the present invention. [Figure 27] This is a cross-sectional view showing a second embodiment of the semiconductor light-emitting device according to the present invention. [Modes for carrying out the invention]

[0009] [First Embodiment] Hereinafter, a first embodiment of the semiconductor light-emitting element, semiconductor light-emitting device, and method for manufacturing the same according to the present invention will be described with reference to the drawings. Figure 1 is a schematic diagram showing a VR goggle, which is an example of a display device including a semiconductor light-emitting device in this embodiment. In the figure, reference numeral 100 denotes the semiconductor light-emitting device.

[0010] The semiconductor light-emitting device 100 according to this embodiment is used in a display device such as a VR goggle. The VR (Virtual Reality) goggle 200 comprises a plurality of semiconductor light-emitting devices 100, as shown in Figure 1. The semiconductor light-emitting devices 100 are positioned in front of the viewer's eyes 202, with the lens 201 in between. The distance between the semiconductor light-emitting device 100 and the viewer's eyes 202 is approximately 5 cm. The semiconductor light-emitting device 100 is, for example, a self-emissive display in which 320 × 180 pixels are densely arranged in a dot matrix. The width of the pixels of the semiconductor light-emitting device 100 may be less than 100 μm. The width of the pixels of the semiconductor light-emitting device 100 is formed to be, for example, 60 μm, 12 μm, or 5 μm.

[0011] Figure 2 is a schematic plan view showing the mounting substrate used in the semiconductor light-emitting device in this embodiment. The semiconductor light-emitting device 100 includes a mounting substrate 90 as shown in Figure 2, and a semiconductor light-emitting element 1 mounted on the mounting area of ​​the mounting substrate 90.

[0012] The mounting substrate 90 is provided with metal bumps 94 that serve as connection terminals to the semiconductor light-emitting element 1, and a plurality of external terminals 90t within the mounting area of ​​the mounting substrate 90. The plurality of metal bumps 94 and the plurality of external terminals 90t are electrically connected by three-dimensional wiring such as wiring 91 and wiring 93. The mounting substrate 90 also incorporates a CMOS (Complementary Metal Oxide Semiconductor) and has a switching function.

[0013] The semiconductor light-emitting element 1 has multiple pixels 70 arranged vertically and horizontally at positions corresponding to the metal bumps 94 in the mounting area of ​​the mounting substrate 90, as described later. The semiconductor light-emitting element 1 is electrically connected to an external terminal 90t and is mounted on the surface of the mounting substrate 90 facing the viewer's eye 202. The light emitted from the semiconductor light-emitting element 1 reaches the viewer's eye 202. In the following explanation, the direction of the semiconductor light-emitting device 100 relative to the viewer's eye 202 is defined as the Z direction. The semiconductor light-emitting device 100 is mainly shown with the direction of the viewer's eye 202 as "up," but the semiconductor light-emitting element 1 is shown with the direction opposite to the viewer's eye 202 as "up." The direction opposite to the viewer's eye 202 is defined as the positive Z direction.

[0014] [Semiconductor light-emitting element of the first embodiment] Figure 3 is a partial plan view showing the arrangement of pixels and other elements of a semiconductor light-emitting element in this embodiment. In Figure 3, multiple pixels are arranged along the XY plane formed by the X and Y directions. The Z direction is the normal direction of the XY plane. The X, Y, and Z directions are orthogonal to each other. The semiconductor light-emitting element 1 has a plurality of pixels 70 partitioned by partition grooves 80. The plurality of pixels 70 are arranged in a matrix, adjacent to each other along the XY plane.

[0015] Figure 4 is a plan view showing the pixels of the semiconductor light-emitting element in this embodiment. The pixels 70 are formed in a substantially square shape. The pixels 70 have sub-pixels 71, which are divided by partition grooves 802, and include sub-pixels 71B that emit blue light, sub-pixels 71G that emit green light, and sub-pixels 71R that emit red light.

[0016] Each sub-pixel 71 has a light-emitting portion 72 and a non-light-emitting portion 73, which are separated by a dividing groove 801. Specifically, the sub-pixel 71B that emits blue light has an emitter portion 72B and a non-emitter portion 73B, the sub-pixel 71G that emits green light has an emitter portion 72G and a non-emitter portion 73G, and the sub-pixel 71R that emits red light has an emitter portion 72R and a non-emitter portion 73R.

[0017] Each sub-pixel 71 has an electrode 31p and an electrode 31n formed on its light-emitting portion 72 and non-light-emitting portion 73, respectively. In addition, each sub-pixel 71 has a conductive via 32 formed on its light-emitting portion 72 and non-light-emitting portion 73, which is electrically connected to the respective electrode 31 (except for the non-light-emitting portion 73R of the red sub-pixel 71R). Specifically, the sub-pixel 71B that emits blue light has an electrode 31p and a conductive via 32p formed in the light-emitting part 72, and an electrode 31n and a conductive via 32n formed in the non-light-emitting part 73. The sub-pixel 71G that emits green light has an electrode 31Gp and a conductive via 32Gp formed in the light-emitting part 72G, and an electrode 31Gn and a conductive via 32Gn formed in the non-light-emitting part 73G. The sub-pixel 71R that emits red light has an electrode 31Rp and a conductive via 32Rp formed in the light-emitting part 72R, and an electrode 31Rn and a conductive via 32Rn formed in the non-light-emitting part 73R.

[0018] Electrodes 31p and 31n are formed on substantially the entire upper surface of the light-emitting portion 72 and non-light-emitting portion 73 of the respective sub-pixels 71. The conductive via 32 is formed in the vicinity of the center of the electrode 31 in the shape of a slit extending in the X direction. As will be described later, the conductive via 32 is formed as a concave shape that is downward in the Z direction from the upper surface of the laminate 30.

[0019] Figures 5 and 6 are cross-sectional views of the pixels of the semiconductor light-emitting element in this embodiment. Figure 5 shows the cross-section of each sub-pixel in the X direction. From left to right, these are cross-sectional views AA, BB, and CC of the plan view shown in Figure 4. Figure 6 is a cross-sectional view DD in a direction intersecting Figure 5. As shown in Figures 5 and 6, the sub-pixel 71 of the semiconductor light-emitting element 1 comprises a sapphire substrate 10 which is the element substrate, a laminate 30, an electrode 31, a conductive via 32, and a dividing groove 801.

[0020] The sapphire substrate (device substrate) 10 is a plate-shaped sapphire with both sides polished to create a flat surface. The thickness of the sapphire substrate 10 is, for example, 300 μm.

[0021] The laminate 30 is laminated on the upper surface of the sapphire substrate 10. Each layer of the laminate 30 is laminated in a predetermined lamination direction. The vertical direction in Figures 5 and 6 is the lamination direction of the laminate 30. The lamination direction of the laminate 30 is perpendicular to the surface of the sapphire substrate 10. As shown in Figures 5 and 6, the laminate 30 has the following layers laminated on the upper surface of the sapphire substrate 10 in the order listed below. First buffer layer 301 First n-type layer 302 First light-emitting layer 303 (blue light-emitting layer) First p-type layer 304 First tunnel junction layer 305 Second n-type layer 306 Second light-emitting layer 307 (green light-emitting layer) Second p-type layer 308 Second tunnel junction layer 309 Third n-type layer 310 Second buffer layer 311 Third light-emitting layer 312 (red light-emitting layer) Third p-type layer 313 Third tunnel junction layer 314 Fourth n-type layer 315

[0022] The first buffer layer 301 is laminated on the upper surface of the sapphire substrate 10. The thickness of the first buffer layer 301 is, for example, 2000 nm. The first buffer layer 301 can be made of AlN or GaN grown at low temperatures. The first buffer layer 301 is located at the bottom layer of the laminate 30. The first buffer layer 301 mitigates the degree of lattice mismatch at least between the sapphire substrate 10 and the first n-type layer 302.

[0023] The first n-type layer 302 is laminated on the upper surface of the first buffer layer 301. The thickness of the first n-type layer 302 is, for example, 2000 nm. The first n-type layer 302 is formed of GaN (n-GaN) doped with n-type impurities such as Si.

[0024] The first light-emitting layer 303 is laminated on the upper surface of the first n-type layer 302. The first light-emitting layer 303 is formed, for example, as a multiple quantum well. The thickness of the first light-emitting layer 303 is, for example, 50 nm. The first light-emitting layer 303 is configured to produce light with an emission wavelength corresponding to blue (for example, 450-470 nm).

[0025] The first p-type layer 304 is laminated on the upper surface of the first light-emitting layer 303. The thickness of the first p-type layer 304 is, for example, 180 nm. The first p-type layer 304 is formed of GaN (p-GaN) to which p-type impurities such as Mg have been added.

[0026] The first tunnel junction layer 305 is laminated on the upper surface of the first p-type layer 304. The thickness of the first tunnel junction layer 305 is, for example, 25 nm. The first tunnel junction layer 305 is formed by laminating an n++ GaN layer with a high concentration of Si and a p++ GaN layer with a high concentration of Mg. Here, n++ means a state in which n-type impurities are added at a high concentration, and p++ means a state in which p-type impurities are added at a high concentration. The tunnel junction layer is a layer that enables current to flow from an n-type semiconductor to a p-type semiconductor.

[0027] The second n-type layer 306 is laminated on the upper surface of the first tunnel junction layer 305. The thickness of the second n-type layer 306 is, for example, 400 nm. The second n-type layer 306 is formed of GaN (n-GaN) doped with n-type impurities such as Si.

[0028] The second light-emitting layer 307 is laminated on the upper surface of the second n-type layer 306. The second light-emitting layer 307 is formed, for example, as a multiple quantum well. The thickness of the second light-emitting layer 307 is, for example, 50 nm. The second light-emitting layer 307 is configured to produce light with an emission wavelength corresponding to green (for example, 500-570 nm).

[0029] The second p-type layer 308 is laminated on the upper surface of the second light-emitting layer 307. The thickness of the second p-type layer 308 is, for example, 180 nm. The second p-type layer 308 is formed of GaN (p-GaN) to which p-type impurities such as Mg have been added.

[0030] The second tunnel junction layer 309 is laminated on the upper surface of the second p-type layer 308. The thickness of the second tunnel junction layer 309 is, for example, 25 nm. The second tunnel junction layer 309 is formed by laminating an n++GaN layer with a high concentration of Si and a p++GaN layer with a high concentration of Mg.

[0031] The third n-type layer 310 is laminated on the upper surface of the second tunnel junction layer 309. The thickness of the third n-type layer 310 is, for example, 400 nm. The third n-type layer 310 is formed of GaN doped with n-type impurities such as Si.

[0032] The second buffer layer 311 is laminated on the upper surface of the third n-type layer 310. The thickness of the second buffer layer 311 is, for example, 600 nm. The second buffer layer 311 mitigates the lattice mismatch between the third light-emitting layer 312 and the third n-type layer 310. The second buffer layer 311 is made of GaInN.

[0033] The third light-emitting layer 312 is laminated on the upper surface of the second buffer layer 311. The third light-emitting layer 312 is formed, for example, as a multiple quantum well. The thickness of the third light-emitting layer 312 is, for example, 50 nm. The third light-emitting layer 312 is configured to produce light with an emission wavelength corresponding to red (for example, 600-650 nm).

[0034] The third p-type layer 313 is laminated on the upper surface of the third light-emitting layer 312. The thickness of the third p-type layer 313 is, for example, 180 nm. The third p-type layer 313 is formed of GaN doped with p-type impurities such as Mg.

[0035] The third tunnel junction layer 314 is laminated on the upper surface of the third p-type layer 313. The thickness of the third tunnel junction layer 314 is, for example, 25 nm. The third tunnel junction layer 314 is formed by laminating an n++GaN layer with a high concentration of Si and a p++GaN layer with a high concentration of Mg.

[0036] The fourth n-type layer 315 is laminated on the upper surface of the third tunnel junction layer 314. The thickness of the fourth n-type layer 315 is, for example, 300 nm. The fourth n-type layer 315 is formed of GaN doped with n-type impurities such as Si.

[0037] Of the above layers, the first n-type layer 302, the first light-emitting layer 303 (blue light-emitting layer), and the first p-type layer 304 constitute the blue light-emitting unit layer 30B. The second n-type layer 306, the second light-emitting layer 307 (green light-emitting layer), and the second p-type layer 308 constitute the green light-emitting unit layer 30G. The third n-type layer 310, the second buffer layer 311, the third light-emitting layer 312 (red light-emitting layer), and the third p-type layer 313 constitute the red light-emitting unit layer 30R. Each color light-emitting unit layer 30 includes at least the light-emitting layer of its respective color and the n-type and p-type layers on either side of it, and is the basic unit of a light-emitting diode.

[0038] Tunnel junction layers 305 and 309 are provided between the p-type layers 304, 308, and 313 and the n-type layers 302, 306, and 310 of the adjacent light-emitting unit layers 30R, 30G, and 30B. A first tunnel junction layer 305 is provided between the blue light-emitting unit layer 30B and the green light-emitting unit layer 30G. A second tunnel junction layer 309 is provided between the green light-emitting unit layer 30G and the red light-emitting unit layer 30R. Furthermore, a third tunnel junction layer 314 and a fourth n-type layer 315 are provided on the upper surface of the red light-emitting unit layer 30R.

[0039] As shown in Figure 6, the partition groove 80 that demarcates the pixel 70 and the partition groove 802 that demarcates the sub-pixel 71 are grooves that extend from the top surface of the laminate 30 to the sapphire substrate 10. Therefore, the pixel 70 and the sub-pixel 71 are formed in an island-like manner on the sapphire substrate 10. In addition, the partition groove 80 is formed perpendicular to the sapphire substrate 10. In a thick laminate 30 in which multiple light-emitting unit layers 30R, 30G, and 30B are stacked, the partition grooves 80 are formed vertically, which narrows the width of the partition grooves 80 and allows for a wider effective area of ​​the pixels 70 and sub-pixels 71. This also makes it advantageous for forming fine pixels.

[0040] As shown in Figure 5, the electrodes 31 of each sub-pixel 71 of each light-emitting color are all formed on the uppermost fourth n-type layer 315 of the laminate 30. The surface of the laminate 30 on which the electrodes 31 are formed becomes the mounting surface that connects to the mounting substrate 90. On the other hand, the dividing grooves 801 and conductive vias 32 of the sub-pixels 71 of each emission color are formed to a predetermined depth to the layer necessary for circuit configuration to the emission-emitting unit layers 30R, 30G, and 30B corresponding to each emission color. In this specification, "depth" refers to the depth from the mounting surface of the laminate 30. Specifically, in the sub-pixel 71B that emits blue light, the dividing groove 801B is to the depth of the first n-type layer 302, the conductive via 32Bp of the light-emitting part 72B is to the depth of the second n-type layer 306, and the conductive via 32Bn of the non-light-emitting part 73B is to the depth of the first n-type layer 302. In the sub-pixel 71G that emits green light, the dividing groove 801G extends to the depth of the second n-type layer 306, the conductive via 32Gp of the light-emitting portion 72G extends to the depth of the third n-type layer 310, and the conductive via 32Gn of the non-light-emitting portion 73G extends to the depth of the second n-type layer 306. In the red-emitting sub-pixel 71R, the conductive via 32Rn of the dividing groove 801R and the non-emitting portion 73R is defined as having a depth to the third n-type layer 310.

[0041] As shown in Figure 4, the conductive via 32 is formed in a slit shape with a longitudinal side and a transverse side when viewed in the Z direction. Furthermore, as shown in Figures 5 and 6, the conductive via 32 has a shape that includes an inclined surface that tapers downward in the Z direction.

[0042] Figure 7 shows the current supply principle of the circuit configuration of the semiconductor light-emitting device of this embodiment. Here, we will explain using the sub-pixel 71G that emits green light as an example.

[0043] Current flows from the positive electrode 31Gp through the conductive via 32Gp to the third n-type layer 310. Here, the conductive via 32Gp has a lower electrical resistance than the laminate 30, and the third light-emitting layer 312 has a band gap. Therefore, there is no current flowing through the third light-emitting layer 312, and the third light-emitting layer 312 does not emit light.

[0044] The current diffuses in the third n-type layer 310 in a direction along the XY plane. The current that has diffused in the direction along the XY plane is injected from the second tunnel junction layer 309 into the second p-type layer 308, passes through the second light-emitting layer 307, and reaches the second n-type layer 306. Then, the entire surface of the second light-emitting layer 307 of the light-emitting section 72G emits light.

[0045] Current diffusion in the third n-type layer 310 along the XY plane is facilitated because the n-type layer has significantly lower resistivity and greater thickness than the p-type layer. Furthermore, the tunnel junction layer enables current flow from the n-type semiconductor to the p-type semiconductor. If the second tunnel junction layer 309 is omitted and the conductive via 32Gp directly reaches the second p-type layer 308, only a portion of the second light-emitting layer 307 will emit light. That is, because the second p-type layer 308 has high resistance, diffusion in the planar direction does not occur. Therefore, current flows only directly beneath the conductive via 32Gp in the second light-emitting layer 307. And light will only be emitted directly beneath the conductive via 32Gp.

[0046] Furthermore, the current that reaches the second n-type layer 306 flows to the second n-type layer 306 on the non-light-emitting portion 73 side, passes through the conductive via 32Gn, and reaches the negative electrode 31Gn.

[0047] Thus, the conductive via 32n on the side of the divided groove 801 and the non-emitting part 73 is set to a depth to the n-type layer of the light-emitting unit layers 30R, 30G, and 30B corresponding to the emitted color. Also, the conductive via 32p on the side of the light-emitting part 72 is set to a depth to the n-type layer via the tunnel junction layer above the light-emitting unit layers 30R, 30G, and 30B corresponding to the emitted color. This creates a circuit configuration to the light-emitting layers of the light-emitting unit layers 30R, 30G, and 30B corresponding to each emitted color. Note that for the light-emitting part 72B of the uppermost red-emitting sub-pixel 71R, an electrode 31Rp is formed on the n-type layer 315 via the tunnel junction layer 314 above the light-emitting unit layer 30R corresponding to the emitted color, so a conductive via 32 is not necessary.

[0048] As described above, the semiconductor light-emitting element 1 has independent circuits formed in each light-emitting unit layer 30R, 30G, and 30B corresponding to the light-emitting color, allowing for independent control of the light-emitting color and amount. Furthermore, multiple electrodes 31 of the semiconductor light-emitting element 1, which serve as electrical terminals for the circuits to the light-emitting unit layers 30R, 30G, and 30B corresponding to each light-emitting color, are formed on the same surface of the laminate 30. This same surface on which the electrodes 31 are formed becomes the mounting surface, allowing for easy and stable electrical connection with the mounting substrate 90.

[0049] The material of the conductive via 32 is not particularly limited as long as it is a conductive material with sufficient conductivity to form the current-carrying circuit described above, but examples include gold, aluminum, and copper. In this embodiment, the opening of the conductive via 32 is slit-shaped. The width dimension of this opening in the Y direction is approximately 2.5 μm. Its shape in the Z direction is a cone shape that includes a sloping surface that tapers from the electrode 31 toward the n-type layer. The taper angle of the inclined surface of this groove is preferably such that the electrode-side opening of the conductive via 32 is not excessively large for small-sized LEDs, and that the conductive material can be stably installed on the side surface of the inclined groove, as will be described later. For this reason, for example, the taper angle of the inclined surface of this groove is preferably 10° to 45°, and more preferably 20° to 40°. The side surface of the conductive via 32 is a surface that is inclined at an angle with respect to the stacking direction of the laminate 30, relative to the side surface of the partition groove 80.

[0050] The opening of the conductive via 32 is not limited to a slit shape; it may also be circular (or conical) or other shapes. However, a slit shape makes it easier to form a narrower shape. A resist mask with smaller dimensions can be formed if the width of the shorter side of the slit shape is greater than the diameter of the circular shape. Also, for a rectangular light-emitting portion 72, a slit shape that is long in the direction of the longer side is advantageous for current diffusion to the light-emitting layer. Note that the conductive via 32 may be formed on the outer circumference of the electrode rather than inside the electrode.

[0051] Figure 8 is an enlarged cross-sectional view of the bottom 801x of the segmented groove 801. The segmented groove 801 shown in Figure 8 includes segmented groove 801B formed in the blue-emitting sub-pixel 71B, segmented groove 801G formed in the green-emitting sub-pixel 71G, and segmented groove 801R formed in the red-emitting sub-pixel 71R. In the red-emitting unit layer 30R, a second buffer layer 311 exists between the third light-emitting layer 312 and the third n-type layer 310, but it is omitted from the illustration in Figure 8 for the sake of explanation.

[0052] As shown in Figure 8, the dividing groove 801 is formed to a depth that reaches the n-type layers 302, 306, and 310 of the light-emitting unit layers 30R, 30G, and 30B, and the bottom portion 801x of the dividing groove 801 is formed in the n-type layers 302, 306, and 310. The bottom portion 801x of the dividing groove 801 has a central portion 801y having a predetermined area.

[0053] A recess 801z is formed in part of the bottom 801x of the divided groove 801. In other words, the bottom 801x is not of uniform depth throughout, and a recess 801z, which is deeper than the central part 801y, is formed along the periphery of the side surface of the divided groove 801. The recess 801z can also be called a cut or notch. The recess 801z is formed in part of the bottom 801x when plasma accumulates along the periphery of the side surface of the divided groove 801 during etching to form the divided groove 801.

[0054] The recess 801z has a significant depth, for example, 50 nm or more, relative to the flat portion of the bottom 801x. The dividing groove 801 can divide the light-emitting layers 303, 307, and 312 of the light-emitting unit layers 30R, 30G, and 30B by the recess 801z of the bottom 801x. In the shallow flat portion of the bottom 801x other than the recess 801z, a larger thickness of the n-type layers 302, 306, and 310 can be retained, and the resistance values ​​of the n-type layers 302, 306, and 310 between the light-emitting portion 72 and the non-light-emitting portion 73 can be kept low. The maximum depth of the dividing groove 801, including the recess 801z, is defined as the range in which the n-type layers 302, 306, and 310 are not divided.

[0055] (First embodiment of a method for manufacturing semiconductor light-emitting elements) Next, the method for manufacturing a semiconductor light-emitting element in this embodiment will be described.

[0056] Figure 9 is a flowchart showing the method for manufacturing a semiconductor light-emitting element in this embodiment. Figure 10 is an explanatory diagram of step S00 showing the method for manufacturing a semiconductor light-emitting element in this embodiment. Figure 11 is an explanatory diagram of step S01 showing the method for manufacturing a semiconductor light-emitting element in this embodiment. Figures 12 to 15 are explanatory diagrams of step S02 showing the method for manufacturing a semiconductor light-emitting element in this embodiment.

[0057] As shown in Figure 9, the method for manufacturing a semiconductor light-emitting element in this embodiment includes an epitaxial stacking step S00, a pixel partition groove formation step S01, a pixel shape processing step S02, a p-active annealing step S03, an insulating film formation step S04, and an electrode formation step S05.

[0058] The manufacturing method for the semiconductor light-emitting element 1 first involves an epitaxial stacking process S00 in which each layer of the stack 30 is formed on the sapphire substrate 10 by epitaxial deposition. In the epitaxial stacking process S00, as shown in Figure 10, each layer constituting the stack 30 shown in Figure 5 is crystallized and stacked on the upper surface of the sapphire substrate 10 using the MOVPE method (metal-organic vapor deposition). This forms the layer structure corresponding to the stack 30. In Figure 10, the sapphire substrate 10 and the stack 30 are schematically shown.

[0059] Next, in the pixel partition groove formation step S01, partition grooves 80 and 802 are formed in the laminate 30 as shown in Figure 11. This partition groove formation step consists of a laminate mask formation step for forming vertical grooves, a groove formation etching step, and a laminate mask removal step.

[0060] The lamination mask formation process involves forming an SiO2 film as a base layer on the entire upper surface of the laminate 30. A Ni film is then laminated as an upper layer in the areas of the base layer other than those where partition grooves 80 and 802 are formed. The base layer can be formed, for example, using a sputtering apparatus. The upper layer can be formed, for example, using a vapor deposition apparatus.

[0061] The multilayer mask, composed of a lower layer and an upper layer, is designed so that in the etching process of the lower layer described later, the etching selectivity ratio of the lower layer material to the upper layer material is 40 or higher. In the case of a combination of SiO2 and Ni, the etching selectivity ratio of SiO2 to Ni is approximately 50. As the lower layer, oxides such as Al2O3 and nitrides such as Si3N4 can be used in addition to SiO2. As the upper layer 52, Pt, Cr, etc., can be used in addition to Ni. Furthermore, the etching selectivity ratio of GaN used in the laminate 30 to SiO2 used in the multilayer mask is approximately 10, and the etching selectivity ratio of the laminate 30 to the multilayer mask is high.

[0062] To form an upper layer film in a predetermined area, a resist mask formed by commonly used lithography can be used. Specifically, a resist material is applied to the upper surface of the lower layer film to form a resist film, and then a resist mask is formed for the areas where the partition grooves 80 and 802 are to be formed. Then, the upper layer film is deposited and laminated onto the exposed upper surface of the lower layer film and the upper surface of the resist mask. By removing the resist mask, the upper layer film can be laminated in areas other than those where the partition grooves 80 and 802 are to be formed.

[0063] Furthermore, the underlying film in the areas forming compartment grooves 80 and 802, which are not covered by the upper film, is removed by dry etching using CF4, a fluoride gas. In this process, since the etching rate of the underlying film is greater than that of the upper film, the sides of the laminated mask are formed with a very small taper and are vertically cut. In this way, the laminated mask is formed. Alternatively, instead of CF4, etching may be performed using SF6 or CHF3, which are fluoride gases, to remove the underlying film in the areas forming compartment grooves 80 and 802.

[0064] The groove-forming etching process removes the laminated body 30 in areas exposed and not covered by the laminated mask by dry etching using Cl2. Etching is performed to a depth that reaches the upper surface of the sapphire substrate 10, and is stopped when the upper surface of the sapphire substrate 10 is reached. As a result, island-like pixels 70 and sub-pixels 71 are formed on the sapphire substrate 10 by partition grooves 80 and 802 that reach the upper surface of the sapphire substrate 10 around the outer periphery of the pixels 70. In this process, etching using a laminated mask with vertical sides allows the partition grooves 80 and 802 to be made deep and vertically cut. Furthermore, the fact that the etching rate of the laminated body 30 is greater than that of the laminated mask also allows the partition grooves 80 and 802 formed on the laminated body 30 to be vertical.

[0065] Then, the laminated mask is removed by hydrofluoric acid treatment. In this way, the process of forming the partition grooves 80 and 802 is completed. In this way, the partition grooves 80 and 802 are formed, and multiple island-shaped pixels 70 and sub-pixels 71 are formed. In the inventors' experiments, the angle between the walls of the partition grooves 80 and 802 and the upper surface of the sapphire substrate 10 is 89 degrees or more, confirming the formation of partition grooves 80 and 802 that are almost vertically cut.

[0066] As shown in Figure 11(b), by forming partition grooves 80 and 802, sub-pixels 71B, 71G, and 71R in pixel 70 are formed, and the pixel partition groove formation step S01 is completed.

[0067] Next, in the pixel shape processing step S02, the grooves of the dividing groove 801 and conductive via 32 are formed by etching multiple times. In the first example of the pixel shape processing step, the grooves of the dividing groove 801 and conductive via 32 are formed sequentially in a multi-stage process, starting from the shallower parts and adding the difference in depth to the deeper parts. Dry etching using a mask is used for groove formation.

[0068] Figure 12 is an explanatory diagram of the first pixel shape processing process. This diagram shows the AA, BB, and CC cross-sections of Figure 4 shown in Figure 5. For sub-pixels 71B, 71G, and 71R shown in Figure 12(a), first, as a first-depth etching process, a groove of the shallowest first depth is formed as shown in Figure 12(b), and grooves of the deeper second and third depths are also formed to the same depth as the first depth. Specifically, using a mask with a pattern for forming grooves corresponding to the first, second, and third depths, grooves are formed for the segmented groove 801R, conductive via 32Rn, and conductive via 32Gp, as well as grooves up to the first depth for the segmented groove 801G, conductive via 32Gn, conductive via 32Bp, segmented groove 801B, and conductive via 32Bn.

[0069] Next, as a second-depth etching process, an additional depth equal to the difference between the first and second depths is formed, as shown in Figure 12(c). In other words, using a mask with a pattern for forming an additional depth equal to the difference between the first and second depths, the grooves of the divided groove 801G, conductive via 32Gn, and conductive via 32Bp are all formed with an additional depth equal to the difference between the first and second depths of the divided groove 801B and conductive via 32Bn.

[0070] Next, as a third-depth etching process, an additional depth equal to the difference between the second and third depths is formed, as shown in Figure 12(d). Specifically, a mask with a pattern for forming an additional groove with a depth equal to the difference between the second and third depths is used to form the divided groove 801B and the conductive via 32Bn with a depth equal to the difference between the second and third depths.

[0071] In this way, by adding the difference in depth, groove formation can be achieved in a time-efficient manner. In other words, the etching time required to form all the grooves in pixel 70 is the same as the etching time required to form the grooves of the third depth. Note that the order of the multi-stage process is not limited to forming the shallower areas first and then adding the difference in depth to the deeper areas. The difference in depth may be formed first, and then the shallower areas may be formed afterward.

[0072] The mask used in the etching process may be made of resin resist material, or it may be made of a metal material such as Ni (nickel). For example, by using a 100 nm thick Ni (nickel) mask made by sputter deposition, the mask is less likely to be damaged even when forming relatively deep grooves. In addition, if the groove shape is measured after groove formation and the depth is insufficient, additional grooves may be formed. When measuring the groove shape, the processed shape is measured with the mask still attached. In this case, since the thickness of the mask is stable, the accuracy of reading the groove depth can be increased. Note that a mask made of a metal material can be used by reversing the mask made of resin resist material.

[0073] In the etching process, the laminate 30 in areas exposed and not covered by the mask layer is removed by dry etching using Cl2 (chlorine gas). At this time, the sides of the divided grooves 801 and conductive vias 32 that are formed become inclined surfaces with a taper angle of about 10° to 30°.

[0074] Next, as the p-activated annealing step S03, a Rapid Thermal Annealing (RTA) treatment is performed. The treatment atmosphere for this step is N2, the annealing temperature is 725°C, and the annealing time is 30 minutes.

[0075] Next, in insulating film formation step S04, an insulating film (passivation film) made of SiO2 is formed on the entire surface of the laminate 30, which has undergone pixel compartment groove formation and pixel shape processing, excluding the openings for forming the electrodes 31 and conductive vias 32. The insulating film is deposited to a thickness of approximately 250 nm by plasma CDV or sputtering.

[0076] Next, in electrode formation step S05, electrodes 31 are formed on the upper surfaces of the light-emitting portion 72 and non-light-emitting portion 73 of the sub-pixel 71. The electrodes 31 are formed by laminating thin metal films by sputtering or vapor deposition. For example, a Cr / Ni / Au lamination can be used, with respective film thicknesses of 10 nm / 20 nm / 170 nm. The positive electrode 31p and the negative electrode 31n are formed simultaneously on the fourth n-type layer 315 using the same material and thickness.

[0077] During the formation of the electrode 31, conductive vias 32 are formed simultaneously. The conductive vias 32 are formed by laminating a thin metal film of the electrode 31 into the groove of the conductive via 32 formed in the pixel shape processing step S02. Since the groove of the conductive via 32 is a tapered inclined surface that opens upward, a stable electrical connection can be easily established from the electrode 31 to the bottom surface of the conductive via 32. Note that the conductive via 32 does not have to be formed at the same time as the electrode 31. It may be formed separately by plating or other means. In that case, the groove of the conductive via 32 may be completely filled with conductive material.

[0078] In the semiconductor light-emitting element manufacturing method of this embodiment, pixels 70, each consisting of numerous sub-pixels 71, can be manufactured all at once on a sapphire substrate 10, which is an element substrate, in an arrangement with spacing suitable for a display device. Furthermore, in this embodiment, the semiconductor light-emitting element can have a wider effective area for the pixels 70 and sub-pixels 71 by narrowing the width of the partition groove 80. On the other hand, by making the groove for forming the conductive via 32 a surface that is inclined at an angle with respect to the stacking direction of the laminate 30 from the side surface of the partition groove, the conductive via 32 can be formed easily and stably. Note that the film thicknesses and processing conditions mentioned above are not limited to the values ​​listed above.

[0079] (Modification 1 of semiconductor light-emitting element) Next, a modification 1 of the method for manufacturing the semiconductor light-emitting element in this embodiment will be described. In this example, the main difference from the semiconductor light-emitting element described above is the pixel shape processing step S02. In the pixel shape processing step S02 of the first embodiment, the division grooves 801 and the grooves of the conductive vias 32 were formed sequentially, starting from the shallower parts and adding the difference to the deeper parts. In contrast, in the pixel shape processing step S02 of modification 1, the division grooves 801 and the grooves of the conductive vias 32 are formed consistently for each groove of the same depth. As a result, for example, the groove of the deepest conductive via 32Bn becomes a continuous, smooth shape. Other components corresponding to the manufacturing method described above are denoted by the same reference numerals and their descriptions are omitted.

[0080] Figure 13 is an explanatory diagram of the pixel shape processing process for Modification 1. First, as a first depth etching process, a mask with a pattern for forming grooves of the first depth is used to form the first depth divided groove 801R and conductive via 32Rn and conductive via 32Gp grooves, as shown in Figure 13(b).

[0081] Next, as a second-depth etching step, a mask with a pattern for forming grooves of the second depth is used to form the second-depth divided groove 801G and the grooves for conductive vias 32Gn and 32Bp, as shown in Figure 13(c).

[0082] Next, as a third-depth etching step, a mask with a pattern for forming grooves of the third depth is used to form the third-depth divided groove 801B and conductive via 32Bn grooves, as shown in Figure 13(d).

[0083] In the pixel shape processing step S02 of Modified Example 1, the etching time is approximately twice as long as that of the pixel shape processing step S02 shown in Figure 12. That is, the etching time required to form all the grooves of the pixel 70 is the etching time required to form the grooves of the third depth, plus the etching time required to form the grooves of the second depth and the grooves of the first depth, respectively. However, when forming fine shapes by sequential formation that adds differences as shown in Figure 12, the positional displacement of the mask relative to the groove width may become significant. In other words, there is a concern that the masks for forming grooves of each depth will be formed with significant positional displacement. This raises concerns that the grooves may become irregularly shaped, or that grooves of the required depth may not be formed.

[0084] For example, in the case of sequential groove formation to a third depth, a stepped shape may occur on the side surface of the groove at the height of the first or second depth. Alternatively, the groove depth may not reach the third depth. In contrast, in the pixel shape processing step S02 of Modified Example 1, grooves can be formed without steps in the parts of the side surface corresponding to the depths of the first and second depths. In other words, in Modified Example 1, in multiple grooves of different depths, grooves that are deeper than others can have a continuous shape without steps on the side surface of the parts corresponding to the other depths. Specifically, a groove with a second depth can have a continuous shape without steps in the depth direction on the side surface of the part corresponding to the first depth, and a groove with a third depth can have a continuous shape without steps in the depth direction on the side surface of the parts corresponding to the first and second depths.

[0085] In the pixel shape processing step S02 of Modified Example 1, even when forming a fine groove shape, grooves without steps can be formed up to a predetermined depth. Then, in the electrode formation step S05, conductive vias 32 can be easily formed that stably electrically connect the electrode 31 to a predetermined n-GaN layer. The predetermined n-GaN layer is the n-type layer of the light-emitting unit layers 30R, 30G, and 30B corresponding to the light-emitting color, and the n-type layer via the tunnel junction layer above the light-emitting unit layers 30R, 30G, and 30B corresponding to the light-emitting color.

[0086] (Modified example 2 of semiconductor light-emitting element) Next, a modified example 2 of the semiconductor light-emitting element in this embodiment will be described. In this example, the main difference from the semiconductor light-emitting element described above is the pixel shape processing step S02. In the pixel shape processing step S02 of the first embodiment and its modified example 1, the process was completed when the grooves of the dividing groove 801 and the conductive via 32 were simultaneously formed to reach a predetermined n-type layer. In contrast, in the pixel shape processing step S02 of modified example 2, additional etching is performed only on the groove of the conductive via 32. As a result, in the same sub-pixel 71, the groove of the conductive via 32n of the non-emitting portion 73 is formed deeper than the groove of the dividing groove 801. Other components corresponding to the manufacturing method described above are denoted by the same reference numerals and their descriptions are omitted.

[0087] Figure 14 is an explanatory diagram of the pixel shape processing step S02 of Modified Example 2. Figure 14(a) shows the state after the pixel shape processing step S02 of Modified Example 1 has been performed, before additional etching. Figure 14(b) shows the state after additional etching has been performed only on the grooves of the conductive via 32.

[0088] In the pixel shape processing step S02 of the modified example 2, as shown in Figure 14(a), the simultaneous formation of grooves reaching a predetermined n-type layer is limited to the upper part of the predetermined n-type layer. Then, as shown in Figure 14(b), only the grooves of the conductive vias 32 are slightly etched to the height of the center of the predetermined n-type layer. As a result, the dividing groove 801 of the sub-pixel 71 is shallower than the conductive via 32p of the light-emitting part 72 of another sub-pixel 71, with a depth to the same n-type layer as the dividing groove 801. In other words, in the division groove 801G of the green-emitting sub-pixel 71G and the conductive via 32Bp of the light-emitting portion 72B of the blue-emitting sub-pixel 71B, which are grooves extending into the second n-type layer 306, the division groove 801G is shallower than the conductive via 32Bp. Furthermore, in the grooves extending into the third n-type layer 310, specifically the dividing groove 801R of the red-emitting sub-pixel 71R and the conductive via 32Gp of the light-emitting portion 72G of the green-emitting sub-pixel 71G, the dividing groove 801R is shallower than the conductive via 32Gp.

[0089] In the pixel shape processing step S02 of the modified example 2, the dividing groove 801 is made into a shallow groove that remains in the upper part of the n-type layer, thereby leaving the n-type layer thicker. This suppresses the increase in resistance of the n-type layer that conducts current from the light-emitting part 72 to the non-light-emitting part 73. In addition, the groove of the conductive via 32 up to the same n-type layer is made deeper than the dividing groove 801 so that the conductive via 32 can stably reach the n-type layer. In this process, grooves of similar depth are simultaneously formed in other subpixels. As a result, grooves are formed that are shallower than the conductive vias of the light-emitting portion of subpixels other than the subpixels, but to the same depth as the n-type layer as the dividing grooves.

[0090] (Modification of semiconductor light-emitting element 3) Next, a third modification of the semiconductor light-emitting element in this embodiment will be described. In this example, the differences from the semiconductor light-emitting element and the first modification described above are that the conductive vias on the non-emitting side of the sub-pixels for green and red light emission are made deeper, and are deeper than the dividing grooves within the sub-pixels, and the pixel shape processing step S02 in the manufacturing method.

[0091] Figure 15 is an explanatory diagram of the pixel shape processing process for the modified example 3. As shown in Figure 15(d), the conductive via 32Rn of the non-emitting portion 73R of the red-emitting sub-pixel 71R is at the second depth. The conductive via 32Gn of the non-emitting portion 73G of the green-emitting sub-pixel 71G is at the third depth.

[0092] First, as part of the first depth etching process, a first depth divided groove 801R and a conductive via 32Gp groove are formed, as shown in Figure 15(b).

[0093] Next, as a second-depth etching process, as shown in Figure 15(c), a second-depth divided groove 801G and grooves for conductive vias 32Rn and 32Bp are formed.

[0094] Next, as a third-depth etching process, as shown in Figure 15(d), a third-depth divided groove 801B and grooves for conductive vias 32Gn and 32Bn are formed.

[0095] The conductive via 32n of the non-emitting portion 73 only needs to reach the n-type layer of the predetermined light-emitting unit; there is no problem if it is deeper. For this reason, the conductive via 32n may extend to the n-type layer of the light-emitting unit below the predetermined light-emitting unit. The thickness of the first n-type layer 302 is, for example, 2000 nm. For this reason, the groove of the conductive via 32Bn should be formed deep from the boundary between the first n-type layer 302 and the first light-emitting layer 303.

[0096] (Modification of semiconductor light-emitting element 4) Next, a fourth modified example of the semiconductor light-emitting element in this embodiment will be described. Figure 16 is an explanatory diagram of the process for manufacturing the fourth modified example. In the fourth modified example, the difference from the first embodiment and each of the modified examples described above is that, as shown in Figure 16(a), the grooves of the conductive vias 32n (32Rn, 32Gn, 32Bn) of the non-light-emitting portion 73 are formed in the pixel compartment groove formation step S01. In the pixel compartment groove formation step S01, etching is performed using a laminated mask having vertical sides. The grooves of the conductive vias 32n are formed consistently perpendicular to the mounting surface of the laminate 30, similar to the compartment grooves 80, and reach a depth that extends to the sapphire substrate 10.

[0097] In Modification 4, the formation of vertical grooves allows for the creation of grooves with less influence from groove taper, such as a taper angle of less than 10 degrees. This enables the formation of grooves for deep conductive vias 32n up to the third depth with smaller diameter grooves. Furthermore, since the formation of grooves for the non-emitting portion 73 of the sub-pixel 71 and the conductive vias 32n is performed using the same mask pattern, the position of the conductive vias 32n in the non-emitting portion 73 can be stabilized in the semiconductor light-emitting element 1. These features are advantageous for forming small conductive via grooves that fit within a limited size non-emitting portion 73, such as a width of 10 μm or less, in high-resolution micro-LEDs.

[0098] As shown in Figure 16, in Modification 4, the groove of the conductive via 32n on the non-emitting side of the sub-pixel 71 is formed to a depth that reaches the sapphire substrate 10. In the independent circuits of each light-emitting unit layer 30R, 30G, and 30B, the path connecting the light-emitting side and the non-light-emitting side of the sub-pixel 71 is the n-type layers 302, 306, and 311 on the sapphire substrate 10 side of the light-emitting layers 303, 307, and 312 of a predetermined light-emitting color. Even if the groove of the conductive via 32n is formed to a depth that reaches the sapphire substrate 10, the resulting change in the path is negligible. Furthermore, the fact that the groove of the conductive via 32n on the non-light-emitting side of the sub-pixel 71 is formed to a depth that reaches the sapphire substrate 10 does not lead to the emission of light from other light-emitting colors in the other light-emitting unit layers 30R, 30G, and 30B. Furthermore, in the modified example 4, the grooves of the conductive via 32n are formed simultaneously with the partition grooves 80 and 802 in the pixel partition groove formation step S01, thus eliminating the need for separate effort to form the grooves of the conductive via 32n.

[0099] In the electrode formation process S05, in order to facilitate the formation of the electrode 31 by laminating a metal thin film in the groove of the vertical conductive via 32n, it is desirable that the sapphire substrate 10 be positioned at a slight inclination from a perpendicular position with respect to the supply direction of the metal that serves as the deposition source. That is, the electrode material from the deposition source should be positioned at an angle greater than 0° to the opening. -1By setting the incident position to an angle range of (2·r / d3) or less, a thin metal film can be deposited in the groove of the vertical conductive via 32n. Furthermore, by using a vapor deposition machine equipped with a substrate rotation mechanism on which the substrate on which the semiconductor light-emitting device is installed rotates, the above conditions can be more easily met. Alternatively, by using sputtering instead of vapor deposition, it is possible to easily deposit a thin metal film in the groove of the vertical conductive via 32n. As a result, as in Modification 4, even if the groove of the conductive via 32n has a surface perpendicular to the sapphire substrate 10, a stable electrical connection can be made, like a tapered inclined surface that widens upwards. In addition, the grooves of the conductive vias 32n may be formed perpendicular to the mounting surface of the laminate 30 in a separate process from the pixel compartment groove formation process S01. In this case as well, the grooves of the conductive vias 32n may be formed using the same laminate mask as used in the pixel compartment groove formation process S01. When perpendicular grooves of the conductive vias 32n are formed in a separate process from the pixel compartment groove formation process S01, the depth of the grooves of the conductive vias 32n may be shallower than the depth to which the sapphire substrate 10 is reached.

[0100] (5 variations of semiconductor light-emitting element) Next, a modified example 5 of the semiconductor light-emitting element in this embodiment will be described. Figure 17 is an explanatory diagram of the process for manufacturing the modified example 5. In modified example 5, the difference from the manufacturing methods of the first embodiment and each of the modified examples described above is that the side surfaces of the dividing grooves 801 of the sub-pixels 71 and the grooves of the conductive vias 32p are formed perpendicular to the mounting surface of the laminate 30 in the pixel shape processing step S02.

[0101] In Modification 5, as shown in Figure 17(a), the grooves for the conductive vias 32n (32Rn, 32Gn, 32Bn) of the non-emitting portion 73 are formed in the pixel partition groove formation step S01, similar to Modification 4 described above. In Modification 5, the laminate 30 on which the conductive vias 32n are formed has a first depth division groove 801R and a conductive via 32Gp groove formed, as shown in Figure 17(b), a second depth division groove 801G and a conductive via 32Bp groove formed, as shown in Figure 17(c), and a third depth division groove 801B formed, as shown in Figure 17(d). As a result, the division groove 801 and the conductive via 32p grooves are consistently formed for each groove of the same depth.

[0102] In the pixel shape processing step S02 of Modified Example 5, the division grooves 801 and conductive vias 32p are formed using a laminated mask similar to that used in the pixel compartment groove formation step S01. This laminated mask is composed of a lower layer and an upper layer, and the combination is such that the etching selectivity ratio of the lower layer material to the upper layer material is 40 or more. In the pixel shape processing step S02 of Modified Example 5, the division grooves 801 and conductive vias 32p are formed at various depths by repeating the laminated mask formation step, groove formation etching step, and laminated mask removal step similar to those used in the pixel compartment groove formation step S01. As a result, the division grooves 801 and conductive vias 32 are formed as grooves perpendicular to the sapphire substrate 10, similar to the compartment grooves 80.

[0103] In Modification 5, since all the divided grooves 801 and conductive vias 32 have vertical surfaces with no inclination angle on their sides, deep grooves can be easily formed even if they are fine grooves with small inner diameters. That is, where r: radius of the opening, d3: depth of the third depth, and θ: inclination angle of the groove, tan -1For small diameters where (r / d3)≦θ, it is not possible to form a groove with a third depth, or the bottom shape becomes unstable. For example, in the configuration of the laminate 30 of this embodiment, if the radius of the opening is 1 μm, it is difficult to stably form a groove with a third depth of about 3 μm on an inclined surface with a taper angle of about 20°. In contrast, by setting θ≦10°, preferably θ≦5°, a third depth of 3 μm can be formed. In modified example 5, θ≦2° can be achieved. That is, θ≦(tan -1 (r / d3) / 2, preferably θ≦(tan -1 By setting (r / d3) / 4, it is possible to form deep grooves even with minute grooves that have a small inner diameter.

[0104] For forming grooves with small inner diameters that reach second or third depths, it is preferable to combine this with a method of consistently forming grooves of the same depth, which is unaffected by mask misalignment in the pixel shape processing step S02. In modified example 5, the differences in groove depths may also be formed sequentially by additional etching. However, in this case, there is a risk of being affected by mask misalignment.

[0105] [Semiconductor light-emitting device of the first embodiment] Figures 18 and 19 are cross-sectional views showing the semiconductor light-emitting device 100 in this embodiment. Figures 18 and 19 correspond to the cross-sections of the partially enlarged front view of the mounting substrate 90 in Figure 2. Furthermore, the semiconductor light-emitting element 1 in Figure 18 corresponds to the AA, BB, and CC cross-sectional views in Figure 5, and the semiconductor light-emitting element 1 in Figure 19 corresponds to the DD cross-sectional view in Figure 6.

[0106] In the semiconductor light-emitting device 100, as shown in Figures 18 and 19, the semiconductor light-emitting element 1 is mounted on the mounting substrate 90 with its electrodes 31 facing the substrate 90. The mounting substrate 90 has anode-side wiring 91 and cathode-side wiring 93 formed on the mounting substrate base 90A, with the same height on the mounting surface side, and metal bumps 94 of the same thickness formed on them. The mounting substrate 90 is a CMOS (Complementary Metal Oxide Semiconductor) substrate with silicon as the base material. The mounting substrate 90 has functions such as switch control and current control.

[0107] The anode-side wiring 91 and cathode-side wiring 93 of the mounting substrate 90 intersect while being electrically insulated from each other by an insulating layer 92. A protrusion 91a is formed on the anode-side wiring 91, and the height of the formation surfaces of the anode-side and cathode-side metal bumps 94 are aligned. High electrical conductivity materials such as Cu (copper) and Au (gold) are used for the wiring 91, protrusion 91a, and wiring 93. For example, Au (gold) is used for the metal bumps 94.

[0108] The semiconductor light-emitting element 1 is mounted on the mounting substrate 90 by, for example, thermocompression bonding at 300°C. In this process, the electrodes 31 of the semiconductor light-emitting element 1 are all at the same height, the wiring 91 and wiring 93 of the mounting substrate 90 are all at the same height, and the thickness of the metal bumps 94 is the same. Therefore, it is easy to apply uniform force to each metal bump 94, and a large number of metal bumps 94 can be uniformly compressed to achieve a stable electrical connection.

[0109] As the metal bumps 94, a bonding material such as a eutectic material that melts and joins, such as AuSn (gold-tin alloy), may be used. In this case, it is necessary not only to electrically connect the electrodes 31 of the predetermined semiconductor light-emitting element 1 to the wiring 91 or wiring 93 of the mounting substrate 90, but also to control the overflow of the bonding material and prevent unintended electrical connections. The semiconductor light-emitting element 1 and semiconductor light-emitting device 100 of the present invention make it easy to apply a controlled, uniform force to each metal bump 94, and are suitable for such bonding.

[0110] Furthermore, when using a bonding material that melts and joins, the self-alignment effect due to the surface tension of the bonding material during melting can be utilized by approximating the shape of the electrode 31 of the semiconductor light-emitting element 1 and the wiring 91 or wiring 93 of the corresponding mounting substrate 90. In addition, it is easier to ensure that the entire electrode surface is in contact with the bonding material, and the physical bond can be made stronger.

[0111] In this embodiment, the semiconductor light-emitting device is mounted on a mounting substrate where multiple electrodes are formed on a mounting surface of the same height. Therefore, without using a mounting substrate with a complex configuration that is time-consuming to manufacture, a semiconductor light-emitting device can be stably mounted on a mounting substrate with a stable mounting surface.

[0112] (Modified example 1 of a semiconductor light-emitting device) Figure 20 is a schematic partial cross-sectional view of a modified example 1 of the semiconductor light-emitting apparatus of this embodiment. The semiconductor light-emitting device 100A of Modified Example 1 is the same as the semiconductor light-emitting device 100 shown in Figure 18, but without the sapphire substrate 10. In other words, the semiconductor light-emitting device 100A of Modified Example 1 is manufactured by performing a lift-off process in which the sapphire substrate 10 is lifted off from the semiconductor light-emitting element 1 after the semiconductor light-emitting element 1 has been mounted on the mounting substrate 90. As a result, in the semiconductor light-emitting device 100A, the sub-pixels 71 of each color are arranged on the mounting substrate 90 in a completely separated and independent state.

[0113] When removing the sapphire substrate 10 of the semiconductor light-emitting element 1, the semiconductor light-emitting element 1 is mounted on a mounting substrate 90, and then the sapphire substrate 10 is peeled off, for example, by laser irradiation. Each sub-pixel 71 of each color is several micrometers thick, and sufficient support for the semiconductor light-emitting element 1 is necessary to minimize damage to each sub-pixel 71 of each color when removing the sapphire substrate 10. The semiconductor light-emitting element 1 of the present invention is suitable for this purpose.

[0114] In particular, by using a bonding material that melts and joins the electrodes, and then removing the sapphire substrate 10 after the entire electrode surface is in contact with the bonding material, damage to the sub-pixels 71 can be suppressed.

[0115] Furthermore, the semiconductor light-emitting device 100A can suppress light interference with other pixels 70 via the sapphire substrate 10. This suppresses false illumination.

[0116] (Modified example 2 of semiconductor light-emitting device) Figure 21 is a schematic partial cross-sectional view of a modified example 2 of the semiconductor light-emitting apparatus of this embodiment. The semiconductor light-emitting device 100B of the modified example 2 is equipped with light-absorbing members 40 between each sub-pixel 71 of the semiconductor light-emitting device 100 shown in Figure 18, and furthermore, the sapphire substrate 10 is removed.

[0117] In the modified example 2, the semiconductor light-emitting device 100B is supported not only by the mounting substrate 90 but also by the light-absorbing member 40, and the sapphire substrate 10 is peeled off in this state. This helps to suppress damage to the sub-pixels 71.

[0118] The light-absorbing member 40 can be any material that absorbs light emitted by the semiconductor light-emitting element 1, such as a metal complex dye, black silicon resin, black epoxy resin, or black paint. This suppresses light interference with other pixels 70 and reduces false illumination.

[0119] (Modified semiconductor light-emitting element 6, modified semiconductor light-emitting device 3) Figure 22 is a cross-sectional view in the Y direction of each pixel of modified example 6 of the semiconductor light-emitting device of this embodiment, and Figure 23 is a schematic partial cross-sectional view of modified example 3 of the semiconductor light-emitting device of this embodiment. In the semiconductor light-emitting element 1 of Modification 6, the partition groove 802 of the sub-pixel 71 of the semiconductor light-emitting element 1 shown in Figure 6 extends to the sapphire substrate 10, whereas the partition groove 802 of the sub-pixel 71 does not extend to the sapphire substrate 10. In the semiconductor light-emitting device 100C of Modification 3, the semiconductor light-emitting element 1 of Modification 6 is mounted on the mounting substrate 90, and the sapphire substrate 10 is removed.

[0120] In the semiconductor light-emitting element 1 of Modification 4, the pixels 70 are independent except when the sapphire substrate 10 is removed. However, the sub-pixels 71, namely the red-emitting sub-pixel 71R, the green-emitting sub-pixel 71G, and the blue-emitting sub-pixel 71B, maintain an integrated structure with the first buffer layer 301 and other components connected continuously. For this reason, the semiconductor light-emitting element 1 of Modification 4 is less susceptible to damage when the sapphire substrate 10 is removed.

[0121] Furthermore, when the sapphire substrate 10 is peeled off, the pixels 70 become independent in the medium of the laminate 30 with a refractive index of 2 or higher. On the other hand, the sub-pixels 71 of each color within the pixel 70 maintain an integrated structure. As a result, the multi-color light emitted from the sub-pixels 71 of each color within the pixel 70 exhibits increased color mixing properties.

[0122] (Other variations of semiconductor light-emitting devices) As shown in Figure 24, the partition groove 80 may be equipped with a light-absorbing member 40 that absorbs light generated from the light-emitting layer. This configuration enhances support and suppresses light from reaching adjacent pixels, thereby reducing false illumination. In order to improve color mixing, the light-absorbing member may not be placed in the partition groove 802. Furthermore, the material, installation method, and effects of the light-absorbing member 40 are not limited to this configuration.

[0123] [Second Embodiment] Hereinafter, a second embodiment of the semiconductor light-emitting element, semiconductor light-emitting device, and method for manufacturing the same according to the present invention will be described with reference to the drawings. The main difference between the semiconductor light-emitting element of the second embodiment and the semiconductor light-emitting element of the first embodiment is that the electrodes on the light-emitting side and the electrodes on the non-light-emitting side are formed on surfaces of different heights. In the first embodiment of the semiconductor light-emitting element, the electrodes on the light-emitting side and the electrodes on the non-light-emitting side were formed on the same plane. In contrast, in the second embodiment of the semiconductor light-emitting element, the non-light-emitting portion of the subpixel is etched to a first depth, and the electrodes on the non-light-emitting side are formed there. Consequently, the corresponding mounting substrates and the form of the semiconductor light-emitting device also differ.

[0124] Figures 25 and 26 are explanatory diagrams of the pixel shape processing process S02 of the semiconductor light-emitting element in this embodiment. Figure 27 is a cross-sectional view showing the semiconductor light-emitting device in this embodiment. In this embodiment, components corresponding to those in the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted.

[0125] First, as a first-depth etching step, as shown in Figure 25(b), the portion of the sub-pixel 71 corresponding to the non-emitting portion 73 is etched to the height of the first depth to form a mesa structure. This forms cathode recesses 77R, 77G, and 77B, which are electrode surface cutouts, in the sub-pixel 71. Next, as a first-depth etching step, as shown in Figure 25(c), grooves for conductive vias 32Gp are formed. Note that the mesa structure and the grooves for conductive vias 32Gp may be formed simultaneously in a single step.

[0126] Next, as a second-depth etching step, a divided groove 801G and a groove for conductive via 32Gn are formed, as shown in Figure 26(d). Then, as a second-depth etching step, a groove for conductive via 32Bp is formed, as shown in Figure 26(e).

[0127] Next, as a third-depth etching step, the divided groove 801B and the groove for the conductive via 32Bn are formed, as shown in Figure 26(f).

[0128] In the semiconductor light-emitting element 1 fabricated in this manner, the electrodes 31p on the light-emitting portion 72 side of each sub-pixel 71 of each color are formed at the same height. Also, the electrodes 31n on the non-light-emitting portion 73 side of each sub-pixel 71 of each color are formed at the same height. However, the light-emitting portion 72 is convex relative to the non-light-emitting portion 73 by the height of the first depth. Therefore, the electrodes 31p on the light-emitting portion 72 side and the electrodes 31n on the non-light-emitting portion 73 side are formed at different heights by the height of the first depth.

[0129] As shown in Figures 25 and 26, in this embodiment, the semiconductor light-emitting device 100 is mounted on a mounting substrate 90 such that the electrode 31 faces the mounting substrate.

[0130] As shown in Figure 27, the semiconductor light-emitting device 100 is mounted on the mounting substrate 90 with the electrodes 31 facing the substrate 90. The mounting substrate 90 has anode-side wiring 91 and cathode-side wiring 93 whose height on the mounting surface side is higher than the anode-side wiring 91 by a first depth. Metal bumps 94 of the same thickness are formed on the anode-side wiring 91 and cathode-side wiring 93, respectively.

[0131] The anode-side wiring 91 and cathode-side wiring 93 of the mounting substrate 90 intersect electrically insulated from each other via an insulating layer 92 having a thickness corresponding to the height of the first depth. Note that the protrusion 91a formed on the mounting substrate 90 of the semiconductor light-emitting device 100 in the first embodiment is omitted and not formed in this embodiment.

[0132] Thus, in the semiconductor light-emitting element and semiconductor light-emitting device of the second embodiment, the multiple electrodes of the semiconductor light-emitting element 1 form independent circuits in each light-emitting unit layer 30R, 30G, and 30B corresponding to the emission color, allowing for independent control of the emission color and emission amount. Furthermore, multiple electrodes on the light-emitting side of the semiconductor light-emitting element 1, which serve as electrical terminals for the circuits to the light-emitting unit layers 30R, 30G, and 30B corresponding to each light-emitting color, are formed on the same plane. In addition, multiple electrodes on the non-light-emitting side are also formed on the same plane. This same plane on which multiple electrodes are formed becomes the mounting surface, allowing for easy and stable electrical connection with the mounting substrate 90. Furthermore, without using complex mounting substrates that require time-consuming manufacturing, a semiconductor light-emitting device can be created in which semiconductor light-emitting elements are stably mounted using a mounting substrate that easily forms a stable mounting surface.

[0133] Although various embodiments of the semiconductor light-emitting element and semiconductor light-emitting device of the present invention have been described above, all of them can be suitably used in VR goggles and AR glasses employing dot matrix displays with a pixel width of less than 100 μm. Furthermore, they can be applied to various display devices other than VR goggles and AR glasses.

[0134] Furthermore, in the present invention, it is also possible to individually select and combine each of the configurations in the above-described embodiments and modifications. [Explanation of symbols]

[0135] 1… Semiconductor light-emitting element 10…Sapphire substrate (device substrate) 30…Laminate 30R…Red light-emitting unit layer (light-emitting unit layer) 30G…Green light-emitting unit layer (light-emitting unit layer) 30B...Blue light-emitting unit layer (light-emitting unit layer) 31...Electrode 31n, 31Rn, 31Gn, 31Bn...Negative electrode 31p, 31Rp, 31Gp, 31Bp…Positive electrode 32, 32Rn, 32Gn, 32Bn, 32Gp, 32Bp... Conductive vias 70... pixels 71... Sub-pixels 71R...Red light-emitting diode 71G...Green LED 71B... Blue light-emitting diode 72, 72R, 72G, 72B… Light-emitting part 73, 73R, 73G, 73B... Non-illuminating parts 77, 77R, 77G, 77B... Cathode recess (electrode surface notch) 80,802…partition ditches 100... Semiconductor light-emitting device 301...First buffer layer 302...First n-type layer (power supply layer) 303...First light-emitting layer (blue light-emitting layer) 304...First p-type layer 305...First tunnel junction layer 306...Second n-type layer (power supply layer) 307...Second light-emitting layer (green light-emitting layer) 308...Second p-type layer 309...Second tunnel junction layer 310... Third n-type layer (power supply layer) 311...Second buffer layer 312...Third light-emitting layer (red light-emitting layer) 313... Third p-type layer 314...Third tunnel junction layer 315...The fourth n-type layer (power supply layer) 801,801R,801G,801B…Dividing groove 801x…Bottom 801y…Flat surface 801z…recess

Claims

1. Multiple light-emitting unit layers (30R, 30G, 30B), each consisting of a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310), are stacked in a predetermined stacking direction. A laminate (30) is provided in which tunnel bonding layers (305, 309) are provided between the p-type layer and the n-type layer of the light-emitting unit layer adjacent to each other in the stacking direction, Multiple pixels (70) are partitioned by partition grooves (80) and each pixel (70) has multiple subpixels (71), The sub-pixel is divided into a light-emitting portion (72) and a non-light-emitting portion (73) by a dividing groove (801) that divides the light-emitting layer of a predetermined light-emitting unit layer. An electrode (31) is provided on the mounting surface of the light-emitting portion and the non-light-emitting portion, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, The side surface of the conductive via is a surface that is inclined at an angle with respect to the stacking direction from the side surface of the partition groove. In the plurality of subpixels, the electrodes on the light-emitting side are formed on the same plane, and the electrodes on the non-light-emitting side are formed on the same plane. Semiconductor light-emitting element.

2. Multiple light-emitting unit layers (30R, 30G, 30B), each consisting of a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310), are stacked in a predetermined stacking direction. A laminate (30) is provided in which tunnel bonding layers (305, 309) are provided between the p-type layer and the n-type layer of the light-emitting unit layer adjacent to each other in the stacking direction, Multiple pixels (70) are partitioned by partition grooves (80) and each pixel (70) has multiple subpixels (71), The sub-pixel is divided into a light-emitting portion (72) and a non-light-emitting portion (73) by a dividing groove (801) that divides the light-emitting layer of a predetermined light-emitting unit layer. An electrode (31) is provided on the mounting surface of the light-emitting portion and the non-light-emitting portion, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, The conductive via includes a plurality of conductive vias of different depths, and the conductive via that is deeper than the other conductive vias has a continuous shape without steps on the side surface of the portion corresponding to the depth of the other conductive vias. In the plurality of subpixels, the electrodes on the light-emitting side are formed on the same plane, and the electrodes on the non-light-emitting side are formed on the same plane. Semiconductor light-emitting element.

3. The side surface of the conductive via is formed perpendicular to the mounting surface. The semiconductor light-emitting element according to claim 2.

4. The electrode on the light-emitting side and the electrode on the non-light-emitting side are formed on the same plane. A semiconductor light-emitting element according to any one of claims 1 to 3.

5. The dividing groove of the sub-pixel is a groove that is shallower than the conductive via of the light-emitting portion of a sub-pixel other than the sub-pixel, and has the same depth as the dividing groove up to the n-type layer. A semiconductor light-emitting element according to any one of claims 1 to 3.

6. In the sub-pixel, the conductive via on the non-emitting portion side is a groove deeper than the dividing groove. A semiconductor light-emitting element according to any one of claims 1 to 3.

7. The division groove has a bottom portion (801x) which has a flat surface (801y), and a recess (801z) which is deeper than the flat surface. A semiconductor light-emitting element according to any one of claims 1 to 3.

8. A semiconductor light-emitting device in which a semiconductor light-emitting element (1) according to any one of claims 1 to 3 is mounted on a mounting substrate (90).

9. Multiple light-emitting unit layers (30R, 30G, 30B), each consisting of a p-type layer (304, 308, 313), a light-emitting layer (303, 307, 312), and an n-type layer (302, 306, 310), are stacked on the element substrate (10) in a predetermined stacking direction. A laminate (30) is provided in which tunnel bonding layers (305, 309) are provided between the p-type layer and the n-type layer of the light-emitting unit layer adjacent to each other in the stacking direction, Multiple pixels (70) are partitioned by partition grooves (80) and each pixel (70) has multiple subpixels (71), The sub-pixel is divided into a light-emitting portion (72) and a non-light-emitting portion (73) by a dividing groove (801) that divides the light-emitting layer of a predetermined light-emitting unit layer. An electrode (31) is provided on the mounting surface of the light-emitting portion and the non-light-emitting portion, and a conductive via (32) is provided from the electrode to a predetermined n-type layer for circuit configuration to the light-emitting layer of the predetermined light-emitting unit layer, A method for manufacturing a semiconductor light-emitting element, wherein in the plurality of subpixels, the electrodes on the light-emitting side are formed on the same plane, and the electrodes on the non-light-emitting side are formed on the same plane, The process includes an epitaxial lamination step (S00) in which each layer of the laminate is formed on the element substrate by epitaxial deposition, A pixel partition groove formation step (S01) in which the partition groove is formed by etching in the stacking direction of the laminate, The pixel shape processing step (S02) is performed by etching multiple times to form the divided groove and the groove of at least the conductive via of the light-emitting portion among the conductive vias, The electrode formation step (S05) in which the electrode and the conductive via are formed, Having, A method for manufacturing semiconductor light-emitting elements.

10. In the multiple etching steps of the aforementioned pixel shape processing process, The division groove and the groove of the conductive via are formed starting from the shallower parts, with the difference in depth being added to the deeper parts. The method for manufacturing a semiconductor light-emitting element according to claim 9.

11. In the multiple etching steps of the aforementioned pixel shape processing process, The divided grooves and the grooves of the conductive vias are formed at the same depth. The method for manufacturing a semiconductor light-emitting element according to claim 9.

12. The grooves of the conductive vias in the non-light-emitting portion are formed in the pixel compartment groove formation step (S01). The method for manufacturing a semiconductor light-emitting element according to claim 9.

13. A semiconductor light-emitting element manufactured by the manufacturing method described in claim 9 is mounted on a mounting substrate (90). A method for manufacturing a semiconductor light-emitting device.

14. After the semiconductor light-emitting element is mounted on the mounting substrate, The system includes a lift-off step for lifting off the element substrate. A method for manufacturing a semiconductor light-emitting device according to claim 13.

15. The pixels of the semiconductor light-emitting element are formed by integrating the plurality of subpixels. A method for manufacturing a semiconductor light-emitting device according to claim 14.

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