Semiconductor equipment

Abstract

To obtain a semiconductor device that can adjust the cathode voltage of a diode to an appropriate voltage even when a relatively high voltage is applied to the N-type high-potential region. [Solution] The semiconductor device 51 includes N-type semiconductor regions 21 and 22 selectively provided in the upper part of the N-type high-voltage isolation region 2, and a P-type semiconductor region 31 selectively provided in the upper part of the N-type high-voltage isolation region 2, to which a power supply voltage V1 lower than the power supply voltage V2 is supplied. The N-type semiconductor region 22 is positioned closer to the N-type high-potential region 3 compared to the N-type semiconductor region 21 and the P-type semiconductor region 31, and the P-type semiconductor region 31 is positioned between the N-type semiconductor region 21 and the N-type high-potential region 3 in a plan view. The power supply voltage V2 is supplied to the anode of the diode D4, the cathode of the diode D4 is electrically connected to the N-type semiconductor region 21, and the N-type semiconductor region 22 is electrically connected to the N-type high-potential region 3.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including an N-type high-potential region provided with a high-voltage side drive circuit.

Background Art

[0002] As a conventional semiconductor device provided with a high-voltage side drive circuit and including an N-type high-potential region, for example, there is a semiconductor device disclosed in Patent Document 1.

[0003] In the semiconductor device disclosed in Patent Document 1, for the purpose of supplying a voltage to the N-type high-potential region provided with the high-voltage side drive circuit (high-voltage floating circuit), a high-voltage holding unit is provided so that a high voltage is not applied to the cathode of the bootstrap diode when a high voltage is supplied to the high-voltage side drive circuit. The anode of the bootstrap diode is connected to the low-voltage side drive circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a conventional semiconductor device typified by the semiconductor device disclosed in Patent Document 1, the p ,

[0007] , , , + , , , , , ,

[0005] , , - , + , , ,

[0006] , , ,

[0004] , , layer surrounding the n + layer is fixed to the same potential as the p - substrate to widen the depletion layer and relax the electric field.

[0006] In a conventional semiconductor device having such a configuration, since the spread of the depletion layer cannot be adjusted, there is a problem that the cathode voltage applied to the cathode of the diode cannot be suppressed to an appropriate voltage that does not become too high.

[0007] Since conventional semiconductor devices have the above problems, they cannot cope with variations in product performance due to variations in the manufacturing process, and there have been restrictions in layout design.

[0008] The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of adjusting the cathode voltage of a diode to an appropriate voltage even when a relatively high voltage is applied to an N-type high potential region.

Means for Solving the Problems

[0009] The semiconductor device according to the present disclosure includes a P-type semiconductor layer, an N-type high potential region provided on the P-type semiconductor layer, an N-type high breakdown voltage isolation region provided on the P-type semiconductor layer and surrounding the N-type high potential region in a plan view, a diode region provided independently of the N-type high breakdown voltage isolation region on the P-type semiconductor layer and having a diode to which a second voltage higher than a first voltage is supplied to an anode, first and second N-type semiconductor regions selectively provided on an upper layer portion of the N-type high breakdown voltage isolation region, and a P-type semiconductor region selectively provided on the upper layer portion of the N-type high breakdown voltage isolation region and to which the first voltage lower than the second voltage is supplied. The semiconductor device is such that the N-type impurity concentrations of the first and second N-type semiconductor regions are set higher than the N-type impurity concentration of the N-type high breakdown voltage isolation region, the first and second N-type semiconductor regions and the P-type semiconductor region are provided without having a contact relationship with each other, the second N-type semiconductor region is arranged closer to the N-type high potential region compared to the first N-type semiconductor region and the P-type semiconductor region, the P-type semiconductor region is arranged between the first N-type semiconductor region and the N-type high potential region in a plan view, the cathode of the diode is electrically connected to the first N-type semiconductor region, and the second N-type semiconductor region is electrically connected to the N-type high potential region.

Advantages of the Invention

[0010] In the semiconductor device of this disclosure, the first voltage applied to the P-type semiconductor region is set lower than the second voltage applied to the first N-type semiconductor region, so that a reverse bias can be applied between the P-type semiconductor region and the N-type high-voltage isolation region.

[0011] Therefore, the depletion layer formed at the interface between the P-type parallel region and the N-type high-voltage isolation region of the P-type semiconductor region can mitigate the electric field in the peripheral region of the first N-type semiconductor region electrically connected to the cathode of the diode.

[0012] Therefore, even if a high-potential power supply voltage higher than the second voltage is applied to the first electrode, the value of the first voltage can be adjusted so that the cathode voltage applied to the diode's cathode does not become too high.

[0013] Furthermore, even if the conditions for achieving the correct cathode voltage differ between devices due to variations in product performance, the semiconductor device of this disclosure can adjust the value of the first voltage for each product, thereby suppressing variations in product performance and improving the failure rate of the devices. [Brief explanation of the drawing]

[0014] [Figure 1] This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to Embodiment 1 of the present disclosure. [Figure 2] This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to Embodiment 2 of the present disclosure. [Figure 3] This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to Embodiment 3 of the present disclosure. [Figure 4] This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to Embodiment 4 of the present disclosure. [Figure 5] This is a schematic explanatory diagram showing the planar structure of a semiconductor device which is a first embodiment of Embodiment 5 of the present disclosure. [Figure 6] This is a schematic explanatory diagram showing the planar structure of a semiconductor device, which is a second embodiment of Embodiment 5 of the present disclosure. [Figure 7] This is a schematic explanatory diagram showing the planar structure of a semiconductor device which is a first embodiment of Embodiment 6 of the present disclosure. [Figure 8] This is a schematic explanatory diagram showing the planar structure of a semiconductor device, which is a second embodiment of Embodiment 6 of the present disclosure. [Figure 9] This is a schematic explanatory diagram showing the planar structure of a semiconductor device, which is a third aspect of Embodiment 6 of the present disclosure. [Figure 10] This is a schematic explanatory diagram showing the planar structure of a semiconductor device which is a first embodiment of Embodiment 7 of the present disclosure. [Figure 11] This is a schematic explanatory diagram showing the planar structure of a semiconductor device, which is a second embodiment of Embodiment 7 of the present disclosure. [Figure 12] This is a schematic explanatory diagram showing the planar structure of a semiconductor device, which is a third embodiment of Embodiment 7 of the present disclosure. [Figure 13] This is a cross-sectional view showing the basic structure of a semiconductor device equipped with an N-type high-potential region and a high-voltage drive circuit. [Modes for carrying out the invention]

[0015] <Basic technology> Figure 13 is a cross-sectional view showing the basic structure of a semiconductor device having an N-type high-potential region with a high-voltage side drive circuit. Figure 13 corresponds to Figure 2, etc., disclosed in Patent Document 1.

[0016] As shown in the figure, the diode D3 region 206 and the high-pressure island are used in n - This shows a bootstrap method in which the drift layer Rn region 208 is mounted on a monolithic high-voltage IC chip. - The drift layer Rn region 208 functions as a high-pressure holding area.

[0017] One end of the external capacitor C1 connected between the VB terminal and the VS terminal is on the monolithic IC chip. - The drift layer Rn and the diode D3 region 206 are connected to, for example, Vcc of a power supply voltage of 15V.

[0018] Thus, in the monolithic high-voltage IC shown in FIG. 13, the anode p of the diode D3 region 206 + layer 221 was connected to the power supply voltage Vcc. And, from the cathode n + layer 222, current was passed through the n - drift layer Rn to an external capacitor C1 to charge the external capacitor C1. The monolithic high-voltage IC shown in FIG. 13 provides a method that does not require separately providing a high-voltage side floating power supply by using the charging voltage charged in the external capacitor C1 as the power supply voltage of the high-voltage side drive circuit.

[0019] In the cross-sectional structure of the bootstrap circuit shown in FIG. 13, it has the diode D3 region 206, the high-voltage island n - drift layer region 208, and the high-voltage side driving CMOS transistor region 209. In the diode D3 region 206, the implanted n + layer 110 is interposed between the n - semiconductor layer 106 and the p - substrate 105. A high-voltage floating circuit serving as a high-voltage side drive circuit is provided in the high-voltage side driving CMOS transistor region 209.

[0020] Also, in the high-voltage island n - drift layer region 208, the p - layers 213 and 214 having the same potential as the substrate 105 are provided to widen the depletion layer and relieve the electric field concentration in the n + region 212. Further, a p + diffusion region 218 that joins and separates the diode D3 region 206 and the high-voltage island n - drift layer region 208 is formed as an interlayer insulating film to a depth reaching the p + substrate 105 within the n - semiconductor layer 106. -

[0021] As is clear from the cross-sectional structure of the bootstrap circuit configured as described above, the diode D3 region 206 has an anode p within the n - ,>semiconductor layer 106 of the diode D3 region 206 +Layer 221 and cathode n + A layer 222 is provided, and embedded n + Layer 110 is the n of diode D3 region 206 - Semiconductor layer 106 and p - By interposing it between substrates 105, the base concentration is increased, lowering the HFE of the parasitic PNP transistor and suppressing the ON operation of the parasitic PNP transistor. Anode p + From layer 221 to diode D3 region 206 - via semiconductor layer 106 - This prevents current from flowing in the direction of the circuit board 105.

[0022] Meanwhile, high-pressure island n - The drift layer region 208 employs a Multiple Floating Field Plate (MFFP). That is, high-pressure island n - The drift layer Rn region 208 is the n of the high-pressure island. - n on the high-potential side within semiconductor layer 106 + Layer 211 and the opening n + Provided on both sides of layer 212, p - A pair of p fixed to the same potential (ground potential GND) as the substrate 105 + By enclosing it with layers 213 and 214, the depletion layer is widened, and the opening n + This reduces the electric field concentration in layer 212. Therefore, when the power element on the high-voltage side turns ON and the power element on the low-voltage side turns OFF, the n of the opening + Although layer 212 is at a floating potential, this potential can be suppressed to a low potential, allowing a high voltage to be maintained.

[0023] Thus, in the bootstrap method for semiconductor devices, which is the basic technology shown in Figure 13, the diode D3 region 206 and the high-pressure island n - By mounting the drift layer region 208 on the high-voltage IC chip, circuit current consumption can be effectively reduced. Also, in Figure 13, diode region D3 206 and high-voltage island n - The configuration, which separates the drift layer Rn region 208 by bonding, makes it possible to mount it on a monolithic high-voltage IC chip.

[0024] Conventional semiconductor devices, represented by the basic technology shown in Figure 13, as described above, have a pair of p + The potential of layers 213 and 214 is p - It is fixed at the same potential as the substrate 105 (ground potential GND). Therefore, conventional semiconductor devices have the problem that they cannot adjust the depletion layer's spread, and thus cannot adjust the cathode voltage applied to the cathode of diode D3 to an appropriate voltage that does not become too high. Embodiments 1 to 7 of this disclosure, described below, aim to solve this problem.

[0025] <Embodiment 1> Figure 1 is an explanatory diagram schematically showing the planar structure of a semiconductor device 51, which is an embodiment 1 of the present disclosure.

[0026] As shown in the figure, the semiconductor device 51 of Embodiment 1 mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3.

[0027] The P-type semiconductor layer 1, N-type high-voltage isolation region 2, N-type high-potential region 3, and diode region 4 shown in Figure 1 are, for example, the p shown in Figure 13. - Substrate 105, high-pressure island n - Drift layer region 208(n - Semiconductor layer 106), high-voltage side drive CMOS transistor region 209 (of n - This corresponds to the semiconductor layer 106) and the diode D3 region 206.

[0028] The N-type high-voltage isolation region 2 is provided on the P-type semiconductor layer 1 and, when viewed from above, completely surrounds the N-type high-potential region 3. In other words, by surrounding the N-type high-voltage isolation region 3 when viewed from above, a Resurf structure can be realized, for example.

[0029] The diode region 4 is provided on the P-type semiconductor layer 1 independently of the N-type high-voltage isolation region 2 and the N-type high-potential region 3, and contains a diode D4 inside. Diode D4 is a bootstrap diode, and the anode of this diode D4 is connected to a low-voltage drive circuit (not shown in Figure 1).

[0030] The N-type high-potential region 3 has a power supply electrode 5 on its surface, which serves as a first electrode for the high-potential side power supply voltage VB, and a reference electrode 6, which serves as a second electrode for the high-potential side reference voltage VS.

[0031] N-type semiconductor regions 21 and 22 are selectively provided as first and second N-type semiconductor regions in the upper layer of the N-type high-voltage isolation region 2.

[0032] A P-type semiconductor region 31 is selectively provided in the upper layer of the N-type high-voltage isolation region 2. The N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 are provided in the upper layer of the N-type high-voltage isolation region 2 without being in contact with each other.

[0033] The cross-sectional structures of the N-type semiconductor regions 21 and 22 shown in Figure 1 are, for example, the n shown in Figure 13. + Region 212 and n + This corresponds to layer 211. The cross-sectional structure of the P-type semiconductor region 31 shown in Figure 1 is, for example, the p shown in Figure 13. + This corresponds to layer 214.

[0034] The N-type impurity concentration in the N-type semiconductor regions 21 and 22 is set higher than the N-type impurity concentration in the N-type high-voltage isolation region 2, and the P-type impurity concentration in the P-type semiconductor region 31 is set higher than the P-type impurity concentration in the P-type semiconductor layer 1.

[0035] The N-type high-potential region 3 exhibits a quadrilateral shape, which is a polygon with more than one triangle when viewed from above. The N-type high-potential region 3 shown in Figure 1 exhibits a horizontally elongated rectangular shape when viewed from above. The N-type semiconductor region 22 is positioned closer to the N-type high-potential region 3 compared to the N-type semiconductor region 21 and the P-type semiconductor region 31. That is, when viewed from above, the N-type semiconductor region 22 is positioned inside the N-type semiconductor region 21.

[0036] The N-type semiconductor region 21 has a first N-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region 3. This at least one side corresponds to one of the right, left, or bottom sides of the N-type high-potential region 3 shown in Figure 1.

[0037] The N-type semiconductor region 22 is positioned between the N-type high-potential region 3 and the N-type semiconductor region 21 when viewed from above. The N-type semiconductor region 22 has a second N-type parallel region that is parallel to at least one side of the N-type high-potential region 3 when viewed from above. This at least one side is common to both the N-type semiconductor regions 21 and 22.

[0038] Furthermore, the P-type semiconductor region 31 has a P-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region 3. This at least one side is a common side between the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31.

[0039] The entire P-type semiconductor region 31 is located between the first N-type semiconductor region, the N-type semiconductor region 21, and the second N-type semiconductor region, the N-type semiconductor region 22, when viewed from above. Therefore, the P-type parallel region of the P-type semiconductor region 31 is located between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type semiconductor region of the N-type semiconductor region 22, when viewed from above. The aforementioned P-type semiconductor region 31 is located between the N-type semiconductor region 21 and the N-type high-potential region 3 when viewed from above.

[0040] In Figure 1, the first N-type parallel region, the second N-type parallel region, and the P-type parallel region appear to be regions parallel to the three sides (right side, left side, and top side) of the N-type high-potential region 3. In this specification, the features of Embodiment 1 are described as follows: "The first N-type parallel region of the N-type semiconductor region 21, the second N-type parallel region of the N-type semiconductor region 22, and the P-type parallel region of the P-type semiconductor region 31 are all parallel to at least one side of the N-type high-potential region 3."

[0041] In the N-type high-voltage isolation region 2, in the gap region where the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 are not formed, a transmission element for transmitting signals between the low-voltage side drive circuit and the high-voltage side drive circuit (high-voltage floating circuit) is provided. The high-voltage side drive circuit is provided within the N-type high-potential region 3.

[0042] The first power supply, power supply 11, supplies a power supply voltage V1, which is the first voltage. The second power supply, power supply 12, supplies a power supply voltage V2, which is the second voltage. Note that power supply voltage V1 is set lower than power supply voltage V2. More precisely, if the voltage drop across diode D4 is VF, then it is set to satisfy {V1 < (V2 - VF)}.

[0043] The power supply voltage V1 supplied from the power supply 11 is applied to the P-type semiconductor region 31 via the wiring L1. That is, one end of the wiring L1 is electrically connected to node P1 on the P-type semiconductor region 31, and the other end of the wiring L1 is electrically connected to the positive terminal of the power supply 11. The negative terminal of the power supply 11 is electrically connected to the ground level, which is the reference potential. The power supply voltage V1 from the power supply 11 is not supplied to the P-type semiconductor layer 1.

[0044] The power supply voltage V2 supplied from power supply 12 is applied to the anode of diode D4 via wiring L2. That is, node P2 on wiring L2 and the anode of diode D4 are electrically connected, and the positive terminal of power supply 12 is electrically connected to wiring L2. The negative terminal of power supply 12 is electrically connected to the ground level, which is the reference potential.

[0045] The cathode of diode D4 is electrically connected to the N-type semiconductor region 21 via wiring L22. That is, the cathode of diode D4 is electrically connected to one end of wiring L22, and node P13 on the N-type semiconductor region 21 is electrically connected to the other end of wiring L22.

[0046] Therefore, the cathode of diode D4 is electrically connected to the N-type high-potential region 3 via a high-voltage isolation element. The "high-voltage isolation element" refers to the region within the N-type high-voltage isolation region 2 that electrically connects the N-type semiconductor regions 21 and 22. The "high-voltage isolation element" is, for example, the n in the basic technology shown in Figure 13. - This corresponds to the drift layer Rn.

[0047] The N-type semiconductor region 22 is electrically connected to the power supply electrode 5, which is the first electrode, via wiring L21. That is, node P12 on the N-type semiconductor region 22 is electrically connected to one end of wiring L21, and node P11 on the power supply electrode 5 is electrically connected to the other end of wiring L21. In this way, the N-type semiconductor region 22 is electrically connected to the N-type high-potential region 3.

[0048] One electrode of the external charging element, capacitor C3, is electrically connected via wiring L3 to the power supply electrode 5, which becomes the first electrode of the N-type high-potential region 3, and the other electrode is connected via wiring L4 to the reference electrode 6, which becomes the second electrode of the N-type high-potential region 3.

[0049] Specifically, one end of wiring L3 is electrically connected to node P3 on the power supply electrode 5, the other end of wiring L3 is electrically connected to one electrode of capacitor C3, one end of wiring L4 is electrically connected to node P4 on the reference electrode 6, and the other end of wiring L4 is electrically connected to the other electrode of capacitor C3.

[0050] A bootstrap circuit can be constructed using this capacitor C3 and diode D4. Therefore, the charge stored in capacitor C3 can drive the high-potential side drive circuit provided in the N-type high-potential region 3.

[0051] Furthermore, the electrical connection of power supplies 11 and 12 and capacitor C3 is not limited to the method using the wirings L1 to L4 and L22 described above, but any other method is possible. For example, pattern wiring may be provided on the P-type semiconductor layer 1, or electrical connection to an externally provided power supply (equivalent to power supplies 11 and 12) and capacitor C3 may be made using wire wiring via electrode pads provided on the power supply electrode 5 or reference electrode 6.

[0052] In the semiconductor device 51 of Embodiment 1, the power supply voltage V1, which is the first voltage applied to the P-type semiconductor region 31, is set lower than the power supply voltage V2, which is the second voltage applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region 31 and the N-type high-voltage isolation region 2.

[0053] Therefore, the depletion layer formed at the interface between the P-type parallel region and the N-type high-voltage isolation region 2 of the P-type semiconductor region 31 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0054] Therefore, even if a high-potential power supply voltage VB, which is higher than the power supply voltage V2, is applied to the power supply electrode 5, the value of the first voltage, the power supply voltage V1, can be adjusted so that the cathode voltage applied to the cathode of the diode D4 constituting the bootstrap circuit does not become too high.

[0055] This is because the power supply voltage V1 supplied from power supply 11 is used as a dedicated setting voltage for the P-type semiconductor region 31. In other words, the power supply voltage V1 is the pair of p-type semiconductor regions shown in Figure 13. + Like the set potential of layers 213 and 214, p - There is no constraint that it must be fixed at the same potential as substrate 105.

[0056] Therefore, the semiconductor device 51 of Embodiment 1 can change the power supply voltage V1 without being subject to the above-mentioned constraints, and thus the depletion layer extension described above can be precisely adjusted so that the cathode voltage of diode D4 becomes an appropriate voltage. This also improves the degree of freedom in the layout design of the semiconductor device 51.

[0057] Furthermore, even if the conditions for the cathode voltage of diode D4 to reach the appropriate voltage differ between devices due to variations in product performance, the semiconductor device 51 of Embodiment 1 can individually adjust the power supply voltage V1 for each device, thereby suppressing variations in product performance and improving the failure rate of the devices.

[0058] Furthermore, the semiconductor device 51 of Embodiment 1 can drive the high-potential side drive circuit provided in the N-type high-potential region 3 by discharging the charging voltage charged in the capacitor C3, through a bootstrap circuit that includes a diode D4 and a charging element capacitor C3.

[0059] <Embodiment 2> Figure 2 is a schematic diagram illustrating the planar structure of a semiconductor device 52, which is an embodiment 2 of the present disclosure.

[0060] As shown in the figure, the semiconductor device 52 of Embodiment 2, like Embodiment 1, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3.

[0061] The semiconductor device 52 of Embodiment 2 has all the features of the semiconductor device 51 of Embodiment 1 shown in Figure 1, and further has the following features.

[0062] The N-type semiconductor region 21 has a first N-type parallel region that, when viewed from above, is parallel to three sides of the N-type high-potential region 3. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 2. Furthermore, the first N-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0063] Thus, the N-type semiconductor region 21 has a first N-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. Therefore, the N-type semiconductor region 21 surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0064] The N-type semiconductor region 22 has a second N-type parallel region that is parallel to the three sides of the N-type high-potential region 3 when viewed from above. The three sides mentioned above correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 2. Furthermore, the second N-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0065] Thus, the N-type semiconductor region 22 has a second N-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common sides between the N-type semiconductor regions 21 and 22. Therefore, the N-type semiconductor region 22 surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0066] The P-type semiconductor region 31 has a P-type parallel region that is parallel to the three sides of the N-type high-potential region 3 when viewed from above. The three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 2. Furthermore, the P-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0067] Thus, the P-type semiconductor region 31 has P-type parallel regions that are parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31. Therefore, the P-type semiconductor region 31 surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0068] Thus, as shown in Figure 2, the semiconductor device 52 of the second embodiment is characterized in that "the first N-type parallel region of the N-type semiconductor region 21, the second N-type parallel region of the N-type semiconductor region 22, and the P-type parallel region of the P-type semiconductor region 31 are all parallel to at least three sides of the N-type high-potential region 3."

[0069] The entire P-type semiconductor region 31 is located between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the P-type parallel region of the P-type semiconductor region 31 is located between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type semiconductor region of the N-type semiconductor region 22 when viewed from above.

[0070] Therefore, in the semiconductor device 52 of Embodiment 2, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 are arranged to surround more than half of the outer periphery of the N-type high-potential region 3 when viewed from above. In addition, the P-type semiconductor region 31 is arranged to surround more than half of the outer periphery of the N-type semiconductor region 22, and the N-type semiconductor region 21 is arranged to surround more than half of the outer periphery of the P-type semiconductor region 31.

[0071] In the semiconductor device 52 of Embodiment 2, the power supply voltage V1, which is the first voltage applied to the P-type semiconductor region 31, is set lower than the power supply voltage V2, which is the second voltage applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region 31 and the N-type high-voltage isolation region 2.

[0072] Therefore, in the semiconductor device 52 of the second embodiment, the depletion layer formed at the interface between the P-type parallel region and the N-type high-voltage isolation region 2 of the P-type semiconductor region 31 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0073] Therefore, similar to Embodiment 1, the semiconductor device 52 of Embodiment 2 can improve the degree of freedom in the layout design of the semiconductor device 52, suppress variations in product performance, and improve the failure rate of the device.

[0074] In addition, in Embodiment 2, the P-type parallel region of the P-type semiconductor region 31, and the first and second N-type parallel regions of the N-type semiconductor regions 21 and 22, are regions parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common sides between the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31.

[0075] Therefore, the first and second N-type parallel regions and the P-type parallel region are located equidistant from at least three sides of the N-type high-potential region 3. Furthermore, in the semiconductor device 52 of Embodiment 2, when a reverse bias is applied between the P-type semiconductor region 31 and the N-type high-voltage isolation region 2, a depletion layer is formed along the P-type parallel region of the P-type semiconductor region 31 that is parallel to at least three sides of the N-type high-potential region 3.

[0076] As a result, the semiconductor device 52 of Embodiment 2 can uniformly set the electric fields around the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31, thereby improving the adjustment accuracy of the cathode voltage of diode D4 and increasing the reliability of the device compared to Embodiment 1. This point will be described in detail below.

[0077] Since the P-type parallel region of the P-type semiconductor region 31 is parallel to at least three sides of the N-type high-potential region 3, the distance from the N-type high-potential region 3 to the P-type parallel region of the P-type semiconductor region 31 is equal. Therefore, the electric field becomes uniform at any point in the P-type parallel region of the P-type semiconductor region 31, and the depletion layer extending toward the N-type semiconductor region 21 spreads in the same manner. Consequently, the cathode voltage of the diode D4 can be precisely adjusted by the power supply voltage V1 applied to the P-type semiconductor region 31.

[0078] Furthermore, in the semiconductor device 51 of Embodiment 1, the P-type parallel region of the P-type semiconductor region 31 is parallel to at least one side of the N-type high-potential region 3, thus providing the effect of uniform electric field at any point in the P-type parallel region. In addition, in order to further improve the uniformity of the depletion layer extension described above, it is desirable to make the formation widths of the P-type semiconductor region 31, the N-type semiconductor regions 21 and 22 equal.

[0079] In addition, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 constituting the semiconductor device 52 of Embodiment 2 are arranged to surround more than half of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0080] Therefore, in the semiconductor device 52 of Embodiment 2, the depletion layer that occurs over a relatively wide area at the interface between the P-type semiconductor region 31 and the N-type high-voltage isolation region 2 can mitigate the electric field in the peripheral region of the N-type semiconductor region 21, thereby increasing the cathode voltage suppression capability of the diode D4.

[0081] Furthermore, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 constituting the semiconductor device 52 of Embodiment 2 surround the outer periphery of the N-type high-potential region 3 in a plan view, extending beyond 3 / 4 of the outer edge. Therefore, the cathode voltage suppression capability of the diode D4 can be further enhanced.

[0082] Furthermore, in order to sufficiently block the current path between the N-type semiconductor regions 21 and 22 and exert the effect of suppressing the cathode voltage of the diode D4, it is desirable that the area in which the P-type semiconductor region 31 surrounds the N-type high-potential region 3 be equal to or greater than the area in which the N-type semiconductor regions 21 and 22 each surround the N-type high-potential region 3.

[0083] <Embodiment 3> Figure 3 is a schematic diagram illustrating the planar structure of a semiconductor device 53, which is an embodiment 3 of the present disclosure.

[0084] As shown in the figure, the semiconductor device 53 of Embodiment 3, like Embodiments 1 and 2, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3.

[0085] In the following description, components similar to those in Embodiments 1 and 2 shown in Figures 1 and 2 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 53 of Embodiment 3.

[0086] The semiconductor device 53 of Embodiment 3 is characterized by the provision of a group of P-type semiconductor regions 31G in place of the P-type semiconductor region 31, compared to Embodiments 1 and 2. That is, the group of P-type semiconductor regions 31G constitutes the P-type semiconductor region in the semiconductor device 53 of Embodiment 3. The cross-sectional structure of the group of P-type semiconductor regions 31G shown in Figure 3 is the same as that of the P-type semiconductor region 31 shown in Embodiments 1 and 2.

[0087] The P-type semiconductor region group 31G is composed of multiple P-type partial semiconductor regions 41 that are provided discretely from each other. The P-type impurity concentration of each of the multiple P-type partial semiconductor regions 41 in the P-type semiconductor region group 31G is set higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0088] The P-type semiconductor region group 31G, like the P-type semiconductor region 31 in Embodiment 2, has a P-type parallel region that is parallel to three sides of the N-type high-potential region 3 when viewed from above. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 3. Furthermore, the P-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0089] Thus, the P-type semiconductor region group 31G has P-type parallel regions that are parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor region group 31G. Therefore, the P-type semiconductor region group 31G surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0090] In the P-type semiconductor region group 31G, relay wiring 25 is provided that is electrically connected to each of the multiple P-type partial semiconductor regions 41. The relay wiring 25 is electrically connected to wiring L1 via node P1.

[0091] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to each of the multiple P-type partial semiconductor regions 41 that constitute the P-type semiconductor region group 31G via the relay wiring 25.

[0092] In the semiconductor device 53 of Embodiment 3 with this configuration, the power supply voltage V1 applied to the P-type semiconductor region group 31G is set lower than the power supply voltage V2 applied to the N-type semiconductor region 21, so that a reverse bias can be applied between the P-type semiconductor region group 31G and the N-type high-voltage isolation region 2.

[0093] Therefore, the semiconductor device 53 of Embodiment 3, like Embodiments 1 and 2, can mitigate the electric field around the N-type semiconductor region 21 by the depletion layer formed at the interface between the P-type semiconductor region group 31G and the N-type high-voltage isolation region 2.

[0094] Since the multiple P-type partial semiconductor regions 41 in the P-type semiconductor region group 31G are arranged discretely from each other, the electric field around the N-type semiconductor region 21 can be relaxed by local partial depletion layer units corresponding to each of the multiple P-type partial semiconductor regions 41.

[0095] As a result, the semiconductor device 53 of Embodiment 3 can finely adjust the cathode voltage of the diode D4 by adjusting the spacing Δ41 between adjacent P-type partial semiconductor regions 41, 41 in a plurality of P-type partial semiconductor regions 41, thereby improving the design freedom of the circuit and layout within the semiconductor device 53.

[0096] For example, if the power supply voltage V1 of power supply 11 is limited due to layout design constraints, the cathode voltage of diode D4 can also be adjusted by adjusting the spacing Δ41 between adjacent P-type subsemiconductor regions 41, 41. Setting the spacing Δ41 to a relatively large value tends to increase the cathode voltage of diode D4, while setting the spacing Δ41 to a relatively small value tends to decrease the cathode voltage of diode D4. The cathode voltage of diode D4 can be adjusted by utilizing the above-mentioned tendencies of the spacing Δ41.

[0097] <Embodiment 4> Figure 4 is a schematic diagram illustrating the planar structure of a semiconductor device 54, which is an embodiment 4 of the present disclosure.

[0098] As shown in the figure, the semiconductor device 54 of Embodiment 4, like Embodiments 1 to 3, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3.

[0099] Hereinafter, components similar to those in Embodiments 1 and 2 shown in Figures 1 and 2 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 54 of Embodiment 4.

[0100] The semiconductor device 54 of Embodiment 4 is characterized by the provision of a P-type semiconductor region 33 in place of the P-type semiconductor region 31, compared to Embodiments 1 and 2. In other words, the P-type semiconductor region 33 becomes the P-type semiconductor region in the semiconductor device 54 of Embodiment 4.

[0101] In the N-type high-voltage isolation region 2, the peripheral region of the N-type semiconductor region 21, which becomes the first N-type semiconductor region, includes a peripheral region 61 which is the first peripheral region on the side approaching the N-type semiconductor region 22 (inner side) and a peripheral region 62 which is the second peripheral region on the side moving away from the N-type semiconductor region 22 (outer side).

[0102] The P-type semiconductor region 33 is provided to completely surround the N-type semiconductor region 21, which becomes the first N-type semiconductor region when viewed from above. The P-type impurity concentration in the P-type semiconductor region 33 is set higher than the P-type impurity concentration in the P-type semiconductor layer 1.

[0103] In this specification, "encircling P-type semiconductor region" means a region provided in at least a portion of each of the peripheral regions 61 and 62 of the N-type semiconductor region 21, and which surrounds the periphery of the N-type semiconductor region 21 when viewed from above. On the other hand, "fully encircling P-type semiconductor region" included in "encircling P-type semiconductor region" means a region provided in the peripheral regions 61 and 62 of the N-type semiconductor region 21, and which surrounds the periphery of the N-type semiconductor region 21 without any gaps when viewed from above.

[0104] Therefore, the P-type semiconductor region 33 becomes a completely enclosed P-type semiconductor region. The P-type semiconductor region 33 has an inner P-type parallel region 331, an outer P-type parallel region 332, and a connecting region 333 as P-type parallel regions. The inner P-type parallel region 331 is formed in the peripheral region 61, which is the first peripheral region, and the outer P-type parallel region 332 is formed in the peripheral region 62, which is the second peripheral region. The inner P-type parallel region 331 and the outer P-type parallel region 332 are connected via the connecting region 333.

[0105] The inner P-type parallel region 331, like the P-type semiconductor region 31 in Embodiment 2, is a region parallel to three sides of the N-type high-potential region 3 when viewed from above. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 4. Furthermore, the inner P-type parallel region 331 has a region parallel to a part of the top side of the N-type high-potential region 3.

[0106] Thus, the inner P-type parallel region 331 is a region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common sides between the N-type semiconductor regions 21 and 22 and the inner P-type parallel region 331. Therefore, when viewed from above, the inner P-type parallel region 331 encloses more than 3 / 4 of the outer periphery of the N-type high-potential region 3.

[0107] The outer P-type parallel region 332 is a region parallel to three sides of the N-type high-potential region 3 when viewed from above. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 4. Furthermore, the outer P-type parallel region 332 also has a region parallel to a part of the top side of the N-type high-potential region 3.

[0108] Thus, the outer P-type parallel region 332 is a region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to the N-type semiconductor regions 21 and 22, as well as to the inner P-type parallel region 331 and the outer P-type parallel region 332. Therefore, when viewed from above, the outer P-type parallel region 332 encloses more than 3 / 4 of the outer periphery of the N-type high-potential region 3.

[0109] Thus, the P-type semiconductor region 33, which is a completely enclosed P-type semiconductor region, has an inner P-type parallel region 331 and an outer P-type parallel region 332 as P-type parallel regions.

[0110] Furthermore, the cross-sectional structure of the P-type semiconductor region 33 shown in Figure 4 is the same as that of the P-type semiconductor region 31 shown in Embodiment 1 and Embodiment 2, for example, the p shown in Figure 13. + Layer 213 or p + This corresponds to layer 214.

[0111] Similar to the P-type semiconductor region 31 in Embodiments 1 and 2, the entire area of ​​the inner P-type parallel region 331 in the P-type semiconductor region 33 is located between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the inner P-type parallel region 331 is located between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type semiconductor region of the N-type semiconductor region 22 when viewed from above.

[0112] In the semiconductor device 54 of Embodiment 4 with this configuration, the power supply voltage V1 applied to the P-type semiconductor region 33 is set lower than the power supply voltage V2 applied to the N-type semiconductor region 21, so that a reverse bias can be applied between the P-type semiconductor region 33 and the N-type high-voltage isolation region 2.

[0113] Therefore, the semiconductor device 54 of Embodiment 4 provides the same effects as Embodiments 1 and 2.

[0114] In addition, the P-type semiconductor region 33, which is a completely surrounding P-type semiconductor region, includes the peripheral regions 61 and 62 and is provided surrounding the N-type semiconductor region 21 in a plan view. Therefore, the depletion layer becomes a surrounding depletion layer that encloses the N-type semiconductor region 21.

[0115] Therefore, the semiconductor device 54 of Embodiment 4 can mitigate the electric field around the N-type semiconductor region 21, including peripheral regions 61 and 62, when a reverse bias is applied.

[0116] Furthermore, since the P-type semiconductor region 33, which forms a completely surrounding P-type semiconductor region, is provided so as to completely enclose the N-type semiconductor region 21 in a plan view, the N-type semiconductor region 21 is surrounded by a depletion layer from all directions, thereby enhancing the suppression effect of the cathode voltage of the diode D4 when a high-potential side power supply voltage VB, which is higher than the power supply voltage V2, is applied to the power supply electrode 5.

[0117] <Embodiment 5> (First aspect) Figure 5 is a schematic diagram illustrating the planar structure of a semiconductor device 55A, which is a first embodiment of Embodiment 5 of the present disclosure.

[0118] As shown in the figure, the semiconductor device 55A, which is the first embodiment of Embodiment 5, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 to 13, and a capacitor C3.

[0119] Hereinafter, components similar to those in Embodiment 4 shown in Figure 4 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 55A, which is the first aspect of Embodiment 5.

[0120] The semiconductor device 55A of Embodiment 5 is characterized by the provision of a pair of P-type semiconductor regions 34 and 35 in place of the P-type semiconductor region 33, compared to Embodiment 4. That is, the pair of P-type semiconductor regions 34 and 35 are the P-type semiconductor regions in the semiconductor device 55A of the first embodiment of Embodiment 5, and also surround P-type semiconductor regions.

[0121] In the N-type high-voltage isolation region 2, similar to the semiconductor device 54 of Embodiment 4, the peripheral region of the N-type semiconductor region 21 includes a peripheral region 61 which is a first peripheral region on the side approaching the N-type semiconductor region 22, and a peripheral region 62 which is a second peripheral region on the side moving away from the N-type semiconductor region 22.

[0122] The P-type semiconductor region 34 and the P-type semiconductor region 35 are provided independently of each other without any contact relationship, and the P-type impurity concentration of each P-type semiconductor region pair 34 and 35 is set higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0123] The combination of P-type semiconductor regions 34 and 35 that constitute the surrounding P-type semiconductor region is arranged to surround the periphery of the N-type semiconductor region 21, which becomes the first N-type semiconductor region when viewed from above.

[0124] The P-type semiconductor region 34 is a first partially surrounding P-type semiconductor region provided in at least a portion of the peripheral region 61 of the N-type semiconductor region 21. The P-type semiconductor region 34 is a second partially surrounding P-type semiconductor region provided in at least a portion of the peripheral region 62 of the N-type semiconductor region 21.

[0125] The P-type semiconductor region 34 provided in the peripheral region 61 corresponds to the inner P-type parallel region 331 of the P-type semiconductor region 33 shown in Figure 4. Similarly, the P-type semiconductor region 35 provided in the peripheral region 62 corresponds to the outer P-type parallel region 332 and the connection region 333 of the P-type semiconductor region 33 shown in Figure 4.

[0126] Therefore, the surrounding P-type semiconductor region formed by the combination of P-type semiconductor region pairs 34 and 35 exhibits a planar and cross-sectional structure similar to that of the P-type semiconductor region 33 of Embodiment 4, which has an inner P-type parallel region 331, an outer P-type parallel region 332, and a connecting region 333.

[0127] In other words, the P-type semiconductor region 34, like the inner P-type parallel region 331 of the P-type semiconductor region 33, has a first partial parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. The P-type semiconductor region 35, like the outer P-type parallel region 332 of the P-type semiconductor region 33, has a second partial parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. Thus, the pair of P-type semiconductor regions 34 and 35 have the first and second partial parallel regions described above as P-type parallel regions.

[0128] Since the P-type semiconductor region 34 that becomes the first partial surrounding P-type semiconductor region and the P-type semiconductor region 35 that becomes the second partial surrounding P-type semiconductor region are provided separately from each other, gap regions 65 and 66 exist between the P-type semiconductor region 34 and the P-type semiconductor region 35.

[0129] Thus, the pair of P-type semiconductor regions 34 and 35 are provided surrounding the periphery of the N-type semiconductor region 21 in a manner that opens the gap regions 65 and 66 in plan view. Note that it is desirable that the gap regions 65 and 66 between the P-type semiconductor region 34 and the P-type semiconductor region 35 be narrow in terms of suppressing an increase in the cathode voltage of the diode D4.

[0130] And, the entire region of the P-type semiconductor region 34 corresponding to the inner P-type parallel region 331 of the P-type semiconductor region 33 is arranged between the N-type semiconductor region 21 and the N-type semiconductor region 22 in plan view. Therefore, the first partial parallel region included in the P-type semiconductor region 34 is arranged between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22 in plan view, similar to the inner P-type parallel region 331 of the P-type semiconductor region 33.

[0131] The semiconductor device 55A which is the first aspect of the fifth embodiment further includes a power supply 13 that is a third power supply for supplying a power supply voltage V3 that becomes a third voltage. The power supply voltage V3 that becomes the third voltage is set lower than the power supply voltage V2 that becomes the second voltage. Exactly, when the voltage drop of the diode D4 is VF, it is set to satisfy {V3 < (V2 - VF)}.

[0132] Note that the magnitude relationship between the power supply voltage V1 and the power supply voltage V3 is arbitrary. That is, the magnitude relationship between the power supply voltage V1 and the power supply voltage V3 can be arbitrarily set within the range that satisfies {V1 < V2, V3 < V2}.

[0133] A power supply voltage V1 is applied from the power supply 11 to the P-type semiconductor region 34 which is the first partial surrounding P-type semiconductor region via the wiring L1. That is, the node P1 on the P-type semiconductor region 34 is electrically connected to one end of the wiring L1.

[0134] A third voltage, the power supply voltage V3, is applied to the second partial surrounding P-type semiconductor region, the P-type semiconductor region 35, via the wiring L5. Specifically, node P5 on the P-type semiconductor region 35 is electrically connected to one end of the wiring L5, and the positive terminal of the power supply 13 is connected to the other end of the wiring L5. The negative terminal of the power supply 13 is electrically connected to the ground level, which is the reference potential. Furthermore, the power supply voltage V3 from the power supply 13 is not supplied to the P-type semiconductor layer 1.

[0135] In the semiconductor device 55A of the first embodiment of Embodiment 5 with this configuration, the power supply voltage V1 applied to the P-type semiconductor region 34 and the power supply voltage V3 applied to the P-type semiconductor region 35 are set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region pair 34 and 35 and the N-type high-voltage isolation region 2.

[0136] Therefore, the semiconductor device 55A in the first aspect of Embodiment 5 provides the same effects as Embodiments 1 and 2.

[0137] In addition, the pair of P-type semiconductor regions 34 and 35 that constitute the surrounding P-type semiconductor region include the peripheral regions 61 and 62 and are arranged to surround the periphery of the N-type semiconductor region 21 in a plan view. Therefore, the depletion layer becomes a surrounding depletion layer that surrounds the N-type semiconductor region 21.

[0138] Specifically, a first peripheral depletion layer is provided at the interface between the P-type semiconductor region 34, which forms the first surrounding P-type semiconductor region, and the N-type high-voltage isolation region 2, and a second peripheral depletion layer is provided at the interface between the P-type semiconductor region 35, which forms the second surrounding P-type semiconductor region, and the N-type high-voltage isolation region 2, and the combination of the first and second peripheral depletion layers forms the surrounding depletion layer.

[0139] As a result, the semiconductor device of this disclosure can surround the N-type semiconductor region 21 in a plan view by the first and second peripheral depletion layers described above, thereby mitigating the electric field around the N-type semiconductor region 21.

[0140] In addition, since the power supply voltage V1 and power supply voltage V3 can be set individually, it is possible to differentiate the extent of the first and second peripheral depletion layers relative to the N-type semiconductor region 21. Therefore, the semiconductor device 55A of the first embodiment of Embodiment 5 has the unique effect of being able to adjust the electric field distribution around the N-type semiconductor region 21 relatively easily.

[0141] (Second aspect) Figure 6 is a schematic diagram illustrating the planar structure of a semiconductor device 55B, which is a second embodiment of Embodiment 5 of the present disclosure.

[0142] As shown in the figure, the semiconductor device 55B, which is the second embodiment of Embodiment 5, includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 to 13, and a capacitor C3 as its main components, similar to the first embodiment of Embodiment 5 shown in Figure 5.

[0143] Hereinafter, components similar to those in the first embodiment of Embodiment 5 shown in Figure 5 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 55B in the second embodiment of Embodiment 5.

[0144] The semiconductor device 55B of Embodiment 5 is characterized by the provision of a group of P-type semiconductor regions 34G in place of the P-type semiconductor region 34, compared to the semiconductor device 55A. That is, the pair of P-type semiconductor regions 34G and 35 are the P-type semiconductor regions in the semiconductor device 55B of the second embodiment of Embodiment 5, and constitute a surrounding P-type semiconductor region.

[0145] The pair of P-type semiconductor regions 34G and 35 that constitute the surrounding P-type semiconductor region are arranged to surround the periphery of the N-type semiconductor region 21, which becomes the first N-type semiconductor region when viewed from above, and the group of P-type semiconductor regions 34G is positioned between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above.

[0146] The P-type semiconductor region group 34G is a first partially surrounding P-type semiconductor region provided in a part of the peripheral region 61, which is the first peripheral region of the N-type semiconductor region 21.

[0147] The P-type semiconductor region group 34G is composed of a plurality of P-type partial semiconductor regions 44 that are provided discretely from each other. The P-type impurity concentration of each of the plurality of P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G is set higher than the P-type impurity concentration of the P-type semiconductor layer 1P. The cross-sectional structure of the P-type semiconductor region group 34G is similar to that of the P-type semiconductor region 34 in the first embodiment.

[0148] In the P-type semiconductor region group 34G, relay wiring 26 is provided that is electrically connected to each of the multiple P-type partial semiconductor regions 44. The relay wiring 26 is electrically connected to wiring L1 via node P1.

[0149] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to each of the multiple P-type partial semiconductor regions 44 that constitute the P-type semiconductor region group 34G via the relay wiring 26.

[0150] On the other hand, the P-type semiconductor region 35 is a second partially surrounding P-type semiconductor region provided in the peripheral region 62 of the N-type semiconductor region 21, similar to the first embodiment.

[0151] Since the group of P-type semiconductor regions 34G, which constitutes the first partially surrounding P-type semiconductor region, and the P-type semiconductor region 35, which constitutes the second partially surrounding P-type semiconductor region, are provided discretely from each other, gap regions 65 and 66 exist between the group of P-type semiconductor regions 34G and the P-type semiconductor region 35.

[0152] In addition, in the multiple P-type partial semiconductor regions 44 that constitute the group of P-type semiconductor regions 34G which are a group of P-type semiconductor regions for partial surrounding, there is a gap Δ44 between adjacent P-type partial semiconductor regions 44, 44.

[0153] Thus, the P-type semiconductor region pairs 34G and 35 are arranged to surround the periphery of the N-type semiconductor region 21 in a manner that, when viewed from above, leaves open gap regions 65 and 66 and multiple intervals Δ44.

[0154] In the semiconductor device 55B of the second embodiment of Embodiment 5 with this configuration, the power supply voltage V1 applied to the P-type semiconductor region group 34G and the power supply voltage V3 applied to the P-type semiconductor region 35 are set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region pair 34 and 35 and the N-type high-voltage isolation region 2.

[0155] Therefore, the semiconductor device 55B in the second aspect of Embodiment 5 provides the same effects as Embodiments 1 and 2.

[0156] In addition, the pair of P-type semiconductor regions 34G and 35, which form the surrounding P-type semiconductor region, include the peripheral regions 61 and 62 and are arranged to surround the periphery of the N-type semiconductor region 21 in a plan view. Therefore, the depletion layer becomes a surrounding depletion layer that encloses the N-type semiconductor region 21.

[0157] Therefore, the semiconductor device 55B, which is the second embodiment of Embodiment 5, has the same effects as the semiconductor device 55A, which is the first embodiment.

[0158] In addition, since the multiple P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G, which forms a group of P-type semiconductor regions for partial surrounding, are arranged discretely from one another, the electric field in the peripheral region 61 of the N-type semiconductor region 21 can be relaxed by local partial depletion layer units corresponding to each of the multiple P-type partial semiconductor regions 44.

[0159] As a result, the semiconductor device 55B, which is the second embodiment of Embodiment 5, can adjust the cathode voltage of the diode D4 by adjusting the spacing Δ44 between adjacent P-type partial semiconductor regions among the multiple P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G, thereby improving the design freedom of the circuit and layout of the semiconductor device 55B.

[0160] In semiconductor device 55B, the first partial surrounding P-type semiconductor region provided in the peripheral region 61 is a group of P-type semiconductor regions 34G consisting of multiple P-type partial semiconductor regions 44, and the second partial surrounding P-type semiconductor region provided in the peripheral region 62 is a single P-type semiconductor region 35.

[0161] In a first modified configuration, the above configuration may be reversed, and a single P-type semiconductor region 34 may be used as the first partially surrounding P-type semiconductor region provided in the peripheral region 61, and a group of P-type semiconductor regions composed of multiple P-type partial semiconductor regions may be used as the second partially surrounding P-type semiconductor region provided in the peripheral region 62.

[0162] In the first modification, a relay wiring for the modification is electrically connected to each of the multiple P-type partial semiconductor regions, and a power supply voltage V3 is supplied from the power supply 13 to the group of P-type semiconductor regions via the relay wiring for the modification. Therefore, in the first modification, the electric field in the peripheral region 62 of the N-type semiconductor region 21 can be relaxed on a local partial depletion layer basis.

[0163] Furthermore, a second modification may be adopted in which both the first and second partial surrounding P-type semiconductor regions are groups of P-type semiconductor regions composed of multiple P-type partial semiconductor regions.

[0164] Thus, the second aspect of Embodiment 5 includes the first and second modifications described above, wherein at least one of the first and second partial surrounding P-type semiconductor regions is a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions.

[0165] <Embodiment 6> (First aspect) Figure 7 is a schematic diagram illustrating the planar structure of a semiconductor device 56A, which is a first embodiment of Embodiment 6 of the present disclosure.

[0166] As shown in the figure, the semiconductor device 56A, which is the first embodiment of Embodiment 6, includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3 as its main components, similar to Embodiments 1 to 4.

[0167] In the following description, components similar to those in Embodiments 1 and 2 shown in Figures 1 and 2 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The focus will be on the characteristic features of the semiconductor device 56A of Embodiment 6.

[0168] The semiconductor device 56A of Embodiment 6 is characterized in that, compared to Embodiments 1 and 2, instead of the P-type semiconductor region 31, it is provided with multiple P-type semiconductor regions 31A and 31B. That is, the P-type semiconductor regions 31A and 31B become the P-type semiconductor regions in the semiconductor device 56A of the first embodiment of Embodiment 6.

[0169] In the semiconductor device 56A, a plurality of P-type semiconductor regions 31A and 31B are provided as a plurality of P-type semiconductor regions that are discretely arranged from each other. That is, the plurality of P-type semiconductor regions in the semiconductor device 56A include a first P-type semiconductor region, which is P-type semiconductor region 31A, and a second P-type semiconductor region, which is P-type semiconductor region 31B.

[0170] Furthermore, the multiple P-type semiconductor regions 31A and 31B are positioned between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the N-type semiconductor region 22 is positioned closer to the N-type high-potential region 3 compared to the N-type semiconductor region 21 and the P-type semiconductor regions 31A and 31B. Also, the P-type semiconductor regions 31A and 31B are positioned between the N-type semiconductor region 21 and the N-type high-potential region 3 when viewed from above.

[0171] P-type semiconductor regions 31A and 31B are selectively and independently provided in the upper layer of the N-type high-voltage isolation region 2. The P-type semiconductor regions 31A and 31B do not have a contact relationship with each other. The P-type impurity concentration of each P-type semiconductor region 31A and 31B is set higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0172] The cross-sectional structures of the P-type semiconductor regions 31A and 31B shown in Figure 7 are, for example, the same as the p shown in Figure 13. + Layer 213 and p + This corresponds to layer 214.

[0173] The entire regions of the P-type semiconductor regions 31A and 31B are, in a plan view, positioned between the N-type semiconductor region 21 and the N-type semiconductor region 22, respectively.

[0174] Of the P-type semiconductor regions 31A and 31B, the P-type semiconductor region 31A is located outside the P-type semiconductor region 31B. That is, the P-type semiconductor region 31A is located closer to the N-type semiconductor region 21 compared to the P-type semiconductor region 31B, and the P-type semiconductor region 31B is located closer to the N-type semiconductor region 22 compared to the P-type semiconductor region 31A.

[0175] Furthermore, the P-type semiconductor region 31A has a first P-type parallel region that is parallel to three sides of the N-type high-potential region 3 when viewed from above. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 7. In addition, the first P-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0176] Thus, the P-type semiconductor region 31A has a first P-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31A. Therefore, the P-type semiconductor region 31A surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0177] Similarly, the P-type semiconductor region 31B has a second P-type parallel region that, when viewed from above, is parallel to three sides of the N-type high-potential region 3. These three sides correspond to the right, left, and bottom sides of the N-type high-potential region 3 shown in Figure 7. Furthermore, the second P-type parallel region has a region that is parallel to a part of the top side of the N-type high-potential region 3.

[0178] Thus, the P-type semiconductor region 31B has a second P-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor regions 31A and 31B. Therefore, the P-type semiconductor region 31B surrounds more than 3 / 4 of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0179] As described above, in the first aspect of Embodiment 6, the P-type semiconductor region has a first P-type parallel region of the P-type semiconductor region 31A and a second P-type parallel region of the P-type semiconductor region 31B.

[0180] As described above, the entire regions of the P-type semiconductor regions 31A and 31B are located between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the first and second P-type parallel regions of the P-type semiconductor regions 31A and 31B are located between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type semiconductor region of the N-type semiconductor region 22 when viewed from above.

[0181] The power supply voltage V1 supplied from power supply 11 is applied to the P-type semiconductor region 31A via wiring L1 and wiring L11, and to the P-type semiconductor region 31B via wiring L1 and wiring L12. Wirings L11 and L12 are wirings branched from node P8 of wiring L1. One end of wiring L11 is electrically connected to node P1 on the P-type semiconductor region 31A, one end of wiring L12 is electrically connected to node P6 on the P-type semiconductor region 31B, and the other ends of wirings L11 and L12 are electrically connected to the intermediate node P8.

[0182] Therefore, in the semiconductor device 56A, which is the first aspect of Embodiment 6, the first voltage, the power supply voltage V1, is commonly applied to the P-type semiconductor regions 31A and 31B, which are the first and second P-type semiconductor regions.

[0183] In the semiconductor device 56A, which is the first embodiment of Embodiment 6, the power supply voltage V1 applied to both the P-type semiconductor regions 31A and 31B is set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor regions 31A and 31B and the N-type high-voltage isolation region 2, respectively.

[0184] Therefore, the depletion layer formed at the interface between the first and second P-type parallel regions of the P-type semiconductor regions 31A and 31B and the N-type high-voltage isolation region 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0185] Therefore, the semiconductor device 56A, which is the first embodiment of Embodiment 6, has the same effects as Embodiments 1 and 2.

[0186] Furthermore, the semiconductor device 56A, which is the first embodiment of Embodiment 6, can gradually mitigate the electric field around the N-type semiconductor region 21 by providing a plurality of P-type semiconductor regions (P-type semiconductor regions 31A and 31B) that are discretely arranged as P-type semiconductor regions.

[0187] The semiconductor device 56A of Embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing first and second P-type semiconductor regions, P-type semiconductor regions 31A and 31B.

[0188] In addition, since the power supply voltage V1, which is the first voltage, is commonly applied to the P-type semiconductor regions 31A and 31B, the semiconductor device 56A of Embodiment 6 can be configured without adding a new power supply.

[0189] (Second aspect) Figure 8 is a schematic diagram illustrating the planar structure of a semiconductor device 56B, which is a second embodiment of Embodiment 6 of the present disclosure.

[0190] As shown in the figure, the semiconductor device 56B, which is the second embodiment of Embodiment 6, includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3 as its main components, similar to the first embodiment of Embodiment 6 shown in Figure 7.

[0191] Hereinafter, components similar to those in the first embodiment of Embodiment 6 shown in Figure 7 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 56B, which is the second embodiment of Embodiment 6.

[0192] The semiconductor device 56B of Embodiment 6 is characterized in that, compared to the first embodiment of Embodiment 6, it is provided with a group of P-type semiconductor regions 31AG and 31BG that constitute a plurality of P-type semiconductor regions, instead of the P-type semiconductor regions 31A and 31B. That is, the group of P-type semiconductor regions 31AG and 31BG become the P-type semiconductor regions in the semiconductor device 56B of the second embodiment of Embodiment 6.

[0193] In the semiconductor device 56B, a plurality of P-type semiconductor regions, namely P-type semiconductor region groups 31AG and 31BG, are provided as a plurality of P-type semiconductor regions that are discretely arranged from each other. That is, the plurality of P-type semiconductor regions in the semiconductor device 56B include a first P-type semiconductor region group, namely P-type semiconductor region group 31AG, and a second P-type semiconductor region group, namely P-type semiconductor region group 31BG.

[0194] In the upper layer of the N-type high-voltage isolation region 2, a P-type semiconductor region group 31AG and a P-type semiconductor region group 31BG are selectively and independently provided.

[0195] The P-type semiconductor region group 31AG is composed of a plurality of P-type partial semiconductor regions 41A that are provided discretely from each other. The P-type semiconductor region group 31BG is composed of a plurality of P-type partial semiconductor regions 41B that are provided discretely from each other. The P-type impurity concentration of each of the plurality of P-type partial semiconductor regions 41A and the plurality of P-type partial semiconductor regions 41B is set higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0196] Furthermore, in the multiple P-type partial semiconductor regions 41A that constitute the P-type semiconductor region group 31AG, there is a gap Δ41A between adjacent P-type partial semiconductor regions 41A, 41A, and in the multiple P-type partial semiconductor regions 41B that constitute the P-type semiconductor region group 31BG, there is a gap Δ41B between adjacent P-type partial semiconductor regions 41B, 41B.

[0197] The P-type semiconductor region group 31AG has a structure similar to the P-type semiconductor region 31A of the first embodiment, except that it is composed of multiple P-type partial semiconductor regions 41A. The P-type semiconductor region group 31BG has a structure similar to the P-type semiconductor region 31B of the first embodiment, except that it is composed of multiple P-type partial semiconductor regions 41B.

[0198] In the P-type semiconductor region group 31AG, a relay wiring 25A is provided that is electrically connected to each of the multiple P-type partial semiconductor regions 41A. The relay wiring 25A is electrically connected to one end of the wiring L11 via node P1.

[0199] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to each of the multiple P-type partial semiconductor regions 41A that constitute the P-type semiconductor region group 31AG via the relay wiring 25A.

[0200] In the P-type semiconductor region group 31BG, relay wiring 25B is provided that is electrically connected to each of the multiple P-type partial semiconductor regions 41B. Relay wiring 25B is electrically connected to one end of wiring L12 via node P6.

[0201] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to each of the multiple P-type partial semiconductor regions 41B that constitute the P-type semiconductor region group 31BG via the relay wiring 25B.

[0202] In the semiconductor device 56B, which is a second embodiment of Embodiment 6, the power supply voltage V1 applied in common to the P-type semiconductor region groups 31AG and 31BG is set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage isolation region 2, respectively.

[0203] Therefore, the depletion layer formed at the interface between the first and second P-type parallel regions of the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage isolation region 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0204] Therefore, the semiconductor device 56B, which is the second aspect of Embodiment 6, provides the same effects as Embodiments 1 and 2.

[0205] Furthermore, in the semiconductor device 56B, which is a second aspect of Embodiment 6, the electric field around the N-type semiconductor region 21 can be gradually reduced by providing a plurality of P-type semiconductor regions (P-type semiconductor region groups 31AG and 31BG) that are discretely arranged as P-type semiconductor regions.

[0206] Furthermore, the semiconductor device 56B of Embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing the first and second P-type semiconductor region groups 31AG and 31BG.

[0207] In addition, since the power supply voltage V1, which is the first voltage, is commonly applied to the P-type semiconductor region groups 31AG and 31BG, the semiconductor device 56B of Embodiment 6 can be configured without adding a new power supply.

[0208] Furthermore, since the multiple P-type partial semiconductor regions 41A in the P-type semiconductor region group 31AG and the multiple P-type partial semiconductor regions 41B in the P-type semiconductor region group 31BG are arranged discretely from each other, the electric field around the N-type semiconductor region 21 can be relaxed at the local partial depletion layer level.

[0209] As a result, the semiconductor device 56B, which is the second aspect of Embodiment 6, has the same effect as the semiconductor device 53 of Embodiment 3 shown in Figure 3 with respect to the P-type semiconductor region groups 31AG and 31BG.

[0210] In addition, the semiconductor device 56B is shown in which both the P-type semiconductor regions 31A and 31B of the first embodiment are replaced with P-type semiconductor region groups 31AG and 31BG.

[0211] In addition to the above configuration, a first modification is possible in which only the P-type semiconductor region 31A of the P-type semiconductor regions 31A and 31B is replaced with the P-type semiconductor region group 31AG, and a second modification is possible in which only the P-type semiconductor region 31B of the P-type semiconductor regions 31A and 31B is replaced with the P-type semiconductor region group 31BG.

[0212] In other words, the second aspect of Embodiment 6 is that at least one of the first and second P-type semiconductor regions is a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions.

[0213] (Third aspect) Figure 9 is a schematic diagram illustrating the planar structure of a semiconductor device 56C, which is a third embodiment of Embodiment 6 of the present disclosure.

[0214] As shown in the figure, the semiconductor device 56C, which is the third aspect of Embodiment 6, includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3 as its main components, similar to the first aspect of Embodiment 6 shown in Figure 7.

[0215] Hereinafter, components similar to those in the first embodiment of Embodiment 6 shown in Figure 7 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 56C, which is the third embodiment of Embodiment 6.

[0216] The semiconductor device 56C of Embodiment 6 is characterized in that, compared to the first embodiment of Embodiment 6, a P-type semiconductor region 33A, which is a completely enclosed P-type semiconductor region, is provided in place of the P-type semiconductor region 31A. That is, the P-type semiconductor region 33A and the P-type semiconductor region 31B become the P-type semiconductor regions in the semiconductor device 56C of the third embodiment.

[0217] The P-type semiconductor region 33A, like the P-type semiconductor region 33 of Embodiment 4, has an inner P-type parallel region 331A formed in the peripheral region 61, an outer P-type parallel region 332A formed in the peripheral region 62, and a connecting region 333A that connects the inner P-type parallel region 331A and the outer P-type parallel region 332A. The inner P-type parallel region 331A has a structure equivalent to the inner P-type parallel region 331 shown in Figure 4, and the outer P-type parallel region 332A has a structure equivalent to the outer P-type parallel region 332 shown in Figure 4.

[0218] The P-type semiconductor region 33A, which is a completely enclosing P-type semiconductor region, is provided so as to completely surround the periphery of the N-type semiconductor region 21, which becomes the first N-type semiconductor region when viewed from above.

[0219] Similar to the P-type semiconductor region 33 in the semiconductor device 54 of Embodiment 4 shown in Figure 4, the entire area of ​​the inner P-type parallel region 331A of the P-type semiconductor region 33A is located between the N-type semiconductor region 21 and the N-type semiconductor region 22. Therefore, the inner P-type parallel region 331A is located between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type semiconductor region of the N-type semiconductor region 22 when viewed from above.

[0220] The power supply voltage V1 supplied from the power supply 11 is applied to the P-type semiconductor region 33 via wiring L1 and wiring L11. That is, node P1 on the P-type semiconductor region 33 is electrically connected to one end of wiring L11.

[0221] The P-type semiconductor region 33A corresponds to the P-type semiconductor region 31A of the first embodiment and has an inner P-type parallel region 331A and an outer P-type parallel region 332A as the first P-type parallel region.

[0222] In the semiconductor device 56C, which is a third aspect of Embodiment 6, the power supply voltage V1 applied to both the P-type semiconductor region 33A and the P-type semiconductor region 31B is set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region 33A and the P-type semiconductor region 31B and the N-type high-voltage isolation region 2, respectively.

[0223] Therefore, the depletion layer formed at the interface between the first and second P-type parallel regions of the P-type semiconductor region 33A and the P-type semiconductor region 31B and the N-type high-voltage isolation region 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0224] Therefore, the semiconductor device 56C, which is the third aspect of Embodiment 6, provides the same effects as Embodiments 1 and 2.

[0225] Furthermore, in the third aspect of Embodiment 6, the semiconductor device 56C can gradually mitigate the electric field around the N-type semiconductor region 21 by providing a plurality of P-type semiconductor regions (P-type semiconductor region 33A and P-type semiconductor region 31B) that are discretely arranged as P-type semiconductor regions.

[0226] The semiconductor device 56C of Embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing the first and second P-type semiconductor regions, P-type semiconductor region 33A and P-type semiconductor region 31B.

[0227] In addition, since the power supply voltage V1, which is the first voltage, is commonly applied to the P-type semiconductor region 33A and the P-type semiconductor region 31B, the semiconductor device 56C of Embodiment 6 can be configured without adding a new power supply.

[0228] Furthermore, since the P-type semiconductor region 33A, which completely encloses the P-type semiconductor region, is provided so as to completely surround the N-type semiconductor region 21 when viewed from above, it has the same effects as the semiconductor device 54 of Embodiment 4.

[0229] Furthermore, in semiconductor device 56C, a first modification is possible in which the P-type semiconductor region 33A is replaced with a group of P-type semiconductor regions composed of multiple P-type partial semiconductor regions, and a second modification is possible in which the P-type semiconductor region 31B is replaced with a group of P-type semiconductor regions 31BG.

[0230] In addition, a third modification is conceivable in which the P-type semiconductor region 31B is replaced with a fully enclosed P-type semiconductor region that surrounds the P-type semiconductor region 33A in a planar view. That is, a configuration in which first and second fully enclosed P-type semiconductor regions are provided that double-enclose the N-type semiconductor region 21 can be considered as a third modification.

[0231] <Embodiment 7> (First aspect) Figure 10 is a schematic diagram illustrating the planar structure of a semiconductor device 57A, which is a first embodiment of Embodiment 7 of the present disclosure.

[0232] As shown in the figure, the semiconductor device 57A, which is the first embodiment of Embodiment 7, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3.

[0233] Hereinafter, components similar to those in the first embodiment of Embodiment 6 shown in Figure 7 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 57A in the first embodiment of Embodiment 7.

[0234] The semiconductor device 57A of the first aspect of Embodiment 7 is characterized in that, compared with the first aspect of Embodiment 6, it further includes a power supply 14 that supplies a power supply voltage V4 which is a fourth voltage. The power supply voltage V4 which is the fourth voltage is set lower than the power supply voltage V2 which is the second voltage. Specifically, assuming the forward voltage drop of the diode D4 is VF, it is set to satisfy {V4 < (V2 - VF)}.

[0235] Note that the magnitude relationship between the power supply voltage V1 and the power supply voltage V4 is arbitrary. That is, the magnitude relationship between the power supply voltage V1 and the power supply voltage V4 can be arbitrarily set within the range that satisfies {V1 < V2, V4 < V2}.

[0236] The power supply voltage V4 which is the fourth voltage is applied to the P-type semiconductor region 31B which is the second P-type semiconductor region via the wiring L6. That is, the node P6 on the P-type semiconductor region 31B is electrically connected to one end of the wiring L6, and the positive electrode of the power supply 14 is connected to the other end of the wiring L6. Note that the negative electrode of the power supply 14 is electrically connected to the ground level which is the reference potential. Also, the power supply voltage V4 from the power supply 14 is not supplied to the P-type semiconductor layer 1.

[0237] In the semiconductor device 57A which is the first aspect of Embodiment 7, the power supply voltage V1 applied to the P-type semiconductor region 31A and the power supply voltage V4 applied to the P-type semiconductor region 31B are set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor regions 31A and 31B and the N-type high-voltage isolation region 2.

[0238] For this reason, the electric field around the N-type semiconductor region 21 which is electrically connected to the cathode of the diode D4 can be relaxed by the depletion layer generated at the interface between the first and second P-type parallel regions of the P-type semiconductor regions 31A and 31B and the N-type high-voltage isolation region 2.

[0239] Therefore, the semiconductor device 57A which is the first aspect of Embodiment 7 exhibits the same effects as those of Embodiment 1 and Embodiment 2.

[0240] Furthermore, the semiconductor device 57A, which is the first embodiment of Embodiment 7, provides the same effects as the semiconductor device 56A, which is the first embodiment of Embodiment 6, by providing a plurality of P-type semiconductor regions (P-type semiconductor regions 31A and 31B) that are discretely arranged as P-type semiconductor regions.

[0241] Furthermore, in the semiconductor device 57A, which is the first embodiment of Embodiment 7, a power supply voltage V1, which is the first voltage, is applied to the P-type semiconductor region 31A, which is the first P-type semiconductor region, and a power supply voltage V4, which is the fourth voltage, is applied to the P-type semiconductor region 31B, which is the second P-type semiconductor region, and the power supplies 11 and 14, which are the first and fourth power supplies, are provided independently of each other. That is, power supply voltages V1 and V4 are independent of each other. For this reason, power supply voltages V1 and V4 can be set individually.

[0242] Therefore, the semiconductor device 57A, which is the first embodiment of Embodiment 7, makes it relatively easy to adjust the electric field distribution around the N-type semiconductor region 21 by gradually mitigating the electric field around the N-type semiconductor region 21 in two stages.

[0243] (Second aspect) Figure 11 is a schematic diagram illustrating the planar structure of a semiconductor device 57B, which is a second embodiment of Embodiment 7 of the present disclosure.

[0244] As shown in the figure, the semiconductor device 57B, which is a second embodiment of Embodiment 7, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3.

[0245] Hereinafter, components similar to those in the second embodiment of Embodiment 6 shown in Figure 8 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 57B in the second embodiment of Embodiment 7.

[0246] The semiconductor device 57B of the second embodiment of Embodiment 7 is characterized in that, similar to the first embodiment of Embodiment 7 shown in Figure 10, it further comprises a power supply 14 which serves as a fourth power supply and supplies a power supply voltage V4 which is a fourth voltage. The power supply voltage V4 is set lower than the power supply voltage V2.

[0247] A fourth voltage, the power supply voltage V4, is applied to the second P-type semiconductor region, the P-type semiconductor region group 31BG, via the wiring L6. That is, node P6 on the P-type semiconductor region group 31BG is electrically connected to one end of wiring L6, and the positive terminal of the power supply 14 is connected to the other end of wiring L6.

[0248] In the semiconductor device 57B, which is a second embodiment of Embodiment 7, the power supply voltage V1 applied to the P-type semiconductor region group 31AG and the power supply voltage V4 applied to the P-type semiconductor region group 31BG are set lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage isolation region 2, respectively.

[0249] Therefore, the depletion layer formed at the interface between the first and second P-type parallel regions of the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage isolation region 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0250] Therefore, the semiconductor device 57B, which is the second embodiment of Embodiment 7, provides the same effects as Embodiments 1 and 2.

[0251] Furthermore, the semiconductor device 57B, which is the second aspect of Embodiment 7, provides the same effects as the semiconductor device 56B, which is the second aspect of Embodiment 6, by providing a plurality of P-type semiconductor regions (P-type semiconductor region groups 31AG and 31BG) that are discretely arranged as P-type semiconductor regions.

[0252] In addition, in the semiconductor device 57B, which is the second aspect of Embodiment 7, a power supply voltage V1 is applied to the P-type semiconductor region group 31AG and a power supply voltage V4 is applied to the P-type semiconductor region group 31BG, and power supplies 11 and 14 are provided independently of each other. Therefore, power supply voltages V1 and V4 can be set individually.

[0253] Therefore, the semiconductor device 57B, which is the second aspect of Embodiment 7, similar to the first aspect of Embodiment 7, allows for relatively easy adjustment of the electric field distribution around the N-type semiconductor region 21 by gradually mitigating the electric field around the N-type semiconductor region 21 in two stages.

[0254] Furthermore, the second aspect of Embodiment 7 is similar to the second aspect of Embodiment 6 in that at least one of the first and second P-type semiconductor regions is a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions.

[0255] (Third aspect) Figure 12 is a schematic diagram illustrating the planar structure of a semiconductor device 57C, which is a third embodiment of Embodiment 7 of the present disclosure.

[0256] As shown in the figure, the semiconductor device 57C, which is a third embodiment of Embodiment 7, mainly includes a P-type semiconductor layer 1, an N-type high-voltage isolation region 2, an N-type high-potential region 3, and a diode region 4 provided on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3.

[0257] Hereinafter, components similar to those in the third aspect of Embodiment 6 shown in Figure 9 will be denoted by the same reference numerals, and their descriptions will be omitted as appropriate. The description will focus on the characteristic features of the semiconductor device 57C in the third aspect of Embodiment 7.

[0258] The semiconductor device 57C of the third embodiment of Embodiment 7 is characterized in that, similar to the first embodiment shown in Figure 10 and the second embodiment shown in Figure 11, it further comprises a power supply 14 which serves as a fourth power supply and supplies a power supply voltage V4 which is a fourth voltage. The power supply voltage V4 is set lower than the power supply voltage V2.

[0259] A power supply voltage V4, which is a fourth voltage, is applied to a P-type semiconductor region 31B, which is a second P-type semiconductor region, via a wiring L6. That is, a node P6 on the P-type semiconductor region 31B is electrically connected to one end of the wiring L6, and the positive electrode of a power supply 14 is connected to the other end of the wiring L6.

[0260] In a semiconductor device 57C, which is a third aspect of Embodiment 7, a power supply voltage V1 applied to a P-type semiconductor region 33A and a power supply voltage V4 applied to a P-type semiconductor region 31B are set lower than a power supply voltage V2 applied to an N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor regions 33A and 31B and an N-type high breakdown voltage isolation region 2.

[0261] For this reason, the electric field around an N-type semiconductor region 21, which is electrically connected to the cathode of a diode D4, can be relaxed by a depletion layer generated at an interface between a first and a second P-type parallel region of the P-type semiconductor region 33A and the P-type semiconductor region 31B and the N-type high breakdown voltage isolation region 2.

[0262] Therefore, the semiconductor device 57C, which is a third aspect of Embodiment 7, exhibits the same effects as those of Embodiment 1 and Embodiment 2.

[0263] Furthermore, the semiconductor device 57C, which is a third aspect of Embodiment 7, exhibits the same effects as those of a semiconductor device 56C, which is a third aspect of Embodiment 6, by providing a plurality of P-type semiconductor regions (P-type semiconductor region 33A and P-type semiconductor region 31B) that are provided separately from each other as P-type semiconductor regions.

[0264] In addition, the semiconductor device 57C, which is a third aspect of Embodiment 7, applies a power supply voltage V1 to the P-type semiconductor region 33A and applies a power supply voltage V4 to the P-type semiconductor region 31B, and the power supply 11 and the power supply 14 are provided independently of each other. That is, the power supply voltage V1 and the power supply voltage V4 are independent of each other. For this reason, the power supply voltage V1 and the power supply voltage V4 can be set individually.

[0265] Therefore, the semiconductor device 57C, which is the third aspect of Embodiment 7, similar to the first and second aspects of Embodiment 7, allows for relatively easy adjustment of the electric field distribution around the N-type semiconductor region 21 by gradually mitigating the electric field around the N-type semiconductor region 21 in two stages.

[0266] In addition, in the third embodiment of Embodiment 7, the first to third modifications are possible as variations of the combination of P-type semiconductor region 33A and P-type semiconductor region 31B, similar to the third embodiment of Embodiment 6.

[0267] <Other> In the embodiment described above, the shape of the N-type high-potential region 3 in plan view is a quadrilateral, but it may also be formed into a polygon with triangles or more sides.

[0268] Furthermore, within the scope of the invention, it is possible to freely combine the embodiments of this disclosure, or to modify or omit the embodiments as appropriate.

[0269] The various aspects of this disclosure are summarized below as an appendix.

[0270] (Note 1) P-type semiconductor layer, An N-type high-potential region provided on the P-type semiconductor layer, An N-type high-voltage isolation region is provided on the P-type semiconductor layer and surrounds the N-type high-potential region in a plan view, A diode region is provided on the P-type semiconductor layer independently of the N-type high-voltage isolation region, and has a diode to which a second voltage higher than a first voltage is supplied to the anode. First and second N-type semiconductor regions are selectively provided in the upper layer of the aforementioned N-type high-voltage isolation region, A semiconductor device comprising a P-type semiconductor region selectively provided in the upper layer of the N-type high-voltage isolation region, to which a first voltage lower than the second voltage is supplied, The N-type impurity concentration in the first and second N-type semiconductor regions is set higher than the N-type impurity concentration in the N-type high-voltage isolation region, and the first and second N-type semiconductor regions and the P-type semiconductor region are provided without any contact relationship with each other. The second N-type semiconductor region is positioned closer to the N-type high-potential region compared to the first N-type semiconductor region and the P-type semiconductor region. The P-type semiconductor region is positioned between the first N-type semiconductor region and the N-type high-potential region in a plan view. The cathode of the diode is electrically connected to the first N-type semiconductor region. The second N-type semiconductor region is electrically connected to the N-type high-potential region. Semiconductor equipment.

[0271] (Note 2) The semiconductor device described in Appendix 1, The aforementioned N-type high-potential region exhibits a polygonal shape with more than one triangle when viewed from above. The first N-type semiconductor region has a first N-type parallel region that is parallel to at least one side of the N-type high-potential region when viewed from above. The second N-type semiconductor region has, in plan view, a second N-type parallel region parallel to at least one side of the N-type high-potential region. The P-type semiconductor region has a P-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region, and the P-type parallel region is positioned between the first N-type parallel region and the second N-type parallel region when viewed from above. Semiconductor equipment.

[0272] (Note 3) A semiconductor device as described in Appendix 1 or Appendix 2, The P-type semiconductor region includes a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions that are provided discretely from each other. The aforementioned semiconductor device is The system further comprises relay wiring that is electrically connected to each of the aforementioned plurality of P-type partial semiconductor regions, The first voltage is applied to each of the plurality of P-type partial semiconductor regions of the P-type semiconductor region group via the relay wiring. Semiconductor device.

[0273] (Appendix 4) A semiconductor device according to Appendix 1 or Appendix 2, In the N-type high breakdown voltage isolation region, the peripheral region of the first N-type semiconductor region includes a first peripheral region on the side approaching the second N-type semiconductor region and a second peripheral region on the side away from the second N-type semiconductor region, The P-type semiconductor region is provided in at least a part of each of the first and second peripheral regions, and includes a surrounding P-type semiconductor region provided so as to surround the first N-type semiconductor region in a plan view. Semiconductor device.

[0274] (Appendix 5) A semiconductor device according to Appendix 4, The surrounding P-type semiconductor region includes a complete surrounding P-type semiconductor region provided so as to surround the periphery of the first N-type semiconductor region without a gap in a plan view. Semiconductor device.

[0275] (Appendix 6) A semiconductor device according to Appendix 4, The surrounding P-type semiconductor region includes a first partial surrounding P-type semiconductor region provided in at least a part of the first peripheral region and a second partial surrounding P-type semiconductor region provided in at least a part of the second peripheral region, and the first and second partial surrounding P-type semiconductor regions are provided discretely from each other, The first voltage is applied to the first partial surrounding P-type semiconductor region, A third voltage lower than the second voltage is applied to the second partial surrounding P-type semiconductor region, Semiconductor device.

[0276] (Appendix 7) A semiconductor device according to Appendix 6, [[ID=…]] Of the first partially surrounding P-type semiconductor region and the second partially surrounding P-type semiconductor region, at least one partially surrounding P-type semiconductor region includes a group of partially surrounding P-type semiconductor regions composed of a plurality of P-type partially semiconductor regions provided discretely from each other. The aforementioned semiconductor device is The system further comprises relay wiring that is electrically connected to each of the aforementioned plurality of P-type partial semiconductor regions, The first voltage or the third voltage is applied to the group of P-type semiconductor regions for partial surrounding via the relay wiring. Semiconductor equipment.

[0277] (Note 8) A semiconductor device described in any of the appendices 1 to 7, The P-type semiconductor region includes a plurality of P-type semiconductor regions that are provided discretely from each other. Semiconductor equipment.

[0278] (Note 9) The semiconductor device described in Appendix 8, The plurality of P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The first voltage is applied in common to the first and second P-type semiconductor regions. Semiconductor equipment.

[0279] (Note 10) The semiconductor device described in Appendix 8, The plurality of P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The first voltage is applied to the first P-type semiconductor region. A fourth voltage lower than the second voltage is applied to the second P-type semiconductor region. The first voltage and the fourth voltage are independent of each other. Semiconductor equipment.

[0280] (Note 11) A semiconductor device as described in any of Appendix 1 to Appendix 10, The N-type high-potential region has a first electrode on its surface for the high-potential side power supply voltage and a second electrode for the high-potential side reference voltage. The charging element further comprises one electrode electrically connected to the first electrode in the N-type high potential region, and the other electrode electrically connected to the second electrode in the N-type high potential region. Semiconductor equipment.

[0281] (Note 12) A semiconductor device described in any of Appendix 1 to Appendix 11, The first and second N-type semiconductor regions and the P-type semiconductor region are each arranged to surround more than half of the outer periphery of the N-type high-potential region when viewed from above. Semiconductor equipment. [Explanation of Symbols]

[0282] 1 P-type semiconductor layer, 2 N-type high-voltage isolation region, 3 N-type high-potential region, 4 diode region, 5 power supply electrode, 6 reference electrode, 11-14 power supply, 21,22 N-type semiconductor region, 31,31A,31B,33,33A,34,35 P-type semiconductor region, 31G,31AG,31BG,34G P-type semiconductor region group, 41,41A,41B,44 P-type partial semiconductor region, 51-54,55A,55B,56A-56C,57A-57C semiconductor device, 61,62 peripheral region, C3 capacitor, D4 diode.

Claims

1. P-type semiconductor layer, An N-type high-potential region provided on the P-type semiconductor layer, An N-type high-voltage isolation region is provided on the P-type semiconductor layer and surrounds the N-type high-potential region in a plan view, A diode region is provided on the P-type semiconductor layer independently of the N-type high-voltage isolation region, and has a diode to which a second voltage higher than a first voltage is supplied to the anode. First and second N-type semiconductor regions are selectively provided in the upper layer of the aforementioned N-type high-voltage isolation region, A semiconductor device comprising a P-type semiconductor region selectively provided in the upper layer of the N-type high-voltage isolation region, to which the first voltage lower than the second voltage is supplied, The N-type impurity concentration in the first and second N-type semiconductor regions is set higher than the N-type impurity concentration in the N-type high-voltage isolation region, and the first and second N-type semiconductor regions and the P-type semiconductor region are provided without any contact relationship with each other. The second N-type semiconductor region is positioned closer to the N-type high-potential region compared to the first N-type semiconductor region and the P-type semiconductor region. The P-type semiconductor region is positioned between the first N-type semiconductor region and the N-type high-potential region in a plan view. The cathode of the diode is electrically connected to the first N-type semiconductor region. The second N-type semiconductor region is electrically connected to the N-type high-potential region. Semiconductor equipment.

2. A semiconductor device according to claim 1, The aforementioned N-type high-potential region exhibits a polygonal shape with more than one triangle when viewed from above. The first N-type semiconductor region has a first N-type parallel region that is parallel to at least one side of the N-type high-potential region when viewed from above. The second N-type semiconductor region has, in plan view, a second N-type parallel region parallel to at least one side of the N-type high-potential region. The P-type semiconductor region has a P-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region, and the P-type parallel region is positioned between the first N-type parallel region and the second N-type parallel region when viewed from above. Semiconductor equipment.

3. A semiconductor device according to claim 1, The P-type semiconductor region includes a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions that are provided discretely from each other. The aforementioned semiconductor device is The system further comprises relay wiring that is electrically connected to each of the aforementioned plurality of P-type partial semiconductor regions, The first voltage is applied to each of the plurality of P-type partial semiconductor regions of the P-type semiconductor region group via the relay wiring. Semiconductor equipment.

4. A semiconductor device according to claim 1, In the N-type high-voltage isolation region, the peripheral region of the first N-type semiconductor region includes a first peripheral region on the side approaching the second N-type semiconductor region and a second peripheral region on the side moving away from the second N-type semiconductor region. The P-type semiconductor region is provided in at least a portion of each of the first and second peripheral regions, and includes a surrounding P-type semiconductor region that surrounds the first N-type semiconductor region when viewed from above. Semiconductor equipment.

5. A semiconductor device according to claim 4, The surrounding P-type semiconductor region includes a completely surrounding P-type semiconductor region that, when viewed from above, completely encloses the periphery of the first N-type semiconductor region without any gaps. Semiconductor equipment.

6. A semiconductor device according to claim 4, The surrounding P-type semiconductor region includes a first partial surrounding P-type semiconductor region provided in at least a part of the first peripheral region and a second partial surrounding P-type semiconductor region provided in at least a part of the second peripheral region, wherein the first and second partial surrounding P-type semiconductor regions are provided discretely from each other. The first voltage is applied to the first partial surrounding P-type semiconductor region. A third voltage lower than the second voltage is applied to the second partial surrounding P-type semiconductor region. Semiconductor equipment.

7. A semiconductor device according to claim 6, Of the first partially surrounding P-type semiconductor region and the second partially surrounding P-type semiconductor region, at least one partially surrounding P-type semiconductor region includes a group of partially surrounding P-type semiconductor regions composed of a plurality of P-type partially semiconductor regions provided discretely from each other. The aforementioned semiconductor device is The system further comprises relay wiring that is electrically connected to each of the aforementioned plurality of P-type partial semiconductor regions, The first voltage or the third voltage is applied to the group of P-type semiconductor regions for partial surrounding via the relay wiring. Semiconductor equipment.

8. A semiconductor device according to any one of claims 1 to 7, The P-type semiconductor region includes a plurality of P-type semiconductor regions that are provided discretely from each other. Semiconductor equipment.

9. A semiconductor device according to claim 8, The plurality of P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The first voltage is applied in common to the first and second P-type semiconductor regions. Semiconductor equipment.

10. A semiconductor device according to claim 8, The plurality of P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The first voltage is applied to the first P-type semiconductor region. A fourth voltage lower than the second voltage is applied to the second P-type semiconductor region. The first voltage and the fourth voltage are independent of each other. Semiconductor equipment.

11. A semiconductor device according to any one of claims 1 to 7, The N-type high-potential region has a first electrode for the high-potential side power supply voltage and a second electrode for the high-potential side reference voltage on its surface. The charging element further comprises one electrode electrically connected to the first electrode in the N-type high potential region, and the other electrode electrically connected to the second electrode in the N-type high potential region. Semiconductor equipment.

12. A semiconductor device according to any one of claims 1 to 7, The first and second N-type semiconductor regions and the P-type semiconductor region are each arranged to surround more than half of the outer periphery of the N-type high-potential region when viewed from above. Semiconductor equipment.

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