Method for manufacturing a semiconductor device and a semiconductor device.

Abstract

To manufacture semiconductor devices with improved avalanche resistance. [Solution] The method for manufacturing a semiconductor device according to this embodiment is to prepare a semiconductor layer having a first main surface and a second main surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, a control electrode provided so as to face the second semiconductor region via an insulating region, and a third semiconductor region of a first conductivity type located between the second main surface and the second semiconductor region, to form a fourth semiconductor region where the impurity concentration of the second conductivity type is a first concentration by ion implanting an impurity of the second conductivity type into the first main surface, to form a fifth semiconductor region where the net impurity concentration of the second conductivity type after compensation between the impurity of the first conductivity type and the impurity of the second conductivity type is a second concentration lower than the first concentration.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] For semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), high avalanche tolerance is desirable. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-101242 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a method for manufacturing a semiconductor device that can produce a semiconductor device with improved avalanche tolerance. [Means for solving the problem]

[0005] The manufacturing method of the semiconductor device according to this embodiment includes a semiconductor layer having a first main surface and a second main surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located above the first semiconductor region, a control electrode provided to face the second semiconductor region via an insulating region, and a third semiconductor region of the first conductivity type located between the second main surface and the second semiconductor region. Prepare a semiconductor layer, ion-implant impurities of the second conductivity type into the first main surface of the semiconductor layer to form a fourth semiconductor region having an impurity concentration of the second conductivity type of a first concentration, and ion-implant impurities of the first conductivity type into the first main surface of the semiconductor layer in an outer peripheral region extending from the side portion of the semiconductor layer to the inside of the semiconductor layer, and after the impurities of the first conductivity type and the impurities of the second conductivity type compensate each other, the net impurity concentration of the second conductivity type is lower than the first concentration. A fifth semiconductor region having a second concentration is formed.

Brief Description of the Drawings

[0006] [Figure 1] It is a plan view of the semiconductor device according to the first embodiment. [Figure 2] It is a bottom view of the semiconductor device according to the first embodiment. [Figure 3] It is a cross-sectional view of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along the line A-A in FIGS. 1 and 2. [Figure 4A] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 4B] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment following FIG. 4A. [Figure 4C] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment following FIG. 4B. [Figure 4D] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment following FIG. 4C. [Figure 4E] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment following FIG. 4D. [Figure 4F]Figure 4E is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 5] This is a plan view of a semiconductor device according to the second embodiment. [Figure 6] This is a bottom view of the semiconductor device according to the second embodiment. [Figure 7] This is a cross-sectional view of the semiconductor device according to the second embodiment, and is a cross-sectional view along the line BB in Figures 5 and 6. [Figure 8] This is a bottom view of a semiconductor device according to Modification 1 of the second embodiment. [Figure 9] This graph shows the evaluation results of the short-circuit withstand capability of semiconductor devices according to the first embodiment, the second embodiment, and the comparative example. [Figure 10A] This is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment. [Figure 10B] This is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment, following Figure 10A. [Figure 10C] Figure 10B is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment. [Figure 11] This is a bottom view of a semiconductor device according to a modified example 2 of the second embodiment. [Figure 12] This is a bottom view of a semiconductor device according to a modified example 3 of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0008] For convenience of explanation, an XYZ orthogonal coordinate system is adopted as shown in FIGS. 1 to 3 and the like. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Also, in the Z-axis direction, the emitter electrode side is also referred to as "up", and the collector electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity.

[0009] Also, in the following description, in order to represent the relative high and low of the impurity concentration in each conductivity type, n - , n, n - , and p + , p, p - notations may be used. That is, n + indicates that the effective n-type impurity concentration is relatively higher than n, and n - indicates that the effective n-type impurity concentration is relatively lower than n. Also, p + indicates that the effective p-type impurity concentration is relatively higher than p, and p - indicates that the effective p-type impurity concentration is relatively lower than p. In the present application, the notation "effective p-type (n-type) impurity concentration" means the net p-type (n-type) impurity concentration after those impurities have compensated for each other when both p-type impurities and n-type impurities are included in each region. On the other hand, in the present application, the mere notation "p-type (n-type) impurity concentration" means the p-type (n-type) impurity concentration before those impurities compensate for each other even when both p-type impurities and n-type impurities are included in each region. The n-type, n + -type and n - -type are an example of the first conductivity type in the claims. The p-type, p + -type and p - -type are an example of the second conductivity type in the claims. In the following description, the n-type and the p-type may be reversed. That is, the first conductivity type may be p-type.

[0010] Furthermore, the impurity concentration in the semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS). The relative levels of impurity concentrations can also be determined, for example, from the carrier concentrations obtained by scanning capacitance microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the semiconductor region can be measured, for example, by surface and cross-sectional analysis using a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscope (SEM).

[0012] (First Embodiment) The semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 to 3. Figure 1 is a plan view of the semiconductor device 1 according to the first embodiment. Figure 2 is a bottom view of the semiconductor device 1 according to the first embodiment. Figure 3 is a cross-sectional view of the semiconductor device 1 according to the first embodiment, and is a cross-sectional view along line AA in Figures 1 and 2. Note that the emitter electrode 12 is omitted in Figure 1, and the collector electrode 11 is omitted in Figure 2.

[0013] The semiconductor device 1 is, for example, an IGBT. In this embodiment, the case in which the semiconductor device 1 is a vertical IGBT having a trench gate structure will be described as an example. However, the semiconductor device 1 may also be a vertical IGBT having a planar gate structure or the like.

[0014] As shown in Figure 3, the semiconductor device 1 according to this embodiment comprises a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, a gate electrode 13, and an insulating region 30.

[0015] The semiconductor layer 2 has a lower surface 2a, an upper surface 2b opposite to the lower surface 2a, and a side portion 2c. The lower surface 2a and the upper surface 2b are examples of the first and second main surfaces in the claims, respectively.

[0016] Furthermore, the semiconductor layer 2 has an outer peripheral region OA that extends inward from the side portion 2c of the semiconductor layer 2, and an inner region IA that is inside the outer peripheral region OA. The inner region IA is the main path for current when the semiconductor device 1 is operating, and is also called the cell region. In Figures 1 to 3, the symbol B1 represents the boundary between the outer peripheral region OA and the inner region IA. As shown in Figures 1 and 2, the outer peripheral region OA, located outside the boundary B1, surrounds the inner region IA, located inside the boundary B1.

[0017] As shown in Figure 3, the semiconductor layer 2 includes, for example, an n-base region 21, a buffer region 22, a p-base region 23, an emitter region 24, a collector region 25, a low-concentration region 27, and a guard ring region 28. Details of these regions will be described later.

[0018] The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity, and for example, boron (B) can be used as the p-type impurity.

[0019] The collector electrode 11 functions as the collector electrode of the IGBT. The collector electrode 11 is provided on the lower surface 2a of the semiconductor layer 2 and is in contact with the collector region 25 and the low-concentration region 27. The collector electrode 11 is an example of the first electrode in the claims. The collector electrode 11 is made of a material containing at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0020] The emitter electrode 12 functions as the emitter electrode of the IGBT. The emitter electrode 12 is provided on the upper surface 2b of the semiconductor layer 2 and is in contact with the p-base region 23, the emitter region 24, and the guard region. The emitter electrode 12 is an example of the second electrode in the claims. The emitter electrode 12 is made of a material that includes at least one of the following: aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0021] The gate electrode 13 functions as the gate electrode of the IGBT. The gate electrode 13 is positioned facing the p-base region 23 via an insulating region 30. In this embodiment, the gate electrode 13 is positioned within the p-base region 23 via the insulating region 30 and is electrically insulated from the emitter electrode 12 and the semiconductor layer 2 by the insulating region 30. The gate electrode 13 is an example of a control electrode in the claims. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the p-base region 23, and carriers flow between the n-base region 21 and the emitter region 24. This turns the IGBT ON.

[0022] The insulating region 30 is provided so as to cover the upper surface of the gate electrode 13 and the side walls of the multiple trenches provided on the upper surface 2b of the semiconductor layer 2. The insulating region 30 is an insulating film containing, for example, silicon oxide or silicon nitride.

[0023] Next, we will describe the details of each region provided within semiconductor layer 2.

[0024] As shown in Figure 3, the n-base region 21 functions as the n-base region (drift region) of the IGBT. The n-base region 21 is located above the buffer region 22 (above the collector electrode 11). The n-base region 21 is an example of the first semiconductor region in the claims. The n-base region 21 is, for example, n - This is a semiconductor region of a certain type. The effective n-type impurity concentration in the n-base region 21 is, for example, 1 × 10⁻⁶. 12 cm -3The above 1 x 10 15 cm -3 The following applies:

[0025] The buffer region 22 functions as a buffer region of the IGBT. The buffer region 22 is located between the n-base region 21 and the collector region 25. The buffer region 22 is an example of the sixth semiconductor region in the claims. The buffer region 22 is, for example, n + This is a semiconductor region of a certain shape. That is, the n-type impurity concentration in buffer region 22 is higher than the n-type impurity concentration in n-base region 21. Also, the effective n-type impurity concentration in buffer region 22 is higher than the effective n-type impurity concentration in n-base region 21. The effective n-type impurity concentration in buffer region 22 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following applies:

[0026] As shown in Figure 3, the buffer region 22 comprises a first portion 22a located within the outer region OA and a second portion 22b located within the inner region IA. The first portion 22a is located above the low-concentration region 27, and the second portion 22b is located above the collector region 25.

[0027] In this embodiment, the concentration of n-type impurities in the first portion 22a is equal to the concentration of n-type impurities in the second portion 22b. That is, the effective concentration of n-type impurities in the first portion 22a is equal to the effective concentration of n-type impurities in the second portion 22b. However, the concentration of n-type impurities in the first portion 22a may be higher than the concentration of n-type impurities in the second portion 22b. In this case, the effective concentration of n-type impurities in the first portion 22a will be higher than the effective concentration of n-type impurities in the second portion 22b.

[0028] Note that the buffer region 22 does not necessarily have to be provided. In this case, for example, the n-base region 21 may also be provided in the position of the buffer region 22. Alternatively, the n-base region 21 does not necessarily have to be provided. In this case, for example, the buffer region 22 may also be provided in the position of the n-base region 21. In this case, the buffer region 22 is an example of the first semiconductor region in the claims.

[0029] The p-base region 23 functions as the p-base region of the IGBT. The p-base region 23 is located above the n-base region 21. The p-base region 23 is an example of the second semiconductor region in the claims. The p-base region 23 is, for example, a p-type semiconductor region. The effective p-type impurity concentration of the p-base region 23 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 19 cm -3 The following applies. As shown in Figure 1, the p-base region 23 extends in the Y-axis direction. In the example shown in Figure 3, the p-base region 23 has a third portion located below the emitter region 24 and a fourth portion extending from the third portion toward the upper surface 2b of the semiconductor layer 2 and penetrating the emitter region 24. The fourth portion is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. The effective p-type impurity concentration of the fourth portion may be higher than the effective p-type impurity concentration of the third portion.

[0030] The emitter region 24 functions as the emitter region of the IGBT. The emitter region 24 is located above the p-base region 23. The emitter region 24 is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. The emitter region 24 is an example of the third semiconductor region in the claims. As shown in Figure 1, the emitter region 24 extends in the Y-axis direction. The emitter region 24 is, for example, n + This is a semiconductor region of a certain type. The effective n-type impurity concentration in the emitter region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0031] The collector region 25 functions as the collector region of the IGBT. As shown in Figure 3, the collector region 25 is located between the collector electrode 11 and the n-base region 21, more specifically between the collector electrode 11 and the buffer region 22. The collector region 25 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The collector region 25 is an example of the fourth semiconductor region in the claims. The collector region 25 is, for example, a p-type semiconductor region. The p-type impurity concentration in the collector region 25 is the first concentration. The effective p-type impurity concentration in the collector region 25 is, for example, 5 × 10⁻¹⁰ 17 cm -3 It is to that extent.

[0032] The low-concentration region 27 is located within the outer peripheral region OA of the semiconductor layer 2. As shown in Figure 2, the low-concentration region 27 is located surrounding the collector region 25. As shown in Figure 3, the low-concentration region 27 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The low-concentration region 27 is an example of the fifth semiconductor region in the claims. The low-concentration region 27 contains n-type impurities and p-type impurities. The p-type impurity concentration in the low-concentration region 27 is, for example, the same as the first concentration of p-type impurities in the collector region 25. On the other hand, the low-concentration region 27 contains, for example, p - This is a semiconductor region of a certain type. That is, the effective p-type impurity concentration in the low-concentration region 27 is a second concentration that is lower than the first concentration. The second concentration is, for example, 1 × 10⁻⁶ 17 cm -3 It is to that extent.

[0033] The values ​​of the first and second concentrations mentioned above are merely examples, and in other embodiments, they may vary by about one to two orders of magnitude.

[0034] Furthermore, as will be described later, the collector region 25 and the low-concentration region 27 are formed by first forming a p-type semiconductor region (p-region 250) on the lower surface 2a of the semiconductor layer 2, and then counter-doping the lower surface 2a of the semiconductor layer 2 in the outer peripheral region OA with n-type impurities. Therefore, the n-type impurity concentration in the low-concentration region 27 is higher than the n-type impurity concentration in the collector region 25.

[0035] In this embodiment, as shown in Figures 1 and 3, a guard ring region 28 is provided. The guard ring region 28 is provided within the outer peripheral region OA of the semiconductor layer 2. The guard ring region 28 is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12. Also, as shown in Figure 1, the guard ring region 28 is in contact with the end of the p-base region 23 in the Y-axis direction. The guard ring region 28 is, for example, a p-type semiconductor region. The effective p-type impurity concentration of the guard ring region 28 is, for example, 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 19 cm -3 The following is true: By providing a guard ring region 28, it is possible to improve the withstand voltage of the semiconductor device 1.

[0036] In the example shown in Figure 3, both the low-concentration region 27 and the guard ring region 28 are located within the outer region OA. On the other hand, neither the low-concentration region 27 nor the guard ring region 28 are located within the inner region IA. In other words, the inner ends of the low-concentration region 27 and the guard ring region 28 coincide and are both located on boundary B1. However, the inner ends of the low-concentration region 27 and the guard ring region 28 do not necessarily have to coincide. That is, the inner end of the low-concentration region 27 may be located inside or outside the inner end of the guard ring region 28.

[0037] Although not shown in the figures, the semiconductor device 1 may further include a field plate electrode (FP electrode) provided within the semiconductor layer 2 via an insulating region. The FP electrode is electrically insulated from the semiconductor layer 2 by the insulating region and is electrically connected to the emitter electrode 12. By providing such an FP electrode, when the IGBT is in the off state, a depletion layer extends from the FP electrode to the surrounding n-base region 21 due to the voltage applied between the collector electrode 11 and the emitter electrode 12. This depletion layer connects with the depletion layer of the adjacent FP electrode, making it possible to improve the breakdown voltage of the semiconductor device 1.

[0038] Furthermore, the configuration of the semiconductor device 1 shown in Figures 1 to 3 is just one example, and this embodiment is not limited thereto. For example, the number of gate electrodes 13 extending in the Y-axis direction, i.e., the number of insulating regions 30, may be more or less than that of the example in Figure 1. Also, gate pads may be provided on the upper surface 2b of the semiconductor layer 2.

[0039] As described above, the semiconductor device 1 according to the first embodiment includes a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, an n-base region 21 of a first conductivity type, a p-base region 23 of a second conductivity type, a gate electrode 13, an emitter region 24 of a first conductivity type, a collector region 25 of a second conductivity type, and a low-concentration region 27 of a second conductivity type. The semiconductor layer 2 has a lower surface 2a and an upper surface 2b. The collector electrode 11 is provided on the lower surface 2a of the semiconductor layer 2. The emitter electrode 12 is provided on the upper surface 2b of the semiconductor layer 2. The n-base region 21 is provided within the semiconductor layer 2. The p-base region 23 is provided within the semiconductor layer 2 and is located above the n-base region 21. The gate electrode 13 is provided facing the p-base region 23 via an insulating region 30. The emitter region 24 is provided within the semiconductor layer 2 and is located above the p-base region 23 and is electrically connected to the emitter electrode 12. The collector region 25 is provided within the semiconductor layer 2, located between the collector electrode 11 and the n-base region 21, electrically connected to the collector electrode 11, and has a p-type impurity concentration of a first concentration. The low-concentration region 27 is provided within the outer peripheral region OA, which extends from the side portion 2c of the semiconductor layer 2 to the inside of the semiconductor layer 2, and is electrically connected to the collector electrode 11. The low-concentration region 27 contains n-type and p-type impurities, has a p-type impurity concentration of a first concentration, and has a second concentration where the net p-type impurity concentration after compensation between the n-type and p-type impurities is lower than the first concentration.

[0040] In this embodiment, the provision of a low-concentration region 27 improves the avalanche tolerance of the semiconductor device 1.

[0041] <Method for manufacturing semiconductor device 1> Next, an example of a manufacturing method for the semiconductor device 1 according to this embodiment will be described with reference to Figures 4A to 4F. Figures 4A to 4F are cross-sectional views illustrating an example of the manufacturing process for the semiconductor device 1 according to the first embodiment. Note that in Figures 4A to 4F, the portion of the p-base region 23 that penetrates the emitter region 24 (the fourth portion) is omitted.

[0042] First, as shown in Figure 4A, a semiconductor layer 2 is prepared, which has a lower surface 2a and an upper surface 2b opposite to the lower surface 2a. The semiconductor layer 2 includes a gate electrode 13, an n-base region 21, a p-base region 23, an emitter region 24, a guard ring region 28, and an insulating region 30.

[0043] Next, as shown in Figure 4B, a buffer region 22 is formed below the n-base region 21 by ion implanting n-type impurities into the lower surface 2a of the semiconductor layer 2. The n-type impurities used at this time are, for example, at least one of phosphorus (P) and arsenic (As). The concentration of n-type impurities in the buffer region 22 is higher than the concentration of n-type impurities in the n-base region 21.

[0044] Next, as shown in Figure 4C, a p-type impurity is ion-implanted into the lower surface 2a of the semiconductor layer 2 to form a p-type region 250. The p-type impurity used at this time is, for example, boron (B). The p-type region 250 is an example of the fourth semiconductor region in the claims. The p-type region 250 is, for example, a p-type semiconductor region. The concentration of the p-type impurity in the formed p-type region 250 is the first concentration.

[0045] Next, as shown in Figure 4D, a resist 41 is formed on a portion of the lower surface 2a of the semiconductor layer 2. More specifically, after forming a resist over the entire lower surface 2a of the semiconductor layer 2, the portion of the resist located in the outer peripheral region OA is removed by photolithography or the like. As a result, the resist 41 is formed on the lower surface 2a of the semiconductor layer 2 in the inner region IA, excluding the outer peripheral region OA.

[0046] Next, as shown in Figure 4E, a low-concentration region 27 is formed by ion implanting (counter-doping) n-type impurities into the lower surface 2a of the semiconductor layer 2. More specifically, the low-concentration region 27 is formed by ion implanting n-type impurities into the outer peripheral region OA of the lower surface 2a of the semiconductor layer 2 that is not covered by the resist 41. The n-type impurities used at this time are, for example, at least one of phosphorus (P) and arsenic (As). The p-type impurity concentration in the low-concentration region 27 is the first concentration. On the other hand, the effective p-type impurity concentration in the low-concentration region 27 is the second concentration, which is lower than the first concentration. Through this process, a collector region 25 is formed in the portion of the p-region 250 that is covered by the resist 41. Note that the n-type impurity concentration in the low-concentration region 27 is higher than the n-type impurity concentration in the collector region 25.

[0047] In addition, during the process of forming the low-concentration region 27, some n-type impurities may diffuse into the buffer region 22. Therefore, if the buffer region 22 is divided into a first portion 22a located within the outer region OA and a second portion 22b located within the inner region IA, the concentration of n-type impurities in the first portion 22a may be higher than the concentration of n-type impurities in the second portion 22b.

[0048] Next, remove the resist 41 as shown in Figure 4F.

[0049] Subsequently, although not shown in the diagram, a collector electrode 11 and an emitter electrode 12 are formed on the lower surface 2a and upper surface 2b of the semiconductor layer 2, respectively.

[0050] The semiconductor device 1 is manufactured through the above process.

[0051] As described above, in the method for manufacturing the semiconductor device 1 according to the first embodiment, a semiconductor layer 2 is prepared, which has a lower surface 2a and an upper surface 2b, and includes an n-base region 21 of a first conductivity type, a p-base region 23 of a second conductivity type located above the n-base region 21, a gate electrode 13 provided so as to face the p-base region 23 via an insulating region 30, and an emitter region 24 of a first conductivity type located between the upper surface 2b and the p-base region 23 of the semiconductor layer 2. P-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer 2 to form a p-region 250 where the p-type impurity concentration is a first concentration, and n-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer 2 in the outer peripheral region OA of the semiconductor layer 2 to form a low-concentration region 27 where the net p-type impurity concentration after compensation between the n-type and p-type impurities is a second concentration lower than the first concentration.

[0052] According to the manufacturing method of the semiconductor device 1 of this embodiment, a low-concentration region 27 can be formed in the outer peripheral region OA, where the effective p-type impurity concentration is lower than that of the collector region 25. Therefore, a semiconductor device 1 with improved avalanche tolerance can be manufactured.

[0053] Furthermore, in the manufacturing method of this embodiment, after forming the p region 250, a low-concentration region 27 is formed by ion implanting n-type impurities into the outer peripheral region OA (counter-doping). Forming the low-concentration region 27 involves forming a resist on the lower surface 2a of the semiconductor layer 2, removing the portion of the resist located in the outer peripheral region OA, ion implanting n-type impurities into the lower surface 2a of the semiconductor layer 2, and removing the remaining portion of the resist (resist 41). This avoids performing photolithography or the like in the inner region IA, and prevents the occurrence of regions with a lower effective p-type impurity concentration (pattern defects) in unintended locations in the collector region 25 than in the collector region 25, due to dust adhesion or residual resist in the inner region IA. As a result, it is possible to suppress the decrease in the short-circuit withstand capability of the semiconductor device 1 due to pattern defects in the collector region 25.

[0054] Furthermore, by intentionally forming a region with a low effective p-type impurity concentration in the collector region 25, it is possible to increase the switching speed of the semiconductor device 1 while suppressing a decrease in short-circuit withstand capability. The following describes such a case as a second embodiment.

[0055] (Second Embodiment) The semiconductor device 1A according to the second embodiment will be described with reference to Figures 5 to 7. Figure 5 is a plan view of the semiconductor device 1A according to the second embodiment. Figure 6 is a bottom view of the semiconductor device 1A according to the second embodiment. Figure 7 is a cross-sectional view of the semiconductor device 1A according to the second embodiment, and is a cross-sectional view along the BB line in Figures 5 and 6. Note that the emitter electrode 12 is omitted in Figure 5, and the collector electrode 11 is omitted in Figure 6. One of the differences between this embodiment and the first embodiment is the presence of a low-concentration region 26. The following description of this embodiment will focus on the differences from the first embodiment.

[0056] As shown in Figures 5 to 7, the semiconductor device 1A further comprises a low-concentration region 26. The low-concentration region 26 is provided within the semiconductor layer 2 so as to be surrounded by a collector region 25. That is, collector regions 25 are provided on both sides of the low-concentration region 26 along the X-axis direction, and collector regions 25 are provided on both sides of the low-concentration region 26 along the Y-axis direction. The low-concentration region 26 is separated from the low-concentration region 27 by the collector region 25. The low-concentration region 26 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11. The low-concentration region 26 is an example of the seventh semiconductor region in the claims. The low-concentration region 27 contains n-type impurities and p-type impurities. The p-type impurity concentration in the low-concentration region 27 is, for example, the same as the first concentration of p-type impurities in the collector region 25. On the other hand, the low-concentration region 26 contains, for example, p - This is a semiconductor region of a certain type. That is, the effective p-type impurity concentration in the low-concentration region 26 is a third concentration that is lower than the first concentration. The third concentration is, for example, 1 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 It is less than.

[0057] As will be described later, the low-concentration region 26 is formed by counter-doping the p-region 250 with n-type impurities. Therefore, the n-type impurity concentration in the low-concentration region 26 is higher than the n-type impurity concentration in the collector region 25.

[0058] As shown in Figure 7, in this embodiment, the buffer region 22 comprises a first portion 22a located within the outer peripheral region OA, and a second portion 22b and a fifth portion 22c located within the inner region IA. The first portion 22a is located above the low-concentration region 27, the second portion 22b is located above the collector region 25, and the fifth portion 22c is located above the low-concentration region 26.

[0059] In this embodiment, the n-type impurity concentration in the fifth portion 22c is equal to the n-type impurity concentration in the second portion 22b. That is, the effective n-type impurity concentration in the fifth portion 22c is equal to the effective n-type impurity concentration in the second portion 22b. However, the n-type impurity concentration in the fifth portion 22c may be higher than the n-type impurity concentration in the second portion 22b. In this case, the effective n-type impurity concentration in the fifth portion 22c will be higher than the effective n-type impurity concentration in the second portion 22b.

[0060] As shown in Figures 5 and 6, in this embodiment, the low-concentration region 26 is located at the center of the inner region IA, i.e., at the center of the collector region 25.

[0061] The low-density region 26 may be located at a location other than the center of the inner region IA. Figure 8 is a bottom view of a semiconductor device 1B according to modification 1 of the second embodiment. In Figure 8, the reference numeral B2 indicates a position that is one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA. In the example in Figure 8, the low-density region 26 is not located at the center of the inner region IA. However, the low-density region 26 is located in the region inside the boundary B2 (hereinafter also referred to as the "cell center") and is not provided in the region between the boundary B1 and the boundary B2 (hereinafter also referred to as the "cell edge"). In other words, the low-density region 26 is located at a distance of one-quarter or more of the width d of the inner region IA from the boundary B1. More specifically, the low-density region 26 is located at a distance of one-quarter or more of the length of the inner region IA in the X-axis direction from the boundary B1, and at a distance of one-quarter or more of the length of the inner region IA in the Y-axis direction from the boundary B1.

[0062] Furthermore, in the example shown in Figure 8, the planar shape of the inner region IA was a square. However, it is not limited to this, and the planar shape of the inner region IA may also be a rectangle. In this case as well, the low-density region 26 is provided so as to be at least one-quarter of the length of the inner region IA in the X-axis direction from the boundary B1, and at least one-quarter of the length of the inner region IA in the Y-axis direction from the boundary B1.

[0063] In the examples in Figures 6 and 8, the width of the low-density region 26 is at least 1 / 60th of the width of the semiconductor layer 2. More specifically, the length of the low-density region 26 in the X-axis and Y-axis directions is at least 1 / 60th of the larger of the X-axis and Y-axis lengths of the semiconductor layer 2.

[0064] Furthermore, in the examples in Figures 6 and 8, the planar shape of the low-concentration region 26 is circular. However, the planar shape of the low-concentration region 26 is arbitrary and may be rectangular, polygonal, or other shapes.

[0065] Because a collector region 25, a low-concentration region 26, and a low-concentration region 27 are provided, the effective p-type impurity concentration along the X-axis and Y-axis increases from the low-concentration region 26 to the collector region 25, and then decreases from the collector region 25 to the low-concentration region 27.

[0066] In this embodiment, the second concentration, which is the effective p-type impurity concentration in the low-concentration region 27, is equal to the third concentration, which is the effective p-type impurity concentration in the low-concentration region 26. The second concentration may be lower than the third concentration.

[0067] The above-mentioned third concentration value is merely an example, and in other embodiments, it may vary by about one to two orders of magnitude.

[0068] Furthermore, the configuration of the semiconductor device 1A shown in Figures 6 to 8 is just one example, and this embodiment is not limited thereto. For example, in the examples in Figures 6 and 8, the low-concentration region 26 is located below the gate electrode 13. However, it is not limited to this, and the low-concentration region 26 may be located in a place other than below the gate electrode 13. In other words, the positional relationship between the low-concentration region 26 and the gate electrode 13 is arbitrary.

[0069] In this embodiment, the low-density region 26 is arranged so as to be surrounded by the collector region 25. This suppresses the amount of holes injected from the collector region 25 to the n-base region 21, thereby reducing the switching loss of the semiconductor device 1A. Here, switching loss refers to the power loss that occurs when the semiconductor device 1A is turned on or off. According to this embodiment, because the low-density region 26 is surrounded by the collector region 25, the amount of holes injected is suppressed more effectively than when it is arranged around the collector region 25. Therefore, according to this embodiment, the switching of the semiconductor device 1A can be increased in speed.

[0070] Furthermore, in this embodiment, the p-type impurity concentration in the low-concentration region 27 is equal to the p-type impurity concentration in the low-concentration region 26. This allows the low-concentration region 26 and the low-concentration region 27 to be formed simultaneously, as will be described later. Note that the p-type impurity concentration in the low-concentration region 27 may be lower than the p-type impurity concentration in the low-concentration region 26. This further improves the avalanche tolerance of the semiconductor device 1A.

[0071] Furthermore, in this embodiment, the low-concentration region 26 is located at the center of the inner region IA on the lower surface 2a of the semiconductor layer 2. This reduces switching losses at the center of the inner region IA where the current density is high, and enables efficient and high-speed switching of the semiconductor device 1A.

[0072] Furthermore, the low-concentration region 26 is located at a distance of at least one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA. This improves the short-circuit withstand capability of the semiconductor device 1A. This effect will be explained in detail below with reference to Figure 9. Figure 9 is a graph showing the evaluation results of the short-circuit withstand capability of semiconductor devices according to the first embodiment, the second embodiment, and the comparative example.

[0073] The horizontal axis in Figure 9 represents the diameter and location of the low-density region 26 in each semiconductor device used for evaluating short-circuit withstand capability. "None" indicates that no low-density region 26 is provided. "Small," "Medium," and "Large" indicate that the diameter of the low-density region 26 is 1 / 300, 1 / 100, and 1 / 60 of the width of the semiconductor layer 2, respectively. "Cell Center" indicates that the low-density region 26 is located in the area inside boundary B2 in Figure 8 (cell center), that is, the low-density region 26 is at least one-quarter of the width d of the inner region IA from boundary B1 between the outer region OA and the inner region IA. "Cell Edge" indicates that the low-density region 26 is located in the area between boundary B1 and boundary B2 (cell edge), that is, the low-density region 26 is not at least one-quarter of the width d of the inner region IA from boundary B1. The semiconductor device 1 according to the first embodiment corresponds to the "None" case in Figure 9. Furthermore, semiconductor device 1A according to the second embodiment and semiconductor device 1B according to modification 1 of the second embodiment both correspond to the "center of the cell" and "large" cases in Figure 9. The vertical axis in Figure 9 represents the gate-emitter voltage applied to each semiconductor device. The cross marks (×) in the graph represent the gate-emitter voltage when the semiconductor device was destroyed, and the circles (○) represent the gate-emitter voltage when the semiconductor device was not destroyed.

[0074] As shown in Figure 9, when the low-concentration region 26 is located in the "center of the cell," the short-circuit withstand capability of the semiconductor device is higher than when it is located at the "end of the cell," regardless of the size of the low-concentration region 26. More specifically, when it is in the "center of the cell" and "small," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "small," when it is in the "center of the cell" and "medium," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "medium," and when it is in the "center of the cell" and "large," the short-circuit withstand capability is higher than when it is at the "end of the cell" and "large." Therefore, by having the low-concentration region 26 located at least one-quarter of the width d of the inner region IA from the boundary B1 between the outer region OA and the inner region IA, the short-circuit withstand capability of the semiconductor device 1A can be improved.

[0075] As shown in Figure 9, when the low-concentration region 26 is located in the center of the cell and is large, the short-circuit withstand capability of the semiconductor device appears to be lower compared to when it is located in the center of the cell and is small, or in the center of the cell and is medium. However, although not shown in the figure, the failure mode of the semiconductor device changes when the low-concentration region 26 is located in the center of the cell and is large. More specifically, when the low-concentration region 26 is located in the center of the cell and is small, or in the center of the cell and is medium, the failure mode of the semiconductor device was failure at shutdown. On the other hand, when the low-concentration region 26 is located in the center of the cell and is large, the failure mode of the semiconductor device was BT (Bias Temperature) failure, which is thermal failure after being turned off. Therefore, when the low-concentration region 26 is located in the center of the cell, the short-circuit withstand capability of the semiconductor device 1A can be further improved by ensuring that the width of the low-concentration region 26 is 1 / 60th or more of the width of the semiconductor layer 2.

[0076] <Manufacturing method for semiconductor device 1A> Next, with reference to Figures 10A to 10C, an example of a manufacturing method for the semiconductor device 1A according to this embodiment will be described, focusing on the differences from the first embodiment. Figures 10A to 10C are cross-sectional views illustrating an example of the manufacturing process for the semiconductor device 1A according to the second embodiment. Note that in Figures 10A to 10C, the portion of the p-base region 23 that is in contact with the emitter electrode 12 (the fourth portion) is omitted.

[0077] After the step of forming the p region 250 as described with reference to Figure 4C, a resist 41A is formed on a part of the lower surface 2a of the semiconductor layer 2, as shown in Figure 10A. More specifically, after forming the resist on the lower surface 2a of the semiconductor layer 2, the portion of the resist located in the outer peripheral region OA and the opening H portion which will later form the low-concentration region 26 are removed by photolithography or the like. This forms the resist 41A shown in Figure 10A.

[0078] Next, as shown in Figure 10B, low-concentration regions 26 and 27 are formed by ion implantation (counter-doping) of n-type impurities into the lower surface 2a of the semiconductor layer 2. More specifically, low-concentration regions 26 and 27 are formed by ion implantation of n-type impurities into the outer peripheral region OA and the opening H of the lower surface 2a of the semiconductor layer 2 that are not covered by the resist 41A. The n-type impurities used at this time are, for example, at least one of phosphorus (P) and arsenic (As). The p-type impurity concentration in both low-concentration regions 26 and 27 is the first concentration. On the other hand, the effective p-type impurity concentration in low-concentration region 26 is a third concentration lower than the first concentration, and the effective p-type impurity concentration in low-concentration region 27 is a second concentration lower than the first concentration. Through this process, a collector region 25 is formed in the portion of the p-region 250 that is covered by the resist 41A. Furthermore, the n-type impurity concentrations in both the low-concentration region 26 and the low-concentration region 27 are higher than the n-type impurity concentrations in the collector region 25.

[0079] In addition, during the process of forming the low-concentration regions 26 and 27, some n-type impurities may diffuse into the buffer region 22. Therefore, if the buffer region 22 is divided into a first portion 22a located within the outer peripheral region OA, a second portion 22b located within the inner region IA, and a fifth portion 22c located above the low-concentration region 26, the n-type impurity concentration in the first portion 22a may be higher than that in the second portion 22b and the fifth portion 22c.

[0080] The subsequent steps are the same as in the first embodiment.

[0081] As described above, in the manufacturing method of the semiconductor device 1A according to the second embodiment, after forming the p region 250, n-type impurities are ion-implanted into a part of the lower surface 2a of the semiconductor layer 2 within the inner region IA to form a low-concentration region 26 surrounded by the collector region 25, where the net p-type impurity concentration after the n-type and p-type impurities compensate for each other is a third concentration lower than the first concentration.

[0082] This makes it possible to manufacture a semiconductor device 1A with high-speed switching.

[0083] Furthermore, according to the manufacturing method of the semiconductor device 1A of this embodiment, the low-concentration region 26 can be formed together with the low-concentration region 27. In this case, the second concentration becomes equal to the third concentration.

[0084] Furthermore, the low-concentration region 26 may be formed before or after the low-concentration region 27. This allows the second concentration to be different from the third concentration. For example, by making the second concentration lower than the third concentration, a semiconductor device 1A with improved avalanche tolerance can be manufactured.

[0085] Furthermore, multiple low-concentration regions 26 may be provided. The semiconductor device 1C according to Modification 2 of the Second Embodiment will now be described with reference to Figure 11. Figure 11 is a bottom view of the semiconductor device 1C according to Modification 2 of the Second Embodiment. The following description of this embodiment will focus on the differences from the second embodiment.

[0086] As shown in Figure 11, the semiconductor device 1C according to this modified example includes a plurality of low-density regions 26. Specifically, in the example in Figure 11, the semiconductor device 1C includes five low-density regions 26. The number of low-density regions 26 may be four or fewer, or six or more.

[0087] Each low-concentration region 26 is provided within the semiconductor layer 2 so as to be surrounded by the collector region 25 and is spaced apart from each other. Each low-concentration region 26 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11.

[0088] The effective p-type impurity concentration in each low-concentration region 26 is lower than the effective p-type impurity concentration in the collector region 25. Note that the effective p-type impurity concentrations in each low-concentration region 26 may all be equal, or the effective p-type impurity concentration in at least one low-concentration region 26 may differ from the effective p-type impurity concentrations in the other low-concentration regions 26.

[0089] In the example shown in Figure 11, each low-concentration region 26 is located inside the boundary B2 (in the center of the cell). Additionally, one of the multiple low-concentration regions 26 is located at the center of the lower surface 2a of the semiconductor layer 2.

[0090] Furthermore, in the example shown in Figure 11, the multiple low-density regions 26 are arranged symmetrically on the lower surface 2a of the semiconductor layer 2. More specifically, the multiple low-density regions 26 are arranged symmetrically with respect to a line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the X-axis, and also symmetrically with respect to a line passing through the same center and parallel to the Y-axis. This allows for efficient and high-speed switching of the semiconductor device 1C. Alternatively, the multiple low-density regions 26 may be arranged symmetrically with respect to at least one line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the XY plane. Or, the multiple low-density regions 26 may be arranged point-symmetrically with respect to the center of the lower surface 2a of the semiconductor layer 2.

[0091] According to this embodiment, the provision of multiple low-concentration regions 26 makes it possible to speed up the switching of the semiconductor device 1C.

[0092] Furthermore, the multiple low-density regions 26 may be arranged such that their density increases as they approach the center of the lower surface 2a of the semiconductor layer 2. Figure 12 is a bottom view of a semiconductor device 1D according to a modified example 3 of the second embodiment.

[0093] In the example shown in Figure 12, among the multiple low-density regions 26, those located near the center of the lower surface 2a of the semiconductor layer 2 are closer to other low-density regions 26 than those located near the boundary B2. Therefore, in the semiconductor device 1C, the density of low-density regions 26 is higher near the center of the lower surface 2a of the semiconductor layer 2 than near the boundary B2. In other words, in the example shown in Figure 12, the multiple low-density regions 26 are arranged such that their density increases as they approach the center of the lower surface 2a of the semiconductor layer 2. This allows for efficient and high-speed switching of the semiconductor device 1D.

[0094] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0095] 1 Semiconductor device 2 Semiconductor layers 11 Collector electrode 12 Emitter electrode 13 gates 21 n base region 22 Buffer area 23 p base region 24. Emitter region 25 Collector area 26,27 Low concentration area 28 Guard Ring Area 30 Insulation Area 41 Resist B1,B2 boundary IA inner area OA outer area

Claims

1. A semiconductor layer is provided comprising a first main surface and a second main surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, a control electrode provided so as to face the second semiconductor region via an insulating region, and a third semiconductor region of a first conductivity type located between the second main surface and the second semiconductor region. A second conductivity type impurity is ion-implanted into the first main surface of the semiconductor layer to form a fourth semiconductor region where the concentration of the second conductivity type impurity is a first concentration. A fifth semiconductor region is formed in which an impurity of a first conductivity type is ion-implanted into the first main surface of the semiconductor layer in an outer peripheral region extending from the side of the semiconductor layer to the inside of the semiconductor layer, and the net impurity concentration of the second conductivity type after compensation between the impurity of the first conductivity type and the impurity of the second conductivity type is a second concentration that is lower than the first concentration. A method for manufacturing a semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type in the fifth semiconductor region is higher than the impurity concentration of the first conductivity type in the fourth semiconductor region.

3. A method for manufacturing a semiconductor device according to claim 1, wherein, after preparing the semiconductor layer, and before forming the fourth semiconductor region, an impurity of a first conductivity type is ion-implanted into the first main surface of the semiconductor layer to form a sixth semiconductor region in which the impurity concentration of the first conductivity type is higher than that of the first semiconductor region.

4. The sixth semiconductor region comprises a first portion located within the outer peripheral region and a second portion located within an inner region inside the outer peripheral region. The method for manufacturing a semiconductor device according to claim 3, wherein the impurity concentration of the first conductivity type in the first part is higher than the impurity concentration of the first conductivity type in the second part.

5. Forming the aforementioned fifth semiconductor region is After forming a resist on the first main surface of the semiconductor layer, the portion of the resist located in the outer peripheral region is removed. Ion implantation of an impurity of a first conductivity type into the first main surface of the semiconductor layer, Removing the remaining portion of the aforementioned resist, A method for manufacturing a semiconductor device according to claim 1, comprising:

6. The first conductive type is n-type, The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity used when forming the fifth semiconductor region is at least one of phosphorus and arsenic.

7. The second conductivity type is p-type, The method for manufacturing a semiconductor device according to claim 1, wherein the impurity of the second conductivity type used when forming the fourth semiconductor region is boron.

8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein, after forming the fourth semiconductor region, an impurity of a first conductivity type is ion-implanted into a part of the first main surface of the semiconductor layer in an inner region inside the outer peripheral region to form a seventh semiconductor region surrounded by the fourth semiconductor region, and the net impurity concentration of the second conductivity type after compensation between the impurity of the first conductivity type and the impurity of the second conductivity type is a third concentration lower than the first concentration.

9. A semiconductor layer comprising a first main surface and a second main surface, The first electrode provided on the first main surface, The second electrode provided on the second main surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and located above the first semiconductor region, A control electrode is provided so as to face the second semiconductor region through an insulating region, A third semiconductor region of a first conductivity type is provided within the semiconductor layer, located on the second semiconductor region, and electrically connected to the second electrode, A fourth semiconductor region of a second conductivity type is provided within the semiconductor layer, located between the first electrode and the first semiconductor region, electrically connected to the first electrode, and having an impurity concentration of the second conductivity type equal to the first concentration. A fifth semiconductor region of a second conductivity type is provided within an outer peripheral region extending from the side of the semiconductor layer to the inside of the semiconductor layer and is electrically connected to the first electrode, and contains impurities of a first conductivity type and impurities of a second conductivity type, wherein the concentration of impurities of the second conductivity type is the first concentration, and the net concentration of impurities of the second conductivity type after compensation between the impurities of the first conductivity type and the impurities of the second conductivity type is a second concentration that is lower than the first concentration. A semiconductor device equipped with the following features.

10. The semiconductor device according to claim 9, wherein the impurity concentration of the first conductivity type in the fifth semiconductor region is higher than the impurity concentration of the first conductivity type in the fourth semiconductor region.

11. The semiconductor layer further comprises a sixth semiconductor region of a first conductivity type, located between the first semiconductor region and the fourth semiconductor region, and having an impurity concentration of the first conductivity type higher than that of the first semiconductor region. The sixth semiconductor region comprises a first portion located within the outer peripheral region and a second portion located within an inner region inside the outer peripheral region. The impurity concentration of the first conductivity type in the first part is higher than the impurity concentration of the first conductivity type in the second part. The semiconductor device according to claim 9.

12. A semiconductor device according to any one of claims 9 to 11, further comprising a seventh semiconductor region of a second conductivity type provided within the semiconductor layer so as to be surrounded by the fourth semiconductor region and electrically connected to the first electrode, the seventh semiconductor region containing an impurity of a first conductivity type and an impurity of a second conductivity type, wherein the concentration of the impurity of the second conductivity type is the first concentration, and the net impurity concentration of the second conductivity type after compensation between the impurity of the first conductivity type and the impurity of the second conductivity type is a third concentration lower than the first concentration.

Images