Printed circuit board

Abstract

The present invention provides a printed circuit board that can improve reliability when connecting multiple wiring sections. [Solution] The present invention provides a printed circuit board 100 comprising: a first wiring section 110 including a first insulating layer 111 and a first conductor layer 112 disposed on at least one surface of the first insulating layer 111; a second wiring section including a second insulating layer 121 and a second conductor layer 122 disposed on at least one surface of the second insulating layer 121 facing one surface of the first insulating layer 111; a joint section 130 disposed between the first and second wiring sections to connect them, including a joint layer 131 and a conductive filler 132 dispersed inside the joint layer 131; and a first insulating film 141 formed in a part of the first conductor layer 111.

Description

Technical Field

[0005] ,

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Recently, due to the development of technologies such as Artificial Intelligence (AI), packages including memory chips such as High Bandwidth Memory (HBM) for geometrically increasing data processing, and processor chips such as Central Processing Unit (CPU), Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA) are being used.

[0003] In printed circuit boards used for such packages, research continues to reduce defects generated during chip mounting and improve yield. As the number of substrate layers increases, the defect rate for each layer accumulates, and the overall yield may decrease. Such a yield decrease is particularly significant in substrates that require fine circuits.

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a printed circuit board capable of improving reliability when connecting a plurality of wiring portions.

Means for Solving the Problems

[0006] In one embodiment, the first insulating film may include at least one of Al2O3, ZnO, TiO2, and SiO2.

[0007] In one embodiment, the first insulating film may be an atomic layer deposition layer.

[0008] In one embodiment, the thickness of the first insulating film may be 5 nm to 15 nm.

[0009] In one embodiment, the first insulating film can also be formed on one surface of the first insulating layer.

[0010] In one embodiment, the first insulating film can expose at least a portion of one surface of the first insulating layer.

[0011] In one embodiment, the first insulating film can come into contact with the conductive filler.

[0012] In one embodiment, the first insulating film can be coated onto a portion of the first conductive layer.

[0013] In one embodiment, the first insulating film may be the surface oxide layer of the first conductive layer.

[0014] In one embodiment, the thickness of the region in the first conductor layer where the first insulating film is formed may be greater than the thickness of the region where the first insulating film is not formed.

[0015] In one embodiment, the joint can be in contact with the surface of the region of the first conductor layer in which the first insulating film is not formed, and with the side surface of the first insulating film.

[0016] In one embodiment, the region of the first conductor layer in which the first insulating film is not formed may have a stepped structure.

[0017] In one embodiment, the region of the first conductor layer in which the first insulating film is not formed may be groove-shaped.

[0018] In one embodiment, the joint can be filled into the groove-shaped region of the first conductive layer.

[0019] In one embodiment, the pitch of the first conductor layer may be narrower than the pitch of the second conductor layer.

[0020] In one embodiment, the second wiring portion may further include a second insulating film formed in a portion of the second conductor layer.

[0021] In one embodiment, a first exposed region in the first conductor layer where the first insulating film is not formed and a second exposed region in the second conductor layer where the second insulating film is not formed can be connected by the conductive filler.

[0022] In one embodiment, the first insulating film may not be formed on the side surface of the first insulating layer, and the second insulating film may not be formed on the side surface of the second insulating layer.

[0023] In one embodiment, the widths of the first insulating layer and the second insulating layer may be substantially the same.

[0024] In one embodiment, the first insulating layer may extend to a side surface of the first insulating layer, and the second insulating layer may not be formed on a side surface of the second insulating layer.

[0025] In one embodiment, the width of the first insulating layer may be narrower than the width of the second insulating layer.

[0026] In one embodiment, the first wiring portion may further include a third conductor layer disposed on the other surface of the first insulating layer facing the one surface, and a third insulating film formed on a part of the third conductor layer.

[0027] In one embodiment, the second wiring portion may further include a fourth conductor layer disposed on the other surface of the second insulating layer facing the one surface, and a fourth insulating film formed on a part of the fourth conductor layer.

Advantages of the Invention

[0028] In the case of a printed circuit board according to an example of the present invention, reliability can be improved when connecting a plurality of wiring portions.

Brief Description of the Drawings

[0029] [Figure 1] It is a block diagram schematically showing an example of an electronic device system. [Figure 2] It is a perspective view schematically showing an example of an electronic device. [Figure 3] It is a cross-sectional view schematically showing an example of a printed circuit board. [Figure 4] An example of the manufacturing process of a printed circuit board is shown. [Figure 5] An example of the manufacturing process of a printed circuit board is shown. [Figure 6] An example of the manufacturing process of a printed circuit board is shown. [Figure 7] An example of the manufacturing process of a printed circuit board is shown. [Figure 8] It is a cross-sectional view schematically showing an example of a printed circuit board. [Figure 9]This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 10] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 11] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 12] This shows an example of the manufacturing process for printed circuit boards. [Figure 13] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 14] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 15] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 16] This is a schematic cross-sectional view showing an example of a printed circuit board. [Modes for carrying out the invention]

[0030] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Therefore, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0031] [Electronic equipment] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0032] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0033] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0034] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0035] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0036] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included, depending on the type of electronic device 1000.

[0037] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, or automobile. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0038] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0039] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the chip-related components described above, and may, for example, be a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with the active and / or passive components built-in. On the other hand, it goes without saying that the electronic device is not necessarily limited to a smartphone 1100, but may be other electronic devices as described above.

[0040] [Printed circuit board] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board. Referring to Figure 3, the printed circuit board 100 according to this embodiment includes a first wiring section 110 and a second wiring section 120, and the first and second wiring sections 110 and 120 are connected by a joint section 130 which includes a bonding layer 131 and a conductive filler 132. Here, the first wiring section 110 includes a first insulating layer 111 and a first conductor layer 112, and the second wiring section 120 includes a second insulating layer 121 and a second conductor layer 122, and a first insulating film 141 is provided in a part of the first conductor layer 112. Similarly, a second insulating film 142 can be provided in a part of the second conductor layer 122, and the following description of the first insulating film 141 can also be applied to the second insulating film 142. As in this embodiment, when connecting the first and second wiring sections 110 and 120, forming the first insulating film 141 in a portion of the first conductor layer 112 prevents unintended electrical connections from occurring between the first conductor layer 112 and the second conductor layer 122, thereby improving the electrical reliability of the printed circuit board 100. The main components of the printed circuit board 100 will be described in detail below.

[0041] The first wiring section 110 includes a first insulating layer 111 and a first conductor layer 112, each of which may have a structure in which multiple layers are laminated. However, the first insulating layer 111 and the first conductor layer 112 may be realized as a single-layer structure, for example, the first wiring section 110 may be bonded to the second wiring section 120 as a single-layer build-up layer. The first insulating layer 111 may include insulating resins such as thermosetting resins like epoxy resin or thermoplastic resins like polyimide, or materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber (glass cloth, glass fabric), for example, ABF (Ajinomoto Build-up Film), prepreg, etc. If necessary, the first insulating layer 111 may also include PID (Photo Imageable Dielectric). The first insulating layer 111 can be obtained by laminating a plurality of insulating layers, where the plurality of insulating layers may contain the same or different insulating materials.

[0042] The first conductor layer 112 is disposed on at least one surface of the first insulating layer 111 and may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first conductor layer 112 may include an electroless plating layer and an electrolytic plating layer, and may further include copper foil as needed. The first conductor layer 112 can perform various functions depending on the design of the layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as data signals, etc. These patterns may each include a trace, a plane, and / or a pad. The first conductor layer 112 can be arranged in a multilayer structure on the surface and inside the first insulating layer 111. In this embodiment, the layer arranged on one side of the first insulating layer 111 is referred to as the first conductor layer 112, and the layer arranged on the other side is referred to as the third conductor layer 114.

[0043] A first via 113 may be provided to connect the first conductor layer 112 and the third conductor layer 114. The first via 113 may be made of metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first via 113 may be formed together with the first conductor layer 112 and may include an electroless plating layer and an electroplating layer. The first via 113 may be a filled type, where the through-holes of the first insulating layer 111 are filled with a metallic material, but is not limited to this; it may also be a conformal type, where the metallic material is arranged along the walls of the through-holes. The first via 113 may have a tapered cross-section. The first via 113 can perform various functions depending on the design of the layer. For example, it may include ground vias, power vias, signal vias, etc. Here, the signal via may include vias for transmitting various signals other than ground vias, power vias, etc., such as data signals.

[0044] Similar to the first wiring section 110, the second wiring section 120 includes a second insulating layer 121 and a second conductor layer 122, which may each have a structure in which multiple layers are laminated. However, the second insulating layer 121 and the second conductor layer 122 may be realized as a single-layer structure, for example, the second wiring section 120 may be bonded to the first wiring section 110 as a single-layer build-up layer. The second insulating layer 121 may include insulating resins such as thermosetting resins like epoxy resin or thermoplastic resins like polyimide, or materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber (glass cloth, glass fabric), for example, ABF (Ajinomoto Build-up Film), prepreg, etc. If necessary, the second insulating layer 121 may also include PID (Photo Imageable Dielectric). The second insulating layer 121 can be obtained by laminating a plurality of insulating layers, where the plurality of insulating layers may contain the same or different insulating materials.

[0045] The second conductor layer 122 is arranged on at least one surface of the second insulating layer 121 and may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second conductor layer 122 may include an electroless plating layer and an electrolytic plating layer, and may further include copper foil as needed. The second conductor layer 122 can perform various functions depending on the design of the layer. For example, it may include ground patterns, power patterns, signal patterns, etc. Here, the signal pattern may include various signals other than ground patterns, power patterns, etc., such as data signals. These patterns may each include traces, planes, and / or pads. The second conductor layer 122 can be arranged in a multilayer structure on the surface and inside the second insulating layer 121. In this embodiment, the layer arranged on one side of the second insulating layer 121 is referred to as the second conductor layer 122, and the layer arranged on the other side is referred to as the fourth conductor layer 124.

[0046] A second via 123 may be provided to connect the second conductor layer 122 and the fourth conductor layer 124. The second via 123 may be made of metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second via 123 may be formed together with the second conductor layer 122 and may include an electroless plating layer and an electroplating layer. The second via 123 may be a filled type, where the through-holes of the second insulating layer 121 are filled with a metallic material, but is not limited to this; it may also be a conformal type, where the metallic material is arranged along the walls of the through-holes. The second via 123 may have a tapered cross-section. The second via 123 can perform various functions depending on the design of the layer. For example, it may include ground vias, power vias, signal vias, etc. Here, the signal via may include vias for transmitting various signals other than ground vias, power vias, etc., such as data signals.

[0047] The joint 130 is positioned between the first and second wiring sections 110 and 120 to connect them, and in addition to this joining function, it can also serve as a path for electrical connection. For this purpose, the joint 130 includes a bonding layer 131 and a conductive filler 132 dispersed within the bonding layer 131. The bonding layer 131 may contain an insulating resin, and may contain a thermopolymerizable compound such as an epoxy compound or a photopolymerizable compound such as an acrylate compound. The conductive filler 132 may contain metal particles such as nickel (Ni), cobalt (Co), silver (Ag), copper (Cu), gold (Au), and palladium (Pd), in which case copper (Cu) particles can be used.

[0048] The joint 130 can be provided to join multiple separately manufactured wiring sections 110 and 120, thereby enabling the efficient realization of a multilayer substrate. The defect rate increases as the number of layers in the substrate increases, and the decrease in yield becomes particularly pronounced in substrates requiring fine circuits. If a fine circuit process is required for some wiring sections, for example, the first wiring section 110, the first wiring section 110 may be realized relatively as a fine circuit. In this case, by manufacturing the second wiring section 120 separately from the first wiring section 110 in a separate process, the defect rate can be reduced compared to manufacturing them at once. In this case, the second wiring section 120, which has a relatively wide pitch, can also be manufactured in a relatively inexpensive process.

[0049] Furthermore, in this embodiment, a first insulating film 141 is used in the region where the first wiring section 110 and the second wiring section 120 are connected, in order to reduce short-circuit failures due to unintended electrical connections. The first insulating film 141 is formed in a part of the first conductor layer 112, for example, in the remaining region of the first conductor layer 112 excluding the pad region connected to the second conductor layer 122. The first insulating film 141 can come into contact with the conductive filler 132 of the joint 130. The first insulating film 141 may be coated on a part of the first conductor layer 112. Alternatively, the first insulating film 141 may be a surface oxide layer of the first conductor layer 112. When the first conductor layer 112 is protected by the first insulating film 141, the first conductor layer 112 can be electrically and effectively protected in the remaining region excluding the connecting region of the wiring sections 110 and 120, thereby improving the electrical reliability of the printed circuit board 100. Furthermore, from the viewpoint of further improving reliability, a second insulating film 142 may be provided, and the second insulating film 142 may be formed in a part of the second conductor layer 122. For example, the second insulating film 142 may be formed in the remaining area of ​​the second conductor layer 122, excluding the pad area connected to the first conductor layer 112. The second insulating film 142 can then come into contact with the conductive filler 132 of the joint 130.

[0050] The first insulating film 141 can be formed to maintain high electrical insulation properties while having a thin thickness. Considering this, the first insulating film 141 can contain at least one of Al2O3, ZnO, TiO2, and SiO2. The first insulating film 141 may be thinner than the other components; for example, its thickness may be 5 nm to 15 nm. As an example of a method for forming such a first insulating film 141, it may be an atomic layer deposited using atomic layer deposition. When the first insulating film 141 is an atomic layer deposited, it can be formed from Al2O3, which can have high insulating properties and adhesion. However, other vapor deposition processes can also be used. Similarly, the second insulating film 142 may be coated on a portion of the second conductive layer 122. Alternatively, the second insulating film 142 may be a surface oxide layer of the second conductive layer 122. The second insulating film 142 can be formed to maintain high electrical insulation properties while having a thin thickness. Taking this into consideration, the second insulating film 142 may contain at least one of Al2O3, ZnO, TiO2, and SiO2. The second insulating film 142 may be thinner than the other components; for example, the thickness of the second insulating film 142 may be 5 nm to 15 nm. As an example of a method for forming such a second insulating film 142, it may be an atomic layer deposited using atomic layer deposition. However, other processes such as vapor deposition can also be used.

[0051] As shown in the illustrated configuration, the first insulating film 141 can be formed on one surface of the first insulating layer 111 in addition to the first conductor layer 112, thereby further reducing the possibility of short circuits. Similarly, the second insulating film 142 can be formed on one surface of the second insulating layer 121 in addition to the second conductor layer 122, thereby further reducing the possibility of short circuits. Alternatively, the first insulating film 141 may be limited to a minimum area necessary to prevent unintended electrical connections between the first conductor layer 112 and the second conductor layer 122. In this case, as shown in the modified example in Figure 8, the first insulating film 141 can be realized in a form that exposes at least a portion of one surface of the first insulating layer 111. Likewise, the second insulating film 142 may be realized in a form that exposes at least a portion of one surface of the second insulating layer 121. On the other hand, in Figures 3 and 8, the first insulating film 141 exposes the entire pad region of the first conductor layer 112, but the first insulating film 141 can extend to one surface of the first conductor layer 112 in such a way that it reduces the width of the exposed region in the pad region of the first conductor layer 112, that is, in such a way that it reduces the area of ​​the exposed region of the first conductor layer 112 (for example, the embodiment in Figure 10). Similarly, the second insulating film 142 can extend to one surface of the second conductor layer 122 in such a way that it reduces the width of the exposed region in the pad region of the second conductor layer 122, that is, in such a way that it reduces the area of ​​the exposed region of the second conductor layer 122.

[0052] Referring again to Figure 3, an electrical connection can be made between the first wiring section 110 and the second wiring section 120 in the region where the first insulating film 141 and the second insulating film 142 are not formed. Specifically, the first exposed region R1 in the first conductor layer 112 where the first insulating film 141 is not formed, and the second exposed region R2 in the second conductor layer 122 where the second insulating film 142 is not formed, can be connected by the conductive filler 132. In this case, although only one first exposed region R1 and one second exposed region R2 are shown in Figure 3, these may be a part of the printed circuit board 100, and multiple first exposed regions R1 and second exposed regions R2 may be provided.

[0053] As further components, the first wiring section 110 may further include a third conductor layer 114 disposed on the other side (the top surface with reference to Figure 3) opposite to the side on which the first conductor layer 112 is formed in the first insulating layer 111, and a third insulating film 143 formed on a part of the third conductor layer 114. The second wiring section 120 may further include a fourth conductor layer 124 disposed on the other side (with reference to Figure 3) opposite to the side on which the second conductor layer 122 is formed in the second insulating layer 121, and a fourth insulating film 144 formed on a part of the fourth conductor layer 124. The third and fourth insulating films 143 and 144 may contain the same materials as the first and second insulating films 141 and 142, and may be formed in the same process as the first and second insulating films 141 and 142.

[0054] Referring to Figures 4 to 7, an example of the manufacturing process of a printed circuit board will be described, focusing on the joining process of the first and second wiring sections 110 and 120. First, after the first wiring section 110 is provided, a mask M1 is formed to cover a part of the first conductor layer 112 (Figure 4). The area covered by mask M1 can be an area that is exposed without the formation of the first insulating film 141. Furthermore, a mask M2 can also be formed to cover a part of the third conductor layer 114. Masks M1 and M2 may contain metals with different etching characteristics from the first and third conductor layers 112 and 114. Next, a first insulating film 141 covering the first conductor layer 112 and a third insulating film 143 covering the third conductor layer 114 are formed (Figure 5). The first and third insulating films 141 and 143 may contain at least one of the following materials that have excellent insulating properties even at relatively thin thicknesses: for example, Al2O3, ZnO, TiO2, and SiO2, and can be formed by processes such as atomic layer deposition. In Figure 5, the first and third insulating films 141 and 143 are not formed on the side surface of the first insulating layer 111. However, in a different case, the first and third insulating films 141 and 143 may also be formed on the side surface of the first insulating layer 111. However, in the panel dicing process described later, the first and third insulating films 141 and 143 do not need to be present on the side surface of the unit printed circuit board.

[0055] Next, masks M1 and M2 are removed to expose a portion of the first conductor layer 112 and the third conductor layer 114, and the joint portion 130 is attached to one side of the first wiring portion 110 (Figure 6). Masks M1 and M2 can be removed by dry or wet etching processes available in the art, such as plasma etching. The joint portion 130 can be made from a semi-cured or uncured bonding layer 131 containing a conductive filler 132. The second wiring portion 120 can be made in the same process as the first wiring portion 110, and the first and second wiring portions 110 and 120 obtained in this way can be bonded together by applying pressure with the joint portion 130 positioned between them (Figure 7). By using the method of bonding the first and second wiring portions 110 and 120 using the joint portion 130, it is possible to replace the hybrid bonding method of Cu layers with Cu layers.

[0056] Referring to Figures 9 to 16, a printed circuit board according to a modified embodiment will be described. First, in the embodiment of Figure 9, the thickness of the region of the first conductor layer 112 where the first insulating film 141 is formed is greater than the thickness of the region where the first insulating film 141 is not formed. In other words, the exposed region R1 of the first conductor layer 112 may be relatively thin. This can be achieved by over-etching, in which a portion of the first conductor layer 112 is removed along with the mask M1 during the manufacturing process described above. In this case, the etching amount of the first conductor layer 112 can be adjusted according to the size of the intended step structure, for example, about 2 μm can be removed. Similarly, a portion of the third conductor layer 114 can be removed along with the mask M2 during the mask removal process, thereby allowing the region of the third conductor layer 114 not covered by the third insulating film 143 to have a relatively thin thickness.

[0057] By partially removing the first conductor layer 112, the region of the first conductor layer 112 where the first insulating film 141 is not formed can have a stepped structure. This allows the joint 130 to contact the surface of the region R1 of the first conductor layer 112 where the first insulating film 141 is not formed and the side surface of the first insulating film 141, thereby improving the bonding between the first conductor layer 112 and the joint 130. Similarly, by partially removing the third conductor layer 114, the region of the third conductor layer 114 where the third insulating film 143 is not formed can have a stepped structure. As an example of such a stepped structure, as shown in the embodiment of Figure 10, the region R1 of the first conductor layer 112 where the first insulating film 141 is not formed may be groove-shaped. In this case, the joint 130 may be filled into the groove-shaped region of the first conductor layer 112. Although not shown in Figure 10, the region of the third conductor layer 114 where the third insulating film 143 is not formed can also be realized as groove-shaped. In Figures 9 and 10, the first conductor layer 112 was used as the basis for the explanation, but the same structure can also be applied to the second conductor layer 122.

[0058] The embodiment shown in Figure 11 illustrates the more specific structure of the first wiring section 210 and the second wiring section 220. In this embodiment, the printed circuit board 200 is connected to the first wiring section 210 and the second wiring section 220 by a joint 230, and the first wiring section 210 and the second wiring section 220 have different structures. Here, "different structures" means that the number of layers, pitch, etc., of the first wiring section 210 and the second wiring section 220 are different. The first wiring section 210 includes a first insulating layer 211 and a first conductor layer 212, which are each realized by a structure in which multiple layers are stacked. The first insulating layer 211 may include insulating resins such as thermosetting resins like epoxy resins or thermoplastic resins like polyimide, or materials obtained by mixing these resins with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber (glass cloth, glass fabric), for example, ABF (Ajinomoto Build-up Film), prepreg, etc. If necessary, the first insulating layer 211 may also include PID (Photo Imageable Dielectric). The first insulating layer 211 can be obtained by laminating a plurality of insulating layers, where the plurality of insulating layers may contain the same or different insulating materials.

[0059] The first conductor layer 212 may include, as a metallic material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first conductor layer 212 may include an electroless plating layer and an electroplating layer, and may further include copper foil as needed. The first conductor layer 212 can perform various functions depending on the design of the layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as data signals, etc. These patterns may each include a trace, a plane, and / or a pad.

[0060] A first via 213 may be provided to connect the conductor layer 212. The first via 213 may be made of metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first via 213 may be formed together with the first conductor layer 212 and may include an electroless plating layer and an electroplating layer. The first via 213 may be a filled type, where the through-holes of the first insulating layer 211 are filled with a metallic material, but is not limited to this; it may also be a conformal type, where the metallic material is arranged along the walls of the through-holes. The first via 213 may have a tapered cross-section. The first via 213 can perform various functions depending on the design of the layer. For example, it may include ground vias, power vias, signal vias, etc. Here, the signal via may include vias for transmitting various signals other than ground vias, power vias, etc., such as data signals.

[0061] A first solder resist layer 214 may be placed outside the first wiring section 210. The first solder resist layer 214 may have an opening that partially exposes the uppermost part of the first conductor layer 212 that is located on the first wiring section 210. The first solder resist layer 214 may contain, but is not limited to, a known solder resist material or a photosensitive insulating material.

[0062] The second wiring section 220 includes a second insulating layer 221 and a second conductor layer 222, each of which may have a structure in which multiple layers are laminated. In the case of the second insulating layer 221, it may include a first core section 221B and build-up sections 221A and 221C arranged above and below it. The first core section 221B may contain an insulating material, which may be an insulating resin such as a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide, or a material in which these resins are mixed with an inorganic filler such as silica, or a resin impregnated with an inorganic filler into a core material such as glass fiber (glass cloth, glass fabric), for example, CCL (copper clad laminate), but is not limited thereto. If necessary, a core insulating layer of another material such as a glass substrate may be introduced as the first core section 221B, or a metal core layer may be used. The first core section 221B is provided with through vias 224, which can connect the second conductor layers 222 located above and below it.

[0063] The build-up sections 221A and 221C are arranged on both sides of the first core section 221B, respectively, and can have a multilayer structure. The build-up sections 221A and 221C may include insulating resins such as thermosetting resins like epoxy resin or thermoplastic resins like polyimide, or materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber (glass cloth, glass fabric), for example, ABF (Ajinomoto Build-up Film), prepreg, etc. If necessary, the build-up sections 221A and 221C may also include PID (Photo Imageable Dielectric). In the second insulating layer 221, the regions constituting the build-up sections 221A and 221C can be obtained by laminating a plurality of insulating layers, where the plurality of insulating layers may contain the same or different insulating materials.

[0064] The second conductor layer 222 may include metallic materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second conductor layer 222 may include an electroless plating layer and an electroplating layer, and may further include copper foil as needed. The second conductor layer 222 can perform various functions depending on the design of the layer. For example, it may include ground patterns, power patterns, signal patterns, etc. Here, the signal pattern may include various signals other than ground patterns, power patterns, etc., such as data signals. These patterns may each include traces, planes, and / or pads.

[0065] As in this embodiment, when the second conductor layer 222 has a multilayer structure, a second via 223 can be provided to connect them. In the case of the second via 223, the metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second via 223 can be formed together with the second conductor layer 222 and may include an electroless plating layer and an electroplating layer. The second via 223 may be a filled type in which the through-hole of the second insulating layer 221 is filled with a metallic material, but is not limited to this, and may also be a conformal type in which the metallic material is arranged along the wall surface of the through-hole. The second via 223 may have a tapered shape in cross-section. The second via 223 can perform various functions depending on the design of the layer. For example, it may include a ground via, a power via, a signal via, etc. Here, the signal via may include vias for transmitting various signals other than ground vias, power vias, etc., such as data signals.

[0066] In the case of the first wiring section 210, the first conductor layer 212 provided therein may be realized by a microcircuit process to have a relatively narrow pitch compared to the second conductor layer 222 of the second wiring section 220. In this case, by manufacturing the second wiring section 220 separately from the first wiring section 210 in a separate process, the defect rate can be reduced compared to manufacturing them at the same time. In this case, the second wiring section 220 having a relatively wide pitch can also be manufactured in a relatively inexpensive process.

[0067] Similar to the embodiments described above, the joint 230 includes a bonding layer 231 and a conductive filler 232, and is provided with a first insulating film 241 formed in a part of the first conductor layer 212. Similarly, a second insulating film 242 may be provided in a part of the second conductor layer 222. In this case, as shown in the figure, the first insulating film 241 may not be formed on the side surface of the first insulating layer 211, and the second insulating film 242 may not be formed on the side surface of the second insulating layer 221. The process of obtaining such a structure will be explained with reference to Figure 12. The first wiring section 210 and the second wiring section 220 may be realized in a panel shape, as shown in Figure 12. That is, the first panel 210P and the second panel 220P can be joined by an adhesive section panel 230P, and a unit printed circuit board can be obtained by cutting them along the dicing line (dashed line). In this case, after dicing, there is no insulating film on the side surface of the unit printed circuit board. Furthermore, with this manufacturing method, the widths of the first insulating layer 211 and the second insulating layer 221 can be substantially the same, as shown in the configuration in Figure 11.

[0068] In contrast, as shown in the embodiment of Figure 13, a structure is also possible in which the first insulating film 241 extends to the side surface of the first insulating layer 211, and the second insulating film 242 is not formed on the side surface of the second insulating layer 221. Such a structure can be obtained by forming the first insulating film 241 on the first wiring section 210 in a unit state, without using a method of dicing after joining the first and second wiring sections 210 and 220. For example, this is the case when using a method in which the second wiring section 220 is diced after joining the first wiring section 210 in a unit state and the second wiring section 220 in a panel state. In this case, the width of the first insulating layer 211 may be narrower than the width of the second insulating layer 221. When the first insulating film 241 is also formed on the side surface of the first insulating layer 211, the overall insulating characteristics of the first wiring section 210 can be improved.

[0069] On the other hand, the structure shown in Figure 13 is not only obtainable when the second wiring section 220 is manufactured in a panel shape and then diced; the second wiring section 220 can also be coupled with the unit-state first wiring section 210 after dicing, i.e., in a unit state. Furthermore, even when the first insulating film 241 extends to the side surface of the first insulating layer 211 in the first wiring section 210, the width of the first insulating layer 211 and the width of the second insulating layer 221 can be substantially the same, as shown in the embodiment of Figure 14. Also, as shown in the embodiment of Figure 15, even when the width of the first insulating layer 211 and the width of the second insulating layer 221 are substantially the same, both the first insulating film 241 and the second insulating film 242 can extend. That is, in addition to the first insulating film 241, the second insulating film 242 can also extend to the side surface of the second insulating layer 221. Furthermore, as shown in the configuration in Figure 16, when the width of the first insulating layer 211 is narrower than the width of the second insulating layer 221, the first insulating film 241 can extend to the side surface of the first insulating layer 211, and the second insulating film 242 can extend to the side surface of the second insulating layer 221.

[0070] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" can mean the shape when the object is cut horizontally, or the planar shape when the object is viewed from above or below.

[0071] In this invention, terms such as "upper side," "upper part," and "upper surface" are used for convenience to mean the direction toward the surface on which electronic components can be mounted, based on the cross-section of the drawing, while terms such as "lower side," "lower part," and "lower surface" are used to mean the opposite direction. However, this is merely a definition of direction for the sake of explanation, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction.

[0072] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0073] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0074] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0075] 100: Printed circuit board 110: 1st wiring section 111: First insulating layer 112: First Conductor Layer 113: First Via 114: Third Conductor Layer 121: Second insulating layer 122: Second conductor layer 123: Second Beer 124: Fourth Conductor Layer 130: Joint 131: Bonding layer 132: Conductive filler 141: First insulating film 142: Second insulating film 143: Third insulating film 144: Fourth insulating film

Claims

1. A first wiring section including a first insulating layer and a first conductor layer disposed on at least one surface of the first insulating layer, A second wiring section including a second insulating layer and a second conductor layer disposed on at least one surface of the second insulating layer facing one surface of the first insulating layer, A joint portion is positioned between the first wiring portion and the second wiring portion to connect the first wiring portion and the second wiring portion, and includes a bonding layer and a conductive filler dispersed inside the bonding layer, A printed circuit board comprising a first insulating film formed in a portion of the first conductor layer.

2. The first insulating film is Al ２ O ３ ZnO, TiO ２ SiO ２ A printed circuit board according to claim 1, comprising at least one of the following.

3. The printed circuit board according to claim 1, wherein the first insulating film is an atomic layer deposition layer.

4. The printed circuit board according to claim 1, wherein the thickness of the first insulating film is 5 nm or more and 15 nm or less.

5. The printed circuit board according to claim 1, wherein the first insulating film is also formed on one surface of the first insulating layer.

6. The printed circuit board according to claim 1, wherein the first insulating film exposes at least a portion of one surface of the first insulating layer.

7. The printed circuit board according to claim 1, wherein the first insulating film is in contact with the conductive filler.

8. The printed circuit board according to claim 1, wherein the first insulating film is coated on a portion of the first conductive layer.

9. The printed circuit board according to claim 1, wherein the first insulating film is a surface oxide layer of the first conductor layer.

10. The printed circuit board according to claim 1, wherein the thickness of the region in the first conductor layer on which the first insulating film is formed is greater than the thickness of the region on which the first insulating film is not formed.

11. The printed circuit board according to claim 10, wherein the joint portion is in contact with the surface of the region of the first conductor layer in which the first insulating film is not formed and with the side surface of the first insulating film.

12. The printed circuit board according to claim 10, wherein the region of the first conductor layer in which the first insulating film is not formed has a stepped structure.

13. The printed circuit board according to claim 12, wherein the region of the first conductor layer in which the first insulating film is not formed is groove-shaped.

14. The aforementioned joint is filled in the groove-shaped region of the first conductor layer, as described in claim 13.

15. The printed circuit board according to claim 1, wherein the pitch of the first conductor layer is narrower than the pitch of the second conductor layer.

16. The printed circuit board according to claim 1, wherein the second wiring portion further includes a second insulating film formed in a part of the second conductor layer.

17. The printed circuit board according to claim 16, wherein a first exposed region in the first conductor layer where the first insulating film is not formed and a second exposed region in the second conductor layer where the second insulating film is not formed are connected by the conductive filler.

18. The first insulating film is not formed on the side surface of the first insulating layer. The printed circuit board according to claim 16, wherein the second insulating film is not formed on the side surface of the second insulating layer.

19. The printed circuit board according to claim 18, wherein the widths of the first insulating layer and the second insulating layer are the same.

20. The first insulating film extends along the side surface of the first insulating layer, The printed circuit board according to claim 16, wherein the second insulating film is not formed on the side surface of the second insulating layer.

21. The printed circuit board according to claim 20, wherein the width of the first insulating layer is narrower than the width of the second insulating layer.

22. The printed circuit board according to claim 1, wherein the first wiring portion further includes a third conductor layer disposed on the other surface of the first insulating layer opposite to the one surface, and a third insulating film formed on a part of the third conductor layer.

23. The printed circuit board according to claim 22, wherein the second wiring portion further includes a fourth conductor layer disposed on the other side of the second insulating layer opposite to the one side, and a fourth insulating film formed on a part of the fourth conductor layer.

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