Non-volatile semiconductor memory

Abstract

To provide a non-volatile semiconductor memory device that can suppress deterioration of the threshold distribution width. [Solution] The non-volatile semiconductor memory device includes a first semiconductor layer including a first memory cell transistor including a first channel, a second semiconductor layer stacked with the first semiconductor layer including a second memory cell transistor including a second channel, a third semiconductor layer stacked on the side opposite to the side where the second semiconductor layer is stacked relative to the first semiconductor layer including a third memory cell transistor including a third channel, and a control circuit that controls the first to third memory cell transistors to enable write operations. When the control circuit performs a write operation on the second memory cell transistor, it supplies a first voltage, which is a reference voltage, to the second channel, supplies a second voltage greater than the first voltage to the first channel, then supplies a second voltage to the third channel, and boosts the voltage supplied to the first channel to a third voltage greater than the second voltage.

Description

Technical Field

[0001] One embodiment of the present disclosure relates to a non-volatile semiconductor memory device.

Background Art

[0002] As a non-volatile semiconductor memory device, a NAND-type flash memory is known. In order to increase the capacity of the NAND-type flash memory, a three-dimensional NAND-type flash memory in which a plurality of memory cells are three-dimensionally arranged has been put into practical use. As forms of the three-dimensional NAND-type flash memory, for example, there are a form in which memory strings are formed vertically and a form in which memory strings are formed horizontally.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] The present invention provides a non-volatile semiconductor memory device that can suppress the deterioration of the threshold distribution width. [Means for solving the problem]

[0006] The non-volatile semiconductor memory device according to this embodiment is 2 nA first semiconductor layer extending in the first direction, comprising a plurality of first memory cell transistors, a plurality of second memory cell transistors, and a plurality of third memory cell transistors, which can be set to threshold voltage levels of more than 2 (where n is an integer greater than or equal to 2); a first bit line extending in a first direction; second bit lines and third bit lines parallel to the first bit line; a source line provided on the opposite side of the first bit line with respect to the first direction and extending in a second direction intersecting the first direction; a first semiconductor layer extending in the first direction, comprising the plurality of first memory cell transistors electrically connected between the first bit line and the source line; a second semiconductor layer stacked with the first semiconductor layer along a third direction intersecting both the first and second directions, comprising the plurality of third memory cell transistors connected between the third bit line and the source line, comprising the plurality of first memory cell transistors, wherein the second semiconductor layer is stacked with the first semiconductor layer along the third direction, comprising the plurality of first memory cell transistors electrically connected between the first bit line and the source line. The device includes a third semiconductor layer stacked on the side opposite to the side being stacked, and a control circuit that controls each of the plurality of first memory cell transistors, each of the plurality of second memory cell transistors, and each of the plurality of third memory cell transistors to enable a write operation including a first operation and a second operation, wherein when the control circuit performs the write operation to write data to one of the plurality of second memory cell transistors, it supplies a first voltage, which is a reference voltage, to the second bit line and the second channel of the plurality of second memory cell transistors, supplies a second voltage greater than the first voltage to the first bit line and the first channel of the plurality of first memory cell transistors, and then supplies the second voltage to the third bit line and the third channel of the plurality of third memory cell transistors, thereby enabling the first operation to be performed, which is to boost the voltage supplied to the first channel to a third voltage greater than the second voltage. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a non-volatile semiconductor memory device according to one embodiment. [Figure 2]This is a circuit diagram of a memory cell array included in a non-volatile semiconductor memory device according to one embodiment. [Figure 3] This is a plan view showing the planar configuration of the memory cell region, a part of the SGD region, and a part of the SGS region of a non-volatile semiconductor memory device according to one embodiment. [Figure 4] This is a plan view showing the planar configuration of a part of the memory cell region and the SGS region of a non-volatile semiconductor memory device according to one embodiment. [Figure 5] This is a circuit diagram showing an example of the circuit configuration of a sense amplifier unit according to one embodiment. [Figure 6] This is a threshold distribution diagram showing an example of the threshold distribution of a memory cell transistor according to one embodiment. [Figure 7] This figure shows an example of a program loop in a non-volatile semiconductor memory device according to one embodiment. [Figure 8] This is a timing chart showing an example of a write operation in a non-volatile semiconductor memory device related to a comparative example. [Figure 9] This is a perspective view showing an example of a channel in a non-volatile semiconductor memory device according to one embodiment. [Figure 10] This is a perspective view showing an example of the channel state in a non-volatile semiconductor memory device relating to a comparative example. [Figure 11] This is a perspective view showing an example of a channel in a non-volatile semiconductor memory device related to a comparative example. [Figure 12] This is a timing chart showing the write operation in a non-volatile semiconductor memory device according to one embodiment. [Figure 13] This is a threshold distribution diagram showing an example of the threshold distribution of a memory cell transistor according to one embodiment. [Figure 14] This is a timing chart showing the write operation in a non-volatile semiconductor memory device according to one embodiment. [Figure 15] This is a timing chart showing the write operation in a non-volatile semiconductor memory device according to one embodiment.

Best Mode for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. When distinguishing between a plurality of components having a common reference numeral, a subscript is added to the common reference numeral for distinction. When no distinction is required for a plurality of components, only the common reference numeral is given to the plurality of components, and no subscript is added.

[0009] In the specification, drawings, and claims of the present application (hereinafter also referred to as "this specification, etc."), the non-volatile semiconductor memory device, which is one of the embodiments, is, for example, a three-dimensional NAND type flash memory, and more specifically, a three-dimensional NAND type flash memory in which memory strings extend in the horizontal direction.

[0010] [First Embodiment] Referring to FIGS. 1 to 13, the non-volatile semiconductor memory device 1 and a method for driving the non-volatile semiconductor memory device 1 will be described.

[0011] [1. Configuration of Memory System] Referring to FIG. 1, the configuration of the memory system will be described. FIG. 1 is a block diagram showing an example of the configuration of a memory system 3 including the non-volatile semiconductor memory device 1. As shown in FIG. 1, the memory system 3 includes the non-volatile semiconductor memory device 1 and a memory controller 2. For example, the memory system 3 is an SSD (solid state drive), a memory card such as an SDTM card, or the like. The memory system 3 may include a host device (not shown). For example, the memory controller 2 controls the write operation, read operation, and erase operation of the non-volatile semiconductor memory device 1.

[0012] [2. Configuration of Non-volatile Semiconductor Memory Device] Referring to Figure 1, the configuration of the non-volatile semiconductor memory device 1 will be described. The non-volatile semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, a status register 12, an address register 13, a command register 14, a sequencer 15, a ready / busy circuit 16, a voltage generation circuit 17, a memory cell array 18, a row decoder 19, a sense amplifier module 20, a data register 21, and a column decoder 22.

[0013] The input / output circuit 10 controls the input (reception) of signal DQ from the memory controller 2 and the output (transmission) of signal DQ to the memory controller 2. For example, signal DQ includes data DAT, address ADD, and command CMD. More specifically, the input / output circuit 10 transmits the data DAT received from the memory controller 2 to the data register 21, the address ADD received from the memory controller 2 to the address register 13, and the command CMD received from the memory controller 2 to the command register 14. The input / output circuit 10 also transmits status information STS received from the status register 12, data DAT received from the data register 21, and address ADD received from the address register 13 to the memory controller 2.

[0014] The logic control circuit 11 receives various control signals from the memory controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequencer 15 according to the received control signals.

[0015] For example, the status register 12 temporarily holds status information STS for write, read, and erase operations, and notifies the memory controller 2 whether each operation has been completed successfully.

[0016] Address register 13 temporarily holds the received address ADD. Address register 13 transfers the row address RADD to row decoder 19 and the column address CADD to column decoder 22.

[0017] Command register 14 temporarily stores the received command CMD and transfers it to sequencer 15.

[0018] The sequencer 15 controls the operation of the non-volatile semiconductor memory device 1. For example, in response to a received command CMD, the sequencer 15 controls the status register 12, the ready / busy circuit 16, the voltage generation circuit 17, the row decoder 19, the sense amplifier module 20, the data register 21, and the column decoder 22, etc., to perform write operations, read operations, erase operations, etc. The sequencer 15 in the non-volatile semiconductor memory device 1 is sometimes referred to as the "controller".

[0019] The ready / busy circuit 16 sends a ready / busy signal RBn to the memory controller 2 according to the operating status of the sequencer 15.

[0020] The voltage generation circuit 17 generates the voltages necessary for writing, reading, and erasing operations in response to the control of the sequencer 15. For example, the voltage generation circuit 17 supplies the generated voltage to the memory cell array 18, the row decoder 19, and the sense amplifier module 20, etc. The row decoder 19 and the sense amplifier module 20 apply the voltage supplied by the voltage generation circuit 17 to the memory cell transistors in the memory cell array 18.

[0021] The memory cell array 18 comprises multiple block BLKs (BLK0 to BLK3, ...) each containing multiple non-volatile memory cell transistors MC associated with rows and columns. Each block BLK contains multiple string units SU (SU0 to SU3, ...). Each string unit SU contains multiple memory groups MG (memory string pairs). The number of block BLKs in the memory cell array 18, the number of string units SU within each block BLK, and the number of memory groups MG within each string unit SU are arbitrary. Details of the memory cell array 18 will be described later.

[0022] The row decoder 19 decodes the row-address RADD. Based on the decoding result, the row decoder 19 applies the required voltage to the memory cell array 18.

[0023] For example, during a read operation, the sense amplifier module 20 senses the data read from the memory cell array 18 and transmits the sensed and read data to the data register 21. Also, for example, during a write operation, the sense amplifier module 20 transmits the write data to the memory cell array 18.

[0024] The data register 21 includes multiple latch circuits. The latch circuits temporarily hold the data to be written or read.

[0025] For example, the column decoder 22 decodes the column address CADD during write, read, and erase operations, and selects a latch circuit in the data register 21 according to the decoding result.

[0026] [3. Memory cell array configuration] Referring to Figure 2, the configuration of the memory cell array 18 will be described. Figure 2 is a circuit diagram showing an example of a memory cell array 18. The circuit configuration of the memory cell array 18 shown in Figure 2 is an example, and the circuit configuration and semiconductor layers (channel layers) of the memory cell array 18 in the non-volatile semiconductor memory device 1 are not limited to the configuration shown in Figure 2. Configurations identical or similar to those in Figure 1 will be described as necessary, and descriptions of configurations identical or similar to those in Figure 1 may be omitted.

[0027] As explained in "2. Configuration of Non-Volatile Semiconductor Memory Device," the memory cell array 18 includes a plurality of block BLKs, each block BLK includes a plurality of string units SUs, and each string unit SU includes a plurality of memory groups MGs (memory string pairs).

[0028] As shown in Figure 2, the multiple memory groups MG are stacked in the Z direction and correspond to multiple semiconductor layers electrically connected to bit line contacts (not shown). For example, the multiple memory groups MG shown in Figure 2 correspond to regions separated by memory trenches MT (see Figures 3 and 4). Each semiconductor layer in the non-volatile semiconductor memory device 1 corresponds to a string unit SU. For example, among the selected gate lines corresponding to semiconductor layer 31 (memory group MG), the drain side is denoted as "SGD" and the source side as "SGS". The channel layer is denoted as "semiconductor layer".

[0029] Furthermore, the memory cell array 18 includes multiple memory groups MG. More specifically, each semiconductor layer 31 (string unit SU) stacked in the Z direction includes multiple memory groups MG separated in the Y direction. Each memory group MG includes two memory strings MSa and MSb, as well as selection transistors ST1 and ST2. When memory strings MSa and MSb in the non-volatile semiconductor memory device 1 are not distinguished, the memory string may be referred to as "memory string MS". Also, the selection transistor ST1 in the non-volatile semiconductor memory device 1 may be referred to as the "drain-side selection transistor", and the selection transistor ST2 in the non-volatile semiconductor memory device 1 may be referred to as the "source-side selection transistor".

[0030] For example, memory string MSa includes four memory cell transistors MCa0, MCa1, MCa2, and MCa3. Similarly, memory string MSb includes four memory cell transistors MCb0, MCb1, MCb2, and MCb3. When memory cell transistors MCa0-MCa3 and MCb0-MCb3 are not distinguished in the non-volatile semiconductor memory device 1, the memory cell transistors may be referred to as "memory cell transistor MC".

[0031] A memory cell transistor (MC) comprises a control gate and a charge storage layer, and stores data nonvolatilously. The memory cell transistor (MC) may be a MONOS type with an insulating layer in the charge storage layer, or an FG type with a conductive layer in the charge storage layer. For example, the memory cell transistor (MC) in the non-volatile semiconductor memory device 1 is of the FG type. Furthermore, for example, the number of memory cell transistors (MC) in each memory string MS may be 8, 16, 32, 48, 64, 96, or 128, and the number of memory string MS is not limited to the example shown in Figure 2. One memory cell transistor (MC) is 2 n The threshold voltage can be set to a number of values ​​(where n is a positive integer) or higher. In this case, multiple memory cells, which are the units of read and write operations, can hold n pages of data.

[0032] The memory cell transistors MCa0 to MCa3 in memory string MSa are connected in series so that their current paths are in series. Similarly, the memory cell transistors MCb0 to MCb3 in memory string MSb are connected in series so that their current paths are in series. The drains of memory cell transistors MCa0 and MCb0 are both connected to the source of selection transistor ST1. The sources of memory cell transistors MCa3 and MCb3 are both connected to the drain of selection transistor ST2. The number of selection transistors ST1 and ST2 in memory group MG is arbitrary, and there must be at least one of each. Also, for example, depending on the dimensions of the semiconductor layer 31 which functions as a channel layer (described later), the memory cell transistors MCa0 to MCa3 and MCb0 to MCb3 may function as a single memory string. In other words, the memory cell transistors MCb0, MCa0, MCb1, MCa1, MCb2, MCa2, MCb3, and MCa3 may function as a single memory string connected in series.

[0033] In a memory group MG arranged along the Z-direction, the gates of the memory cell transistors MC are commonly connected to a single word line WL via a contact plug CWL (see Figure 3). For example, the gates (gate electrodes) of multiple memory cell transistors MCa0 arranged along the Z-direction are connected to a common word line WLa0. Similarly, the gates (gate electrodes) of multiple memory cell transistors MCa1, MCa2, and MCa3 are connected to a common word line WLa1, WLa2, and WLa3, respectively. Similarly, the gates (gate electrodes) of multiple memory cell transistors MCb0 to MCb3 are connected to a common word line WLb0 to WLb3, respectively. A single page consists of multiple memory cell transistors MC connected to a common word line WL. The multiple data (threshold voltages) stored by the multiple memory cell transistors MC contained in a single page correspond to the 1-page data described later.

[0034] The drains of each selection transistor ST1 in multiple memory groups MG arranged along the Z direction are connected to different bit lines BL. The gates (gate electrodes) of each selection transistor ST1 in multiple memory groups MG arranged along the Z direction are connected to a single selection gate line SGD (e.g., SDG1). The drains of each selection transistor ST1 in multiple memory groups MG arranged along the Z direction are connected to different bit line contacts (not shown in the diagram) to the corresponding bit lines BL. The selection gate line SGD is sometimes referred to as the "drain-side selection gate line".

[0035] More specifically, for example, in the selection transistor ST1 corresponding to the memory group MG located in the uppermost layer, the drain is connected to the bit line BLk-1 and the gate electrode is connected to the selection gate line SGD1. In the selection transistor ST1 corresponding to the memory group MG located in the lowermost layer, the drain is connected to the bit line BLk+1 and the gate electrode is connected to the selection gate line SGD1. In the selection transistor ST1 corresponding to the memory group MG stacked one layer along the Z direction relative to the memory group MG located in the lowermost layer, the drain is connected to the bit line BLk and the gate electrode is connected to the selection gate line SGD1.

[0036] The source of each selection transistor ST2 in multiple memory groups MG arranged along the Z direction is connected to a single source line SL1 via a contact plug (source line contact plug CSL, conductive layer 45, see Figure 4). The gate (gate electrode) of each selection transistor ST2 in multiple memory groups MG arranged along the Z direction is connected to a single selection gate line SGS (e.g., SGS1). The selection gate line SGS is sometimes referred to as the "source-side selection gate line".

[0037] Although not shown in the diagram, the multiple memory groups MG arranged along the Z direction in the non-volatile semiconductor memory device 1 are also arranged along the Y direction. For example, the non-volatile semiconductor memory device 1 includes a configuration in which multiple memory groups MG arranged along the Z direction constitute a single memory configuration, and multiple memory configurations are arranged adjacent to each other along the Y direction.

[0038] Multiple semiconductor layers 31 (see Figures 3 and 4) are arranged in layers in the Z direction. The layered semiconductor layers 31 are separated in the Y direction by memory trenches MT that extend in the X direction. The semiconductor layers 31 separated in the Y direction in each layer extend in the Z and X directions, respectively, to form memory groups MG. Thus, the layered semiconductor layers 31 form multiple memory groups MG arranged in the Y direction. For example, the multiple layered semiconductor layers 31 in the non-volatile semiconductor memory device 1 include semiconductor layers 31 from the 1st layer to the nth layer, arranged from top to bottom along the Z direction as the 1st layer, 2nd layer, ..., the (k-1)th layer, the (k+1)th layer, ..., the (n-1)th layer, and the nth layer. Here, the numerical value k is a natural number greater than 2, and the numerical value n is a natural number greater than the numerical value k+1. For example, the multiple semiconductor layers 31 shown in Figure 2 are the (k-1)th layer, the (k)th layer, and the (k+1)th layer, arranged from top to bottom along the Z direction.

[0039] For example, the non-volatile semiconductor memory device 1 includes a substrate (not shown) having a main surface extending in the X direction (first direction) and the Y direction (second direction) intersecting the X direction. As shown in Figure 2, the non-volatile semiconductor memory device 1 includes a bit line BLk (first bit line) arranged on one side of the substrate in the Z direction (third direction) intersecting the X and Y directions and extending in the X direction, a source line SL1 arranged on one side of the substrate in the Z direction and extending in the Y and Z directions, a selection transistor ST1-k (first drain-side selection transistor) arranged on one side of the substrate in the Z direction and extending in the X direction and connected to the bit line BLk, and a selection transistor ST2 connected to the source line SL1. A first channel (k-th layer) of semiconductor layer 31 has -k (first source-side selection transistor) and a memory cell transistor MCb1(BLk) (first memory cell transistor) connected between selection transistor ST1-k and selection transistor ST2-k, and a second drain-side selection transistor ST1-k-1 (second bit line) is located on one side (upper side) in the Z direction relative to the first channel of semiconductor layer 31, extends in the X direction, and is connected to a bit line BLk-1 (second bit line) different from bit line BLk, and a source line SL A (k-1) semiconductor layer 31 (second channel) has a selection transistor ST2-k-1 (second source-side selection transistor) connected to 1, and a memory cell transistor MCb1 (BLk-1) (second memory cell transistor) connected between selection transistor ST1-k-1 and selection transistor ST2-k-1, and a bit line BLk+ which is located on the opposite side of the (k-1) semiconductor layer 31 along the Z direction from the side where the (k-1) semiconductor layer 31 is located, extends in the X direction, and is different from the bit line BLk and bit line BLk-1. A semiconductor layer 31 (third channel) of the (k+1) layer has a selection transistor ST1-k+1 (third drain-side selection transistor) connected to line 1 (third bit line), a selection transistor ST2-k+1 (third source-side selection transistor) connected to line SL1, and a memory cell transistor MCb1(BLk+1) (third memory cell transistor) connected between selection transistors ST1-k+1 and ST2-k+1, and the gate (gate electrode) of the memory cell transistor Mcb1(BLk+1),It has a word line WLb1 that functions as the gate (gate electrode) of memory cell transistor MCb1(BLk) and the gate (gate electrode) of memory cell transistor MCb1(BLk-1).

[0040] [4. Structure of the memory cell region, part of the SGD region, SGS region, and step contact region] Referring to Figures 3 and 4, an example of the planar configuration of the memory cell region MCA, part of the SGD region SGDA, and part of the SGS region SGSA will be described. Figure 3 is a planar view showing an example of the memory cell region MCA, part of the SGD region SGDA, and part of the SGS region SGSA of the memory cell array 18. Figure 4 is a planar view showing an example of the memory cell region MCA, SGS region SGSA, and step contact region SCSA corresponding to the selected gate line SGS of the memory cell array 18. The planar configurations of each region of the memory cell array 18 in the non-volatile semiconductor memory device 1 shown in Figures 3 and 4 are examples, and the planar configurations of each region of the memory cell array 18 of the non-volatile semiconductor memory device are not limited to the examples shown in Figures 3 and 4. Configurations identical or similar to those in Figures 1 and 2 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 and 2 may be omitted.

[0041] As shown in Figure 3, memory trenches MT are provided between adjacent semiconductor layers 31 arranged along the Y direction. An insulating layer (not shown) is embedded in the memory trenches MT.

[0042] In the memory cell region (MCA), an insulating layer 32 is provided on the side surface of the semiconductor layer 31. The insulating layer 32 functions as an etching stopper when forming the insulating layer 36 (tunnel insulating film) and the charge storage layer 35, which will be described later.

[0043] Furthermore, multiple word line pillars (WLPs) are provided in the memory cell region (MCA) to isolate the memory trench (MT). Each word line pillar (WLP) includes a conductive layer (33) extending in the Z direction and an insulating layer (34) in contact with the side surface of the conductive layer (33). The conductive layer (33) functions as a contact plug (CWL). The insulating layer (34) functions as a block insulating film for the memory cell transistor (MC).

[0044] Between the word line pillar (WLP) and the semiconductor layer 31, a charge storage layer 35 and an insulating layer 36 are provided, separated from the insulating layer 32 along the Y direction. The insulating layer 36 functions as a tunnel insulating film. More specifically, in the XY plane, one side of the charge storage layer 35 along the X direction is in contact with the insulating layer 34 of the word line pillar (WLP), and the other side is in contact with the insulating layer 36. The other side is the other side along the X direction and the two sides along the Y direction. Parts of the sides of the insulating layer 36 are in contact with the semiconductor layer 31 and the insulating layer 32.

[0045] Therefore, between the conductive layer 33 and the semiconductor layer 31, an insulating layer 34, a charge storage layer 35, and an insulating layer 36 are formed in order from the conductive layer 33 toward the semiconductor layer 31. The region including a part of the semiconductor layer 31, a part of the conductive layer 33, a part of the insulating layer 34, the charge storage layer 35, and the insulating layer 36 functions as a memory cell transistor MC. The region including a part of the semiconductor layer 31, a part of the conductive layer 33, a part of the insulating layer 34, the charge storage layer 35, and the insulating layer 36 is also referred to as the "intersection region between the semiconductor layer 31 and the word line pillar WLP". In the example shown in Figure 3, in one semiconductor layer 31, the intersection region between the semiconductor layer 31 and the word line pillar WLP located on the lower side of the paper in Figure 3 functions as a memory string MSa (memory cell transistor MCa), and the intersection region between the semiconductor layer 31 and the word line pillar WLP located on the upper side of the paper in Figure 3 functions as a memory string MSb (memory cell transistor MCb). Furthermore, for example, multiple memory cell transistors MCa corresponding to one semiconductor layer 31 are arranged sequentially as MCa0, MCa1, ... from the SGD region SGDA toward the SGS region SGSA. Similarly to the memory cell transistors MCa, the memory cell transistors MCb are arranged sequentially as MCb0, MCb1, ... from the SGD region SGDA toward the SGS region SGSA.

[0046] Furthermore, as shown in Figure 4, for example, the memory cell region MCA and SGS region SGSA of the memory cell array 18 may have a configuration in which four semiconductor layers 31 are independently connected in the vicinity of the SGS region SGSA, and the SGS region SGSA may be provided with a conductive layer 45 that penetrates the semiconductor layer 31. The conductive layer 45 functions as a source wire contact plug CSL. The semiconductor layer 31 has a circular shape in the connection region with the conductive layer 45. The shape of the semiconductor layer 31 in the connection region with the conductive layer 45 is arbitrary. For example, the shape of the connection region may be polygonal. The connection region should have a shape that ensures a sufficient margin in the XY plane so that when processing the hole of the source wire contact plug CSL that penetrates the semiconductor layer 31, the hole of the source wire contact plug CSL does not protrude from the semiconductor layer 31 due to manufacturing variations, etc.

[0047] Similar to the insulating layer 32 in the memory cell region (MCA), an insulating layer 46 is provided in the SGS region (SGSA) so as to surround the side surface of the semiconductor layer 31. That is, the insulating layer 46 is provided so as to be in contact with the side surface of the semiconductor layer 31. The insulating layer 46 functions as a gate insulating film for the selection transistors ST2-k-1 to ST2-k+1. The side surface of the insulating layer 46 that is in contact with the semiconductor layer 31 and the side surface opposite to the insulating layer 46 are in contact with the conductive layer 47. For example, SiO2 is used for the insulating layer 46. Preferably, the insulating layer 46 is made of an ONO film. For example, if threshold adjustment of the selection transistors ST2-k-1 to ST2-k+1 is required, it is preferable that the insulating layer 46 be made of an ONO film consisting of a three-layer structure of stacked SiO2, SiN, and SiO2, instead of an ONO film.

[0048] The conductive layer 47 functions as a selectable gate line (SGS). More specifically, the conductive layer 47 includes a first portion extending in the Y direction and a plurality of second portions in the SGS region (SGSA) where one side contacts the insulating layer 46 and the ends contact the first portion of the conductive layer 47. A conductive material is used for the conductive layer 47. The conductive material may be, for example, a metallic material, a semiconductor such as Si with impurities added, or phosphorus (P) added polysilicon.

[0049] In the SGS region SGSA, the region including the semiconductor layer 31 from the memory cell region MCA to the conductive layer 45, the insulating layer 46, and the second portion of the conductive layer 47 functions as the selection transistor ST2. More specifically, the second portion of the conductive layer 47 functions as the gate electrode of the selection transistor ST2, the insulating layer 46 functions as the gate insulating film of the selection transistor ST2, and the channel of the selection transistor ST2 is formed in the semiconductor layer 31.

[0050] A conductive layer 49 and an insulating layer 44, penetrating the first portion of the conductive layer 47, are provided in the stepped contact region SCSA. The conductive layer 49 functions as a contact plug CSGS. The insulating layer 44 functions as a dummy pillar HR. For example, the conductive layer 49 is connected to each of the first portions of the conductive layer 47 stacked in the Z direction. An insulating layer 40i is formed between the unconnected conductive layer 47 and conductive layer 49. The insulating layer 40i is composed of insulating layers 41, 42, and 43. The insulating layer 41 is provided so as to be in contact with the side surface of the conductive layer 49. The side surface of the conductive layer 49 is also referred to as the "outer surface". The insulating layer 42 is provided so as to be in contact with a part of the outer surface of the insulating layer 41. The insulating layer 43 is provided so as to be in contact with the outer surface of the insulating layer 42. A conductive material is used for the conductive layer 49. The conductive material may be, for example, a metallic material, and more specifically, W and TiN may be used. For example, a stepped contact region SCSA is a region in which multiple selection gate lines SGS (including multiple selection gate lines SGS such as SGS0, SGS1, SGS2, SGS3, ...) are arranged in a stepped manner.

[0051] Furthermore, as shown in Figure 3, for example, the insulating layer 38 in the SGD region SGDA is provided so as to surround the side surface of the semiconductor layer 31, similar to the insulating layer 46 in the SGS region SGSA. The insulating layer 38 functions as a gate insulating film of the selected transistor ST1. The insulating layer 38 may be made of the same insulating material as the insulating layer 46.

[0052] The insulating layer 38 has a side facing the semiconductor layer 31 that is in contact with the conductive layer 39. The conductive layer 39 functions as a selected gate line SGD. More specifically, the conductive layer 39 includes a first portion (not shown) extending in the Y direction and a plurality of second portions in the SGD region SGDA, one of which is in contact with the insulating layer 38 and the end of which is in contact with the first portion of the conductive layer 39. The conductive layer 39 may be made of the same conductive material as the conductive layer 47.

[0053] Furthermore, similar to the selection transistor ST2 in the SGS region SGSA, in the SGD region SGDA, the region including the semiconductor layer 31 from the memory cell region MCA to the conductive layer 39, the insulating layer 38, and the second portion of the conductive layer 39 functions as the selection transistor ST1. More specifically, the second portion of the conductive layer 39 functions as the gate electrode of the selection transistor ST1, the insulating layer 38 functions as the gate insulating film of the selection transistor ST1, and the channel of the selection transistor ST1 is formed in the semiconductor layer 31.

[0054] Although not shown in the diagram, for example, in the SGD region SGDA, similar to the SGS region SGSA, four semiconductor layers 31 are independently connected in the vicinity of the SGD region SGDA, and a conductive layer that penetrates the semiconductor layers 31 and functions as a contact plug may be provided. The semiconductor layers 31 in the SGD region SGDA may have a circular shape in the connection region with the conductive layer that functions as a contact plug, similar to the SGS region SGSA. The conductive layer that functions as a contact plug may be made of the same conductive material as the conductive layer 45 (source line contact plug CSL). Although not shown in the diagram, a stepped contact region corresponding to the SGD region SGDA may be provided on the SGD region SGDA side, similar to the stepped contact region SCSA on the SGS region SGSA side. The stepped contact region corresponding to the SGD region SGDA is a stepped contact region corresponding to the selected gate line SGD, and is, for example, a region in which multiple selected gate lines SGD (including multiple selected gate lines SGD such as SGD0, SGD1, SGD2, SGD3, ...) are provided in a stepped manner.

[0055] [5. Circuit configuration of the sense amplifier unit] Referring to Figure 5, an example of the circuit configuration of the sense amplifier unit SAU will be explained. Figure 5 is an example of the circuit configuration of the sense amplifier unit SAU. Note that the circuit configuration of the sense amplifier unit SAU shown in Figure 5 is just one example, and the circuit configuration of the sense amplifier unit SAU of the non-volatile semiconductor memory device 1 is not limited to the example shown in Figure 5. Explanations of configurations that are the same as or similar to those in Figures 1 to 4 will be explained as necessary, and explanations of configurations that are the same as or similar to those in Figures 1 to 4 may be omitted.

[0056] The sense amplifier module 20 includes multiple sense amplifier units SAU, each associated with a bit line BL1 to BLm (where m is a natural number greater than or equal to 2). Figure 5 shows the circuit configuration of one sense amplifier unit SAU.

[0057] For example, the sense amplifier unit SAU can temporarily hold the data read on the corresponding bit line BL. Furthermore, the sense amplifier unit SAU can perform logical operations using the temporarily stored data and can temporarily hold the data after the logical operations. For instance, the non-volatile semiconductor memory device 1 can perform read and write operations using the sense amplifier module 20 (sense amplifier unit SAU).

[0058] As shown in Figure 5, the sense amplifier unit SAU includes a sense amplifier section SA, and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS so that they can send and receive data from each other.

[0059] For example, in a read operation, the sense amplifier section SA senses the data read to the corresponding bit line BL and determines whether the read data is "0" or "1". The sense amplifier section SA includes, for example, a p-channel MOS transistor 120, n-channel MOS transistors 121 to 128, and a capacitor 129.

[0060] One end of transistor 120 is connected to the power line, and the gate of transistor 120 is connected to node INV in the latch circuit SDL. One end of transistor 121 is connected to the other end of transistor 120, and the other end of transistor 121 is connected to node COM, and the control signal BLX is input to the gate of transistor 121. One end of transistor 122 is connected to node COM, and the control signal BLC is input to the gate of transistor 122. Transistor 123 is a high-voltage MOS transistor, one end of transistor 123 is connected to the other end of transistor 122, and the other end of transistor 123 is connected to the corresponding bit line BL, and the control signal BLS is input to the gate of transistor 123.

[0061] One end of transistor 124 is connected to node COM, the other end of transistor 124 is connected to node SRC, and the gate of transistor 124 is connected to node INV. One end of transistor 125 is connected to the other end of transistor 120, the other end of transistor 125 is connected to node SEN, and the control signal HLL is input to the gate of transistor 125. One end of transistor 126 is connected to node SEN, the other end of transistor 126 is connected to node COM, and the control signal XXL is input to the gate of transistor 126.

[0062] One end of transistor 127 is grounded, and the gate of transistor 127 is connected to node SEN. One end of transistor 128 is connected to the other end of transistor 127, and the other end of transistor 128 is connected to bus LBUS, and the control signal STB is input to the gate of transistor 128. One end of capacitor 129 is connected to node SEN, and the clock CLK is input to the other end of capacitor 129.

[0063] For example, the control signals BLX, BLC, BLS, HLL, XXL, and STB are generated by the sequencer 15. Also, for example, a voltage VDD (second voltage), which is the internal power supply voltage of the non-volatile semiconductor memory device 1, is applied to the power line connected to one end of the transistor 120. Also, for example, a voltage VSS (first voltage) of the non-volatile semiconductor memory device 1 is applied to node SRC. For example, voltage VSS is a voltage that can define other voltages with respect to voltage VSS, and voltage VSS may be a reference voltage, may be 0V, or may be ground potential (earth potential).

[0064] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold the read data. For example, the latch circuit XDL is connected to the data register 21 and is used for data input and output between the sense amplifier unit SAU and the input / output circuit 10.

[0065] For example, the latch circuit SDL includes inverters 130 and 131, and n-channel MOS transistors 132 and 133. The input node of inverter 130 is connected to node LAT, and the output node of inverter 130 is connected to node INV. The input node of inverter 131 is connected to node INV, and the output node of inverter 131 is connected to node LAT. One end of transistor 132 is connected to node INV, and the other end of transistor 132 is connected to bus LBUS, and the control signal STI is input to the gate of transistor 132. One end of transistor 133 is connected to node LAT, and the other end of transistor 133 is connected to bus LBUS, and the control signal STL is input to the gate of transistor 133. For example, the data held at node LAT corresponds to the data held in the latch circuit SDL, and the data held at node INV corresponds to the inverted data of the data held at node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are similar to, for example, the circuit configuration of latch circuit SDL, so their explanation is omitted.

[0066] The timing at which each sense amplifier unit SAU in the sense amplifier module 20 determines the data read to the bit line BL is based on the timing at which the control signal STB is asserted. In this specification, "the sequencer 15 asserts the control signal STB" corresponds to the sequencer 15 changing the control signal STB from the "L" level to the "H" level.

[0067] Note that the configuration of the sense amplifier module 20 in the non-volatile semiconductor memory device 1 is not limited to the configuration shown in Figure 5. For example, in the sense amplifier unit SAU, the transistor 128 to which the control signal STB is input to the gate may be a p-channel MOS transistor. In this case, "the sequencer 15 asserts the control signal STB" corresponds to the sequencer 15 changing the control signal STB from an "H" level to an "L" level.

[0068] Furthermore, the number of latch circuits in the sense amplifier unit SAU can be set to any number. For example, in this case, the number of latch circuits is designed based on the number of bits of data held by a single memory cell transistor MC. Also, multiple bit lines BL may be connected to a single sense amplifier unit SAU via a selector.

[0069] [6. Threshold distribution of memory cell transistors] Referring to Figure 6, an example of the threshold distribution of a memory cell transistor (MC) will be explained. Figure 6 is a threshold distribution diagram showing an example of the threshold distribution of a memory cell transistor (MC). Note that the threshold distribution of the memory cell transistor (MC) of the non-volatile semiconductor memory device 1 is not limited to the example shown in Figure 6. Configurations identical or similar to those in Figures 1 to 5 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0070] For example, the non-volatile semiconductor memory device 1 uses the TLC (Triple-Level Cell) method, which stores 3 bits of data in a single memory cell transistor MC, as the writing method for the memory cell transistor MC.

[0071] Figure 6 shows examples of the threshold distribution, data allocation, read voltage, and verify voltage of memory cell transistors (MCs) in a TLC (Transistor-Low Cell) system. In the threshold distribution shown in Figure 6, the vertical axis corresponds to the number of memory cell transistors (MCs), and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistors (MCs).

[0072] As shown in Figure 6, the multiple memory cell transistors (MCs) in the TLC system form eight threshold distributions. These eight threshold distributions (write levels, program target levels) are referred to as "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from lowest to highest threshold voltage. Different 3-bit data are assigned to each of the "Er" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, for example, as shown below. “Er” level: “111” (“lower bit / middle bit / higher bit”) data "A" Level: "011" Data "B" Level: "001" Data "C" level: "000" data "D" Level: "010" Data "E" level: "110" data "F" level: "100" data “G” level: “101” data In other words, TLC has two configurable memory cell transistors (MCs). n This corresponds to the case where the numerical value n is 3 at threshold voltages of a certain number (where n is a positive integer) or higher.

[0073] Between adjacent threshold distributions, a verification voltage used for the write operation is set. Specifically, verification voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to the "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, respectively.

[0074] For example, the verify voltage AV is set between the maximum threshold voltage at the "Er" level and the minimum threshold voltage at the "A" level. When the verify voltage AV is applied to a memory cell transistor MC, memory cell transistors MC whose threshold voltage falls within the "Er" level are turned ON, and memory cell transistors MC whose threshold voltage falls within the threshold distribution of the "A" level or higher are turned OFF.

[0075] Additionally, other verify voltages such as BV, CV, DV, EV, FV, and GV are set similarly to verify voltage AV. Verify voltage BV is set between level "A" and level "B", verify voltage CV is set between level "B" and level "C", verify voltage DV is set between level "C" and level "D", verify voltage EV is set between level "D" and level "E", verify voltage FV is set between level "E" and level "F", and verify voltage GV is set between level "F" and level "G".

[0076] For example, the verify voltage AV may be set to 0.8V, the verify voltage BV to 1.6V, the verify voltage CV to 2.4V, the verify voltage DV to 3.1V, the verify voltage EV to 3.8V, the verify voltage FV to 4.6V, and the verify voltage GV to 5.6V. Note that the verify voltages AV, BV, CV, DV, EV, FV, and GV are not limited to the examples shown here. For example, the verify voltages AV, BV, CV, DV, EV, FV, and GV may be set in steps as appropriate within the range of 0V to 7.0V.

[0077] Furthermore, between adjacent threshold distributions, the read voltages used for each read operation may be set. For example, the read voltage AR used to determine whether the threshold voltage of a memory cell transistor MC falls within the "Er" level or above the "A" level is set between the maximum threshold voltage at the "Er" level and the minimum threshold voltage at the "A" level.

[0078] Other read voltages BR, CR, DR, ER, FR, and GR may be set similarly to read voltage AR. For example, read voltage BR may be set between level "A" and level "B", read voltage CR between level "B" and level "C", read voltage DR between level "C" and level "D", read voltage ER between level "D" and level "E", read voltage FR between level "E" and level "F", and read voltage GR between level "F" and level "G".

[0079] Furthermore, the read path voltage VREAD is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., the "G" level). When the read path voltage VREAD is applied to the gate of a memory cell transistor MC, it turns ON regardless of the data being stored.

[0080] For example, the verify voltages AV, BV, CV, DV, EV, FV, and GV are set to higher voltages than the read voltages AR, BR, CR, DR, ER, FR, and GR. In other words, the verify voltages AV, BV, CV, DV, EV, FV, and GV are set near the lower tail of the threshold distributions for the "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0081] For example, when the data allocation described above is applied, the lower-level bit page data is determined by the read results using read voltages AR and ER during the read operation. The middle-level bit page data is determined by the read results using read voltages BR, DR, and FR. The upper-level bit page data is determined by the read results using read voltages CR and GR. Thus, since the lower-level, middle-level, and upper-level page data are determined by two, three, and two read operations, respectively, this data allocation is called the "2-3-2 code".

[0082] Note that the number of bits of data stored in a single memory cell transistor MC and the data assignment to the threshold distribution of the memory cell transistor MC, as explained with reference to Figure 6, are examples and are not limited to the examples shown in Figure 6. For example, 2 bits or 4 bits or more of data may be stored in a single memory cell transistor MC. Also, each read voltage and read path voltage may be set to the same voltage value in each method, or they may be set to different voltage values.

[0083] [7. Overview of Write and Read Operations] Referring to Figure 7, the operation method of the memory cell array shown in Figure 2 will be explained. Figure 7 is a diagram showing an example of a program loop in the non-volatile semiconductor memory device 1. Note that the program loop of the non-volatile semiconductor memory device 1 is not limited to the example shown in Figure 7. Configurations identical or similar to those in Figures 1 to 6 will be explained as necessary, and explanations of identical or similar configurations in Figures 1 to 6 may be omitted.

[0084] For example, as explained in "3. Memory Cell Array Configuration," if the number of semiconductor layers 31 is n, then the region separated by the memory trench MT contains n memory groups MG stacked in the Z direction. Each string unit SU constitutes one block BLK that operates simultaneously. Write, read, and erase operations are performed on a block BLK basis.

[0085] The non-volatile semiconductor memory device 1 repeatedly executes a program loop during a write operation. The program loop includes a program operation and a verify operation. The program operation is an operation that increases the threshold voltage of the selected memory cell transistor MC by injecting electrons into the charge storage layer of the selected memory cell transistor MC. Alternatively, the program operation is an operation that maintains the threshold voltage of the selected memory cell transistor MC by prohibiting the injection of electrons into the charge storage layer. The verify operation is an operation that follows the program operation and checks whether the threshold voltage of the selected memory cell transistor MC has reached the target level by performing a read operation using the verify voltage. The selected memory cell transistor MC whose threshold voltage has reached the target level is then disabled for writing.

[0086] The non-volatile semiconductor memory device 1 repeatedly executes a program loop including the program operation and verify operation described above, thereby raising the threshold voltage of the selected memory cell transistor MC to the target level.

[0087] Electrons stored in the charge storage layer may be stored in an unstable state. Therefore, from the time the above-described program operation is completed, electrons stored in the charge storage layer of the memory cell transistor MC may leave the charge storage layer over time. When electrons leave the charge storage layer, the threshold voltage of the memory cell transistor MC decreases. Therefore, in the read operation performed after the completion of the write operation, a read voltage lower than the verify voltage is used to address this decrease in the threshold voltage of the memory cell transistor that may occur over time. Note that the read operation may include a verify operation. Furthermore, in this specification, each operation of the non-volatile semiconductor memory device 1 is included in its respective operation method. More specifically, the write operation of the non-volatile semiconductor memory device 1 is included in the write operation method, the read operation of the non-volatile semiconductor memory device 1 is included in the read operation method, the erase operation of the non-volatile semiconductor memory device 1 is included in the erase operation method, and the verify operation of the non-volatile semiconductor memory device 1 is included in the verify operation method.

[0088] For example, the example program loop shown in Figure 7 shows the program target levels ("Er" level to "G" level) vertically and the number of times the program loop is executed in the non-volatile semiconductor memory device 1 (loop count) horizontally. In addition, the "○" in Figure 7 indicates the program target level to which the program operation is targeted in each loop, and the "-" in Figure 7 indicates the program target level to which the program operation is not targeted in each loop.

[0089] For example, as shown in Figure 7, the number of loops in the non-volatile semiconductor memory device 1 is 7. Also, referring to Figure 7, the memory cell transistor MC targeting level "A" is subject to programming in the first loop, but not in subsequent loops. Similar to the memory cell transistor MC targeting level "A", the memory cell transistor MC targeting level "B" is subject to programming in the first and second loops, but not in subsequent loops. The memory cell transistor MC targeting levels "C" to "G" are subject to programming, similar to the memory cell transistor MC targeting level "A" and the memory cell transistor MC targeting level "B".

[0090] [7-1. Example of writing operation] Referring to Figures 2, 8 to 11, an example of the writing operation of a non-volatile semiconductor device in a comparative example will be explained. Referring to Figures 2, 9, 12, and 13, an example of the writing operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 will be explained.

[0091] Figure 8 is a timing chart showing an example of a write operation in a non-volatile semiconductor memory device according to a comparative example, and is a timing chart showing an example of the time change of voltages applied to various circuit components. Figure 9 is a perspective view showing an example of a channel layer in a non-volatile semiconductor memory device 1, and is a schematic diagram focusing on the memory string MSb among the memory strings of each semiconductor layer 31 shown in Figure 2. Figures 10 and 11 are schematic diagrams showing an example of the state of the channel layer in a non-volatile semiconductor memory device in a comparative example. Figure 12 is a timing chart showing a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1, and is a timing chart showing an example of the time change of voltages applied to various circuit components. Figure 13 is a threshold distribution diagram showing an example of the threshold distribution of a memory cell transistor MC.

[0092] The timing charts shown in Figures 8 and 12 are merely examples illustrating the time variation of voltages applied to various circuit components, and do not necessarily accurately depict the voltage supplied to the word line WL, the potential changes of the selection gate lines SGD and SGS, etc. Furthermore, the perspective views and diagrams showing the channel layer and its state shown in Figures 9 to 12, as well as the threshold distribution of the memory cell transistor MC of the non-volatile semiconductor memory device 1 shown in Figure 13, are schematic representations, and are not limited to the examples shown in Figures 9 to 13. Also, configurations identical or similar to those in Figures 1 to 7 will be explained as necessary, and explanations of identical or similar configurations may be omitted. When explaining the writing operation of the non-volatile semiconductor device in the comparative example, if the non-volatile semiconductor device in the comparative example includes a configuration similar to that of the non-volatile semiconductor memory device 1, the same reference numerals as those used in the non-volatile semiconductor memory device 1 will be used for explanation.

[0093] In the following explanation, we will focus on the memory string MSb among the memory strings of each semiconductor layer 31. The selected gate line SGD connected to the memory cell transistor MC that is the target of operation in each memory string MS is denoted as the selected gate line SEL-SGD, and the selected gate line SGD connected to other memory cell transistors MC is denoted as the unselected gate line USEL-SGD. The word line WL connected to the memory cell transistor MC that is the target of operation in each memory string MS is denoted as the selected word line SEL-WL, and the word lines connected to other memory cell transistors MC are denoted as the unselected word line USEL-WL. Among the memory strings of each semiconductor layer 31, the bit line BL connected to the memory string containing the memory cell transistor MC that is the target of operation is denoted as the bit line ProgramBL. The bit line BL connected to the memory string containing a memory cell transistor MC other than the target of operation is denoted as the bit line InhibitBL. Note that in the write operation, the voltage supplied to the selected gate line SGS connected to the memory cell transistor MC in each memory string MS is the voltage VSS, and the selected gate line SGS is not distinguished by the memory cell transistor MC in each memory string MS and is denoted as "selected gate line SGS".

[0094] For example, a memory cell transistor (MC) that is the target of operation is one on which data (threshold voltage) is written, while memory cell transistors (MCs) other than the target of operation are memory cell transistors (MCs) on which data (threshold voltage) is not written. For example, memory cell transistors (MCs) other than the target of operation are referred to as "memory cell transistors that are not the target of operation."

[0095] Furthermore, each of the multiple bit lines BL (e.g., BLk-1, BLk, BLk) is connected to the sense amplifier unit SAU corresponding to each of the multiple bit lines BL. Also, as shown in Figure 6, for example, transistor 122 included in the sense amplifier unit SAU is controlled to be on and off based on the voltage supplied to the control signal BLC, and transistor 123 included in the sense amplifier unit SAU is controlled to be on and off based on the voltage supplied to the control signal BLS. When 123 is on, the sense amplifier unit SAU supplies the voltage VDD and the data (threshold voltage) stored in the latch circuits SDL, ADL, BDL, CDL, or XDL to the bit line BL. Note that the operation of transistor 123 in the writing operation of the memory cell array 18 of the non-volatile semiconductor memory device 1 is the same as the operation of transistor 122, and therefore, in the explanation of the writing operation of the memory cell array 18 of the non-volatile semiconductor memory device 1, the operation of transistor 122 will be explained, and the explanation of the operation of transistor 123 will be omitted.

[0096] Furthermore, as shown in the memory string MSb in Figure 9, for example, the (k+1)th semiconductor layer 31 is denoted as channel layer (k+1) (Channel(k+1)), the (k)th semiconductor layer 31 is denoted as channel layer (k) (Channel(k)), and the (k-1)th semiconductor layer 31 is denoted as channel layer (k-1) (Channel(k-1)). Referring to Figures 2 and 9, the bit line BL, selected gate line SGD, and SGS connected to Channel(k+1) are bit line BLk+1, selected gate line SGD1, and SGS1; the bit line BL, selected gate line SGD, and SGS connected to Channel(k) are bit line BLk, selected gate line SGD1, and SGS1; and the bit line BL, selected gate line SGD, and SGS connected to Channel(k-1) are bit line BLk-1, selected gate line SGD1, and SGS1. Furthermore, the voltages shown in Figure 8 or Figure 12 are supplied to the respective selection gate lines SGD and SGS.

[0097] Furthermore, referring to Figures 2 and 9, memory cell transistors MCb1(BLk-1), MCb1(BLk), and Mcb1(BLk+1) are connected to the same selection word line SEL-WLb1 and are memory cell transistors MC within the same page controlled by the same selection word line SEL-WLb1, the same selection gate lines SGD1 and SGS1. As mentioned above, Figure 9 is a schematic diagram focusing on the memory string MSb, and is a schematic diagram showing multiple memory cell transistors MC (MCb1(BLk-1), MCb1(BLk), Mcb1(BLk+1)) connected to the same selection word line SEL-WLb1 within the memory string MSb, and is a schematic diagram showing one of the multiple memory cell transistors MC connected to the same selection word line SEL-WLb1.

[0098] Furthermore, the program target level for memory cell transistor MCb1(BLk-1) is "G" level (program target "G"). The program target level for memory cell transistor MCb1(BLk) is "Er" level (program target "Er"), and the program target level for memory cell transistor MCb1(BLk-1) is "D" level (program target "D").

[0099] Furthermore, the memory controller 2 transmits a signal (write operation signal) to the non-volatile semiconductor memory device to instruct it to perform a data writing operation. For example, when the non-volatile semiconductor memory device receives the write operation signal, the sequencer 15, via the logic control circuit 11, input / output circuit 10, and command register 14, controls the sense amplifier module 20, the row decoder 19, the voltage generation circuit 17, etc., based on the write operation signal to perform the write operation. For example, the voltage generation circuit 17, sense amplifier module 20, and row decoder 19 controlled by the sequencer 15 are supplied with voltage to the word line WL, the selection gate line SGD, the selection gate line SGS, the source line SL, the bit line BL, the control signal BLS, the control signal BLC, etc.

[0100] [7-1-1. An example of writing operation of a non-volatile semiconductor device in a comparative example] First, an example of the writing operation of a non-volatile semiconductor device in a comparative example will be explained with reference to Figures 8 to 11. [7-1-1-1. Example of write operation up to time T0] The write operation up to time T0 includes putting the non-volatile semiconductor memory device 1 into a standby state. For example, the standby state is a state in which the non-volatile semiconductor memory device 1 is waiting for data to be written.

[0101] As shown in Figure 8, until time T0, the following are supplied with voltage VSS: selected gate line SEL-SGD (SGD1), unselected gate line USEL-SGD (SGD0, SGD2, SGD3, ...), selected gate line SGS (SGS0, SGS1, SGS3, ...), selected word line SEL-WLb1, unselected word lines USEL-WL other than selected word line SEL-WLb1, bit line ProgramBL, bit line InhibitBL, channels of memory cell transistors subject to operation, channels of memory cell transistors not subject to operation, and control signal BLC.

[0102] As shown in Figure 8, since voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state.

[0103] [7-1-1-2. Example of a write operation between time T0 and T1] Next, the write operation at time T0 to T1 will be described. For example, the write operation at time T0 to T1 includes supplying voltage VSGPCH to the selected gate line SEL-SGD and the unselected gate line USEL-SGD, and supplying voltage VCHPCH to the selected word line SEL-WLb1 and the unselected word line USEL-WL.

[0104] As shown in Figure 8, at times T0 to T1, the selected gate line SEL-SGD and the unselected gate line USEL-SGD are supplied with the voltage VSGPCH, and the selected word line SEL-WLb1 and the unselected word line USEL-WL are supplied with the voltage VSGPCH. In addition, the voltage supplied to the control signal BLC gradually increases toward the voltage VDD+VTH. Furthermore, the selected gate line SGS, the bit line ProgramBL, the bit line InhibitBL, the channels of memory cell transistors that are subject to operation, and the channels of memory cell transistors that are not subject to operation are supplied with the voltage VSS, as in the case up to time T0.

[0105] Based on the voltage supplied to each control line at time T1, the selection transistors ST1-k-1, ST1-k, and ST1-k+1, the memory cell transistors MCb0~MCb3, and the memory cell transistors MCa0~MCa3 are turned ON, while the selection transistors ST2-k-1, ST2-k, and ST2-k+1 remain OFF.

[0106] As a result, at time T1, the voltage VSS supplied to bit line BLk-1 is supplied to the selection transistor ST1-k-1 and the respective channels (k-1) of the memory cell transistors MCb0 to MCb3 connected to the selection transistor ST1-k-1, the voltage VSS supplied to bit line BLk is supplied to the selection transistor ST1-k and the respective channels (k) of the memory cell transistors MCb0 to MCb3 connected to the selection transistor ST1-k, and the voltage VSS supplied to bit line BLk+1 is supplied to the selection transistor ST1-k+1 and the respective channels (k+1) of the memory cell transistors MCb0 to MCb3 connected to the selection transistor ST1-k+1.

[0107] [7-1-1-3. Example of a write operation at time T1 to T2] Next, the write operation at times T1 to T2 will be described. The write operation at times T1 to T2 is an operation to precharge the bit line InhibitBL and the channels of memory cell transistors that are not subject to operation. For example, the write operation at times T1 to T2 includes supplying voltage VDD to the bit line InhibitBL and supplying voltage VDD to the channels of memory cell transistors connected to the bit line InhibitBL that are not subject to operation.

[0108] As shown in Figure 8, at times T1 to T2, the control signal BLC is supplied with the voltage VDD+VTH. Also, similar to time T1, the selected gate line SEL-SGD and the unselected gate line USEL-SGD are supplied with the voltage VSGPCH, the selected word line SEL-WLb1 and the unselected word line USEL-WL are supplied with the voltage VSGPCH, and the selected gate line SGS is supplied with the voltage VSS.

[0109] Based on the voltage supplied to each control line at time T2, the selection transistors ST1-k-1, ST1-k, and ST1-k+1, memory cell transistors MCb0~MCb3, and memory cell transistors MCa0~MCa3 remain ON, while the selection transistors ST2-k-1, ST2-k, and ST2-k+1 remain OFF. When the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the sense amplifier unit SAU connected to the bit line ProgramBL turns ON, and voltage VSS is supplied to the bit line ProgramBL, as well as to the channels of the memory cell transistors that are to be operated. When the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the sense amplifier unit SAU connected to the bit line InhibitBL turns ON, and voltage VDD is supplied to the bit line InhibitBL, as well as to the channels of the memory cell transistors that are not to be operated. Note that voltage VDD is supplied to multiple bit line InhibitBLs at the same timing.

[0110] [7-1-1-4. Example of a write operation at time T2~T3] Next, the write operation at times T2 to T3 will be explained. As shown in Figure 8, at times T2 to T3, the voltage supplied to the selected gate line SEL-SGD and the unselected gate line USEL-SGD changes from voltage VSGPCH to voltage VSS, and the voltage supplied to the selected word line SEL-WLb1 and the unselected word line USEL-WL also changes from voltage VSGPCH to voltage VSS. Also, similar to time T2, voltage VSS is supplied to the selected gate line SGS, the bit line ProgramBL, the channel of the memory cell transistor to be operated on, and the control signal BLC, while voltage VDD is supplied to the bit line InhibitBL and the memory cell transistor that is not to be operated on. Therefore, since voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state.

[0111] [7-1-1-5. Example of a write operation at time T3~T4] Next, the write operation at times T3 to T4 will be described. The write operation at times T3 to T4 includes boosting the channels of memory cell transistors that are not the target of the operation from a state where voltage VDD is supplied to a state where voltage VCHA is supplied.

[0112] As shown in Figure 8, at times T3 to T4, the selected gate line SEL-SGD changes from being supplied with voltage VSS to being supplied with voltage VSG, the unselected gate line USEL-SGD is supplied with voltage VSS, the selected word line SEL-WLb1 and the unselected word line USEL-WL change from being supplied with voltage VSS to being supplied with voltage VPASS, and the control signal BLC changes from being supplied with voltage VSS to being supplied with voltage VBLC. Also, similar to time T3, the selected gate line SGS, the bit line ProgramBL, and the channels of memory cell transistors that are subject to operation are supplied with voltage VSS, while the bit line InhibitBL and the channels of memory cell transistors that are not subject to operation are supplied with voltage VDD.

[0113] The voltage VSS supplied to the bit line ProgramBL is sufficiently lower than the voltage VSG supplied to the selection gate line SEL-SGD. Therefore, the selection transistor ST1 connected to the bit line ProgramBL is turned ON, and the voltage VSS is supplied to the channel of the memory cell transistor being operated. The voltage VDD supplied to the bit line InhibitBL is sufficiently higher than the voltage VSG supplied to the selection gate line SEL-SGD. Therefore, the voltage VSG supplied to the gate of the selection transistor ST1 connected to the bit line InhibitBL is relatively low, and the selection transistor ST1 is turned OFF. The voltage VPASS is supplied to the selection word line WLb1 and the non-selection word line WL, and the memory cell transistors MC in each layer are turned ON.

[0114] Therefore, the bit line InhibitBL and the channel of the memory cell transistor that is not to be operated are electrically disconnected. As a result, the capacitive coupling between the channel of the memory cell transistor that is not to be operated and the unselected word line USEL-WL causes the channel of the memory cell transistor that is not to be operated to be boosted from a state where voltage VDD is supplied to a state where voltage VCHA is supplied.

[0115] [7-1-1-6. Example of a write operation at time T4~T5] Next, the write operation at time T4 to T5 will be explained. The write operation at time T4 to T5 is the operation of writing a threshold voltage corresponding to the program target level to the memory cell transistor that is the target of the operation. As shown in Figure 8, at time T4 to T5, the selection gate line SEL-SGD (SGD1) is supplied with voltage VSG, the bit line ProgramBL is supplied with voltage VSS, and the selection transistor ST1 connected to the bit line ProgramBL remains in the ON state. Also, the bit line InhibitBL is supplied with voltage VDD, and the selection transistor ST1 connected to the bit line InhibitBL becomes OFF. The selection word line SEL-WLb1 changes from being supplied with voltage VPASS to being supplied with voltage VPGM, and the memory cell transistor MC electrically connected to the selection word line SEL-WLb1 becomes ON. Also, similar to time T4, the voltage supplied to the channels of the memory cell transistors that are being operated remains at voltage VSS, the voltage supplied to the channels of the memory cell transistors that are not being operated remains at voltage VCHA, the selection gate line SGS is supplied with voltage VSS, the selection transistor ST2 remains in the off state, and the control signal BLC remains supplied with voltage VBLC.

[0116] For example, when the selection word line SEL-WLb1 is supplied with voltage VPGM and the memory cell transistor to be operated is turned ON, the bit line ProgramBL changes from being supplied with voltage VSS to being supplied with a voltage corresponding to the program target level. For example, voltage VPGM is a voltage sufficiently higher than the voltage corresponding to the program target level. Therefore, the memory cell transistor to be operated is given an electric field due to the potential difference between the channel voltage VSS and the voltage VPGM of the selection word line SEL-WLb1, and electrons are injected into the charge storage layer of the memory cell transistor. As a result, the memory cell transistor to be operated is programmed with a program corresponding to the program target level, and the threshold voltage of the memory cell transistor rises. Note that voltage VPGM is sometimes referred to as the "write voltage".

[0117] The channels of memory cell transistors that are not to be programmed and connected to the bit line InhibitBL maintain a state where voltage VCHA is supplied. Therefore, an electric field is applied to the memory cell transistors that are not to be programmed due to the potential difference between the channel voltage VCHA and the voltage VPGM of the selection word line SEL-WLb1. If the potential difference between voltage VCHA and voltage VPGM is sufficiently small, electrons are not injected (or only very small amounts are injected) into the charge storage layer of the memory cell transistors that are not to be programmed. As a result, the memory cell transistors that are not to be programmed are not programmed, and the threshold voltage of those memory cell transistors does not rise (or rises only very slightly).

[0118] [7-1-1-7. Specific Examples of Writing Operations of Non-Volatile Semiconductor Devices in Comparative Examples] First, referring to Figures 8 and 10, we will explain specific examples of the first to fourth loops in the program loop shown in Figure 7.

[0119] When the voltage VPGM is supplied to the selection word line SEL-WLb1 shown in Figure 8, the voltage VSS is supplied to Channel(k-1) from the bit line BLk-1 via the selection transistor ST1-k-1, and the voltage VSS is supplied to Channel(k+1) from the bit line BLk+1 via the selection transistor ST1-k+1. As a result, the threshold voltages of the memory cell transistor MCb1(BLk-1) in the k-1 layer and the memory cell transistor MCb1(BLk+1) in the k+1 layer increase.

[0120] On the other hand, when the voltage VDD is supplied to the bit line BLk, the selection transistor ST1-k connected to the bit line BLk is cut off, so Channel(k) is in a floating state.

[0121] As a result, for example, when the voltage VPASS is supplied to the selection word line SEL-WLb1, Channel(k) is boosted from a state where voltage VDD is supplied to a state where voltage VCH1 is supplied. Therefore, even if the voltage supplied to the selection word line SEL-WLb1 increases from voltage VPASS to voltage VPGM, the potential difference between the voltage supplied to the selection word line SEL-WLb1 and the voltage supplied to Channel(k) does not increase. Consequently, the threshold voltage of the memory cell transistor MCb1(BLk), which includes a portion of Channel(k), does not increase.

[0122] Next, referring to Figures 8 and 11, we will explain specific examples of the 5th to 7th loops in the program loop shown in Figure 7. In the 5th to 7th program loops, memory cell transistors with a program target level of "D" are not subject to operation, but memory cell transistors with a program target level of "G" are subject to operation. Therefore, the voltage VPGM is supplied to the selection word line SEL-WLb1.

[0123] In other words, as shown in Figure 8 for the bit line InhibitBL and the channel of the memory cell transistor that is not subject to operation, the bit line BLk+1 and Channel(k+1) connected to bit line BLk+1 are supplied with voltage VDD, just like the bit line BLk and Channel(k) connected to bit line BLk. As a result, the selection transistor ST1-k+1 is cut off, and Channel(k+1) is in a floating state. Therefore, Channel(k+1) is boosted, just like Channel(k). As a result, the voltage VPGM is supplied to the selection word line SEL-WLb1, and Channel(k+1) is boosted from the state where voltage VDD is supplied (see the channel of the memory cell transistor that is not subject to operation in Figure 8) to the state where voltage VCH2 is supplied (see Channel(k+1) in Figure 11).

[0124] Here, the memory cell transistor MCb1(BLk), which includes part of Channel(k), has a program target at the "Er" level, and when the voltage VPGM is supplied to the selection word line SEL-WLb1, Channel(k) is boosted from a state where voltage VDD is supplied to a state where voltage VCH1 is supplied. Also, the threshold voltage of the memory cell transistor MCb1(BLk+1), which includes part of Channel(k+1), has risen to the "D" level, which is higher than the "Er" level. As mentioned above, when the voltage VPGM is supplied to the selection word line SEL-WLb1, the voltage supplied to Channel(k+1) changes from a state where voltage VDD is supplied to a state where voltage VCH2 is supplied. At this time, since Channel(k) is in a floating state, due to the influence of the voltage VCH2 supplied to Channel(k+1), for example, Channel(k) is further boosted from a state where voltage VCH1 is supplied to a state where a voltage higher than voltage VCH1, VCH3, is supplied.

[0125] Here, the larger the potential difference between the voltage supplied to the selection word line SEL-WLb1 and the voltage supplied to Channel(k), the more likely an unintended rise in the threshold voltage is to occur in the memory cell transistor MCb1(BLk). In the aforementioned state of Channel(k), although voltage VCH3 is supplied, the potential difference between the voltage VPGM supplied to the selection word line SEL-WLb1 and voltage VCH3 is still large, and this is a potential difference that can cause an unintended rise in the threshold voltage of the memory cell transistor MCb1(BLk). Therefore, for example, a memory cell transistor written with a low threshold voltage for the program target level is more likely to experience an unintended rise in the threshold voltage in the later program loops, such as from the 5th loop to the 7th loop. For example, this increased likelihood of an unintended rise in the threshold voltage is sometimes expressed as "increased likelihood of program disturbance."

[0126] Therefore, the writing operation of the non-volatile semiconductor device in the comparative example is prone to unintended increases in the threshold voltage (making program disturbance more likely).

[0127] [7-1-2. An example of a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1] Next, with reference to Figures 9, 12, and 13, an example of a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 will be described. The timing chart shown in Figure 12 corresponds to the timing charts for the 5th to 7th loops in the program loop shown in Figure 7.

[0128] In an example of a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1, the selected memory cell transistor MC targeted for the write operation is the memory cell transistor MC connected to the bit line BLk-1, the source line SL1, and the selected word line SEL-WLb1. This memory cell transistor MC is the memory cell transistor MCb1(BLk-1) shown in Figure 3 or Figure 9, and the memory cell transistor MCb1(BLk-1) includes a part of the k-1 layer semiconductor layer 31 (Channel(k-1)). The bit line BLk-1 is the bit line ProgramBL.

[0129] Furthermore, in an example of a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1, the non-selected memory cell transistors MC that are not subject to the write operation are the memory cell transistor MCb1(BLk) connected to the bit line BLk, source line SL1, and selection word line SEL-WLb1, and the memory cell transistor Mcb1(BLk+1) connected to the bit line BLk+1, source line SL1, and selection word line SEL-WLb1. Also, as shown in Figure 3 or Figure 9, the memory cell transistor MCb1(BLk) includes a part of the k-layer semiconductor layer 31 (Channel(k)), and the memory cell transistor Mcb1(BLk+1) includes a part of the k+1-layer semiconductor layer 31 (Channel(k+1)). Note that the bit line BLk is the bit line InhibitBL(BLk), and the bit line BLk+1 is the bit line InhibitBL(BLk+1).

[0130] In the writing operation of the memory cell array 18 of the non-volatile semiconductor memory device 1, the time changes of the voltage at each time point for the selected gate line SEL-SGD (SGD1), the unselected gate line USEL-SGD (SGD0, SGD2, SGD3, ...), the selected gate line SGS (SGS0, SGS1, SGS2, SGS3, ...), the selected word line SEL-WLb1, the unselected word line USEL-WL other than the selected word line SEL-WLb1, and the control signal BLC are the same as the time changes of the voltage at each time point for the writing operation of the non-volatile semiconductor memory device in the comparative example, specifically for the selected gate line SEL-SGD (SGD1), the unselected gate line USEL-SGD (SGD0, SGD2, SGD3, ...), the selected gate line SGS (SGS0, SGS1, SGS2, SGS3, ...), the selected word line SEL-WLb1, the unselected word line USEL-WL other than the selected word line SEL-WLb1, and the control signal BLC. Therefore, in the explanation of the writing operation in the memory cell array 18 of the non-volatile semiconductor memory device 1, the explanation of the time changes of the voltage at each time point for the selected gate line SEL-SGD, the unselected gate line USEL-SGD, the selected gate line SGS, the selected word line SEL-WLb1, and the unselected word lines USEL-WL other than the selected word line SEL-WLb1 is omitted.

[0131] [7-1-2-1. Example of write operation up to time T0] First, we will explain the write operation up to time T0.

[0132] As shown in Figure 12, until time T0, the bit lines ProgramBLk-1, InhibitBLk, and InhibitBLk+1 are supplied with voltage VSS. Bit line ProgramBLk-1 is sometimes referred to as the "second bit line," bit line InhibitBLk as the "first bit line," and bit line InhibitBLk+1 as the "third bit line."

[0133] As mentioned above, the channel layer of the memory cell transistor MC targeted for writing is Channel(k-1), and the channel layer of the memory cell transistor MC not targeted for writing is Channel(k) or Channel(k+1). The voltage VSS is supplied to Channel(k-1), Channel(k), and Channel(k+1). Furthermore, the data latch DL shown in Figure 12 represents data (threshold voltage) calculated using the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU. For example, the calculated data may be stored in any of the latch circuits SDL, ADL, BDL, CDL, or XDL. For example, at time T0, no data is stored in the data latch DL.

[0134] As shown in Figure 12, since a voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state.

[0135] [7-1-2-2. Example of a write operation between time T0 and T1] Next, we will explain the writing operation at time T0 to T1.

[0136] As shown in Figure 12, from time T0 to T1, the voltage supplied to the control signal BLC gradually increases toward the voltage VDD + VTH (the eighth voltage). Also, the voltage VSS is supplied to the selection gate line SGS (SGS1), bit line ProgramBLk-1, bit line InhibitBLk, bit line InhibitBLk+1, Channel(k-1), Channel(k), and Channel(k+1), as before time T0. Note that, as before time T0, no data is stored in the data latch DL.

[0137] Here, voltage VSGPCH may be a voltage greater than voltage VCHPCH, or it may be the same magnitude as voltage VCHPCH. Also, for example, voltage VCHPCH is greater than voltage VSS. Furthermore, voltage VDD is greater than voltage VSS and may be the same as or approximately the same as voltage VCHPCH.

[0138] Based on the voltage supplied to each control line at time T1, the selection transistors ST1-k-1, ST1-k, and ST1-k+1, the memory cell transistors MCb0~MCb3, and the memory cell transistors MCa0~MCa3 are turned ON, while the selection transistors ST2-k-1, ST2-k, and ST2-k+1 remain OFF.

[0139] As a result, at time T1, the voltage VSS supplied to bit line BLk-1 is supplied to the selection transistor ST1-k-1 and the respective Channel(k-1) (second channel) of the memory cell transistors MCb0~MCb3 (second memory cell) connected to the selection transistor ST1-k-1, the voltage VSS supplied to bit line BLk is supplied to the selection transistor ST1-k and the respective Channel(k) (first channel) of the memory cell transistors MCb0~MCb3 (first memory cell) connected to the selection transistor ST1-k, and the voltage VSS supplied to bit line BLk+1 is supplied to the selection transistor ST1-k+1 and the respective Channel(k+1) (third channel) of the memory cell transistors MCb0~MCb3 (third memory cell) connected to the selection transistor ST1-k+1.

[0140] [7-1-2-3. Example of a write operation at time T1 to T2] Next, the write operation at time T1 to T2 will be explained. The write operation at time T1 to T2 is the operation of precharging bit line InhibitBL(BLk), bit line InhibitBL(BLk+1), Channel(k), and Channel(k+1). For example, the write operation at time T1 to T2 includes supplying voltage VDD to bit line InhibitBL(BLk), then supplying voltage VDD to bit line InhibitBL(BLk+1), and raising the voltage supplied to bit line InhibitBL(BLk) from voltage VDD to voltage VDD+dv (third voltage). Furthermore, the write operation at times T1 to T2 includes supplying voltage VDD to bit line InhibitBL(BLk), supplying voltage VDD to channel(k) of memory cell transistor MCb1(BLk) connected to bit line InhibitBL(BLk), and then supplying voltage VDD to bit line InhibitBL(BLk+1), thereby increasing the voltage supplied to channel(k) from voltage VDD to voltage VDD+dv.

[0141] As shown in Figure 12, at times T1 to T2, the control signal BLC is supplied with the voltage VDD + VTH. Also, similar to time T1, the selection gate line SGS (SGS1), bit lines ProgramBLk-1 and Channel (k-1) are supplied with the voltage VSS.

[0142] Based on the voltage supplied to each control line at time T2, the selection transistors ST1-k-1, ST1-k, and ST1-k+1, the memory cell transistors MCb0~MCb3, and the memory cell transistors MCa0~MCa3 remain ON, while the selection transistors ST2-k-1, ST2-k, and ST2-k+1 remain OFF. Furthermore, when the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the sense amplifier unit SAU connected to the bit line InhibitBLk-1 turns ON, the voltage VSS is supplied to the bit line ProgramBLk-1, and the voltage VSS is also supplied to the selection transistor ST1-k-1 and the respective Channel(k-1) (first channel) of the memory cell transistors MCb0~MCb3 (first memory cells) connected to the selection transistor ST1-k-1. Furthermore, when the voltage VDD+VTH is supplied to the control signal BLC, transistor 122 of the sense amplifier unit SAU connected to the bit line InhibitBL(BLk) turns ON, supplying the voltage VDD to the bit line InhibitBL(BLk), and simultaneously supplying the voltage VDD to the selection transistor ST1-k and the respective Channel(k) of the memory cell transistors MCb0~MCb3 connected to the selection transistor ST1-k.

[0143] When voltage VDD is supplied to the bit line InhibitBL(BLk) and Channel(k), the memory cell transistor MCb1(BLk) enters a floating state. In this state, when voltage VDD is supplied to the bit line InhibitBL(BLk+1) and Channel(k+1), the voltage supplied to bit line InhibitBL(BLk+1)(Channel(k+1)) and bit line InhibitBL(BLk)(Channel(k)) rise from voltage VDD to voltage VDD+dv due to capacitive coupling between bit line InhibitBL(BLk+1)(Channel(k+1)) and bit line InhibitBL(BLk)(Channel(k)). Also, at the timing when voltage VDD is supplied to Channel(k), the data latch DL displays a threshold voltage of the program target level at the "Er" level, which is calculated using a logical operation with the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU. The threshold voltage of the program target level at the "Er" level may be stored in one of the latch circuits SDL, ADL, BDL, CDL, or XDL. Furthermore, when voltage VDD is supplied to Channel(k+1), the data latch DL displays the threshold voltage for the program target level, which is calculated using the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU, ranging from level "A" to level "F". The threshold voltage for the program target level, ranging from level "A" to level "F", may be stored in any of the latch circuits SDL, ADL, BDL, CDL, or XDL.

[0144] After the voltage VDD is supplied to Channel(k) and then to Channel(k+1), the voltage VSS is supplied to the control signal BLC.

[0145] [7-1-2-4. Example of a write operation at time T2~T3] Next, the writing operation at times T2 to T3 will be explained. As shown in Figure 12, at times T2 to T3, similar to time T2, the voltage VSS is supplied to the selection gate line SGS (SGS1), bit lines ProgramBLk-1 and Channel(k-1), and control signal BLC, the voltage VDD+dv is supplied to the bit line InhibitBLk and Channel(k), and the voltage VDD is supplied to the bit line InhibitBLk+1 and Channel(k+1). Also, similar to time T2, the data latch DL represents the threshold voltage of the program target level from "A" to "F" levels, which is calculated using the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU. For example, the threshold voltage of the program target level from "A" to "F" levels is stored in one of the latch circuits SDL, ADL, BDL, CDL, or XDL. Therefore, since the voltage VSS is supplied to each control line, each memory cell transistor MC is in the off state.

[0146] [7-1-2-5. Example of a write operation at time T3~T4] Next, the write operation at time T3 to T4 will be explained. The write operation at time T3 to T4 includes the boosting of Channel(k+1) of the non-selective memory cell transistor MC(Mcb1(BLk+1)) from a state where voltage VDD is supplied to a state where voltage VCHB (fifth voltage) is supplied, and the boosting of Channel(k) of the non-selective memory cell transistor MC(MCb1(BLk)) from a state where voltage VDD+dV is supplied to a state where voltage VCHC (sixth voltage) is supplied.

[0147] As shown in Figure 12, at times T3 to T4, the selected gate line SEL-SGD (SGD1) changes from being supplied with voltage VSS to being supplied with voltage VSG, the unselected gate line USEL-SGD (SGD1) is supplied with voltage VSS, the selected word line SEL-WLb1 and the unselected word line USEL-WL change from being supplied with voltage VSS to being supplied with voltage VPASS (fourth voltage), and the control signal BLC changes from being supplied with voltage VSS to being supplied with voltage VBLC. Also, similar to time T3, the selected gate line SGS (SGS1), bit lines ProgramBLk-1 and Channel(k-1), and control signal BLC are supplied with voltage VSS, the bit line InhibitBLk is supplied with voltage VDD+dv, and the bit line InhibitBLk+1 is supplied with voltage VDD. Also, similar to time T2, the bit line ProgramBLk-1 is supplied with voltage VSS. The data latch DL represents the threshold voltages for program target levels ranging from "A" to "F," calculated using the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU. For example, the threshold voltages for program target levels ranging from "A" to "F" are stored in one of the latch circuits SDL, ADL, BDL, CDL, or XDL.

[0148] The voltage VSS supplied to the bit line ProgramBLk-1 is sufficiently lower than the voltage VSG supplied to the select gate line SEL-SGD. Therefore, the select transistor ST1-k-1 connected to the bit line ProgramBLk-1 turns ON, and the voltage VSS is supplied to Channel(k-1). The unselected gate line SGD(SGD1) is supplied with the voltage VSS, and the bit line InhibitBLk+1 is supplied with the voltage VDD. Also, the unselected gate line SGD(SGD1) is supplied with the voltage VSS, and the bit line InhibitBLk is supplied with the voltage VDD+dV. The voltage VDD supplied to the bit line InhibitBLk+1 and the voltage VDD+dV supplied to the bit line InhibitBLk are sufficiently higher than the voltage VSG supplied to the select gate line SEL-SGD. Therefore, the voltage VDD supplied to the gate of the selection transistor ST1-k+1 connected to the bit line InhibitBLk+1, and the voltage VSG supplied to the gate of the selection transistor ST1-k connected to the bit line InhibitBLk, become relatively low, causing the selection transistors ST1-k+1 and ST1-k to be in the off state. The voltage VPASS is supplied to the selection word line WLb1 and the non-selection word line WL, and the memory cell transistors MC in each layer are in the on state.

[0149] Therefore, the bit line InhibitBLk+1 and Channel(k+1) are electrically disconnected, and the bit line InhibitBLk and Channel(k) are electrically disconnected. As a result, due to the capacitive coupling between Channel(k+1) and the non-selected word line USEL-WL, Channel(k+1) is boosted from a state where voltage VDD is supplied to a state where voltage VCHB is supplied, and due to the capacitive coupling between Channel(k), Channel(k+1), and the non-selected word line USEL-WL, Channel(k) is boosted from a state where voltage VDD+dV is supplied to a state where voltage VCHC is supplied.

[0150] For example, voltage VSG is less than voltage VSGPCH, voltage VPASS (fourth voltage) is greater than voltage VCHPCH, voltage VCHC is greater than voltage VCHB, and voltages VCHB and VCHC are greater than voltages VDD and VDD+dV.

[0151] As explained in "7-1-1. An Example of Writing Operation of a Non-Volatile Semiconductor Device in a Comparative Example" with reference to Figures 8, 10, and 11, the non-volatile semiconductor memory device in the comparative example includes the fact that, at times T1 to T4, voltage VDD is supplied to multiple bit lines InhibitBL (BLk, BLk+1 in Figure 12) at the same timing, and when the voltage supplied to Channel(k+1) becomes voltage VCH2, the voltage supplied to Channel(k) changes from voltage VCH1 to voltage VCH3. As a result, the potential difference between voltage VPGM supplied to the selection word line SEL-WLb1 and voltage VCH3 remains large, and the non-volatile semiconductor memory device in the comparative example is prone to unintended increases in threshold voltage (program disturbances are more likely to occur). Therefore, for example, when using the non-volatile semiconductor memory device in the comparative example, the threshold voltage distribution width widens and the distribution widths of adjacent levels become closer, resulting in a deterioration of the threshold voltage distribution shown in Figure 7.

[0152] On the other hand, in the non-volatile semiconductor memory device 1, when voltage VDD is supplied to the bit line InhibitBLk, the memory cell transistor MC (memory cell transistor MCb1(BLk)) which includes a part of Channel(k) connected to the bit line InhibitBLk becomes floating, and voltage VDD is supplied to the bit line InhibitBLk+1. Therefore, using the capacitive coupling between Channel(k+1) and Channel(k), the voltage supplied to Channel(k) can be increased to voltage VDD+dV.

[0153] Therefore, in subsequent operation, the non-volatile semiconductor memory device 1 can boost the channel (k) of the memory cell transistor MCb1(BLk) to a voltage VCHC that is greater than the voltages VCH1 to VCH3 in the comparative example. As a result, the non-volatile semiconductor memory device 1 can suppress interference between channel (k) and channel (k+1), and can also suppress the rewriting of the threshold voltage stored in the memory cell transistor MCb1(BLk), thereby suppressing deterioration of the threshold voltage distribution.

[0154] [7-1-2-6. Example of a write operation at time T4~T5] Next, the write operation at time T4-T5 will be explained. The write operation at time T4-T5 is the operation of writing a threshold voltage of the program target level "G" level to the select memory cell transistor MCb1(BLk-1). As shown in Figure 12, the bit line ProgramBLk-1 is supplied with voltage VSS, and the select transistor ST1-k-1 remains in the ON state. The non-selected gate line USEL-SGD(SGD1) is supplied with voltage VSS, the bit line InhibitBLk is supplied with voltage VDD+dV, and the select transistor ST1-k is in the OFF state. Also, the non-selected gate line USEL-SGD(SGD1) is supplied with voltage VSS, the bit line InhibitBLk+1 is supplied with voltage VDD, and the select transistor ST1-k+1 is in the OFF state. The selection word line SEL-WLb1 changes from being supplied with voltage VPASS to being supplied with voltage VPGM (the 7th voltage), and the memory cell transistors MCb1(BLk-1), MCb1(BLk), and Mcb1(BLk+1) turn ON. Also, similar to time T4, the voltage supplied to Channel(k-1) remains at voltage VSS, the voltage supplied to Channel(k) remains at voltage VCHC, the voltage supplied to Channel(k+1) remains at voltage VCHB, the selection gate line SGS(SGS1) is supplied with voltage VSS, the selection transistors ST2-k-1, ST2-k, and ST2-k+1 remain OFF, and the control signal BLC remains supplied with voltage VBLC. Furthermore, similar to time T4, the data latch DL represents the threshold voltages for program target levels from "A" to "F" levels, which are calculated using the latch circuits SDL, ADL, BDL, CDL, or XDL within the sense amplifier unit SAU. For example, the threshold voltages for program target levels from "A" to "F" levels are stored in one of the latch circuits SDL, ADL, BDL, CDL, or XDL.

[0155] For example, voltage VPGM is greater than voltage VPASS, voltage VCHB, and voltage VCHC. Also, voltage VCHB and voltage VCHC are less than voltage VPASS, and greater than voltage VSGPCH and voltage VCHPCH.

[0156] When the selection word line SEL-WLb1 is supplied with voltage VPGM and the memory cell transistor MCb1 is turned ON, the voltage supplied to the bit line ProgramBLk-1 is the threshold voltage for the program target level "G" from voltage VSS. Voltage VPGM is a voltage that is sufficiently higher than the threshold voltage for the program target level "G". Note that voltage VPGM is sometimes called the write voltage.

[0157] The Channel(k) of the memory cell transistor MCb1(k) connected to the bit line InhibitBLk maintains a state where the voltage VCHC is supplied. Therefore, the write operation of the non-volatile semiconductor memory device 1 can suppress the rewriting of the threshold voltage stored in the memory cell transistor MCb1(k) (in this case, the threshold voltage when the program target level is "Er" level).

[0158] Furthermore, the potential difference between the voltage VCHC (boost voltage) supplied to Channel(k+1) of the memory cell transistor MCb1(BLk+1) connected to the bit line InhibitBLk+1 and the voltage VPGM (write voltage) supplied to the selection word line WLb1 connected to the memory cell transistor MCb1(BLk+1) is smaller than the potential difference between voltage VCH3 and voltage VPGM in the comparative example of the non-volatile semiconductor memory device. Therefore, the write operation of the non-volatile semiconductor memory device 1 can reduce the potential difference between the boost voltage and the write voltage. When the boost voltage is small, the potential difference between the boost voltage and the write voltage becomes large, which may cause the threshold voltage stored in the memory cell transistor MC to be rewritten. In this case, for example, as shown in Figure 13, the distribution width of the "Er" level threshold voltage widens as shown by the dashed line, so the gap between the distribution width of the "Er" level threshold voltage and the distribution width of the adjacent "A" level threshold voltage becomes narrower, or the distribution width of the "Er" level threshold voltage may overlap with the distribution width of the adjacent "A" level threshold voltage. On the other hand, the write operation of the non-volatile semiconductor memory device 1 increases the boost voltage, and the potential difference between the boost voltage and the write voltage can be reduced. Therefore, as shown in Figure 13, the distribution width of the threshold voltage at the "Er" level, which is spread out as a dashed line, can be narrowed as shown by the thick solid line, and the distribution width of adjacent threshold voltages can be increased (the threshold window can be expanded). Also, similar to the case where the program target level is the "Er" level, when the program target level is the "A" level, the distribution width of the threshold voltage at the program target level of "A" level, which is spread out as a dashed line, can be narrowed as shown by the thick solid line, and the distribution width of adjacent threshold voltages can be increased (the threshold window can be expanded). Also, similar to the case where the program target level is the "Er" level, when the program target level is the "B" level, the distribution width of the threshold voltage at the program target level of "B" level can be narrowed as shown by the thick solid line, and the distribution width of adjacent threshold voltages can be increased (the threshold window can be expanded).In other words, the write operation of the non-volatile semiconductor memory device 1 is applicable across the entire page, and it is possible to suppress deterioration of the threshold voltage distribution when viewed across the entire page.

[0159] Furthermore, the non-volatile semiconductor memory device 1 is designed to withstand a certain degree of error. For example, to correct such errors, the memory system 3 includes ECC (Error Checking and Correcting) in the memory controller 2. Generally, the higher the error rate, the more ECC resources are required. The non-volatile semiconductor memory device 1 can reduce the error rate within a page, improving operational accuracy. In addition, the non-volatile semiconductor memory device 1 can reduce the error rate within a page, thereby reducing the ECC resources required to match the reduced error rate within a page. As a result, the memory system 3 using the non-volatile semiconductor memory device 1 is a cost-effective system.

[0160] In addition, during the writing operation of the non-volatile semiconductor memory device 1, the operation up to time T2 may be referred to as the "first operation," and the operation from time T3 to time T5 may be referred to as the "second operation."

[0161] [Second Embodiment] Referring to Figure 14, an example of a write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 according to the second embodiment will be described. Figure 14 is a timing chart showing the write operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 according to the second embodiment.

[0162] The timing chart according to the second embodiment includes configurations 1 to 3 shown below. Configurations 1 to 3 differ from an example of the writing operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 according to the first embodiment. Configuration 1: The control signal BLC changes from a state where voltage VSS is supplied to a state where voltage VBLDR (the 9th voltage) is supplied between times T0 and T1. Configuration 2: The control signal BLC changes from a state where voltage VBLDR is supplied to a state where voltage VDD+VTH is supplied between times T1 and T2. Configuration 3: Voltage VBLDR is a voltage greater than voltage VDD + VTH.

[0163] Configurations other than Configurations 1 to 3 are the same as those in the example of the writing operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the first embodiment. Therefore, a description of the same configurations and functions as in the example of the writing operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the first embodiment is omitted.

[0164] The write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the second embodiment has the same effects as the write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the first embodiment.

[0165] [Third Embodiment] Referring to Figure 15, an example of a write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the third embodiment will be described. Figure 15 is a timing chart showing the write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the third embodiment.

[0166] The timing chart according to the third embodiment includes configurations 4 and 5 shown below. Configurations 4 and 5 differ from the example of writing operation in the memory cell array 18 of the non-volatile semiconductor memory device 1 according to the first embodiment. Configuration 4: The bit lines InhibitBLk+1 and Channel(k+1) are supplied with voltage VDD at a timing corresponding to the time of the data (threshold voltage) processed by the data latch DL. Configuration 5: Bit lines InhibitBLk and Channel(k) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied when voltage VDD is supplied to bit lines InhibitBLk+1 and Channel(k+1).

[0167] Configurations other than configurations 4 and 5 are the same as those in the example of the write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the first embodiment. Therefore, a description of the same configurations and functions as in the example of the write operation in the memory cell array 18 of the non-volatile semiconductor storage device 1 according to the first embodiment is omitted.

[0168] For example, as shown by the solid waveform in Figure 15, at time T11, the bit lines InhibitBLk+1 and Channel(k+1) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied at the timing when the threshold voltage for program target level "A" is calculated in the data latch DL. Also, the bit lines InhibitBLk and Channel(k) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied at the timing when voltage VDD is supplied to bit lines InhibitBLk+1 and Channel(k+1).

[0169] Furthermore, as shown by the dashed waveform in Figure 15, for example, at time T12 following time T11, the bit lines InhibitBLk+1 and Channel(k+1) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied at the timing when the threshold voltage for program target level "B" is calculated in the data latch DL. Also, the bit lines InhibitBLk and Channel(k) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied at the timing when voltage VDD is supplied to bit lines InhibitBLk+1 and Channel(k+1).

[0170] Furthermore, as shown by the dashed waveform in Figure 15, for example, at time T13 following time T12, bit line InhibitBLk+1 and Channel(k+1) change from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied at the timing when the threshold voltage of program target level "C" to "F" is calculated in data latch DL. Also, bit line InhibitBLk) and Channel(k) change from a state where voltage VDD is supplied to bit line InhibitBL(BLk+1) and Channel(k+1) to a state where voltage VDD+dV is supplied at the timing when voltage VDD is supplied to bit line InhibitBL(BLk+1) and Channel(k+1).

[0171] The non-volatile semiconductor memory device 1 writes the threshold voltage to the memory cell transistor MC at different speeds depending on the threshold voltage level ("Er" level to "G" level). In the third embodiment, the non-volatile semiconductor memory device 1 can change the timing of changing the channel (e.g., Channel(k)) one layer below the channel (e.g., Channel(k-1)) in the Z direction from a state where voltage VDD is supplied to a state where voltage VDD+dV is supplied, depending on the threshold voltage level ("Er" level to "G" level). As a result, the non-volatile semiconductor memory device 1 in the third embodiment can optimize the timing of boosting and increasing the voltage of the channel one layer below the channel in the Z direction for the channel included in the memory cell transistor to be written, depending on the threshold voltage level ("Er" level to "G" level).

[0172] [Other embodiments] Each component described as part of the memory system 3 in the first to third embodiments above may be implemented in hardware or software, or in combination with hardware and software.

[0173] In the above embodiment, when the terms "identical" and "matching" are used, "identical" and "matching" may include cases where errors within the design range are included.

[0174] Furthermore, when it is stated that a certain voltage is applied or supplied, this includes both performing a control to apply or supply that voltage and the voltage actually being applied or supplied. Moreover, applying or supplying a certain voltage may include, for example, applying or supplying a voltage of 0V.

[0175] In this specification, "connection" refers to an electrical connection, and does not exclude, for example, the use of another element in between.

[0176] Although several embodiments of this disclosure have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and may be combined as appropriate without departing from the spirit of the invention, and various omissions, substitutions, and modifications are permitted. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0177] 1: Non-volatile semiconductor memory device, 2: Memory controller, 3: Memory system, 10: Input / output circuit, 11: Logic control circuit, 12: Status register, 13: Address register, 14: Command register, 15: Sequencer, 16: Ready / busy circuit, 17: Voltage generation circuit, 18: Memory cell array, 19: Row decoder, 20: Sense amplifier module, 21: Data register, 22: Column decoder, 31: Semiconductor layer, 32: Insulating layer, 33: Conductive layer, 34: Insulating layer, 35: Charge storage layer, 36: Insulating layer 38: insulating layer, 39: conductive layer, 40i: insulating layer, 41: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: conductive layer, 46: insulating layer, 47: conductive layer, 49: conductive layer, 120: transistor, 121: transistor, 122: transistor, 123: transistor, 124: transistor, 125: transistor, 126: transistor, 127: transistor, 128: transistor, 129: capacitor, 130: inverter, 131: inverter, 132: transistor, 133: transistor

Claims

1. Each is 2 ｎ Multiple first memory cell transistors, multiple second memory cell transistors, and multiple third memory cell transistors, which can be set to threshold voltage levels of 2 or more (where n is an integer greater than or equal to 2), A first bit line extending in the first direction, The first bit line and the second and third bit lines are parallel to each other, A source line provided on the opposite side of the first bit line with respect to the first direction, extending in a second direction intersecting the first direction, The first semiconductor layer includes a plurality of first memory cell transistors electrically connected between the first bit line and the source line, and extends in the first direction. The plurality of second memory cell transistors connected between the second bit line and the source line, and the second semiconductor layer stacked with the first semiconductor layer along a third direction intersecting both the first and second directions, The third semiconductor layer includes a plurality of third memory cell transistors connected between the third bit line and the source line, and is stacked along the third direction on the side opposite to the side on which the second semiconductor layer is stacked relative to the first semiconductor layer, A control circuit is provided to enable each of the plurality of first memory cell transistors, each of the plurality of second memory cell transistors, and each of the plurality of third memory cell transistors to perform a write operation including a first operation and a second operation. Includes, The aforementioned control circuit is When performing the write operation to write data to one of the multiple second memory cell transistors, The first operation is controlled to enable the following: supplying a first voltage, which is a reference voltage, to the second bit line and the second channel of the plurality of second memory cell transistors; supplying a second voltage greater than the first voltage to the first bit line and the first channel of the plurality of first memory cell transistors; then supplying the second voltage to the third bit line and the third channel of the plurality of third memory cell transistors; and boosting the voltage supplied to the first channel to a third voltage greater than the second voltage. Non-volatile semiconductor memory device.

2. Further including a word line parallel to the source line along the second direction, The word line is connected to the one second memory cell transistor, one of the plurality of first memory cell transistors, and one of the plurality of third memory cell transistors. The aforementioned first memory cell transistor is the 2 ｎ Among the more than two possible levels (where n is an integer greater than or equal to 2), the lowest threshold voltage level is written. The non-volatile semiconductor memory device according to claim 1.

3. A drain-side selection gate line that intersects the first bit line, the second bit line, and the third bit line, A source-side selection gate line parallel to the aforementioned source line, A first drain-side selection transistor is electrically connected between the first bit line and the plurality of first memory cell transistors, A first source-side selection transistor is electrically connected between the plurality of first memory cell transistors and the source line, A second drain-side selection transistor is electrically connected between the second bit line and the plurality of second memory cell transistors, A second source-side selection transistor is electrically connected between the plurality of second memory cell transistors and the source line, A third drain-side selection transistor is electrically connected between the third bit line and the plurality of third memory cell transistors, A third source-side selection transistor is electrically connected between the plurality of third memory cell transistors and the source line, It further includes, The drain-side selection gate wire is connected to the first drain-side selection transistor, the second drain-side selection transistor, and the third drain-side selection transistor. The source-side selection gate line is connected to the first source-side selection transistor, the second source-side selection transistor, and the third source-side selection transistor. The non-volatile semiconductor memory device according to claim 2.

4. The control circuit supplies the same voltage as the second voltage to the word line and supplies a voltage greater than or equal to the second voltage and less than or equal to the third voltage to the drain-side selection gate line. Controlling the first operation, which includes supplying the first voltage to the source-side selected gate line, to enable execution. The non-volatile semiconductor memory device according to claim 3.

5. The control circuit controls the second operation to be executable, which includes, after the first operation, supplying the first voltage to the word line, the drain-side select gate line and the source-side select gate line, supplying a voltage greater than the first voltage but less than the second voltage to the drain-side select gate line after supplying the first voltage, supplying a fourth voltage greater than the third voltage after supplying the first voltage to the word line, boosting the voltage supplied to the third channel to a fifth voltage greater than the second voltage, and boosting the voltage supplied to the first channel to a sixth voltage greater than the third voltage. The sixth voltage is greater than the fifth voltage. The non-volatile semiconductor memory device according to claim 4.

6. The control circuit supplies the fourth voltage to the word line, then supplies a seventh voltage which is greater than the fifth and sixth voltages, maintains the voltage supplied to the third channel at the fourth voltage, maintains the voltage supplied to the first channel at the fifth voltage, maintains the voltage supplied to the second channel at the first voltage, and supplies the second memory cell transistor with the second ｎ Controlling the second operation to be executable, which includes controlling to write a threshold voltage of any one of the levels of more than or equal to, The non-volatile semiconductor memory device according to claim 5.

7. Each of the first bit line, the second bit line, and the third bit line is connected, and each includes a plurality of latch circuits and a transistor connected to a control signal, and the plurality of latch circuits are used to perform calculation processing, thereby the 2 ｎ It further includes a sense amplifier section capable of generating and storing threshold voltages of a level greater than or equal to, The control circuit controls the sense amplifier section connected to the second bit line and controls the second operation, which includes supplying a threshold voltage of any one of the levels to the second bit line and the one second memory cell transistor, to enable the execution of this operation. The non-volatile semiconductor memory device according to claim 6.

8. The control circuit controls the second operation to be executable, which includes supplying an eighth voltage greater than the second voltage to the control signal, turning on the transistor, and then supplying a threshold voltage of any one of the levels to the second bit line and the one second memory cell transistor. The non-volatile semiconductor memory device according to claim 7.

9. The control circuit supplies the control signal with a ninth voltage greater than the eighth voltage, and then supplies the eighth voltage. The non-volatile semiconductor memory device according to claim 8.

10. The control circuit generates the two units generated by the sense amplifier unit. ｎ The second operation, which includes adjusting the timing of supplying the second voltage to the third channel in accordance with a threshold voltage level above a certain threshold voltage, is made executable. The non-volatile semiconductor memory device according to claim 7.

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