Motherboard for display device, display device, and method for manufacturing a display device.

Abstract

To suppress the decline in the reliability of display devices. [Solution] The mother board for the display device comprises a plurality of panel sections, display elements arranged in a display area, a rib layer having a pixel aperture that overlaps with the display elements, and an inspection pad arranged in a peripheral area. The inspection pad has a first metal layer and a second metal layer that overlaps the first metal layer. The rib layer is arranged between the first metal layer and the second metal layer and has a first aperture through which the second metal layer contacts the first metal layer. The first metal layer has a first layer made of a first metal material, a second layer made of a second metal material that overlaps the first layer, and a third layer made of the first metal material that overlaps the second layer. The third layer has a region in the first aperture that exposes the second layer. The second metal layer has a first contact portion in the region that contacts the second layer and a second contact portion that contacts the third layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a mother board for a display device, a display device, and a method for manufacturing a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for suppressing a decrease in reliability are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a mother board for a display device, a display device, and a method for manufacturing a display device that can suppress a decrease in reliability.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the mother board for a display device comprises a plurality of panel portions having a display area and a peripheral area surrounding the display area, a display element disposed in the display area, a rib layer disposed in the display area and the peripheral area and having a pixel aperture that overlaps with the display element, and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer that overlaps the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer and further has a first aperture in which the second metal layer contacts the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material and overlapping the first layer, and a third layer formed of the first metal material and overlapping the second layer. The third layer has a region in the first aperture that exposes the second layer. The second metal layer has, in the region, a first contact portion that contacts the second layer and a second contact portion that contacts the third layer.

[0006] According to another embodiment, the mother board for a display device includes a plurality of panel portions having a display area and a peripheral area surrounding the display area, a display element disposed in the display area, a rib layer disposed in the display area and the peripheral area and having a pixel aperture that overlaps with the display element, and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer that overlaps the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer and has a first aperture through which the second metal layer contacts the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material that overlaps the first layer, and a third layer formed of the first metal material that overlaps the second layer. The second metal layer has a fourth layer formed of the first metal material, a fifth layer formed of the second metal material that overlaps the fourth layer, and a sixth layer formed of the first metal material that overlaps the fifth layer. The inspection pad has a first portion in which the first, second, fourth, fifth, and sixth layers are laminated, and a second portion in which the first, second, third, fourth, fifth, and sixth layers are laminated.

[0007] According to one embodiment, the display device comprises a display area, a peripheral area surrounding the display area, a display element disposed in the display area, a rib layer disposed in the display area and the peripheral area and having a pixel aperture that overlaps with the display element, and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer that overlaps the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer and has a first aperture through which the second metal layer contacts the first metal layer. The first metal layer has a first layer made of a first metal material, a second layer made of a second metal material that overlaps the first layer, and a third layer made of the first metal material that overlaps the second layer. The third layer has a region in the first aperture that exposes the second layer. The second metal layer has a first contact portion in the region that contacts the second layer and a second contact portion that contacts the third layer.

[0008] Furthermore, according to another embodiment, the display device comprises a peripheral region surrounding the display region, a display element disposed in the display region, a rib layer disposed in the display region and the peripheral region and having a pixel aperture that overlaps with the display element, and an inspection pad disposed in the peripheral region. The inspection pad has a first metal layer and a second metal layer that overlaps the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer and has a first aperture through which the second metal layer contacts the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material that overlaps the first layer, and a third layer formed of the first metal material that overlaps the second layer. The second metal layer has a fourth layer formed of the first metal material, a fifth layer formed of the second metal material that overlaps the fourth layer, and a sixth layer formed of the first metal material that overlaps the fifth layer. The inspection pad has a first portion in which the first, second, fourth, fifth, and sixth layers are laminated, and a second portion in which the first, second, third, fourth, fifth, and sixth layers are laminated.

[0009] According to one embodiment, the method for manufacturing a display device includes preparing a substrate having a panel portion including a display area and a peripheral area surrounding the display area, forming a first metal layer in the peripheral area, forming a rib layer of inorganic material above the first metal layer, forming an inspection opening in the rib layer that overlaps with the first metal layer, forming a sealing layer of inorganic material that covers the rib layer and the inspection opening, forming an opening in the rib layer and the sealing layer that exposes the first metal layer, placing a resist having a cleaning opening that overlaps the opening, cleaning the first metal layer exposed through the cleaning opening, and forming a second metal layer that overlaps the first metal layer. The position where the cleaning opening is formed does not overlap with the position where the inspection opening is formed. [Brief explanation of the drawing]

[0010] [Figure 1]FIG. 1 is a plan view showing a schematic configuration example of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of the layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device along line III-III in FIG. 2. [Figure 4] FIG. 4 is a schematic plan view of a mother board according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view of a part of the mother board. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device along line VI-VI in FIG. 5. [Figure 7] FIG. 7 is a partial enlarged view showing part VII in FIG. 6. [Figure 8] FIG. 8 is a partial enlarged view showing part VIII in FIG. 6. [Figure 9] FIG. 9 is a flowchart showing an example of a manufacturing method of the display device. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 14A] FIG. 14A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 14B]Figure 14B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 15A] Figure 15A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 15B] Figure 15B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 16A] Figure 16A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 16B] Figure 16B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 17A] Figure 17A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 17B] Figure 17B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 18A] Figure 18A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 18B] Figure 18B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 19A] Figure 19A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 19B] Figure 19B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 20A] Figure 20A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 20B] Figure 20B is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 21] Figure 21 is a schematic cross-sectional view showing the process of forming the display element. [Figure 22] Figure 22 is a schematic cross-sectional view showing the process of forming the display element. [Figure 23] Figure 23 is a schematic cross-sectional view showing the process of forming the display element. [Figure 24] Figure 24 is a schematic cross-sectional view showing the process of forming the display element. [Figure 25] Figure 25 is a diagram for explaining the opening overlapping the inspection pad. [Figure 26]Figure 26 is a schematic cross-sectional view showing the manufacturing process of a comparative example of a display device. [Figure 27] Figure 27 is a schematic cross-sectional view showing the manufacturing process of a comparative example of a display device. [Figure 28] Figure 28 is a schematic cross-sectional view showing the manufacturing process of a comparative example of a display device. [Figure 29] Figure 29 is a schematic cross-sectional view showing the manufacturing process of a comparative example of a display device. [Figure 30] Figure 30 is a schematic cross-sectional view showing the manufacturing process of a comparative example of a display device. [Figure 31] Figure 31 is a schematic plan view of the motherboard according to the second embodiment. [Modes for carrying out the invention]

[0011] The embodiments will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation; however, these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and in each drawing, components that perform the same or similar functions as those described above in previously shown drawings are denoted by the same reference numerals, and redundant detailed explanations may be omitted as appropriate.

[0012] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.

[0013] In the following explanation, "overlapping" includes not only cases where another element overlaps the target element from the third direction Z, but also cases where it overlaps from the opposite direction to the third direction Z. Furthermore, "overlapping" includes not only cases where the target elements are in contact with each other, but also cases where the target elements are spaced apart, or where another element is located between the target elements.

[0014] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0015] [First Embodiment] Figure 1 is a plan view showing a schematic configuration example of a display device DSP according to this embodiment. The display device DSP comprises a display panel PNL including an insulating substrate 10 and a plurality of conductive pads PD. The substrate 10 has a circular main body portion 10a and an extension portion 10b extending from the main body portion 10a in a second direction Y. The extension portion 10b is formed in a trapezoidal shape in which the width in the first direction X decreases as it moves away from the main body portion 10a. The extension portion 10b has a substrate end 10c extending in the first direction X.

[0016] However, the shape of the substrate 10 in plan view may be other shapes such as a rectangle, square, or ellipse. The substrate 10 is formed of an insulating material such as glass or plastic.

[0017] The display panel PNL further comprises a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The display area DA overlaps with the main body 10a in a plan view. In this embodiment, the shape of the display area DA in a plan view is circular. However, the shape of the display area DA in a plan view may be other shapes such as a rectangle, square, or ellipse.

[0018] The peripheral region SA has a mounting region MA. The mounting region MA corresponds to the region that overlaps with the extension 10b in a plan view. Multiple pads PD are provided in the mounting region MA. In the example shown in Figure 1, the multiple pads PD are arranged at equal intervals in the first direction X. The flexible printed circuit board (FPC) is connected to the multiple pads PD via adhesive. In addition to the flexible printed circuit board (FPC), IC chips and the like may be further mounted in the mounting region MA.

[0019] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX comprises multiple subpixels SP. In one example, pixel PX comprises a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. In addition to the three subpixels of the above colors, pixel PX may also have four or more subpixels, including subpixels of other colors such as white.

[0020] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0021] In pixel switch 2, the gate electrode is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In the example shown in Figure 1, the scan line GL extends in the first direction X, and the signal line SL extends in the second direction Y. The signal line SL connects pixel circuit 1 and pad PD. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to the anode of display element DE. Note that the configuration of pixel circuit 1 is not limited to the example shown.

[0022] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example shown in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the first direction X. Furthermore, sub-pixels SP2 and SP3 are aligned in the second direction Y.

[0023] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown in Figure 2.

[0024] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example shown in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3.

[0025] In other words, among the sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Note that the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel apertures AP1, AP2, and AP3 may have the same size.

[0026] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0027] Display elements DE1, DE2, and DE3 are arranged in the display area DA. The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. Display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0028] A partition wall 6 is positioned in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 overall. In the example shown in Figure 2, the partition wall 6 has a planar shape similar to that of the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively.

[0029] From another perspective, the rib layer 5 and partition wall 6 are grid-like in plan view, surrounding each of the display elements DE1, DE2, and DE3. Partition wall 6 surrounds the pixel apertures AP1, AP2, and AP3. Partition wall 6 also serves as wiring to supply a common voltage to the upper electrodes UE1, UE2, and UE3.

[0030] In this embodiment, inorganic insulating layers IL1, IL2, and IL3 are positioned below the lower electrodes LE1, LE2, and LE3, respectively. In the example shown in Figure 2, the inorganic insulating layers IL1, IL2, and IL3 are spaced apart from each other.

[0031] The inorganic insulating layers IL1, IL2, and IL3 each have an outer shape that is slightly larger than the lower electrodes LE1, LE2, and LE3, respectively. That is, the edge E1x of the inorganic insulating layer IL1 protrudes from the edge E1 of the lower electrode LE1 all around.

[0032] Furthermore, the end E2x of the inorganic insulating layer IL2 protrudes from the end E2 of the lower electrode LE2 over its entire circumference. The end E3x of the inorganic insulating layer IL3 protrudes from the end E3 of the lower electrode LE3 over its entire circumference.

[0033] Note that the shapes of the inorganic insulating layers IL1, IL2, and IL3 are not limited to the example shown in Figure 2. For example, parts of the inorganic insulating layers IL1, IL2, and IL3 may be connected. Also, parts of the ends E1x, E2x, and E3x may overlap with the lower electrodes LE1, LE2, and LE3.

[0034] The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 (more specifically, to the drain electrodes of the drive transistors 3 shown in Figure 1) through contact holes (not shown). All of the contact holes (not shown) overlap with the rib layer 5 and the partition wall 6.

[0035] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0036] The inorganic insulating layers IL1, IL2, and IL3 are placed on top of the organic insulating layer 12. The lower electrodes LE1, LE2, and LE3 are placed on top of the inorganic insulating layers IL1, IL2, and IL3, respectively. In other words, in the display area DA, the inorganic insulating layers IL1, IL2, and IL3 are placed between the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3.

[0037] The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 (ends E1, E2, and E3 shown in Figure 2) and the ends of the inorganic insulating layers IL1, IL2, and IL3 (ends E1x, E2x, and E3x shown in Figure 2) are all covered by the rib layer 5.

[0038] The partition wall 6 includes a conductive lower portion 61 positioned on the rib layer 5 and an upper portion 62 positioned on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. In other words, the partition wall 6 is overhanging in that both ends of the upper portion 62 protrude beyond the sides of the lower portion 61.

[0039] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in the example shown in Figure 3, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is located on top of the axial layer 64. The second top layer 66 is located on top of the first top layer 65.

[0040] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0041] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0042] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0043] Sub-pixels SP1, SP2, and SP3 are surrounded by sealing layers SE11, SE12, and SE13, respectively, which cover the stacked films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 surrounding sub-pixel SP3.

[0044] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0045] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0046] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0047] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive). In addition, color filters corresponding to the colors of the sub-pixels SP1, SP2, and SP3 may be placed above the display elements DE1, DE2, and DE3, respectively.

[0048] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The inorganic insulating layers IL1, IL2, IL3, the rib layer 5, and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0049] The inorganic insulating layers IL1, IL2, and IL3 are formed from different inorganic insulating materials than, for example, the rib layer 5. In one example, the inorganic insulating layers IL1, IL2, and IL3 are formed from silicon nitride, the rib layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride. The resin layers RS1 and RS2 are formed from resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0050] The lower electrodes LE1, LE2, and LE3 are multilayer structures containing transparent electrodes made of an oxide conductive material such as ITO, and metallic electrodes made of a metallic material such as silver. The upper electrodes UE1, UE2, and UE3 are made of a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0051] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the third direction Z in sequence. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0052] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0053] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel current corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0054] The organic layers OR1, OR2, and OR3 emit light in response to the current flowing through them. Specifically, when a current is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a current is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a current is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0055] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0056] The bottom layer 63 and the axial layer 64 are formed of, for example, a metallic material. Examples of metallic materials for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). Examples of metallic materials for the axial layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the axial layer 64 may have a laminated structure of multiple layers. Furthermore, the axial layer 64 may include a layer formed of an insulating material. Additionally, the lower part 61 may have a single-layer structure formed of a conductive material.

[0057] For example, the first top layer 65 is formed of a metallic material, and the second top layer 66 is formed of a transparent conductive oxide. As the metallic material for the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide for the second top layer 66, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide) can be used. The upper part 62 may have a single-layer structure formed of a specific material. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0058] During the manufacturing of a display device (DSP), a large motherboard is created in which multiple areas (panel sections) corresponding to the display panel PNL are formed. The following describes the configurations that can be applied to this motherboard.

[0059] Figure 4 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular, as shown in the figure, but it may also have other shapes such as a circle.

[0060] The motherboard MB has multiple panel sections PP arranged in a matrix, and margin areas BA surrounding these panel sections PP. In the example shown in Figure 4, the multiple panel sections PP are arranged in a first direction X and a second direction Y with margin areas BA in between. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example.

[0061] Figure 5 is a schematic plan view of a portion of the motherboard MB. This figure focuses on one panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut the panel section PP from the motherboard MB.

[0062] The panel section PP has the display area DA and the peripheral area SA described above. Furthermore, the peripheral area SA includes an inspection area TA. Multiple inspection pads TD are arranged in the inspection area TA for inspecting the operation of the display panel PNL. The inspection pads TD are, for example, rectangular in shape. The inspection pads TD are arranged at intervals in the first direction X.

[0063] A cut line CL2 is formed on the panel portion PP. The cut line CL2 corresponds to the outer shape of the display panel PNL shown in Figure 1. The cut line CL2 divides the panel portion PP into a part including the display area DA and a part including the inspection area TA.

[0064] The inspection pad TD is positioned between the display area DA and the cut line CL1. In other words, the cut line CL2 is positioned between the display area DA and the inspection pad TD.

[0065] Although not shown in the diagram, multiple inspection pads are also placed in the margin area BA. These inspection pads may include inspection pads for checking the operation of the display panel PNL and inspection pads for measuring the thickness of specific layers formed on the motherboard MB. Furthermore, multiple alignment marks may be placed in the margin area BA.

[0066] Figure 6 is a schematic cross-sectional view of the display device DSP along the VI-VI line in Figure 5. In Figure 6, a portion of the panel section PP, including the inspection area TA with the inspection pad TD, is shown.

[0067] As described above, the display device DSP includes a circuit layer 11. The circuit layer 11 is located above the substrate 10, spanning the display area DA and the peripheral area SA. The circuit layer 11 includes inorganic insulating layers 111, 112, and 113, an organic insulating layer 114, and wiring TW (inspection wiring). The wiring TW connects the inspection pad TD to the object to be inspected. The wiring TW includes wiring TW1 and TW2.

[0068] The inorganic insulating layer 111 is placed on the substrate 10. The wiring TW1 is placed on top of the inorganic insulating layer 111. The wiring TW1 is formed on the same layer as, for example, the scan line GL. The inorganic insulating layer 112 is placed on top of the inorganic insulating layer 111 and the wiring TW1.

[0069] Wiring TW2 is located on the inorganic insulating layer 112. Wiring TW2 is formed on the same layer as, for example, the signal line SL. Wiring TW2 is electrically connected to wiring TW1 via a contact hole (not shown). The inorganic insulating layer 113 is located on the inorganic insulating layer 112 and wiring TW2. The organic insulating layer 114 is located on the inorganic insulating layer 113.

[0070] The display device DSP further comprises a metal layer M3 (first metal layer). The metal layer M3 is located on top of the organic insulating layer 114. In addition, at least a portion of the metal layer M3 is located directly above the wiring TW2.

[0071] The metal layer M3 is electrically connected to the wiring TW2. Specifically, the metal layer M3 is in contact with the wiring TW2 through openings in the inorganic insulating layer 113 and the organic insulating layer 114.

[0072] The organic insulating layer 12 is arranged across the display area DA and the peripheral area SA. The organic insulating layer 12 is placed on top of the organic insulating layer 114 and the metal layer M3. The organic insulating layer 12 has an opening 121 (second opening).

[0073] The display device DSP further comprises an inorganic insulating layer IL. The inorganic insulating layer IL is formed from the same material and using the same manufacturing process as the inorganic insulating layers IL1, IL2, and IL3 in the display area DA, for example. In the inspection area TA, the inorganic insulating layer IL is positioned between the organic insulating layer 12 and the rib layer 5. The inorganic insulating layer IL has an opening ILA (third opening).

[0074] The rib layer 5 is positioned across the display area DA and the peripheral area SA. The rib layer 5 is positioned on top of the organic insulating layer 12 and the inorganic insulating layer IL. In other words, the organic insulating layer 12 is positioned between the metal layer M3 and the rib layer 5. The rib layer 5 has a greater thickness than, for example, the inorganic insulating layer IL. The rib layer 5 has an opening 51 (first opening).

[0075] The sealing layer SE2 is positioned across the display area DA and the peripheral area SA. The sealing layer SE2 is positioned on top of the rib layer 5. The sealing layer SE2 has an opening SEA (fourth opening).

[0076] The opening 121 in the organic insulating layer 12, the opening ILA in the inorganic insulating layer IL, the opening 51 in the rib layer 5, and the opening SEA in the sealing layer SE2 overlap each other. These openings 121, ILA, 51, and SEA overlap the metal layer M3. In other words, the metal layer M3 is exposed through the openings 121, ILA, 51, and SEA.

[0077] The display device DSP further comprises a metal layer M4 (second metal layer). The inspection pad TD is composed of metal layers M3 and M4. Metal layer M4 is located directly above metal layer M3 and is electrically connected to metal layer M3. In other words, metal layer M4 is in contact with metal layer M3 at openings 121, ILA, 51, and SEA. Focusing on rib layer 5, rib layer 5 is positioned between metal layer M3 and metal layer M4.

[0078] Here, we will explain the structure of metal layers M3 and M4. Metal layers M3 and M4 are multilayer structures containing multiple layers formed from different metallic materials.

[0079] The metal layer M3 has a first layer M31 that overlaps the organic insulating layer 114, a second layer M32 that overlaps the first layer M31, and a third layer M33 that overlaps the second layer M32. The first layer M31 and the third layer M33 are formed of a first metal material, and the second layer M32 is formed of a second metal material.

[0080] The first layer M31 is in contact with the wiring TW2. The third layer M33 has a region A3 that exposes the second layer M32 of the metal layer M3. Region A3 is located directly above the wiring TW2.

[0081] The metal layer M4 has a fourth layer M41 that overlaps the metal layer M3, a fifth layer M42 that overlaps the fourth layer M41, and a sixth layer M43 that overlaps the fifth layer M42. The fourth layer M41 and the sixth layer M43 are formed of a first metal material, and the fifth layer M42 is formed of a second metal material. Here, as an example, the first metal material is a titanium-based material and the second metal material is an aluminum-based material, but the first and second metal materials are not limited to this example.

[0082] Furthermore, the fourth layer M41 of the metal layer M4 has a first contact portion C1 that contacts the second layer M32 and a second contact portion C2 that contacts the third layer M33. The first contact portion C1 and the second contact portion C2 are located inside the opening 121 of the organic insulating layer 12.

[0083] The first contact portion C1 overlaps with region A3. The second contact portion C2 does not overlap with region A3. The first contact portion C1 is located above the wiring TW, and the second contact portion C2 is not located above the wiring TW. Focusing on the inspection pad TD, the inspection pad TD has a first portion P1 including the first contact portion C1 and a second portion P2 including the second contact portion C2.

[0084] Figure 7 is a magnified view of section VII in Figure 6. Figure 8 is a magnified view of section VIII in Figure 6. Figure 7 shows the first section P1 of the inspection pad TD, and Figure 8 shows the second section P2 of the inspection pad TD.

[0085] As shown in Figure 7, the first part P1 consists of a first layer M31, a second layer M32, a fourth layer M41, a fifth layer M42, and a sixth layer M43. As shown in Figure 8, the second part P2 consists of a first layer M31, a second layer M32, a third layer M33, a fourth layer M41, a fifth layer M42, and a sixth layer M43.

[0086] The thickness T21 of the second part P2 is greater than the thickness T11 of the first part P1. The distance between the second layer M32 and the fifth layer M42 in the second part P2 is greater than the distance between the second layer M32 and the fifth layer M42 in the first part P1.

[0087] In other words, the thickness T22 of the layer formed of the second metallic material between the second layer M32 and the fifth layer M42 in the second part P2 is greater than the thickness T12 of the layer formed of the second metallic material between the second layer M32 and the fifth layer M42 in the first part P1.

[0088] The inorganic insulating layers 111, 112, and 113 are formed from either silicon oxide, silicon nitride, or silicon oxynitride. The wiring TW2 is formed from, for example, multiple layers. The wiring TW2 is formed in the same way as, for example, the metal layers M3 and M4.

[0089] Furthermore, at least one of the wiring TW2, metal layers M3, and M4 may be formed by placing an aluminum layer between layers formed of molybdenum-based material. The organic insulating layer 114 is formed of an organic insulating material such as polyimide.

[0090] Next, we will describe an example of a manufacturing method for a display device DSP.

[0091] Figure 9 is a flowchart of an example of a manufacturing method for a display device DSP. Figures 10A to 20B are schematic cross-sectional views showing the manufacturing process of a display device DSP. Figures 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A mainly focus on the inspection pad TD, while Figures 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B mainly focus on the pad PD.

[0092] In forming the panel portion PP, a circuit layer 11 and a metal layer M3 are first formed on the substrate 10 of the mother board MB (step PR1 in Figure 9). Step PR1 includes preparing the substrate 10 having the panel portion PP.

[0093] The circuit layer 11 includes inorganic insulating layers 111, 112, and 113, an organic insulating layer 114, and wiring TW. The circuit layer 11 is formed over the entire motherboard MB, including not only the display area DA but also the peripheral area SA.

[0094] The metal layer M3 is formed in the peripheral region SA, which includes the inspection region TA, as shown in Figures 10A and 10B. The process for forming the metal layer M3 includes forming a first layer M31 with a first metal material, forming a second layer M32 with a second metal material, forming a third layer M33 with the first metal material, and patterning the first layer M31, the second layer M32, and the third layer M33. The first layer M31, the second layer M32, and the third layer M33 are formed, for example, by sputtering.

[0095] Next, an organic insulating layer 12 is formed above the circuit layer 11 and the metal layer M3 (step PR2 in Figure 9). The organic insulating layer 12 is formed over the entire motherboard MB, including not only the display area DA but also the peripheral area SA. Step PR2 includes patterning the organic insulating layer 12. An opening 121 (shown in Figure 6) is formed in the organic insulating layer 12.

[0096] Next, as shown in Figures 10A and 10B, an inorganic insulating layer IL and a rib layer 5 are formed above the organic insulating layer 12 and the metal layer M3 (step PR3 in Figure 9). The rib layer 5 is formed over the entire motherboard MB. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0097] After process PR3, a process to form the inspection opening AP10 is carried out (process PR4 in Figure 9). In process PR4, the resist R1 is placed on the rib layer 5. As shown in Figure 11A, the resist R1 has an opening above the wiring TW and above the stepped portion 12a of the organic insulating layer 12 (shown in Figure 12A). In contrast, as shown in Figure 11B, the resist R1 does not have an opening above the pad PD.

[0098] Subsequently, dry etching is performed on the rib layer 5 and the inorganic insulating layer IL using the resist R1 as a mask. This removes the portions of the rib layer 5 and the inorganic insulating layer IL that are exposed from the resist R1.

[0099] After step PR4, as shown in Figure 12A, an inspection opening AP10 is formed in the rib layer 5 and the inorganic insulating layer IL, overlapping with the metal layer M3. The inspection opening AP10 is formed in the region that overlaps with the wiring TW within the region that overlaps with the metal layer M3.

[0100] Furthermore, the rib layer 5 and the inorganic insulating layer IL are removed in the region that overlaps with the stepped portion 12a of the organic insulating layer 12. As a result, the sealing layer SE2, described later, adheres closely to the stepped portion 12a of the organic insulating layer 12, making it less likely to peel off.

[0101] Furthermore, the rib layer 5 and inorganic insulating layer IL that overlap the pad PD are not removed. After the dry etching described above, the resist R1 is removed (peeled off) as shown in Figures 13A and 13B.

[0102] After process PR4, as shown in Figure 13A, a portion of the metal layer M3 of the inspection pad TD is exposed, but as shown in Figure 13B, the metal layer M3 of the pad PD is not exposed. The metal layer M3 of the pad PD is covered by the inorganic insulating layer IL and the rib layer 5, thereby protecting the metal layer M3 in subsequent processes (processes in which the display elements DE1, DE2, and DE3 are formed).

[0103] After process PR4, processes for forming the display elements DE1, DE2, and DE3 are carried out (processes PR5 to PR7 in Figure 9). After forming the display elements DE1, DE2, and DE3, a lighting test of the display elements DE1, DE2, and DE3 is performed using the metal layer M3 exposed from the inspection opening AP10 of the inspection pad TD (process PR8 in Figure 9).

[0104] After step PR8, a sealing layer SE2 is formed covering the rib layer 5, as shown in Figures 14A and 14B (step PR9 in Figure 9). The sealing layer SE2 is formed over the entire mother substrate MB, for example by CVD. The sealing layer SE2 covers the inspection opening AP10, as shown in Figure 14A. In other words, the sealing layer SE2 is in contact with the metal layer M3 at the inspection opening AP10.

[0105] Following step PR9, a process is carried out to form an opening that exposes the metal layer M3 (step PR10 in Figure 9). In other words, a process is carried out to remove the sealing layer SE2, rib layer 5, and inorganic insulating layer IL from the pad PD and inspection pad TD.

[0106] In process PR10, the resist R2 is placed on top of the sealing layer SE2. As shown in Figures 15A and 15B, the resist R2 has an open shape above the pad PD and the inspection pad TD.

[0107] Subsequently, dry etching is performed on the sealing layer SE2, rib layer 5, and inorganic insulating layer IL using the resist R2 as a mask. This removes the portions of the sealing layer SE2, rib layer 5, and inorganic insulating layer IL that are exposed from the resist R2.

[0108] After step PR10, as shown in Figures 16A and 16B, openings overlapping with the metal layer M3 are formed in the rib layer 5, the inorganic insulating layer IL, and the sealing layer SE2. Focusing on the inspection pad TD, an opening 51 is formed in the rib layer 5, an opening ILA is formed in the inorganic insulating layer IL, and an opening SEA is formed in the sealing layer SE2. Focusing on the pad PD, the metal layer M3 is exposed. After the etching described above, the resist R2 is removed as shown in Figures 17A and 17B.

[0109] After step PR10, the region of the third layer M33 of the metal layer M3 that overlaps with the inspection opening AP10 is dry-etched at least twice. As a result, the third layer M33 overlapping the inspection opening AP10 is removed, and region A3 is formed. As described above, the second layer M32 of the metal layer M3 is exposed from region A3. Region A3 has an area equivalent to, for example, the inspection opening AP10.

[0110] Next, after process PR10, the lighting test of the display elements DE1, DE2, and DE3 is performed using the metal layer M3 of the inspection pad TD (process PR11 in Figure 9).

[0111] After step PR11, a step is performed to remove the sealing layer SE2 from the pad PD (step PR12 in Figure 9). In step PR12, a resist R3 is placed on top of the sealing layer SE2. The resist R3 covers the opening 121 of the organic insulating layer 12, the opening 51 of the rib layer 5, the opening ILA of the inorganic insulating layer IL, and the opening SEA of the sealing layer SE2. As shown in Figure 18B, the resist R3 is not placed on top of the pad PD.

[0112] As shown in Figure 18A, the resist R3 has an opening above the inspection pad TD. Specifically, the resist R3 has an opening AP20. In this embodiment, the opening AP20 is an example of a cleaning opening.

[0113] The third layer M33 of the metal layer M3 is exposed through opening AP20. Focusing on inspection opening AP10, the position where opening AP20 is formed does not overlap with the position where inspection opening AP10 is formed. Subsequently, dry etching of the sealing layer SE2 is performed using resist R3 as a mask.

[0114] After step PR12, the sealing layer SE2 is removed in the region containing the pad PD (for example, between adjacent pads PD). In contrast, in the inspection pad TD, the oxide film on the surface of the third layer M33 of the metal layer M3 exposed from the opening AP20 is removed. In other words, the surface of the third layer M33 is cleaned by dry etching. Step PR12 corresponds to the step for cleaning the metal layer M3.

[0115] Furthermore, the etching in process PR12 is performed with an intensity that does not cause the third layer M33 exposed through the opening AP20 to disappear. After the dry etching described above, the resist R3 is removed as shown in Figures 19A and 19B.

[0116] After step PR12, a step for forming a metal layer M4 is carried out (step PR13 in Figure 9). Step PR13 includes forming a fourth layer M41 with a first metal material, forming a fifth layer M42 with a second metal material, forming a sixth layer M43 with a first metal material, and patterning the fourth layer M41, fifth layer M42, and sixth layer M43. The fourth layer M41, fifth layer M42, and sixth layer M43 are formed, for example, by sputtering.

[0117] From another perspective, in process PR13, a first portion P1 (shown in Figure 6) and a second portion P2 (shown in Figure 6) are formed in the inspection pad TD. The second contact portion C2 (shown in Figure 6) corresponds to the portion that overlaps with the region where the opening AP20 is formed (the region where the oxide film has been removed from the surface of the third layer M33).

[0118] In the example shown in Figure 20A, the second contact portion C2 is positioned offset from the first contact portion C1 in the direction opposite to the second direction Y. Alternatively, the second contact portion C2 may be positioned offset from the first contact portion C1 in the first direction X, the direction opposite to the first direction X, or the second direction Y.

[0119] After process PR13, inspection pads TD and PD, including the metal layer M4, are formed as shown in Figures 20A and 20B. Subsequently, after processes such as the formation of the resin layer RS2 (process PR14 in Figure 9), each panel section PP is cut out from the motherboard MB along the cut line CL1 (process PR15 in Figure 9). Then, the inspection area TA (inspection pad TD) is separated from the peripheral area SA along the cut line CL2 (process PR16 in Figure 9). This completes the display panel PNL.

[0120] Figures 21 to 24 are schematic cross-sectional views showing the process of forming the display elements DE1, DE2, and DE3, respectively. Figures 21 to 24 mainly focus on the sub-pixels SP1, SP2, and SP3. Note that in Figures 21 to 24, elements below the organic insulating layer 12 are omitted. When process PR4 is completed, as shown in Figure 21, a partition wall 6 is formed on the rib layer 5 in the display area DA.

[0121] Next, a process for forming the display element DE1 is carried out (process PR5 in Figure 9). In forming the display element DE1, a multilayer film FL1 and a sealing layer SE11 are formed as shown in Figure 21. The multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1, as shown in Figure 3. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0122] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel section PP, but also the peripheral area SA and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0123] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 21, a resist R5 is placed on top of the sealing layer SE11. The resist R5 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0124] Subsequently, an etching process is performed using resist R5 as a mask. As a result, as shown in Figure 22, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist R5 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA and the margin region BA, the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R5 is removed.

[0125] After process PR5, a process for forming the display element DE2 is carried out (process PR6 in Figure 9). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0126] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partition walls 6. By patterning the multilayer film FL2 and the sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 23. For example, in the peripheral region SA and the blank region BA, the multilayer film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0127] After process PR6, a process for forming the display element DE3 is carried out (process PR7 in Figure 9). The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0128] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partition walls 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 24. For example, in the peripheral region SA and the blank region BA, the multilayer film FL3 and the sealing layer SE13 are removed by etching during the patterning process.

[0129] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0130] Figure 25 is a diagram illustrating the openings 121, ILA, 51, and SEA that overlap the inspection pad TD. In Figure 25, some elements such as the metal layer M4 have been omitted.

[0131] The area of ​​the opening 121 in the organic insulating layer 12 is smaller than the area of ​​the opening 51 in the rib layer 5 when viewed from above. The opening ILA in the inorganic insulating layer IL has an area equivalent to, for example, the opening 51 when viewed from above. In other words, the edge of opening ILA is aligned with the edge of opening 51. The area of ​​opening SEA in the sealing layer SE2 is smaller than the areas of openings 51 and ILA, and larger than the area of ​​opening 121 when viewed from above.

[0132] Furthermore, as shown in Figure 25, the region where dry etching is performed in process PR4 is defined as region AE1, the region where dry etching is performed in process PR10 is defined as region AE2, and the region where dry etching is performed in process PR12 is defined as region AE3.

[0133] In Figure 25, region AE1 is hatched with dots, region AE2 is hatched with diagonal lines, and region AE3 is hatched with crosses.

[0134] The outline of region AE1 corresponds to the edge of opening 51, ILA. The inner region of region AE1 overlaps with inspection opening AP10 (region A3 of metal layer M3). The outline of region AE2 corresponds to the edge of opening SEA of sealing layer SE2. Region AE3 overlaps with opening AP20 of resist R3. As described above, the position where opening AP20 is formed does not overlap with the position where inspection opening AP10 is formed.

[0135] Figures 26 to 30 are schematic cross-sectional views showing the manufacturing process of a comparative example display device DSP10. Figures 26 to 30 mainly focus on the inspection pad TD.

[0136] First, as shown in Figure 26, a circuit layer 11, a metal layer M3, an organic insulating layer 12, an inorganic insulating layer IL, and a rib layer 5 are formed on the substrate 10 of the motherboard MB.

[0137] Next, a process is carried out to form openings AP100 in the inorganic insulating layer IL and the rib layer 5. In this process, a resist with an opening shape above the inspection pad TD is placed on the rib layer 5. Then, using the resist as a mask, dry etching is performed on the rib layer 5 and the inorganic insulating layer IL.

[0138] This removes the portions of the rib layer 5 and the inorganic insulating layer IL that are exposed from the resist. After this process, as shown in Figure 27, an opening AP100 is formed in the rib layer 5 and the inorganic insulating layer IL. The metal layer M3 is exposed through the opening AP100.

[0139] Next, after processes such as forming the display elements DE1, DE2, and DE3, and performing lighting inspections, a sealing layer SE2 is formed that covers the rib layer 5. The sealing layer SE2 covers the opening AP100.

[0140] Next, a process is carried out to remove the sealing layer SE2 from the inspection pad TD. In this process, a resist with an open shape above the inspection pad TD is placed on top of the sealing layer SE2.

[0141] Subsequently, dry etching is performed on the encapsulation layer SE2 using the resist as a mask. This removes the portion of the encapsulation layer SE2 that is exposed from the resist. After this process, an opening AP200 is formed in the encapsulation layer SE2, as shown in Figure 28.

[0142] The third layer M33, which overlaps the opening AP200, is subjected to dry etching at least twice. This removes the third layer M33 in the region overlapping the opening AP200, exposing the second layer M32 of the metal layer M3 through the opening AP200.

[0143] Next, a process is carried out to remove the sealing layer SE2 from the pad PD. Focusing on the inspection pad TD, as shown in Figure 29, a resist R3 with an open shape is placed on top of the sealing layer SE2 on the inspection pad TD. In other words, the resist R3 has an opening AP300.

[0144] The location where the opening AP300 is formed overlaps with the aforementioned openings AP100 and AP200. The second layer M32 of the metal layer M3 is exposed through the opening AP300. During this process, the second layer M32, which is made of an aluminum-based material, is dissolved by the resist developer, or the surface of the exposed second layer M32 is oxidized. Subsequently, as shown in Figure 30, a process for forming the metal layer M4 is carried out.

[0145] In the comparative example DSP10, the fourth layer M41 of the metal layer M4 is in contact with the second layer M32 of the metal layer M3, as shown in Figure 30. The second layer M32, which is in contact with the fourth layer M41, is, for example, oxidized.

[0146] Because the oxidized second layer M32 has high resistance, the connection resistance between metal layer M3 and metal layer M4 increases. This can lead to poor electrical contact between metal layer M3 and metal layer M4. Using such an inspection pad TD to inspect the display area DA, etc., can reduce the reliability of the motherboard and display device.

[0147] In this embodiment, the metal layer M4 has a second contact portion C2 that contacts the third layer M33 of the metal layer M3. At the second contact portion C2, it contacts the third layer M33 of the oxidized metal layer M3, rather than the second layer M32, thus reducing the connection resistance between the metal layer M3 and the metal layer M4.

[0148] This allows for the formation of an inspection pad TD on the motherboard MB in which metal layers M3 and M4 are stably connected. By using such an inspection pad TD, the display area DA (e.g., display elements DE1, DE2, DE3, etc.) can be reliably inspected. As a result, a decrease in the reliability of the motherboard MB and the display device DSP can be suppressed.

[0149] Furthermore, in the manufacturing method according to this embodiment, the position where the opening AP20 (shown in Figure 18A) is formed does not overlap with the position where the inspection opening AP10 (shown in Figure 13A) is formed.

[0150] Therefore, the third layer M33 of the metal layer M3 is exposed through the opening AP20. This allows the oxide film on the surface of the third layer M33 exposed through the opening AP20 to be removed (cleaned) in step PR12. As a result, defects in the electrical contact between the metal layer M3 and the metal layer M4 become less likely to occur. In other words, in this embodiment, a contact area can be formed in which defects in the electrical contact between the metal layer M3 and the metal layer M4 are less likely to occur.

[0151] Furthermore, the second layer M32 is not exposed through the opening AP20. Therefore, compared to the manufacturing method of the display device DSP10 according to the comparative example described with reference to Figure 29, the elution of the second layer M32 from the metal layer M3 can be suppressed.

[0152] With the motherboard MB, display device DSP, and manufacturing method for the display device DSP configured as described above, a decrease in reliability can be suppressed. In addition, various other desirable effects can be obtained from this embodiment.

[0153] [Second Embodiment] A second embodiment will now be described. The configurations of the display device DSP, motherboard MB, and method for manufacturing the display device DSP, which are not mentioned in this embodiment, can be the same as those in the first embodiment described above.

[0154] Figure 31 is a schematic plan view of the motherboard MB according to this embodiment. In this embodiment, the display area DA is a long rectangle in the second direction Y. The inspection pad TD is located near the pad PD (peripheral area SA). Specifically, the inspection pad TD is located between the cut line CL2 and the display area DA. Note that the arrangement of the inspection pad TD is not limited to the example shown in Figure 31. For example, the inspection pad TD may be located between adjacent pads PD.

[0155] By cutting along the cut line CL2, a display panel for a display device DSP equipped with an inspection pad TD can be formed. Even if the panel portion PP has such a configuration, the same effects as in the first embodiment can be obtained by applying the configuration disclosed in the first embodiment.

[0156] Furthermore, various other configurations can be applied to the panel section PP. For example, the display area DA of each panel section PP may be a long rectangle in the first direction X, or it may be a square. Also, the display area DA may have a shape that includes multiple straight lines and curved sections.

[0157] All display devices, motherboards, and manufacturing methods that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices, motherboards, and manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0158] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of components, or to add, omit, or change the conditions of processes, to the above-described embodiments are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0159] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0160] 5...Rib layer, 6...Partition wall, 10...Substrate, 11...Circuit layer, 12...Organic insulating layer, 51...Aperture, 111,112,113,IL...Inorganic insulating layer, 114...Organic insulating layer, AP1,AP2,AP3...Pixel aperture, AP10...Inspection aperture, AP20...Aperture, BA...Margin area, C1...First contact area, C2...Second contact area, CL1,CL2...Cut line, DA...Display area, DE1,DE2,DE3...Display element, DSP...Display device, ILA...Aperture, M 3...metal layer, M4...metal layer, M31...1st layer, M32...2nd layer, M33...3rd layer, M41...4th layer, M42...5th layer, M43...6th layer, MB...mother board, OR1,OR2,OR3...organic layer, P1...1st part, P2...2nd part, PD...pad, PNL...display panel, PP...panel part, SA...peripheral area, SE2...encapsulation layer, SEA...opening, TA...inspection area, TD...inspection pad, TW...wiring, UE1,UE2,UE3...upper electrode.

Claims

1. Multiple panel sections having a display area and a peripheral area surrounding the display area, A display element arranged in the aforementioned display area, A rib layer is arranged in the display area and the peripheral area and has a pixel aperture that overlaps with the display element, The system comprises an inspection pad arranged in the peripheral region, The aforementioned inspection pad is The first metal layer and The first metal layer has a second metal layer that overlaps it, The aforementioned rib layer is Displaced between the first metal layer and the second metal layer, The second metal layer further has a first opening that contacts the first metal layer, The first metal layer is A first layer formed of a first metal material, A second layer is formed of a second metallic material and overlaps the first layer, It has a third layer formed of the first metal material and overlapping the second layer, The third layer has a region in the first opening that exposes the second layer. The aforementioned second metal layer is In the region, a first contact portion that contacts the second layer, It has a second contact portion that contacts the third layer, Motherboard for display devices.

2. Further comprising inspection wiring overlapping the first metal layer, The first contact portion is located above the inspection wiring, The second contact portion is not located above the inspection wiring. Mother board for display device according to claim 1.

3. The material further comprises an organic insulating layer disposed between the first metal layer and the rib layer, The organic insulating layer has a second opening that overlaps the first opening, The area of ​​the second opening is smaller than the area of ​​the first opening in a plan view. The first contact portion and the second contact portion are located inside the second opening. Mother board for display device according to claim 1.

4. The system further comprises an inorganic insulating layer disposed between the organic insulating layer and the rib layer, The inorganic insulating layer has a third opening that overlaps the first and second openings. Motherboard for display device according to claim 3.

5. The display area further comprises partition walls surrounding the pixel aperture, The partition wall includes a lower part positioned above the rib layer and an upper part having an end protruding from the side surface of the lower part. Mother board for display device according to claim 1.

6. In the display area and the surrounding area, a sealing layer is further provided, which is positioned above the rib layer and is made of an inorganic material. The sealing layer has a fourth opening that overlaps the first opening, The area of ​​the fourth opening is smaller than the area of ​​the first opening in a plan view. Mother board for display device according to any one of claims 1 to 5.

7. Multiple panel sections having a display area and a peripheral area surrounding the display area, A display element arranged in the aforementioned display area, A rib layer is arranged in the display area and the peripheral area and has a pixel aperture that overlaps with the display element, The system comprises an inspection pad arranged in the peripheral region, The aforementioned inspection pad is The first metal layer and The first metal layer has a second metal layer that overlaps it, The aforementioned rib layer is Displaced between the first metal layer and the second metal layer, The second metal layer has a first opening that contacts the first metal layer, The first metal layer is A first layer formed of a first metal material, A second layer is formed of a second metallic material and overlaps the first layer, It has a third layer formed of the first metal material and overlapping the second layer, The aforementioned second metal layer is A fourth layer formed of the first metal material, A fifth layer formed of the second metal material and overlapping the fourth layer, It has a sixth layer made of the first metal material and overlapping the fifth layer, The aforementioned inspection pad includes: A first portion comprising the first layer, the second layer, the fourth layer, the fifth layer and the sixth layer stacked together, A second portion is formed in which the first, second, third, fourth, fifth, and sixth layers are stacked, Motherboard for display devices.

8. The thickness of the second part is greater than the thickness of the first part. Mother board for display device according to claim 7.

9. The distance between the second layer and the fifth layer in the second portion is greater than the distance between the second layer and the fifth layer in the first portion. Mother board for display device according to claim 7.

10. The system further includes a cut line for separating the inspection pad from the surrounding area. Mother board for display device according to claim 1 or 7.

11. Display area and, The surrounding area that encloses the aforementioned display area, A display element arranged in the aforementioned display area, A rib layer is arranged in the display area and the peripheral area and has a pixel aperture that overlaps with the display element, The system comprises an inspection pad arranged in the peripheral region, The aforementioned inspection pad is The first metal layer and The first metal layer has a second metal layer that overlaps it, The aforementioned rib layer is Displaced between the first metal layer and the second metal layer, The second metal layer has a first opening that contacts the first metal layer, The first metal layer is A first layer formed of a first metal material, A second layer is formed of a second metallic material and overlaps the first layer, It has a third layer formed of the first metal material and overlapping the second layer, The third layer has a region in the first opening that exposes the second layer. The aforementioned second metal layer is In the region, a first contact portion that contacts the second layer, It has a second contact portion that contacts the third layer, Display device.

12. Further comprising inspection wiring overlapping the first metal layer, The first contact portion is located above the inspection wiring, The second contact portion is not located above the inspection wiring. The display device according to claim 11.

13. Display area and, The surrounding area that encloses the aforementioned display area, A display element arranged in the aforementioned display area, A rib layer is arranged in the display area and the peripheral area and has a pixel aperture that overlaps with the display element, The system comprises an inspection pad arranged in the peripheral region, The aforementioned inspection pad is The first metal layer and The first metal layer has a second metal layer that overlaps it, The aforementioned rib layer is Displaced between the first metal layer and the second metal layer, The second metal layer has a first opening that contacts the first metal layer, The first metal layer is A first layer formed of a first metal material, A second layer is formed of a second metallic material and overlaps the first layer, It has a third layer formed of the first metal material and overlapping the second layer, The aforementioned second metal layer is A fourth layer formed of the first metal material, A fifth layer formed of the second metal material and overlapping the fourth layer, It has a sixth layer made of the first metal material and overlapping the fifth layer, The aforementioned inspection pad includes: A first portion comprising the first layer, the second layer, the fourth layer, the fifth layer and the sixth layer stacked together, A second portion is formed in which the first, second, third, fourth, fifth, and sixth layers are stacked, Display device.

14. The thickness of the second part is greater than the thickness of the first part. The display device according to claim 13.

15. The distance between the second layer and the fifth layer in the second portion is greater than the distance between the second layer and the fifth layer in the first portion. The display device according to claim 13.

16. A substrate is prepared having a panel section that includes a display area and a peripheral area surrounding the display area, A first metal layer is formed in the peripheral region. A rib layer of inorganic material is formed above the first metal layer. An inspection opening is formed in the rib layer that overlaps with the first metal layer. A sealing layer of inorganic material is formed to cover the rib layer and the inspection opening. Openings are formed in the rib layer and the sealing layer to expose the first metal layer. A resist having a cleaning opening that overlaps the aforementioned opening is placed, The first metal layer exposed through the cleaning opening is cleaned. A second metal layer is formed which overlaps the first metal layer. This includes, The position where the cleaning opening is formed does not overlap with the position where the inspection opening is formed. A method for manufacturing a display device.

17. The formation of the inspection opening, the formation of the opening, and the cleaning are carried out by dry etching. A method for manufacturing a display device according to claim 16.

18. Forming the first metal layer is The first layer is formed by the first metallic material. A second layer is formed on top of the first layer using a second metallic material. The first metal material is used to form a third layer that overlaps the second layer. This includes, The third layer is exposed from the cleaning opening, A method for manufacturing a display device according to claim 17.

19. Forming the aforementioned second metal layer is The first metal material is used to form the fourth layer, A fifth layer is formed using the second metal material, which overlaps the fourth layer. The first metal material is used to form a sixth layer that overlaps the fifth layer. Including, A method for manufacturing a display device according to claim 18.

20. Forming the aforementioned second metal layer is The first layer, the second layer, the fourth layer, the fifth layer and the sixth layer are stacked to form a first portion, The first layer, the second layer, the third layer, the fourth layer, the fifth layer and the sixth layer are stacked to form a second portion, Including, A method for manufacturing a display device according to claim 19.

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