memory devices

Abstract

Suppress defects. [Solution] The memory device 1 of the embodiment includes a second chip 10 bonded to a first chip 20, the second chip including a laminate 900 including a plurality of conductive layers 103 arranged in a first direction perpendicular to the chip surface, a semiconductor layer 101a above the laminate, a first contact CC1 including a portion that penetrates at least the first conductive layer of the plurality of conductive layers, is connected to the first conductive layer and is located within the semiconductor layer, a second contact CC1 including a portion that penetrates at least the second conductive layer of the plurality of conductive layers, is connected to the second conductive layer and is located within the semiconductor layer, and is aligned with the first contact in a second direction parallel to the chip surface, and a separation member BB1 provided in the semiconductor layer between the first and second contacts. The dimension of the separation member along the second direction opposite to the first chip is greater than the dimension of the separation member along the second direction on the first chip side.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices.

Background Art

[0002] As a memory device capable of storing data non-volatilely, NAND flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress defects in memory devices.

Means for Solving the Problems

[0005] The memory device of the embodiment comprises a substrate, a first chip including a circuit on the substrate, and a second chip bonded to the first chip, wherein the second chip is a laminate including a plurality of conductive layers spaced apart from each other in a first direction perpendicular to the surface of the second chip, and a memory pillar penetrating the plurality of conductive layers, a first semiconductor layer provided above the laminate in the first direction and connected to a source line, and a first conductive layer penetrating at least one of the plurality of conductive layers and connected to the first conductive layer The device comprises: a first contact whose portion opposite to the first chip is located within the first semiconductor layer; a second contact that penetrates at least a second conductive layer among the plurality of conductive layers and is connected to the second conductive layer, whose portion opposite to the first chip is located within the first semiconductor layer and is aligned with the first contact in a second direction parallel to the surface of the second chip; and a first separating member that separates the first semiconductor layer in a second direction between the first contact and the second contact. The first separating member includes a first portion located along the first chip-side surface of the first semiconductor layer and a second portion located along the surface opposite to the first chip of the first semiconductor layer, wherein the first dimension of the second portion along the second direction is greater than the second dimension of the first portion along the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the overall configuration of the memory device according to the first embodiment. [Figure 2] Circuit diagram of a memory cell array of a memory device according to the first embodiment. [Figure 3] A schematic diagram of the bonding structure of the memory device according to the first embodiment. [Figure 4] A cross-sectional view showing an example of the structure of a memory device according to the first embodiment. [Figure 5] A plan view showing the layout of the memory device according to the first embodiment. [Figure 6]A cross-sectional view showing an example of the structure of a memory cell array in a memory device according to the first embodiment. [Figure 7] A cross-sectional view showing an example of the structure of a memory pillar in a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing the structure of the bonding pad of the memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example of the structure of the isolation member of the memory device according to the first embodiment. [Figure 10] A plan view showing an example of the structure of the contact and isolation members of a memory device according to the first embodiment. [Figure 11A] A cross-sectional view showing an example of the structure of the contact and isolation members of a memory device according to the first embodiment. [Figure 11B] A cross-sectional view showing an example of the structure of the contact and isolation members of a memory device according to the first embodiment. [Figure 12] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 13] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 14] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 15] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 16] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 17] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 18] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 19] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 20] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 21] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the first embodiment. [Figure 22] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 23] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 24] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 25] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 26] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 27] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 28] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 29] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 30] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 31] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the first embodiment. [Figure 32] Plan view showing a structural example of the memory device of the second embodiment. [Figure 33] Cross-sectional view showing a structural example of the memory device of the second embodiment. [Figure 34] Cross-sectional view showing a structural example of the memory device of the third embodiment. [Figure 35] Cross-sectional view showing a structural example of the contacts and separation members of the memory device of the fourth embodiment. [Figure 36] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the fourth embodiment. [Figure 37] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the fourth embodiment. [Figure 38] Cross-sectional process diagram showing a step of the manufacturing method of the memory device of the fourth embodiment. [Figure 39]A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 40] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 41] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 42] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 43] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 44] A cross-sectional process diagram showing one step in the manufacturing method of a memory device according to the fourth embodiment. [Figure 45] A cross-sectional view showing an example of the structure of a memory device according to the fifth embodiment. [Modes for carrying out the invention]

[0007] The embodiment of the memory device and the method for manufacturing the memory device will be described with reference to Figures 1 to 45. In the following description, elements having the same function and configuration will be denoted by the same reference numeral. In addition, in each of the following embodiments, if components that are denoted by reference numerals with distinguishing numerals / letters at the end (for example, circuits, wiring, various voltages and signals, etc.) do not need to be distinguished from one another, the reference numerals / letters at the end will be omitted.

[0008] <Embodiment> (1) First Embodiment A memory device and a method for manufacturing the memory device according to the first embodiment will be described with reference to Figures 1 to 31.

[0009] (a) Configuration example (a-1) Overall configuration of the memory device Referring to Figure 1, an example of the overall configuration of the memory device 1 of this embodiment will be described. Figure 1 is a block diagram showing the overall configuration of the memory device 1 of this embodiment. In Figure 1, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0010] Memory device 1 is, for example, a three-dimensional stacked NAND flash memory. A three-dimensional stacked NAND flash memory includes a plurality of memory cells (hereinafter also called memory cell transistors) arranged in three dimensions on a semiconductor substrate.

[0011] As shown in Figure 1, the memory device 1 of this embodiment includes a plurality of plane PLNs, a voltage generation circuit 23, and a sequencer 24.

[0012] Each of the multiple plane PLNs is a group of circuits that can operate independently and in parallel (simultaneously) with respect to each other. Each of the multiple plane PLNs includes a memory cell array 11, a row decoder 21, and a sense amplifier 22.

[0013] Each memory cell array 11 contains multiple block blocks (BLKs). A block block is, for example, a collection of multiple memory cells whose data is erased all at once. The memory cells are arranged three-dimensionally within the memory cell array 11. The multiple memory cells within a block block are associated with rows and columns. Details of the internal configuration of the memory cell array 11 and block blocks will be described later.

[0014] The row decoder 21 is a circuit that decodes row addresses. Row addresses are address signals that specify the row-direction wiring of the memory cell array 11. Based on the decoding result of the row addresses, the row decoder 21 supplies the voltage used for the operation of the memory cell array 11 to the memory cell array 11.

[0015] The sense amplifier 22 is a circuit that performs data writing and reading. During a read operation, the sense amplifier 22 senses the data read from the memory cell array 11. During a write operation, the sense amplifier 22 supplies a voltage to the memory cell array 11 corresponding to the data to be written.

[0016] The voltage generation circuit 23 is a circuit that generates various voltages used for writing, reading, and erasing operations. For example, the voltage generation circuit 23 is connected to the row decoder 21 and sense amplifier 22 of each plane PLN. The voltage generation circuit 23 supplies the generated voltage to each row decoder 21 and each sense amplifier 22.

[0017] The sequencer 24 is the control circuit for the memory device 1. The sequencer 24 controls the overall operation of the memory device 1. For example, the sequencer 24 is connected to the row decoder 21, the sense amplifier 22, and the voltage generation circuit 23. The sequencer 24 controls the row decoder 21, the sense amplifier 22, and the voltage generation circuit 23. Based on the control of an external controller (not shown), the sequencer 24 performs write operations, read operations, erase operations, etc., on the memory cell array 11.

[0018] In the following, the group of circuits that control the operation of the memory cell array 11, such as the row decoder 21, sense amplifier 22, voltage generation circuit 23, and sequencer 24, will also be called CMOS circuits (or peripheral circuits).

[0019] (a-2) Circuit configuration of memory cell array Referring to Figure 2, an example of the circuit configuration of the memory cell array 11 will be described. Figure 2 is a circuit diagram of the memory cell array 11. The example in Figure 2 shows the circuit configuration of one block BLK.

[0020] As shown in Figure 2, a block BLK includes multiple string units SU. A string unit SU is a collection of multiple NAND strings NS that are selected together, for example, during a write or read operation. A NAND string NS includes a collection of multiple memory cells MC connected in series. For example, one block BLK includes four string units SU0, SU1, SU2, and SU3.

[0021] The number of block BLKs in the memory cell array 11 and the number of string units SUs within each block BLK are arbitrary.

[0022] Each NAND string NS includes multiple memory cells MC, select transistors ST1 and ST2. In the example in Figure 2, the NAND string NS includes eight memory cells MC0, MC1, ..., MC6, MC7. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0023] A memory cell (MC) is a memory element that stores data non-volatilely. A memory cell MC is a transistor that includes a control gate and a charge storage layer. A memory cell MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type transistor or an FG (Floating Gate) type transistor. In a MONOS type memory cell transistor, an insulating layer such as a silicon nitride layer is used for the charge storage layer. In an FG type memory cell transistor, a conductive layer such as a polysilicon layer is used for the charge storage layer. The following description will focus on the case where the memory cell MC is a MONOS type transistor.

[0024] The select transistors ST1 and ST2 are switching elements. Each select transistor ST1 and ST2 is used to select the string unit SU during various operations of the memory device 1. The number of select transistors ST1 and ST2 in the NAND string NS is arbitrary. It is sufficient that there is one or more select transistors ST1 and ST2 in the NAND string NS.

[0025] The current paths of select transistor ST2, memory cells MC0, ..., MC7, and select transistor ST1 within the NAND string NS are connected in series. The drain of select transistor ST1 is connected to the bit line BL. The source of select transistor ST2 is connected to the source line SL.

[0026] Each control gate of memory cells MC0, ..., MC7 within the same block BLK is connected to the corresponding word line WL0, ..., WL7. Each of the four string units SU contains a memory cell MC0. The control gates of multiple memory cells MC0 within a block BLK are connected in common to a single word line WL0. Memory cells MC1, ..., MC7 are also connected to their corresponding word lines WL1, ..., WL7, respectively, similar to memory cells MC0.

[0027] The gates of multiple select transistors ST1 within a string unit SU are connected in common to a single select gate line SGD. More specifically, the gates of multiple select transistors ST1 within a string unit SU0 are connected in common to select gate line SGD0. The gates of multiple select transistors ST1 within a string unit SU1 are connected in common to select gate line SGD1. The gates of multiple select transistors ST1 within a string unit SU2 are connected in common to select gate line SGD2. The gates of multiple select transistors ST1 within a string unit SU3 are connected in common to select gate line SGD3.

[0028] The gates of multiple select transistors ST2 within block BLK are connected in common to a single select gate line SGS. Note that, similar to the select gate line SGD, multiple different select gate lines SGS may be provided within block BLK for each string unit SU.

[0029] Word lines WL0, ..., WL7, select gate lines SGD0, ..., SGD3, and select gate line SGS are connected to the row decoder 21, respectively.

[0030] The bit line BL is commonly connected to one NAND string NS within each string unit SU of each block BLK. The same column address is assigned to multiple NAND strings NS connected to a single bit line BL. Each bit line BL is connected to the sense amplifier 22.

[0031] Source lines SL are shared, for example, among multiple blocks BLK within a single plane PLN. Source lines SL are independent for each plane PLN.

[0032] A collection of multiple memory cells MC connected to a common word line WL within a single string unit SU is denoted, for example, as a cell unit CU. For example, write and read operations are performed on a cell unit CU basis.

[0033] (a-3) Overview of the bonding structure of memory devices Referring to Figure 3, the general structure of the memory device 1 of this embodiment will be described. Figure 3 is a bird's-eye view showing the general structure of the bonded memory device 1.

[0034] As shown in Figure 3, the memory device 1 of this embodiment includes two semiconductor chips 10 and 20.

[0035] One of the two semiconductor chips 10, 20 is an array chip (also called a memory cell array chip) 10. The array chip 10 is a chip equipped with multiple memory cell arrays 11.

[0036] Of the two semiconductor chips 10 and 20, the other is a CMOS circuit chip (also called a CMOS chip) 20. The CMOS circuit chip 20 is a chip equipped with a CMOS circuit that controls the array chip 10.

[0037] The memory device 1 of this embodiment is formed by bonding an array chip 10 and a CMOS circuit chip 20. The memory device 1 has a structure in which the array chip 10 and the CMOS circuit chip 20 are bonded together (hereinafter referred to as the "bonded structure"). In the following, when the array chip 10 and the CMOS circuit chip 20 are not distinguished, each of the array chip 10 and the CMOS circuit chip 20 will simply be referred to as a chip.

[0038] Multiple array chips 10 may be provided within the memory device 1. In this case, multiple array chips 10 may be bonded together so as to be stacked on a CMOS circuit chip 20. Multiple CMOS circuit chips 20 may also be provided within the memory device 1.

[0039] As shown in Figure 3, the array chip 10 includes a plurality of pads (electrodes, conductive layers, conductors) 111 on plane F1. The CMOS circuit chip 20 includes a plurality of pads 211 on plane F2. The pads 111 and 211 are used for bonding the two chips together.

[0040] In the bonded memory device 1, the surface F1 of the array chip 10 is bonded to the surface F2 of the CMOS circuit chip 20. Thus, the surface F1 on which the pads 111 of the array chip 10 are located faces the surface F2 on which the pads 211 of the CMOS circuit chip 20 are located. Hereafter, the surfaces F1 and F2 on which the array chip 10 and the CMOS circuit chip 20 are bonded will also be referred to as the bonding surface BF.

[0041] In the bonded structure, the pad 111 of the array chip 10 and the pad 211 of the CMOS circuit chip 20 are bonded together. This forms a single bonded pad BP within the memory device 1. In other words, the electrodes constituting the pad 111 on the array chip 10 are bonded to the electrodes constituting the pad 211 on the CMOS circuit chip 20. This forms the bonded pad BP of the bonded memory device 1.

[0042] The bonded pad BP includes an active pad and a dummy pad. The active pad functions as a signal or power path during the operation of memory device 1. The active pad is electrically connected to either the signal or power path. The dummy pad does not function as a signal or power path during the operation of memory device 1. The dummy pad is not electrically connected to the signal or power path.

[0043] In the following, the surface (bonding surface BF) on which the array chip 10 and the CMOS circuit chip 20 are bonded together is referred to as the XY plane. Within the XY plane, mutually orthogonal directions are referred to as the X direction and the Y direction. The X direction and the Y direction are parallel to the XY plane. The direction that is approximately perpendicular to the XY plane and moves from the array chip 10 toward the CMOS circuit chip 20 is referred to as the Z1 direction. The direction that is approximately perpendicular to the XY plane and moves from the CMOS circuit chip 20 toward the array chip 10 is referred to as the Z2 direction. When the Z1 direction and the Z2 direction are not distinguished, the direction that is approximately perpendicular to the XY plane is referred to as the Z direction.

[0044] (a-4) Structure of memory devices Referring to Figure 4, an example of the structure of the memory device 1 of this embodiment will be described. Figure 4 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1. In Figure 4, the main components of the memory device 1 of this embodiment are shown in detail.

[0045] As described above, the memory device 1 of this embodiment shown in Figure 4 has a bonded structure of an array chip 10 and a CMOS circuit chip 20.

[0046] The array chip 10 includes memory pillar MP, semiconductor layers 101a, 101c, insulating layers 102, 102A, 109, 121, 125, 126, 128, 129, 150, 160, 162, 165, 169, insulator 151, insulating film 155, conductive layer (word line and select gate line) 103, wiring 106, 127, 163, conductors 104, 161, 164, contacts CX, CZ, CC1, CC2, metal layer 120, and electrodes (pads) 111.

[0047] The CMOS circuit chip 20 includes a semiconductor substrate 200, a transistor TR, conductors (plugs) 204, 208, 210, wiring 205, 209, electrodes (pads) 211, and insulating layers 260, 269. The transistor TR includes a gate insulating layer 202, a gate electrode 203, and a source / drain layer (not shown).

[0048] Electrodes 111 and 211 are used in the bonded pad BP. The contact surface between the insulating layer 169 and the insulating layer 269 is the bonded surface BF of the two chips 10 and 20.

[0049] (a-5) Structure of the array chip Referring to Figures 4 and 5, the structure of the array chip 10 in the memory device 1 of this embodiment will be described.

[0050] Referring to Figure 5, the layout of the array chip 10 of the memory device 1 in this embodiment will be described.

[0051] Figure 5 is a plan view showing the layout of the core area of ​​the array chip 10 in the memory device 1 of this embodiment.

[0052] In the array chip 10 of the memory device 1, the core region includes multiple memory cell array areas MA, a contact area CA, a pad area PA, and a plane isolation area DA.

[0053] If the memory device 1 includes multiple planes PLN, the array chip 10 includes multiple memory cell array areas MA. For example, the multiple memory cell array areas MA are aligned in the X direction within the core region. Each of the multiple memory cell array areas MA includes a memory cell array 11. Each memory cell array area MA is provided for each plane PLN.

[0054] The plane isolation area DA partitions the memory cell array area MA (memory cell array 11) into planes PLN. The plane isolation area DA surrounds each memory cell array area MA. The plane isolation area DA separates multiple memory cell arrays 11 into planes PLN. The plane isolation area DA has a grid-like layout when viewed from the Z direction. The plane isolation area DA is laid out between two memory cell array areas MA, between the memory cell array area MA and the contact area CA, and between the memory cell array area MA and the pad area PA.

[0055] The plane separation area DA includes a grid-like slit (opening) when viewed from the Z direction. The separation member BB2, described later, is provided within the slit. The separation member BB2 has a grid-like structure depending on the shape of the slit. The slit and the separation member BB2 have a portion extending in the X direction and a portion extending in the Y direction.

[0056] The contact area CA is located within the core region, surrounding multiple memory cell array areas MA. Multiple contacts CC2, described later, are provided within the contact area CA.

[0057] The pad area PA is located within the region between the contact area CA and the memory cell array area MA. The pad area PA includes a plurality of pads 99. For example, the pads 99 in the pad area PA are external connection terminals. The pads 99 in the pad area PA are electrically connected to contacts CC2 in the contact area CA, wiring in the memory cell array area MA, and / or wiring in the CMOS circuit chip 20, etc.

[0058] The array chip 10 further includes a kerf region (not shown) at the end of the array chip 10, and a peripheral region (not shown) between the kerf region and the core region. The kerf region includes a dicing area, alignment making and characteristic checking patterns, etc. The peripheral region includes edge seals, etc.

[0059] In Figure 4, the portions of the array chip 10 corresponding to the AA line of the memory cell array area MA, the BB line of the contact area CA, and the CC line of the plane isolation area DA in Figure 5 are extracted and shown.

[0060] As shown in Figure 4, in the memory cell array area MA, the semiconductor layer 101a extends in the X and Y directions. The semiconductor layer 101a provided within the memory cell array area MA functions as part of the source line SL. For example, the semiconductor layer 101a contains silicon.

[0061] In the memory cell array area MA, multiple insulating layers 102, 102A and multiple conductive layers 103 are alternately stacked one layer at a time on the Z1-oriented surface of the semiconductor layer 101a. A laminate 900 containing multiple insulating layers 102, 102A and multiple conductive layers 103 is provided within the memory cell array area MA. Multiple conductive layers 103, stacked spaced apart in the Z direction by the insulating layers 102, are provided between the CMOS circuit chip 20 and the semiconductor layer 101a. In the example in Figure 4, 10 insulating layers 102 and 10 conductive layers 103 are alternately stacked one layer at a time. The number of insulating layers 102 and conductive layers 103 stacked in the Z direction is set according to the configuration of the memory cell array 11 (e.g., storage capacity).

[0062] Each of the multiple conductive layers 103 extends in the X direction and functions as one of the word lines WL, select gate lines SGD, and select gate lines SGS. The conductive layer 103 contains a conductive material such as tungsten (W).

[0063] The insulating layer 102 separates two adjacent conductive layers 103 in the Z direction. The insulating layer 102 contains an insulating material such as silicon oxide. Of the multiple insulating layers 102, 102A, the insulating layer 102A located closest to the CMOS circuit chip 20 has a thicker film thickness than the other insulating layers 102.

[0064] Multiple memory pillars MP are provided within the memory cell array area MA. Each memory pillar MP corresponds to one NAND string NS. The memory pillars MP have, for example, a cylindrical shape extending in the Z direction. The memory pillars MP penetrate (pass through) multiple insulating layers 102, 102A and multiple conductive layers 103.

[0065] The side surface of the memory pillar MP (the surface intersecting the XY plane) faces the conductive layer 103. The Z2 end of the memory pillar MP penetrates the semiconductor layer 101a. The memory pillar MP includes a memory layer 142, a semiconductor layer 143, and a core layer 144. The semiconductor layer 143 extends in the Z direction. A portion of the semiconductor layer 143 is in contact with the metal layer 120 on the semiconductor layer 101a. Details of the structure of the memory pillar MP will be described later.

[0066] For example, an insulating layer 109, such as aluminum oxide, may be provided between the conductive layer 103 and the insulating layers 102, 102A, and between the conductive layer 103 and the memory pillar MP.

[0067] In the following, at the ends of each member in the Z direction, the end on the Z2 direction side of the member is also called the top, and the end on the Z1 direction side of the member is also called the bottom.

[0068] The metal layer 120 is provided on the semiconductor layer 101a. The metal layer 120 is electrically connected to the semiconductor layer 101a and the semiconductor layer 143 of the memory pillar MP. The metal layer 120 functions as a source wire SL. Thus, the source wire SL includes the metal layer 120 and the portion of the semiconductor layer 101a that contacts the memory pillar MP.

[0069] The structure of the source wire SL is not limited to the example using the metal layer 120. For example, the source wire SL may have a structure in which a source wire SL made of a semiconductor layer is connected to the semiconductor layer 143 of the memory pillar MP through an opening formed in the memory layer 142 of the memory pillar MP. In this case, the semiconductor layer of the source wire SL covers the end of the memory pillar MP.

[0070] For example, a slit (not shown) extending in the X direction is provided within a laminate 900 containing insulating layers 102, 102A and conductive layers 103. An insulator (not shown) is filled inside the slit. This insulator penetrates multiple insulating layers 102, 102A and multiple conductive layers 103. For example, a region demarcated by the insulator (and slit) corresponds to one block BLK. The slit is also used to supply etching agent and raw materials for the conductive layer 103 into the laminate 900 during the process of forming the conductive layer 103.

[0071] A conductor 104 is provided within the insulating layer 162 on the Z1-oriented surface of the memory pillar MP. The conductor 104 has, for example, a cylindrical shape extending in the Z direction. Wiring 106 is provided within the insulating layer 165 on the Z1-oriented surface of the conductor 104. Multiple wirings 106 are aligned in the X direction within the memory cell array area MA. Each of the multiple wirings 106 extends in the Y direction. Each of the multiple memory pillars MP is electrically connected to one of the multiple wirings 106 via the conductor 104. Wiring 106 functions as a bit line BL. Wiring 106 includes, for example, copper (Cu).

[0072] The ends of the laminate 900, which includes multiple insulating layers 102, 102A and multiple conductive layers 103, in the X direction are processed in a stepped manner. Hereinafter, the stepped portion of the laminate 900 will be referred to as the stepped structure. The stepped structure is covered with an insulating layer 160. Furthermore, hereinafter, the region within the memory cell array area MA where the stepped structure is located will be referred to as the extraction area.

[0073] In the stepped structure, the conductive layer 103 includes a portion (hereinafter referred to as a terrace) on the Z1 side that is not covered by the laminated insulating layer 102 and other conductive layers 103 (i.e., does not overlap with other conductive layers 103). The conductive layer 103 contacts the contact (contact plug) CC1 at the terrace. This electrically connects the conductive layer 103 to the contact CC1.

[0074] Multiple contacts CC1 are provided within the extraction area of ​​the memory cell array area MA. The multiple contacts CC1 are aligned in the X and / or Y directions. The contacts CC1 penetrate the stepped insulating layer 102 and the conductive layer 103. The contacts CC1 are conductors. The contacts CC1 have a cylindrical shape extending in the Z direction. The contacts CC1 include a portion 90 that contacts the terraces of the conductive layer 103. The contacts CC1 include a portion 91 that reaches the semiconductor layers 101a, 101c and the insulating layer 121. Details of the structure of the contacts CC1 will be described later.

[0075] The conductor (via plug) 161 is provided within the insulating layer 162. The wiring 163 is provided within the insulating layer 165. The wiring 163 is connected to contact CC1 via the conductor 161. The wiring 163 is electrically connected to electrode 111, for example, via the conductor 164 in the insulating layer 165.

[0076] Multiple support members HR are provided in the pull-out area. The support members HR penetrate the stepped insulating layer 102 and the conductive layer 103. The support members HR have a cylindrical shape extending in the Z direction. The support members HR function as members to prevent the collapse of the laminate 900 during the formation process of the conductive layer 103, which will be described later. The material of the support members HR is an insulator such as silicon oxide. Details of the structure of the support members HR will be described later.

[0077] An insulating layer 150b is provided within the insulating layer 160 on the side surface of portion 90 of contact CC1. An insulating layer 150a is provided between insulating layer 150b and insulating layer 109. For example, an insulator 151 is provided between contact CC1 and the side surface of conductive layer 103. For example, an insulating film 155 is provided between portion 91 of contact CC1 and semiconductor layers 101a and 101c.

[0078] The insulating layer 169 is provided on the surface of the insulating layer 165 facing the Z1 direction. Multiple electrodes 111 are provided in the same layer as the insulating layer 169. The electrodes 111 are arranged within the insulating layer 169. The electrodes 111 have a rectangular shape when viewed from the Z direction. In the memory cell array area MA, the electrodes 111 are provided on the surface of the conductor 164 facing the Z1 direction. The electrodes 111 are electrically connected to one of the multiple wirings 163 corresponding to one wiring 163. The electrodes 111 are in contact with the corresponding electrodes 211 of the CMOS circuit chip 20. The electrodes 111 and 211 function as a bonding pad BP. The electrodes 111 contain copper. The number of layers of conductors 161, 164 and wiring 163 provided between the electrodes 111 and contact CC1 is arbitrary.

[0079] The bonded pad BP includes an active pad connected to the circuit and a dummy pad that is not connected to the circuit.

[0080] In Figure 4, although not shown, an electrode 111 is provided within the memory cell array area MA to electrically connect the wiring (bit line) 106 and the CMOS circuit chip 20.

[0081] Insulating layers 125 and 126 are laminated on the Z2-oriented surface of the semiconductor layer 101c and on the metal layer 120. The insulating layer 126 extends in the X and Y directions on the Z2-oriented surface of the insulating layer 125. The insulating layer 125 is silicon oxide made from SiH4. The insulating layer 126 is silicon oxide.

[0082] The wiring 127 is provided on the surface of the insulating layer 126 facing the Z2 direction. For example, within the memory cell array area MA, the wiring 127 is electrically connected to the metal layer (source wire) 120 via contacts (conductors) CX provided in the insulating layers 125 and 126. The contacts CX are members continuous with the wiring 127. The contacts CX are formed by embedding members of the wiring 127 into openings formed in the insulating layers 125 and 126.

[0083] Insulating layers 128 and 129 are laminated on the surface of the wiring 127 facing the Z2 direction. Insulating layer 128 is provided between insulating layer 129 and the wiring 127. The material of insulating layer 128 is silicon oxide made from TEOS. The material of insulating layer 129 is silicon nitride.

[0084] For example, in a certain region of the memory cell array area MA (e.g., the extraction area), the contact area CA, and the plane isolation area BA, a semiconductor layer 101c and an insulating layer 121 are provided between the semiconductor layer 101a and the insulating layer 125. The insulating layer 121 is provided between the semiconductor layer 101a and the semiconductor layer 101c. The material of the semiconductor layer 101c is, for example, silicon. The material of the insulating layer 121 is, for example, silicon oxide.

[0085] In the following, the laminate including the semiconductor layer 101a, the insulating layer 121, and the semiconductor layer 101c is referred to as the dummy layer DM. Furthermore, a configuration further including the insulating layer 125 on the semiconductor layer 101c may also be referred to as the dummy layer DM.

[0086] In this embodiment, the separation member BB1 is provided within the dummy layer DM of the draw-out area. The separation member BB1 separates the dummy layer DM into multiple parts. The separation member BB1 electrically separates multiple contacts CC1 aligned in the X direction and multiple contacts CC1 aligned in the Y direction. The separation member BB1 is positioned between two adjacent contacts CC1. The separation member BB1 electrically separates two contacts CC1 within the dummy layer DM. The separation member BB1 has a forward tapered cross-sectional shape. A forward tapered shape is a tapered shape in which the dimension along the direction parallel to the chip surface of the member (X direction or Y direction) decreases from the Z2 direction side to the Z1 direction side. Details of the structure of the separation member BB1 will be described later.

[0087] For example, a separation member BB1 is further provided at the boundary between the drawer area and the area containing multiple memory pillars MP (the end of the drawer area).

[0088] This section describes the contact area CA of the array chip 10.

[0089] The contact area CA includes semiconductor layers 101a, 101c and an insulating layer 121. The insulating layer 121 is provided between the two semiconductor layers 101a and 101c. Semiconductor layer 101a is provided on the plane of the insulating layer 160 facing the Z2 direction. The insulating layer 121 is provided on semiconductor layer 101a. Semiconductor layer 101c is provided on insulating layer 121. For example, the semiconductor layers 101a and 101c of the contact area CA are separated from the semiconductor layers 101a and 101c in the memory cell array area MA by a plane isolation area DA.

[0090] Multiple contacts (contact plugs) CC2 are provided within the contact area CA. The contacts CC2 are positioned to correspond to openings provided within the dummy layer DM and the insulating layers 125 and 126. The contacts CC2 have a cylindrical shape, extending primarily in the Z direction within the insulating layer 160. The Z2-direction end of the contacts CC2 protrudes from the insulating layer 160. The Z2-direction end of the contacts CC2 is located within the layer of the dummy layer DM. The contacts CC2 are used for electrical connections between the wiring 127 and components within the CMOS circuit chip 20 (e.g., transistors TR). The contacts CC2 include, for example, tungsten.

[0091] The wiring 127 is electrically connected to contact CC2 via contact (conductor) CZ. Contact CZ is provided within openings in the insulating layers 125, 126 and dummy layer DM. Contact CZ is a continuous component with respect to the wiring 127. The sides of contact CZ are covered by insulating layer 126. Insulating layer 126 is provided between the sides of contact CZ and dummy layer DM, and between the sides of contact CZ and insulating layer 125. Contact CZ is electrically isolated from dummy layer DM by insulating layer 126.

[0092] In the contact area CA, insulating layers 128 and 129 are laminated on the wiring 127 and insulating layer 126.

[0093] Within the contact area CA, multiple electrodes (pads) 111 are provided within the insulating layer 169. Within the contact area CA, each electrode 111 has a rectangular shape when viewed from the Z direction.

[0094] Electrode 111 is electrically connected to contact CC2 via a plurality of conductors 161, 164 and wiring 163. Conductors 161 are provided on the surfaces of the plurality of contacts CC2 facing in the Z1 direction. Wiring 163 is provided on the surfaces of conductors 161 facing in the Z1 direction. Conductor 164 is provided on the surfaces of wiring 163 facing in the Z1 direction.

[0095] Note that the configuration of the multiple conductors 161, 164 and the multiple wires 163 for connecting contact CC2 and electrode 111 is not limited to the example in Figure 5. The number of each conductor 161, 164 between contact CC2 and electrode 111, and the number of wires 163 between contact CC2 and electrode 111 can be changed as appropriate.

[0096] Electrode 111 electrically connects the array chip 10 and the CMOS circuit chip 20. Electrode 111 contacts the corresponding electrode 211 on the CMOS circuit chip 20. This forms a bonding pad BP within the contact area CA.

[0097] This section describes the plane isolation area DA of the array chip 10.

[0098] A layer (dummy layer DM) containing semiconductor layers 101a, 101c and an insulating layer 121 is provided on the surface of the insulating layer 160 in the plane isolation area DA that faces the Z2 direction.

[0099] The semiconductor layers 101a, 101c and insulating layer 121a within the plane isolation area DA are not used as paths to electrically connect the memory cell array 11 to other components. However, the semiconductor layers 101a, 101c of the plane isolation area DA may include portions that are continuous with the semiconductor layers 101a, 101c of the memory cell array area MA.

[0100] The insulating layers 125 and 126 are laminated on the plane of the semiconductor layer 101c facing the Z2 direction. The wiring 127 may be provided on the insulating layer 126 within the plane isolation area DA.

[0101] In the plane separation area DA, insulating layers 128 and 129 are laminated above insulating layer 126 via wiring 127.

[0102] Within the plane separation area DA, a separation member (insulator) BB2 is provided. For example, the separation member BB2 is provided within a slit (opening) formed within the plane separation area DA. The slit is provided within the semiconductor layer 101a, the insulating layer 121, the semiconductor layer 101c, and the insulating layer 125. The insulator, acting as the separation member BB2, is filled into the slit. The separation member BB2 is adjacent to the semiconductor layers 101a, 101c, and the insulating layer 121 in the X direction (or Y direction).

[0103] In addition, in a certain region between two memory cell array areas MA, the isolation member BB2 may be provided between the semiconductor layers 101a and 101c belonging to each memory cell array area MA. The insulator acting as the isolation member BB2 separates the semiconductor layer 101a (and semiconductor layer 101c) in one memory cell array 11 from the semiconductor layer 101a (and semiconductor layer 101c) in the other memory cell array 11 between two adjacent memory cell arrays 11. Between the memory cell array area MA and the contact area CA, the isolation member BB2 is provided between the semiconductor layer 101a (and semiconductor layer 101c) and the dummy layer DM. The insulator acting as the isolation member BB2 separates the semiconductor layer 101a (and semiconductor layer 101c) from the dummy layer DM.

[0104] The separating member BB2 has a tapered cross-sectional shape. The tapered shape of the separating member BB2 is a forward taper shape. The details of the structure of the separating member BB2 will be described later.

[0105] The insulator used in the separation member BB2 is a member continuous with the insulating layer 126. The insulator as the separation member BB2 is a portion (projection) that protrudes from the insulating layer 126 in the Z1 direction. The Z1 direction end of the insulator as the separation member BB2 is in contact with the insulating layer 160. The material of the separation member BB2 is the same as the material of the insulating layer 126 (for example, silicon oxide).

[0106] Furthermore, the separation member BB2 may be a member that is not continuous with the insulating layer 126. The separation member BB2 may contain an insulating material different from the material of the insulating layer 126. Voids may also be provided inside the separation member BB2.

[0107] In this way, the separation member BB2 separates the semiconductor layer 101a (and semiconductor layer 101c) included in the source line SL of the memory cell array area MA into multiple parts (multiple memory cell arrays 11) for each plane PLN. The semiconductor layer 101a (and semiconductor layer 101c) included in the source line SL is independent of each part of the memory cell array 11. As a result, multiple memory cell arrays 11 corresponding to each of the multiple planes PLN are provided within the array chip 10.

[0108] (a-6) Structure of a CMOS circuit chip The cross-sectional structure of the CMOS circuit chip 20 in the memory device 1 of this embodiment will now be described.

[0109] As shown in Figure 4, the CMOS circuit chip 20 includes a semiconductor substrate 200. In the CMOS circuit chip 20, a plurality of transistors TR are provided on the surface of the semiconductor substrate 200 facing the Z2 direction. The transistors TR are used as components of the low decoder 21, sense amplifier 22, voltage generation circuit 23, and sequencer 24. The transistors TR include a gate insulating layer 202, a gate electrode 203, and a source / drain layer (not shown). The gate insulating layer 202 is provided on the surface of the semiconductor substrate 200 facing the Z2 direction. The gate electrode 203 is provided on the gate insulating layer 202. The source / drain layer is provided within the semiconductor substrate 200.

[0110] An insulating layer 260 is provided on the surface of the semiconductor substrate 200 facing the Z2 direction. The insulating layer 260 covers the transistor TR, conductors 204, 208, 210, and wiring 205, 209. For example, the insulating layer 260 has a multilayer structure (multilayer wiring structure) including multiple insulating films. The number of wiring layers provided within the CMOS circuit chip 20 is arbitrary.

[0111] The insulating layer 269 is provided on the surface of the insulating layer 260 facing the Z2 direction. The surface of the insulating layer 269 facing the Z2 direction is in contact with, for example, the surface of the insulating layer 169 facing the Z1 direction. The surfaces of the insulating layer 269 and insulating layer 169 that are in contact with each other correspond to the bonding surface BF of the two semiconductor chips 10 and 20.

[0112] Multiple electrodes (pads) 211 are provided within the insulating layer 269. The electrodes 211 are connected to the electrodes 111 and the conductor 210. For example, the electrodes 211 have a rectangular shape when viewed from the Z direction.

[0113] As a result, the transistor TR on the semiconductor substrate 200 is electrically connected to the memory cell array 11 of the array chip 10, or to contacts CC1 and CC2 of the array chip 10.

[0114] The gate electrode 203, conductors 204, 208, 210, wiring 205, 209, and electrode 211 include, for example, conductive materials such as metals or semiconductors. Electrode 211 includes, for example, copper. The gate insulating layer 202 and insulating layers 260, 269 include, for example, insulating materials such as silicon oxide.

[0115] (a-7) Structure of a memory cell array Referring to Figure 6, the details of the cross-sectional structure of the memory cell array 11 will be described. Figure 6 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 11. In Figure 6, two memory pillars MP included in the memory cell array 11 are shown.

[0116] As shown in Figure 6, the semiconductor layer 101a functions as part of the source line SL. The semiconductor layer 101a contains, for example, silicon. The semiconductor layer 101a contains, for example, phosphorus (P) as a semiconductor impurity.

[0117] Multiple (e.g., 10) insulating layers 102 and multiple (e.g., 10) conductive layers 103 are alternately stacked one layer at a time on the surface of the semiconductor layer 101a facing the Z1 direction.

[0118] In the example shown in Figure 6, each of the 10 conductive layers 103 functions, in order from the side closest to the semiconductor layer 101a, as a select gate line SGS, word lines WL0, WL1, ..., WL6, WL7, and select gate line SGD. Note that each of the select gate lines SGS and SGD may be composed of multiple conductive layers 103.

[0119] For example, a titanium nitride (TiN) / tungsten (W) laminated structure can be used as the conductive material for the conductive layer 103. In this case, the titanium nitride is formed to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten and / or as an adhesion layer to improve the adhesion of tungsten, for example, when tungsten is formed by chemical vapor deposition (CVD).

[0120] For example, an insulating layer 109 made of a high dielectric constant material such as aluminum oxide (AlO) is formed to cover the conductive layer 103 between two stacked insulating layers 102. The insulating layer 109 is provided between the conductive layer 103 and the insulating layer 102, and between the conductive layer 103 and the memory pillar MP.

[0121] Multiple memory pillars MP are provided within the memory cell array 11. Memory pillars MP extending in the Z direction penetrate 10 conductive layers 103. One end of a memory pillar MP in the Z direction (the end in the Z2 direction) penetrates a semiconductor layer 101a. The memory pillar MP may have a structure in which multiple pillars are connected in the Z direction.

[0122] The internal structure of the memory pillar MP is described below. The memory pillar MP includes a memory layer 142, a semiconductor layer 143, a core layer 144, and a capping layer 145.

[0123] The memory layer 142 includes a block insulating layer 40, a charge storage layer 41, and a tunnel insulating layer 42. The sides of the core layer 144 are covered in order from the outside of the memory pillar MP by the block insulating layer 40, the charge storage layer 41, the tunnel insulating layer 42, and the semiconductor layer 143.

[0124] The semiconductor layer 143 is provided so as to be in contact with the side surface of the tunnel insulating layer 42. The semiconductor layer 143 is the region where the current paths (channels) of the memory cell MC and select transistors ST1 and ST2 are formed. The semiconductor layer 143 covers the side and bottom surfaces of the core layer 144. At one end of the memory pillar MP in the Z direction (the end in the Z2 direction), the block insulating layer 40, the charge storage layer 41, and the tunnel insulating layer 42 are removed. As a result, the semiconductor layer 143 is partially exposed. The impurity concentration of the exposed portion 143a of the semiconductor layer 143 (hereinafter referred to as the exposed portion) is higher than the impurity concentration of the portion of the semiconductor layer 143 covered by the memory layer 142 (hereinafter referred to as the covered portion). For example, the crystallinity of the exposed portion 143a of the semiconductor layer 143 is higher than the crystallinity of the covered portion of the semiconductor layer 143. The semiconductor layer 143 contains silicon.

[0125] A metal layer (source wire) 120 is provided on the Z2-direction end (exposed portion) 143a of the semiconductor layer 143 and on the semiconductor layer 101a. The metal layer 120 is in direct contact with the semiconductor layers 101a and 143 (143a).

[0126] The cap layer 145 is provided at the other end of the memory pillar MP in the Z direction (the end in the Z1 direction) so as to cover the Z1-side ends of the semiconductor layer 143 and the core layer 144. For example, the side surface of the cap layer 145 is in contact with the tunnel insulating layer 42. The cap layer 145 contains, for example, silicon.

[0127] The conductor 104 is provided on the surface of the cap layer 145 facing the Z1 direction. Wiring (bit lines) 106 is provided on the surface of the conductor 104 facing the Z1 direction.

[0128] Refer to Figure 7 to see an example of the cross-sectional structure of the memory pillar MP along the XY plane (planar structure viewed from the Z direction). More specifically, Figure 7 shows the cross-sectional structure of the memory pillar MP in a layer including the conductive layer 103.

[0129] In a cross-section including the conductive layer 103, the core layer 144 is provided, for example, in the central part of the memory pillar MP. The semiconductor layer 143 covers the sides of the core layer 144. The tunnel insulating layer 42 covers the sides of the semiconductor layer 143. The charge storage layer 41 covers the sides of the tunnel insulating layer 42. The block insulating layer 40 covers the sides of the charge storage layer 41. The conductive layer 103 covers the sides of the block insulating layer 40. Each of the core layer 144, the tunnel insulating layer 42, and the block insulating layer 40 contains, for example, silicon oxide. The charge storage layer 41 has the function (property) of storing charge. The charge storage layer 41 contains, for example, silicon nitride.

[0130] For example, an insulating layer 109 containing a metal oxide such as aluminum oxide (AlO) is provided between the conductive layer 103 and the block insulating layer 40.

[0131] A memory cell MC is formed by combining a memory pillar MP with a conductive layer 103 acting as a word line WL. A select transistor ST1 is formed by combining a memory pillar MP with a conductive layer 103 acting as a select gate line SGD. A select transistor ST2 is formed by combining a memory pillar MP with a conductive layer 103 acting as a select gate line SGS. Thus, each memory pillar MP can function as a single NAND string NS.

[0132] (a-8) Cross-sectional structure of the adhesive pad The cross-sectional structure of the bonded pad BP will be explained with reference to Figure 8. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the bonded pad BP. Note that in Figure 8, for the sake of simplicity, the structure of a bonded pad BP that is not connected to a circuit (dummy pad) is shown as an example.

[0133] As shown in Figure 8, electrode 111 includes a copper layer 70 and a barrier metal layer 71. Electrode 211 includes a copper layer 72 and a barrier metal layer 73.

[0134] In the bonding process between the array chip 10 and the CMOS circuit chip 20, electrode 111 is connected to electrode 211. In the example in Figure 8, the area of ​​electrode 111 and the area of ​​electrode 211 on the bonding surface BF are approximately equal. In such a case, if copper is used for electrodes 111 and 211, the copper layer 70 of electrode 111 and the copper layer 72 of electrode 211 become integrated. As a result, it may become difficult to confirm the boundary between the copper of the two electrodes 111 and 211. However, the bonding of the two semiconductor chips 10 and 20 can be confirmed by the distortion of the shape of the bonded electrodes 111 and 211 due to misalignment during bonding, and / or by the misalignment of the barrier metal layers 71 and 73 (occurrence of discontinuities on the sides).

[0135] When electrodes 111 and 211 are formed by the damascene method, the sides of electrodes 111 and 211 have a tapered shape. Therefore, the cross-sectional shape of the bonding pad BP along the Z direction in the portion where electrodes 111 and 211 are bonded together is not a straight line, but a non-rectangular shape.

[0136] When electrodes 111 and 211 are bonded together, the barrier metal layers 71 and 73 cover the bottom surface, sides, and top surface of the copper layers 70 and 72 that form the bonded pad BP. In contrast, in general wiring using copper, an insulating layer (such as SiN or SiCN) is provided on the top surface of the copper to prevent oxidation, and the barrier metal is not provided on the top surface of the copper. Therefore, even if there is no misalignment during bonding, it is possible to distinguish between the bonded pad BP and a general wiring layer.

[0137] (a-9) Structure of the plane separation area Figure 9 is a cross-sectional view showing the structure of the separation member BB2 within the plane separation area DA.

[0138] As shown in Figure 9, the separation member BB2 is provided within an opening OX formed in the laminate, which includes the insulating layer 125 and the dummy layer DM, within the plane separation area DA. The separation member BB2 divides the semiconductor layers 101a, 101c and the insulating layer 121 of the dummy layer DM into multiple portions 101a-3, 101a-4, 101c-3, 101c-4, 121-3, and 121-4.

[0139] The separating member BB2 has a tapered cross-sectional shape. The tapered shape of the separating member BB2 is a forward taper shape. The separating member BB2 includes a plurality of parts b21, b22, b23, b24, and b25 aligned in the Z direction.

[0140] Part b21 is located along the Z1-direction side (bottom surface) of the semiconductor layer 101a. Part b22 is located along the Z2-direction side (top surface) of the semiconductor layer 101a. Part b23 is located along the Z1-direction side (bottom surface) of the semiconductor layer 101c. Part b24 is located along the Z2-direction side (top surface) of the semiconductor layer 101c (the position of the Z1-direction side of the insulating layer 125). Part b25 is located on the Z2-direction side (top surface) of the insulating layer 125.

[0141] With respect to the linewidth dimensions of portions b21 and b22 of the separating member BB2 within the semiconductor layer 101a, the dimension D2b of portion b22 along the X direction (or Y direction) is greater than the dimension D2a of portion b21 along the X direction (or Y direction).

[0142] Regarding the dimensions in the line width direction of portions b23 and b24 of the separating member BB2 within the semiconductor layer 101c, the dimension D2d of portion b24 along the X direction (or Y direction) is greater than the dimension D2c of portion b23 along the X direction (or Y direction).

[0143] With respect to the dimensions in the line width direction of portions b24 and b25 of the separating member BB2 within the insulating layer 125, the dimension D2e of portion b25 along the X direction (or Y direction) is greater than the dimension D2d of portion b24 along the X direction (or Y direction).

[0144] Thus, the dimension (line width) of the separating member BB2 along the X direction (or Y direction) increases as you move from the Z1 direction to the Z2 direction.

[0145] Therefore, with respect to the separation member BB2 embedded in the laminate including the dummy layer DM and the insulating layer 125, the dimension D2e of the separation member BB2 in the direction along the surface of the chip 10 on the Z2 direction side is greater than the dimension D2a of the separation member BB2 in the direction along the surface of the chip 10 on the Z1 direction side.

[0146] (a-10) Structure within the drawer area Referring to Figures 10, 11A, and 11B, the structure of the components within the extraction area of ​​the memory cell array area MA in the memory device 1 of this embodiment will be described.

[0147] Figure 10 is a plan view showing the structure of contact CC1 and isolation member BB1 in the withdrawal area of ​​the memory cell array 11 in the memory device 1 of this embodiment. Figures 11A and 11B are cross-sectional views showing the structure of contact CC1 and isolation member BB1 in the withdrawal area of ​​the memory cell array 11 in the memory device 1 of this embodiment. Figure 11A shows the structure of contact CC1 and its neighboring members in the withdrawal area along the X direction. Figure 11B shows the structure of contact CC1 and its neighboring members in the withdrawal area along the Y direction.

[0148] As shown in Figures 10, 11A, and 11B, in the lead-out area, contact CC1 penetrates one or more conductive layers 103 within the stepped structure. Contact CC1 penetrates the conductive layer 103 to be connected. Contact CC1 penetrates other conductive layers 103 and insulating layer 102 between the conductive layer 103 to be connected and the semiconductor layer 101a. For example, multiple contacts CC1 are aligned along the X direction (and Y direction).

[0149] The contact CC1 includes a portion (hereinafter also referred to as the overhang) 90 that protrudes in directions parallel to the surface of the chip (X and Y directions). The contact CC1 contacts the terrace of the corresponding conductive layer 103 by the overhang 90. At the contact portion between the conductive layer 103 and the overhang 90, the insulating layer 109 is removed from the conductive layer 103. As a result, the Z2-direction surface of the overhang 90 directly contacts the Z1-direction surface of the conductive layer 103.

[0150] The side surface of the protruding portion 90 is covered with an insulating layer 150b. An insulating layer 150a is provided between the insulating layer 150b and the conductive layer 103 (insulating layer 109) in the Z direction. The insulating layer 109 is sandwiched between the insulating layer 150a and the conductive layer 103. The insulating layers 150a and 150b extend in the Y direction. The insulating layers 150a and 150b are components used when forming the protruding portion 90 or products resulting from such components. The material of the insulating layers 150a and 150b is silicon oxide.

[0151] Contact CC1 is electrically isolated from other conductive layers 103 other than the corresponding conductive layer (the conductive layer to be connected) 103 by an insulator 151. The insulator 151 is provided between the side surface of contact CC1 and the side surfaces of one or more conductive layers 103 through which contact CC1 penetrates. The material of the insulator 151 is silicon oxide.

[0152] Contact CC1 includes a portion (hereinafter also referred to as the protrusion) 91 that protrudes into the dummy layer DM. For example, the protrusion 91 of contact CC1 penetrates the semiconductor layer 101a. The Z2-direction end (upper end) of contact CC1 is located within the semiconductor layer 101c. Depending on the manufacturing process, the diameter and cross-sectional area parallel to the chip surface may decrease from the Z1-direction to the Z2-direction of the upper end of contact CC1. Therefore, contact CC1 tends to have an inverse tapered shape.

[0153] In the extraction area, the dummy layer DM is provided so as to overlap the stepped structure (laminated body 900) in the Z direction. As described above, the dummy layer DM includes a semiconductor layer (e.g., silicon layer) 101a, an insulating layer (e.g., silicon oxide layer) 121, and a semiconductor layer (e.g., silicon layer) 101c. The protrusion 91 penetrates the semiconductor layer 101a and the insulating layer 121 of the dummy layer DM. The Z2 end of the protrusion 91 reaches the semiconductor layer 101c of the dummy layer DM.

[0154] An insulating film 155 is provided between the dummy layer DM and the protrusion 91 of the contact CC1. Within the dummy layer DM, the insulating film 155 covers the protrusion 91. The insulating film 155 electrically isolates the dummy layer DM from the contact CC1. The material of the insulating film 155 is silicon oxide.

[0155] As described above, multiple support members (e.g., silicon oxide columns) HR are provided within the extraction area. For example, each contact CC1 is provided within the region between two support members HR aligned in the X direction (or Y direction). Multiple contacts CC1 and multiple support members HR are arranged alternately in the X direction (or Y direction).

[0156] The support member HR penetrates one or more insulating layers 102 and one or more conductive layers 103 within the staircase structure. The Z2 end of the support member HR reaches the layer where the dummy layer DM is provided. The Z2 end of the support member HR is located in the layer where the semiconductor layer 101c is provided in the Z direction. The support member HR adjacent to contact CC1 in the X direction penetrates the insulating layer 150a. The support member HR adjacent to contact CC1 in the Y direction penetrates the insulating layers 150a and 150b.

[0157] The memory device 1 of this embodiment includes a separation member BB1 within the draw-out area. The separation member BB1 protrudes in the Z direction from the insulating layer 126 toward the stepped structure of the laminate 900. The separation member BB1 is continuous with the insulating layer 126. The separation member BB1 is an insulator. The material of the separation member BB1 is silicon oxide, the same as the material of the insulating layer 126.

[0158] Furthermore, the separation member BB1 may be a member that is not continuous with the insulating layer 126. The separation member BB1 may contain an insulating material different from the material of the insulating layer 126. Voids may also be provided inside the separation member BB1.

[0159] For example, the separating member BB1 has a grid-like layout when viewed from the Z direction. The separating member BB1 includes a portion b1 extending in the X direction and a portion b2 extending in the Y direction. In the Z direction, the separating member BB1 is positioned within the pull-out area so as to overlap with the support member HR. The portion of the dummy layer DM surrounded by the grid-like separating member BB1 has a rectangular planar shape when viewed from the Z direction.

[0160] The separation member BB1 penetrates the insulating layer 125 and the dummy layer DM. The separation member BB1 is provided within a slit (opening) OP formed within the dummy layer DM and the insulating layer 125. The separation member BB1 is provided between adjacent dummy layers DM in the X and Y directions. The separation member BB1 is positioned within the region between two contacts CC1 aligned in the X (or Y) direction. The separation member BB1 is in contact with the support member HR. For example, the separation member BB1 covers the side surface of the support member HR within the layers of the dummy layer DM.

[0161] The separation member BB1 has a tapered cross-sectional shape. The tapered shape of the separation member BB1 is a forward taper shape, similar to the shape of the separation member BB2. The separation member BB1 is provided within an opening OP formed in a laminate including the insulating layer 125 and the dummy layer DM. The separation member BB1 includes a plurality of parts b11, b12, b13, b14, and b15 aligned in the Z direction.

[0162] Part b11 is located along the Z1-direction side (bottom surface) of the semiconductor layer 101a. Part b12 is located along the Z2-direction side (top surface) of the semiconductor layer 101a. Part b13 is located along the Z1-direction side (bottom surface) of the semiconductor layer 101c. Part b14 is located along the Z2-direction side (top surface) of the semiconductor layer 101c (the position of the Z1-direction side of the insulating layer 125). Part b15 is located on the Z2-direction side (top surface) of the insulating layer 125.

[0163] Regarding the dimensions in the line width direction of portions b11 and b12 of the separating member BB1 within the semiconductor layer 101a, the dimension D1b of portion b12 along the X direction (or Y direction) is larger than the dimension D1a of portion b11 along the X direction (or Y direction).

[0164] Regarding the dimensions in the line width direction of portions b13 and b14 of the separating member BB1 within the semiconductor layer 101c, the dimension D1d of portion b14 along the X direction (or Y direction) is greater than the dimension D1c of portion b13 along the X direction (or Y direction).

[0165] With respect to the dimensions in the line width direction of portions b14 and b15 of the separating member BB1 within the insulating layer 125, the dimension D1e of portion b15 along the X direction (or Y direction) is greater than the dimension D1d of portion b14 along the X direction (or Y direction).

[0166] Thus, the dimension (line width) of the separating member BB1 along the X direction (or Y direction) increases as you move from the Z1 direction towards the Z2 direction.

[0167] Therefore, with respect to the separation member BB1 embedded in the laminate including the dummy layer DM and the insulating layer 125, the dimension D1e along the X direction (or Y direction) on the Z2 direction side of the separation member BB1 is greater than the dimension D1a along the X direction (or Y direction) on the Z1 direction side of the separation member BB1.

[0168] Depending on the forward taper shape of the separation member BB1, the semiconductor layers 101a, 101c and insulating layers 121, 125 within the region enclosed by the separation member BB1 have an inverse taper cross-sectional shape. The dimension of the semiconductor layer 101a along the X direction (or Y direction) is greater than the dimension of the insulating layer 125 along the X direction (or Y direction). For example, the dimension of the separation member BB1 in the Z direction is equal to the sum of the dimension of the dummy layer DM in the Z direction and the dimension of the insulating layer 125 in the Z direction.

[0169] For example, dimension D1e of separation member BB1 is greater than dimension D2e of separation member BB2. For example, dimension D1a of separation member BB1 is greater than dimension D2a of separation member BB2.

[0170] Furthermore, in each portion (position) b11, b12, b13, b14, b15 of the separating member BB1 in the Z direction, the dimension of a certain portion of the separating member BB1 along the X direction may be substantially the same as, or different from, the dimension of that portion of the separating member BB1 along the Y direction.

[0171] In this embodiment, the isolation member BB1 divides the semiconductor layers 101a, 101c and the insulating layer 121 of the dummy layer DM into a plurality of parts 101a-1, 101a-2, ..., 101c-1, 101c-2, ..., 121-1, 121-2, ... for each contact CC1 reaching the dummy layer DM. As a result, the plurality of parts of the semiconductor layers 101a, 101c are electrically isolated from each other. The semiconductor layers 101a, 101c surrounded by the isolation member BB1 are not electrically connected to other members (e.g., wiring or pads) on the Z2 side.

[0172] In the memory device 1 of this embodiment, the separation member BB1 electrically isolates the multiple contacts CC1 from each other without being connected via a dummy layer DM.

[0173] (b) Manufacturing method The manufacturing method of the memory device 1 of the first embodiment will be described with reference to Figures 12 to 31. Figures 12 to 23 are cross-sectional process diagrams showing the manufacturing process of the array chip 10 in the memory device 1 of this embodiment.

[0174] As shown in Figure 12, on the first surface of the array chip 10 facing the Z1 direction, a semiconductor layer 101c, such as a silicon layer, is formed on a semiconductor substrate (e.g., a silicon substrate) 100, for example, by CVD. An insulating layer 121, such as a silicon oxide layer, is formed on the semiconductor layer 101c. A semiconductor layer 101a, such as a silicon layer, is formed on the insulating layer 121.

[0175] A laminate 900, including multiple insulating layers 102, 102A and multiple sacrificial layers 999, is formed on a semiconductor layer 101a by CVD. In the laminate 900, the insulating layers 102 and the sacrificial layers 999 are deposited alternately in the Z1 direction. The sacrificial layers 999 are layers that will be replaced by conductive layers (word lines) in a later process. The insulating layers 102, 102A are, for example, silicon oxide layers. The sacrificial layers 999 are, for example, silicon nitride layers.

[0176] In the laminate 900, the thickness of the uppermost insulating layer 102A in the Z direction is thicker than the thickness of the other insulating layers 102 in the Z direction.

[0177] An insulating layer 999A is formed on the insulating layer 102A. The material of the insulating layer 999A is the same as the material of the sacrificial layer 999 (e.g., silicon nitride).

[0178] In the extraction area of ​​the array chip 100, the edges of the laminate 900 in the X direction are processed into a stepped shape by photolithography and etching.

[0179] As a result, a staircase structure is formed within the drawer area. In the staircase structure, each sacrificial layer 999 has its surface (the side facing the Z1 direction) exposed at the portion that becomes a terrace of the conductive layer 103.

[0180] In the contact area CA and the plane isolation area DA, the insulating layers 102, 102A, 999A and the sacrificial layer 999 are removed.

[0181] As shown in Figure 13, the insulating layer 150a is formed on the insulating layers 102, 102A, 999A and the sacrificial layer 999 by CVD so as to cover the stepped structure. The insulating layer 150a covers the side walls (steps) of the insulating layers 102, 102A and the sacrificial layer 999 in the drawout area. Hereinafter, the insulating layer 150a will also be called the side wall spacer film. The material of the side wall spacer film 150a is, for example, silicon oxide. For example, the film thickness of the side wall spacer film 150a in the Z direction is substantially equal to the film thickness of the insulating layer 102 in the Z direction.

[0182] Multiple insulating layers 150x are formed on the sidewall spacer film 150a by CVD and etching. Each of the multiple insulating layers 150x has an independent pattern for each step (terrace) of the stepped structure. For example, the insulating layer 150x is positioned in the region corresponding to the contact area between the terrace of the later-formed conductive layer 103 and the contact CC1. The insulating layer 150x extends in the Y direction. Hereinafter, the insulating layer 150x will be referred to as the spacer film. The material of the spacer film 150x is, for example, the same as the material of the sacrificial layer 999 (e.g., silicon nitride). For example, the film thickness T1 of the spacer film 150x in the Z direction is substantially equal to the sum of the film thickness T2 of one insulating layer 102 and the film thickness T3 of one sacrificial layer 999.

[0183] As shown in Figure 14, in the memory cell array area MA, an insulating layer 160, such as a silicon oxide layer, is formed on the sidewall spacer film 150a and the spacer film 150x by a CVD method using TEOS. The insulating layer 160 is planarized by a chemical mechanical polishing (CMP) method, using the uppermost insulating layer 102A of the laminate 900 as a stopper.

[0184] In the contact area CA and the plane separation area DA, the insulating layer 160 is formed on the semiconductor layer 101a.

[0185] As shown in Figure 15, within the extraction area of ​​the memory cell array area MA, multiple openings are formed within a predetermined area of ​​the insulating layer 160 by photolithography and etching. The lower end of the openings reaches the semiconductor layer 101c. After the formation of the openings, multiple support members HR are formed within the openings. The support members HR penetrate the side wall spacer film 150a and the stepped structure of the laminate 900. The support members HR are formed from an insulator such as silicon oxide.

[0186] Of the multiple support members HR, the support member HR located at the contact CC1 formation coordinate is selectively removed. As a result, an opening OP1 extending from the insulating layer 160 to the semiconductor layer 101c is formed at the contact CC1 formation coordinate in the drawout area. For example, a portion of the support member HR (not shown) may remain at the bottom of the opening OP1.

[0187] Within the contact area CA, an opening OP1 whose bottom reaches the semiconductor layer 101c is similarly formed within the insulating layer 160 in the formation coordinates of contact CC2.

[0188] As shown in Figure 16, etching is performed such that the spacer film 150x is selectively removed through the opening OP1.

[0189] As a result, the spacer film 150x recedes in a direction parallel to the surface of the semiconductor substrate 100. Consequently, a depression (groove) R1a is formed in the opening OP1 in a direction parallel to the surface of the semiconductor substrate 100, corresponding to the position of the terrace portion of the conductive layer 103. The depression R1a is formed corresponding to the position of the spacer film 150x between the insulating layer 160 and the insulating layer 150a.

[0190] A sacrificial layer 999 made of the same material as the spacer film 150x is etched (removed) at the same time as the spacer film 150x.

[0191] At the location of the sacrificial layer 999, recesses R1b are formed corresponding to the space between the sidewall spacer film 150a and the insulating layer 102, and between two adjacent insulating layers 102 in the Z direction.

[0192] Due to the thickness of the spacer film 150x, the dimension of recess R1a in the Z direction is larger than the dimension of recess R1b in the Z direction.

[0193] As shown in Figure 17, the insulator 151 is formed within the opening OP1, which includes the recesses R1a and R1b. The insulator 151 is selectively etched by isotropic etching, such as wet etching.

[0194] The insulator 151 is removed from within the recess R1a, which has a large space. Within the recess R1a, the spacer film 150x is exposed to the opening OP1.

[0195] On the other hand, the insulator 151 remains in recess R1b, which has a smaller space than recess R1a. The sacrificial layer 999 is sealed by the insulator 151 remaining in recess R1b and is not exposed to the opening OP1.

[0196] For example, at the bottom of the opening OP1, the insulator 151 is removed. The semiconductor layers 101a, 101c and the insulating layer 121 are exposed to the opening OP1.

[0197] As shown in Figure 18, the insulating film 155 is formed on the surfaces of the semiconductor layers 101a, 101c and the insulating layer 121 exposed through the opening OP1 by the Water vapor generation (WVG) method.

[0198] For example, in the contact area CA, the insulating film 155 is formed on the surface of the exposed semiconductor layers 101a, 101c and the insulating layer 121.

[0199] As shown in Figure 19, the spacer film 150x is selectively etched (removed). The spacer film 150x recedes further in a direction parallel to the surface of the semiconductor substrate 100. As a result, the dimension of the recess R2 of the spacer film 150x in the direction parallel to the surface of the semiconductor substrate 100 is expanded compared to the dimension of the insulator 151 in the direction parallel to the surface of the semiconductor substrate 100.

[0200] As shown in Figure 20, in the draw-out area and contact area CA, the sacrificial member 180 is filled into the opening OP1, which includes the recess R2. The sacrificial member 180 is selectively removed from the upper surface of the insulating layers 160, 102A by etching. The upper end of the sacrificial member 180 is aligned with the upper surface of the insulating layer 160. The material of the sacrificial member 180 is a semiconductor, such as amorphous silicon.

[0201] As shown in Figure 21, a replacement process is performed to form the word line WL. The sacrificial layer 999 is selectively removed through a slit (not shown) formed within the laminate 900. The spacer film 150x is divided into multiple parts in the Y direction by this slit. The spacer film 150x is in contact with the slit. The support member HR prevents the collapse of the laminate 900 in the state where the sacrificial layer 999 has been removed.

[0202] After the removal of the sacrificial layer 999, an insulating layer 109, such as an aluminum oxide film, is formed in the space left by the removal of the sacrificial layer 999 from the laminate 900, so as not to fill that space. A conductive layer 103 is formed on the insulating layer 109 in the space left by the removal of the sacrificial layer 999 from the laminate 900.

[0203] In this embodiment, in the extraction area, the spacer film 150x is removed simultaneously with the removal of the sacrificial layer 999. The space created by the removal of the spacer film 150x is connected to the slit. The insulating layer 109 and the conductive layer 103 are formed in the space created by the removal of the spacer film 150x. However, the space created at the location of the spacer film 150x is larger than the space between the insulating layers 102. Therefore, the space created at the location of the spacer film 150x is not blocked by the insulating layer 109 and the conductive layer 103.

[0204] After this, the insulating layer 109 and conductive layer 103 in the slit (not shown) for replacement processing are removed. At this time, the insulating layer 109 and conductive layer 103 in the space created at the position of the spacer film 150x in the draw-out area are removed simultaneously with the insulating layer 109 and conductive layer 103 in the slit.

[0205] An insulator such as silicon oxide is filled into the slit. Simultaneously, the insulating layer 150b is filled into the space created at the location of the spacer film 150x.

[0206] As shown in Figure 22, the sacrificial member 180 is removed in the lead-out area and contact area CA of the memory cell array area MA. An opening OP2 is created by the removal of the sacrificial member 180. At the bottom of the recess R2, a portion of the insulating layer 150a and insulating layer 109 is removed through the opening OP2. As a result, the terrace of the conductive layer 103 is exposed in the recess R2 in the lead-out area.

[0207] As shown in Figure 23, the conductor is filled into the opening OP2, which includes the recess R2. This forms the contact CC1 within the opening OP2 of the lead-out area.

[0208] Each of the formed contacts CC1 penetrates one or more insulating layers 102 and one or more conductive layers 103. The Z2-direction end (projection 91) of the contact CC1 reaches the insulating film 155 within the semiconductor layers 101a and 101c. The contact CC1 contacts the terraces of the corresponding conductive layers 103 via portions (overhangs 90) that protrude in the X (and Y) directions. This electrically connects the contact CC1 to the corresponding conductive layers 103.

[0209] An insulator 151 is provided between the side surface of contact CC1 and the side surface of conductive layer 103. This electrically isolates contact CC1 from other conductive layers 103 other than the corresponding conductive layer 103.

[0210] In the contact area CA, contact CC2 is formed within the insulating layer 160 substantially simultaneously with the formation of contact CC1. The edges of contact CC2 reach into the insulating film 155 within the semiconductor layers 101a and 101c.

[0211] Subsequently, various conductors 104, 161, 164, wiring 106, 163, electrodes 111, and insulating layers 162, 165, 169 connected to the memory pillar MP and contacts CC1, CC2 are sequentially formed using well-known techniques.

[0212] The array chip 10 is formed through the above process.

[0213] The CMOS circuit chip 20 is manufactured separately from the array chip 10.

[0214] Figures 24 to 31 are cross-sectional process diagrams showing the manufacturing process after bonding the array chip 10 and the CMOS circuit chip 20 in the memory device 1 of this embodiment.

[0215] As shown in Figure 24, the array chip 10 is bonded to the CMOS circuit chip 20 such that the surface of the array chip 10 facing the Z1 direction faces the surface of the CMOS circuit chip 20 facing the Z2 direction. After bonding the two chips, the semiconductor substrate 100 of the array chip 10 is removed by grinding, wet etching, and CMP methods. This exposes the semiconductor layer 101c in the Z2 direction.

[0216] As shown in Figure 25, a resist mask 182 is formed on the semiconductor layer 101c by photolithography and etching. An opening OP3 is formed within the resist mask 182. The opening OP3 is provided within the resist mask 182 so that the semiconductor layer 101c in the region where the memory pillar MP is formed in the memory cell array area MA is exposed.

[0217] In the draw-out area, contact area CA, and plane isolation area DA, the semiconductor layer 101c is covered by a resist mask 182.

[0218] As shown in Figure 26, based on the pattern of the resist mask 182, the semiconductor layer 101c is partially removed (etched) by reactive ion etching (RIE). This exposes the Z2-direction edge of the memory pillar MP. The etching creates a step between the semiconductor layer 101a and the semiconductor layer 101c within the memory cell array area MA.

[0219] The exposed multilayer film 142 of the memory pillar MP is removed by etching. This exposes the semiconductor layer 143 of the memory pillar MP.

[0220] Ion implantation of the semiconductor layer 143 adds impurities (dopants) to the exposed portion (exposed part) 143a of the semiconductor layer 143.

[0221] Next, laser annealing is performed on the exposed portion 143a to which impurities have been added. This causes the exposed portion 143a of the semiconductor layer 143 to crystallize.

[0222] As shown in Figure 27, after the resist mask 182 is removed, the metal layer 120 is formed on the semiconductor layers 101a and 101c by physical vapor deposition (PVD), photolithography, and etching. The metal layer 120 extends from the Z2-oriented surface of semiconductor layer 101a to the Z2-oriented surface of semiconductor layer 101c, via the side surface of semiconductor layer 101c.

[0223] The insulating layer 125 is formed on the array chip 10 by CVD so as to cover the semiconductor layer 101c and the metal layer 120.

[0224] As shown in Figure 28, in the plane separation area DA, slits (openings) OP4a for separating planes PLN are formed within the insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a. As a result, in the plane separation area DA, the semiconductor layers 101a and 101c are separated for each plane PLN. The slits OP4a have a grid-like structure when viewed from the Z direction. The slits OP4a have a forward-tapered cross-sectional shape.

[0225] Simultaneously with the formation of the opening OP4a in the plane separation area DA, the opening OP4b is formed in the contact area CA within the insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a such that the Z2-direction end (insulating film 155) of contact CC2 is exposed. For example, the opening OP4b has a square or circular structure when viewed from the Z direction. The opening OP4b has a forward-tapered cross-sectional shape.

[0226] Simultaneously with the separation of semiconductor layers 101a and 101c in the plane separation area DA, a slit OP4c is formed within the lead-out area of ​​the array chip 10 so as to penetrate the insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a in the Z direction. The slit OP4c is formed to have a grid-like layout when viewed from the Z direction. The slit OP4c has a forward-tapered cross-sectional shape.

[0227] The slit OP4c is provided within the region between two adjacent contacts CC1. For example, the slit OP4c is formed in a position that overlaps with the support member HR in the Z direction.

[0228] The insulating layer 102 on the source wire side of the laminate 900 (the uppermost insulating layer in the Z2 direction) is exposed through the slit OP4c. At the location of the slit OP4c, a step (groove) may be formed on the exposed portion of the insulating layer 102, depending on the etching process used to form the slit OP4c.

[0229] As shown in Figure 29, the insulating layer 126 is formed on the insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a by CVD. The inside of the slit OP4a in the plane isolation area DA, the inside of the opening OP4b in the contact area CA, and the inside of the slit OP4c in the extraction area (memory cell array area MA) are filled with the insulating layer 125.

[0230] In this way, the same process forms the separation member BB1 in the extraction area and the separation member BB2 in the plain separation area DA within the slits OP4a and OP4c formed in the insulating layers 121 and 125 and the semiconductor layers 101a and 101c. The separation members BB1 and BB2 are insulators continuous with the insulating layer 126.

[0231] Note that the separation members BB1 and BB2 may be formed in a different process than the formation of the insulating layer 126. For example, a member (insulator) for forming the separation members BB1 and BB2 is embedded in the slits OP4a and OP4c. After this, the insulating layer 126 is formed on the insulating layer 125 and the separation members BB1 and BB2.

[0232] During the formation of the separating members BB1 and BB2, voids may occur within the separating members BB1 and BB2.

[0233] The formed separation members BB1 and BB2 have a lattice-like structure when viewed from the Z direction. The formed separation members BB1 and BB2 have a forward-tapered cross-sectional structure according to the shape of the slits OP4a and OP4c. That is, in the separation members BB1 and BB2, the dimension along the X direction (or Y direction) of the portion on the Z2 direction side (array chip 10 side) is larger than the dimension along the X direction (or Y direction) of the portion on the Z1 direction side (CMOS circuit chip 20 side).

[0234] As shown in Figure 30, an opening is formed within the insulating layers 125 and 126 by photolithography and etching at a position overlapping the metal layer 120 of the memory cell array area MA in the Z direction.

[0235] After the opening is formed, metal wiring 127 is formed on the insulating layer 126. The wiring 127 is processed into a predetermined shape by photolithography and etching.

[0236] The components of the wiring 127 are embedded within the openings of the insulating layers 125 and 126. This forms the contact CX within the opening so that it connects to the metal layer 120.

[0237] In the contact area CA, an opening is formed in the insulating layer 126 in a region overlapping with contact CC2 in the Z direction, by a process simultaneous with the formation of the opening in the memory cell array area MA. During the formation of this opening, the insulating film 155 covering the Z2-direction end of contact CC2 is removed. Wiring 127 is formed on the insulating layer 126 so as to fill the opening. As a result, in the contact area CA, contact CZ is formed so as to connect wiring 127 to contact CC2. Contact CZ directly contacts contact CC2. Note that during the formation of opening OP4b (see Figure 28), the insulating film 155 covering the Z2-direction end of contact CC2 may be removed.

[0238] For example, in the plane separation area DA, the wiring 127 is formed on the insulating layer 126.

[0239] As shown in Figure 31, an oxide insulating layer 128 is formed on the wiring 127 and the insulating layer 126. A nitride insulating layer 129 is formed on the insulating layer 128.

[0240] Through the above steps, the memory device 1 of this embodiment is completed.

[0241] (c) Summary In memory devices, contacts that penetrate multiple conductive layers are used to connect the multiple conductive layers and wiring in the stepped structure. In this case, the contacts are electrically isolated from other components other than the corresponding conductive layers.

[0242] For example, if a contact reaches a semiconductor layer that overlaps with a step structure in the Z direction, the contact is electrically isolated from the semiconductor layer by an insulating film formed between the semiconductor layer and the contact.

[0243] If the insulating film formed between the contact and the semiconductor layer is thin, the contact may become electrically connected to the semiconductor layer. In this case, multiple contacts may be electrically connected through the semiconductor layer.

[0244] If a thick insulating film is formed between the contact and the semiconductor layer to ensure sufficient insulation between them, there is a risk of volume expansion of the component due to the formation of the insulating film within the stepped structure near the contact. The formation of this insulating film is performed before the sacrificial layer-conductive layer replacement process in the stepped structure (laminated body).

[0245] In this case, after the sacrificial layer is removed from the inside of the stepped structure during the replacement process, the expanded insulating film compresses the space where the sacrificial layer was removed. That is, the space where the sacrificial layer was removed becomes smaller. As a result, defects in the embedding of the conductive layer in the space where the sacrificial layer was removed may occur.

[0246] Therefore, it was difficult to increase the thickness of the insulating film between the contact and the semiconductor layer.

[0247] As shown in Figures 4, 10 to 11B, in the memory device 1 of this embodiment, an insulating isolation member BB1 is provided within the draw-out area where the stepped structure is located. The isolation member BB1 divides the semiconductor layers 101a and 101c that overlap with the stepped structure in the Z direction into a plurality of parts 101a-1, 101a-2, ..., 101c-1, 101c-2, ... The isolation member BB1 is provided between a plurality of contacts CC1 that each penetrate the stepped structure.

[0248] In this way, the separation member BB1 electrically isolates the multiple contacts CC1 from each other. As a result, in this embodiment, electrical conduction between the multiple contacts CC1 is prevented without increasing the thickness of the insulating film 155.

[0249] The contact CC1 formed to penetrate the stepped structure and the semiconductor layer 101a tends to decrease in diameter and cross-sectional area from the Z1 direction to the Z2 direction. Therefore, the separating member BB1, which has a tapered cross-sectional shape in which the dimension in the line width direction increases from the Z1 direction to the Z2 direction, can separate the semiconductor layer 101a with high positional accuracy while suppressing interference with the contact CC1 between multiple contacts CC1.

[0250] On the other hand, the upper end of contact CC1 may be located within the region between the Z2-direction side surface (upper surface) and the Z1-direction side surface (lower surface) of the upper semiconductor layer 101c of the two stacked semiconductor layers 101a and 101c. That is, contact CC1 is located on the lower surface of semiconductor layer 101c, but not on the upper surface of semiconductor layer 101c. Therefore, even when the upper end of contact CC1 is located within semiconductor layer 101c, the separation member BB1 having the forward taper shape described above can separate the semiconductor layer 101c with good positional accuracy between multiple contact CC1s while suppressing interference with contact CC1.

[0251] Furthermore, the isolation member BB1 for separating contacts CC1 is formed substantially simultaneously with the isolation member BB2 for separating planes PLN (source lines). Therefore, in the memory device 1 of this embodiment, even if the isolation member BB1 is formed within the memory cell array area MA, an increase in manufacturing steps and an excessive increase in cost are avoided.

[0252] As described above, the memory device 1 of this embodiment can suppress defects such as short circuits between components.

[0253] (2) Second embodiment Referring to FIGS. 32 and 33, the memory device of the second embodiment will be described.

[0254] FIG. 32 is a plan view showing a structural example of the memory device 1 of the present embodiment. FIG. 33 is a cross-sectional view showing a structural example of the memory device 1 of the present embodiment.

[0255] As shown in FIGS. 32 and 33, the support member HR may be formed in the region between the contact CC1 and the separation member BB1. The end portion of the support member HR in the Z2 direction is located in the semiconductor layer 101c of the dummy layer DM.

[0256] The separation member BB1 does not overlap the support member HR in the Z direction. The separation member BB1 surrounds the region of the dummy layer DM where the support member HR and the contact CC1 are provided.

[0257] For example, one of the two support members HR sandwiching one contact CC1 in the X direction penetrates the insulating layer 150b.

[0258] In the present embodiment, similar to the first embodiment, in the lead-out area of the memory cell array area MA, the semiconductor layers 101a and 101c are independent for each corresponding contact CC1. As a result, the plurality of contacts CC1 are separated from each other.

[0259] As described above, the memory device of the second embodiment can suppress defects of the memory device substantially in the same manner as the first embodiment.

[0260] (3) Third Embodiment Referring to FIG. 34, the memory device of the third embodiment will be described.

[0261] FIG. 34 is a cross-sectional view showing a structural example of the memory device 1 of the present embodiment.

[0262] As shown in Figure 34, in this embodiment, no insulating film covering the protrusion 91 of contact CC1 is provided within the dummy layer DM. The protrusion 91 is in direct contact with the semiconductor layers 101a and 101c.

[0263] As described above, within the draw-out area, the semiconductor layers 101a and 101c are electrically isolated for each corresponding contact CC1 by a grid-like separation member (insulator) BB1.

[0264] Therefore, even if contact CC1 is in direct contact with semiconductor layers 101a and 101c, current does not flow between the semiconductor layer 101a, which functions as part of the source line SL, and contact CC1, and between the two contact CC1, due to the interruption by the isolation member BB1.

[0265] Therefore, the insulating film 155 in the above embodiment may not necessarily be provided between the contact CC1 and the semiconductor layers 101a and 101c.

[0266] For example, in the manufacturing process of the memory device 1 of this embodiment, the process for forming an insulating film between the semiconductor layers 101a, 101c and the protruding portion 91 of the contact CC1 (WVG process) can be reduced. As a result, the manufacturing cost of the memory device 1 of this embodiment can be reduced.

[0267] As described above, the memory device of the third embodiment can suppress memory device failures, similar to the embodiments described above.

[0268] (4) Fourth Embodiment A fourth embodiment of the memory device and its manufacturing method will be described with reference to Figures 35 to 44.

[0269] (a) Structure example Figure 35 is a cross-sectional view showing the structure of the contact CC3 and isolation member BB1 in the draw-out area of ​​the memory cell array 11 in the memory device 1 of this embodiment.

[0270] As shown in Figure 35, in the memory device 1 of this embodiment, a plurality of contacts (contact plugs) CC3 are provided in the lead-out area within the memory cell array area MA. Similar to the embodiment described above, the contacts CC3 penetrate one or more insulating layers 102 and one or more conductive layers 103 within the stepped structure of the lead-out area.

[0271] In this embodiment, the structure of contact CC3 differs from the structure of contact CC1 of the memory device 1 in other embodiments. The protruding portion 90 on the side of contact CC3 contacts the side of the conductive layer 103 (word line WL and select gate lines SGD, SGS). The conductive layer 103 has a portion that protrudes in the Z1 direction at the contact portion with contact CC3.

[0272] This ensures an electrical connection between the contact CC3 and the conductive layer 103 in the memory device 1 of this embodiment.

[0273] The support member HR may be positioned within the region between the separating member BB1 and the contact CC3, similar to the structure shown in Figure 32.

[0274] (b) Manufacturing method The manufacturing method of the memory device 1 of this embodiment will be described with reference to Figures 36 to 44. Each of Figures 36 to 44 is a cross-sectional process diagram showing the manufacturing process of the memory device 1 of this embodiment.

[0275] As shown in Figure 36, the semiconductor layers 101a, 101c and the insulating layer 121 are formed on the semiconductor substrate 100, similar to the manufacturing method of the memory device 1 of the first embodiment. A laminate 900 including a plurality of insulating layers 102, 102A and a plurality of sacrificial layers 999 is formed on the semiconductor layer 101a. A stepped structure is formed at the end of the laminate 900 in the X direction.

[0276] The spacer film 150y is formed so as to cover the laminate 900. The material of the spacer film 150y is the same as, for example, the material of the sacrificial layer 999 (e.g., silicon nitride).

[0277] The spacer film 150y is processed into a predetermined shape by photolithography and RIE. As a result, as shown in FIG. 37, a plurality of spacer films 150z are formed so as to be individualized for each step of the stepped structure. For example, the film thickness T4 of the spacer film 150z is substantially the same as the film thickness T2 of the insulating layer 102.

[0278] The insulating layer 160 is formed on the laminate 900 and the spacer film 150z. The insulating layer 160 is planarized by etch-back and CMP methods so that the upper surface of the insulating layer 160 is aligned with the upper surface of the laminate 900. The material of the insulating layer 160 is, for example, silicon oxide formed using TEOS.

[0279] In the contact area CA and the plane separation area DA, the insulating layer 160 is formed on the semiconductor layer 101a.

[0280] As shown in FIG. 38, in the lead-out area of the memory cell array area MA, a plurality of support members HR are formed so as to penetrate the stepped structure. The lower end of the support member HR reaches the semiconductor layer 101c.

[0281] Of the plurality of support members HR, the support member HR at the position where the contact CC3 is formed is removed. As a result, an opening OP1 is formed in the region where the contact CC3 is to be formed. For example, at the bottom of the opening OP1, the semiconductor layers 101a and 101c are exposed.

[0282] In the contact area CA, an opening OP1 having the semiconductor layers 101a and 101c exposed at the bottom is formed at the position where the contact CC2 is formed, simultaneously with the opening OP1 in the lead-out area.

[0283] The spacer film 150z is selectively etched through the opening OP1. As a result, the spacer film 150z recedes in a direction parallel to the surface of the semiconductor substrate 100. The sacrificial layer 999, which is made of the same material as the spacer film 150z, also recedes in a direction parallel to the surface of the semiconductor substrate 100, similar to the spacer film 150z.

[0284] As a result, groove R5a is formed within the opening OP1, corresponding to the position of the terrace portion of the conductive layer 103. Groove R5b is formed between two adjacent insulating layers 102 in the Z direction.

[0285] For example, with respect to the Z direction, the dimension of groove R5a is larger than the dimension of groove R5b.

[0286] As shown in Figure 39, the insulator 151 is formed within the opening OP1, which includes the recesses R5a and R5b.

[0287] Wet etching is selectively performed on the insulator 151. The insulator 151 remains in the groove R5b of the opening OP1. The insulator 151 is removed from the groove R5a, which has a larger dimension.

[0288] Next, an oxidation treatment using the WVG method is performed. The exposed portions of the semiconductor layers 101a, 101c and the insulating layer 121 are oxidized. As a result, an insulating film 155 is formed on the semiconductor layers 101a, 101c and the insulating layer 121 at the bottom of the opening OP1.

[0289] As shown in Figure 40, the sacrificial member 180 is filled into the opening OP1 which includes the groove R5a. The sacrificial member 180 is, for example, amorphous silicon. The groove R5a is closed by the sacrificial member 180.

[0290] As shown in Figure 41, a replacement process is performed to form the conductive layer 103. This forms the insulating layer 109 and the conductive layer (word lines and select gate lines) 103 in the space within the laminate 900 where the sacrificial layer 999 has been removed.

[0291] As described above, the material of the spacer film 150z is the same as the material of the sacrificial layer 999. Therefore, the spacer film 150z is also removed together with the sacrificial layer 999. Within the extraction area, the conductive layer 103 and the insulating layer 109 are formed in the space where the spacer film 150z was removed.

[0292] As shown in Figure 42, the sacrificial member 180 is selectively removed in the extraction area. This forms an opening OP2. The insulating layer 109 covering the side surface of the conductive layer 103 is exposed to the opening OP2. In the opening OP2, the exposed insulating layer 109 is selectively removed. This exposes the side surface of the conductive layer 103 within the opening OP2.

[0293] As shown in Figure 43, the conductor CC3 is filled into the opening OP2. As described above, in the lead-out area (staircase structure), the insulating layer 109 is removed from the side of the conductive layer 103. Therefore, the conductor CC3 filled into the opening OP2 is in direct contact with the conductive layer 103. This ensures an electrical connection between the conductor CC3 and the conductive layer 103.

[0294] As a result, contact CC3 is formed so as to connect with the conductive layer 103. The side surface of contact CC3 is in direct contact with the corresponding side surface of the conductive layer 103.

[0295] In the contact area CA, contact CC2 is formed within the insulating layer 160 substantially simultaneously with the formation of contact CC3.

[0296] The edges of contacts CC2 and CC3 reach into the insulating film 155 within the semiconductor layers 101a and 101c.

[0297] Subsequently, bit lines BL and other wirings 163, etc., are formed on the array chip 10, similar to the embodiment described above. After the array chip 10 is formed through the above steps, the array chip 10 is bonded to the CMOS circuit chip 20, similar to the embodiment described above.

[0298] Subsequently, as shown in Figure 44, the isolation member BB1 is formed in the extraction area of ​​the memory cell array area MA substantially simultaneously with the formation of the isolation member BB2 in the plane isolation area DA, by substantially the same process as the manufacturing process described in Figures 24 to 29 above. As a result, the semiconductor layers 101a and 101c are divided into multiple parts within the extraction area. Consequently, adjacent contacts CC3 are electrically isolated by the isolation member BB1.

[0299] Subsequently, the memory device 1 of this embodiment is completed by substantially the same process as the manufacturing process shown in Figures 30 and 31 above.

[0300] In this embodiment, the oxidation step of semiconductor layers 101a and 101c by the WVG method shown in Figure 39 may be omitted.

[0301] The memory device 1 of this embodiment can achieve substantially the same effects as the embodiment described above.

[0302] (5) Fifth embodiment Referring to Figure 45, a memory device of the fifth embodiment will be described.

[0303] Figure 45 is a cross-sectional view showing an example of the structure of the memory device 1 of this embodiment.

[0304] As shown in Figure 45, the support members HR aligned in the X direction with respect to contact CC1 may be positioned within the lead-out area of ​​the memory cell array area MA so as to penetrate the insulating layers 150a and 150b. In the layer where the support member HR penetrates the terrace of the conductive layer 103, the sides of the support member HR are in contact with the insulating layers 150a and 150b. The end of the support member HR in the Z2 direction is in contact with the separation member BB1.

[0305] Furthermore, within the draw-out area, the contact CC1 may be arranged so that it is aligned diagonally with respect to the XY plane.

[0306] The memory device 1 of this embodiment can obtain the same effects as the embodiment described above.

[0307] (6) Others In the above-described embodiment, a memory device 1 having a configuration in which one CMOS circuit chip 20 is provided for one array chip 10 is shown as an example. However, the memory device 1 of the embodiment may have a configuration in which multiple CMOS circuit chips 20 are provided for one array chip 10, or a configuration in which multiple array chips 10 are provided for one CMOS circuit chip 20.

[0308] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0309] 1: Memory device, 10: Array chip, PLN: Plane, 11: Memory cell array, 101a, 101c: Semiconductor layer, 103: Conductive layer, CC1, CC2, CC3: Contact, BB1, BB2: Isolation member, HR: Support member, MA: Memory cell array area, CA: Contact area, DA: Plane isolation area.

Claims

1. A first chip including a substrate and a circuit on the substrate, The second chip is bonded to the first chip, It is equipped with, The second chip is, A laminate comprising a plurality of conductive layers spaced apart from each other in a first direction perpendicular to the surface of the second chip, and a memory pillar penetrating the plurality of conductive layers, A first semiconductor layer provided above the laminate in the first direction and connected to a source line, A first contact penetrates at least one of the plurality of conductive layers, is connected to the first conductive layer, and the portion of the first contact that is opposite to the first chip from the first conductive layer is located within the first semiconductor layer, A second contact that penetrates at least the second conductive layer of the plurality of conductive layers, is connected to the second conductive layer, and whose portion opposite to the first chip from the second conductive layer is located within the first semiconductor layer, and is aligned with the first contact in a second direction parallel to the surface of the second chip, A first separating member that separates the first semiconductor layer in the second direction between the first contact and the second contact, Includes, The first separation member includes a first portion located along the first chip-side surface of the first semiconductor layer and a second portion located along the surface of the first semiconductor layer opposite to the first chip. The first dimension of the second portion along the second direction is greater than the second dimension of the first portion along the second direction. Memory device.

2. The second chip is, A second semiconductor layer provided in the same layer as the first semiconductor layer, A second separating member is provided between the first semiconductor layer and the second semiconductor layer to separate the first semiconductor layer and the second semiconductor layer from each other. It further includes, The first semiconductor layer is a wiring that belongs to the first memory cell array, The second semiconductor layer is a wiring that belongs to a second memory cell array different from the first memory cell array. The memory device according to claim 1.

3. The second separation member includes a third portion located along the first chip-side surface of the first and second semiconductor layers, and a fourth portion located along the surface of the first and second semiconductor layers opposite to the first chip. The third dimension of the fourth portion along the second direction is greater than the fourth dimension of the third portion along the second direction. The memory device according to claim 2.

4. The material of the second separating member is the same as the material of the first separating member. The memory device according to claim 2.

5. A first chip including a substrate and a circuit on the substrate, The second chip is bonded to the first chip, It is equipped with, The second chip is, A laminate comprising a plurality of conductive layers spaced apart from each other in a first direction perpendicular to the surface of the second chip, and a memory pillar penetrating the plurality of conductive layers, A semiconductor layer provided above the laminate in the first direction, A first contact penetrates at least one of the plurality of conductive layers, is connected to the first conductive layer, and has its upper end located within the semiconductor layer, A second contact that penetrates at least the second conductive layer among the plurality of conductive layers, is connected to the second conductive layer, has its upper end located within the semiconductor layer, and is aligned with the first contact in a second direction parallel to the surface of the second chip, A separation member that separates the semiconductor layer in the second direction between the first contact and the second contact, Includes, The separation member includes a first portion located along the first chip-side surface of the semiconductor layer and a second portion located along the surface of the semiconductor layer opposite to the first chip. The first dimension of the second portion along the second direction is greater than the second dimension of the first portion along the second direction. Memory device.

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