Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device with a trench structure that can reduce Qg without increasing Ron. [Solution] The semiconductor device comprises a semiconductor portion having a trench extending along a first direction, having a first electrode, a first semiconductor layer of a first conductivity type provided on and connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, and a gate electrode arranged in the trench in a second direction perpendicular to the first direction, facing the second semiconductor layer and the third semiconductor layer, and having a facing surface formed so as to move away from the third semiconductor layer as it extends upward, at a position facing the third semiconductor layer.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Techniques related to MOS (metal-oxide-semiconductor) with a trench structure have been developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of embodiments of the present invention is to provide a semiconductor device with a trench structure and a method for manufacturing the same, which can reduce Qg (total gate charge) without increasing Ron (drain-source resistance value / also referred to as on-resistance).

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor portion having a first electrode, a first semiconductor layer of a first conductivity type provided on and connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, with a trench formed therein extending along a first direction, a gate electrode arranged in the trench in a second direction perpendicular to the first direction so as to face the second and third semiconductor layers, and having a facing surface formed so as to move away from the third semiconductor layer as it moves upward at a position facing the third semiconductor layer, a first insulating portion provided continuously on the semiconductor portion and in the trench, a second insulating portion provided on the gate electrode and made of a different material from the first insulating portion, and a second electrode provided on the semiconductor portion and connected to the second and third semiconductor layers.

[0006] A method for manufacturing a semiconductor device according to an embodiment comprises the steps of: forming a silicon nitride film on a structure having a recess formed on the gate electrode, the structure having a trench extending along a first direction and including a semiconductor portion containing silicon, a gate electrode provided in the trench and containing silicon, and an insulating portion disposed between the semiconductor portion and the gate electrode; forming a silicon oxide film on the silicon nitride film; removing the silicon oxide film in a region excluding the area directly above the recess by performing a planarization treatment; etching the silicon nitride film using the silicon oxide film on the recess as a mask; and performing an oxidation treatment on the gate electrode. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of a semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view of region D1 at height L1. [Figure 3] This is a cross-sectional view of region D1 at height L2. [Figure 4] This is a cross-sectional view of region D1 at height L3. [Figure 5] It is a sectional view taken along the V-V line in FIGS. 2 to 4. [Figure 6] It is an enlarged view of region D4. [Figure 7] It is a sectional view taken along the VII-VII line in FIGS. 2 to 4. [Figure 8] It is a sectional view taken along the VIII-VIII line in FIGS. 2 to 4. [Figure 9] It is a perspective view schematically showing region D2. [Figure 10] It is a perspective view schematically showing a part of the structure of region D3. [Figure 11] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 12] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 13] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 14] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 15] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 16] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 17] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 18] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 19] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 20] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment. [Figure 21] It is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of the respective parts are not necessarily the same as those in reality. In the specification and the drawings, the same reference numerals are given to the same elements as those described above with respect to the already shown drawings, and the detailed description thereof will be omitted as appropriate.

[0009] In the description of the embodiments, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 41 to the source electrode 42 is defined as the Z direction. Two directions perpendicular to the Z direction and perpendicular to each other are defined as the X direction and the Y direction.

[0010] In addition, with regard to terms used in this specification for specifying shapes, geometric conditions, and their degrees, such as "parallel", "same", etc., they are not bound by strict meanings and are to be interpreted including ranges where similar functions can be expected.

[0011] In the following description, n + 、n - and p + 、p notations represent the relative levels of impurity concentrations in each conductivity type. That is, notations with a "+" indicate that the impurity concentration is relatively higher than that of notations without either "+" or "-", and notations with a "-" indicate that the impurity concentration is relatively lower than that of notations without either. When both p-type and n-type impurities are included in each region, these notations represent the relative levels of the net impurity concentration after compensation between these impurities. For each of the embodiments described below, the p-type and n-type of each semiconductor region may be inverted to implement each embodiment.

[0012] (1. Structure of Semiconductor Device 100) Referring to FIGS. 1 to 10, the semiconductor device 100 according to the present embodiment will be described. FIG. 1 is a plan view of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view at the height L1 of region D1. FIG. 3 is a cross-sectional view at the height L2 of region D1. Figure 4 is a cross-sectional view of region D1 at height L3. Figure 5 is a cross-sectional view of the VV line in Figures 2 to 4. Figure 6 is an enlarged view of region D4. Figure 7 is a cross-sectional view taken along the line VII-VII in Figures 2 to 4. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figures 2 to 4. Figure 9 is a schematic perspective view of region D2. Figure 10 is a schematic perspective view showing a portion of the structure of region D3.

[0013] The semiconductor device 100 is, for example, a power MOSFET. As shown in Figure 1, the upper surface of the semiconductor device 100 has a source electrode 42 as a second electrode, a gate pad 61, and gate wiring 62. The lower surface of the semiconductor device 100 has a drain electrode 41 as a first electrode that extends over the entire surface.

[0014] The source electrodes 42 are arranged in a rectangular shape with their longer side in the first direction (the Y direction in the drawing, hereinafter simply referred to as the Y direction) in a plan view. For example, three source electrodes 42 are arranged on the top surface of the semiconductor device 100, but the device is not limited to this example. For example, the gate pads 61 are arranged in a rectangular shape at one end of the second direction (the X direction in the drawing, hereinafter simply referred to as the X direction) perpendicular to the first direction in a plan view, and at one end of the corner in the Y direction. The gate wiring 62 is arranged to extend from the gate pads 61 in the X direction, and further, to extend in the Y direction so as to be adjacent to the source electrodes 42. The position where the gate pads 61 are arranged is not limited to this example.

[0015] As shown in Figures 2 to 4, the semiconductor device 100 is configured with a cell section (a region having a structure shown in the V-V cross section), a gate finger section (a region having a structure shown in the VII-VII cross section), and a source finger section (a region having a structure shown in the VIII-VIII cross section).

[0016] As shown in Figure 5, the cell portion includes a semiconductor portion 10, a drain electrode 41 as the first electrode, and a source electrode 42.

[0017] The semiconductor portion 10 includes, for example, silicon and is provided between the drain electrode 41 and the source electrode 42. The semiconductor portion 10 includes a first semiconductor layer 10a of a first conductivity type, a second semiconductor layer 10b of a second conductivity type, a third semiconductor layer 10c of a first conductivity type, and a fourth semiconductor layer 10d of a second conductivity type. Hereinafter, as an example, the first conductivity type will be described as n-type and the second conductivity type as p-type, but it is not limited to this.

[0018] The first semiconductor layer 10a is, for example, an n placed on the upper surface of the drain electrode 41. + Shape drift layer and n + n placed on the upper surface of the shape drift layer - It includes a shape drift layer. The first semiconductor layer 10a extends between the drain electrode 41 and the source electrode 42.

[0019] The second semiconductor layer 10b is, for example, a p-type base layer. The second semiconductor layer 10b is provided on the first semiconductor layer 10a.

[0020] The third semiconductor layer 10c is, for example, n + This is a source layer. The third semiconductor layer 10c is partially provided on the second semiconductor layer 10b. The third semiconductor layer 10c is electrically connected to the source electrode 42.

[0021] The fourth semiconductor layer 10d is, for example, p + This is a contact layer. The fourth semiconductor layer 10d is partially provided on the second semiconductor layer 10b. The fourth semiconductor layer 10d contains a second conductivity type impurity at a higher concentration than the second conductivity type impurity in the second semiconductor layer 10b. The source electrode 42 is electrically connected to the second semiconductor layer 10b, the third semiconductor layer 10c, and the fourth semiconductor layer 10d via the source contact 51.

[0022] Multiple trenches TR extending along the X direction are formed in the semiconductor portion 10. The trenches TR are formed, for example, in the shape of elongated grooves with curved bottoms, but are not limited to this example. A field plate electrode 11, a gate electrode 12, and a first insulating portion 30 are arranged within the trenches TR.

[0023] The field plate electrode 11 is provided in the lower part of the trench TR in the cell portion so as to extend in the X direction. Specifically, the field plate electrode 11 is positioned opposite the first semiconductor layer 10a. The field plate electrode 11 is a conductor and is electrically connected to the source electrode 42 via the field plate contact 57 in the source finger portion, as will be described later. The shape of the field plate electrode 11 in the ZX plane may, for example, be a semi-elongated cylinder that is elongated vertically and curved along the cross-section of the trench TR, but is not limited to this example.

[0024] The gate electrode 12 is provided so as to extend in the X direction at the top of the trench TR in the cell portion. The gate electrode 12 may be polysilicon, for example, silicon mixed with impurities. Specifically, the gate electrode 12 is positioned to face the second semiconductor layer 10b and the third semiconductor layer 10c. The gate electrode 12 has opposing surfaces 13 at both ends along the Y direction, which are formed so as they move upward, away from the third semiconductor layer 10c, at a position facing the third semiconductor layer 10c. The shape of the gate electrode 12 below the opposing surfaces 13 in the ZX plane may be rectangular, for example, but is not limited to this example. Details of the opposing surfaces 13 will be described later.

[0025] The first insulating portion 30 contains silicon oxide (SiO2) and is provided continuously within the trench TR and on top of the semiconductor portion 10. Specifically, the first insulating portion 30 comprises a field plate insulating portion 30a, an interlayer portion 30b, a gate insulating portion 30c, and an upper layer portion 30d.

[0026] The field plate insulating portion 30a is positioned around the field plate electrode 11 on the sides and below to insulate the field plate electrode 11 from the first semiconductor layer 10a. The interlayer portion 30b is positioned in layers between the gate electrode 12 and the field plate electrode 11 to insulate the gate electrode 12 from the field plate electrode 11.

[0027] The gate insulating portion 30c is positioned around the side of the gate electrode 12 to insulate the gate electrode 12 from the second semiconductor layer 10b and the third semiconductor layer 10c. The upper layer portion 30d is positioned in a layered manner on top of the third semiconductor layer 10c to insulate the third semiconductor layer 10c from the gate electrode 12.

[0028] A second insulating portion 31, made of a different material than the first insulating portion 30, is placed on the gate electrode 12. The second insulating portion 31 includes, for example, silicon nitride (SiN) and insulates the gate electrode 12 and the source electrode 42 from each other.

[0029] As shown in Figure 6, the opposing surface 13 is formed at both ends along the Y direction in a position opposite the third semiconductor layer 10c, and moves away from the third semiconductor layer 10c as it extends upward. The opposing surface 13 may be a curved surface as shown in Figure 6 as an example, or it may be a flat surface as another example. The height H1 of the opposing surface 13 in the Z direction is preferably about H1 / H2 = 1 / 2 of the height H2 of the third semiconductor layer 10c. The width W3 of the opposing surface 13 in the Y direction is preferably about W3 / W4 = 1 / 3 of the distance W4 between the second semiconductor layer 10b and the gate electrode.

[0030] As shown in Figure 7, the gate finger portion includes a drain electrode 41, a semiconductor portion 10, and gate wiring 62.

[0031] The semiconductor portion 10 of the gate finger includes a first semiconductor layer 10a of a first conductivity type and a second semiconductor layer 10b of a second conductivity type. A pair of gate trenches TG extending along the Y direction are formed in the semiconductor portion 10 of the gate finger. The gate trenches TG are formed in the shape of an elongated groove with a curved bottom, for example, but are not limited to this example. A field plate electrode 11, a gate electrode 12, and a gate contact 55 are arranged inside the gate trenches TG.

[0032] The gate contact 55 is conductive and electrically connects the gate wiring 62 to the first connecting portion 12a of the gate electrode 12. As a result, current flows from the gate wiring 62 through the first connecting portion 12a to the gate electrode 12. Furthermore, the cross-sectional area (area in the XZ plane) S1 of the gate electrode 12 in the gate finger portion shown in Figure 7 may, for example, be smaller than the cross-sectional area (area in the YZ plane) S2 of the gate electrode 12 in the cell portion shown in Figure 5. A first insulating portion 30 is arranged around the field plate electrode 11 and the gate electrode 12.

[0033] As shown in Figure 8, the source finger portion is arranged with a drain electrode 41, a semiconductor portion 10, and a source electrode 42.

[0034] The semiconductor portion 10 of the source finger includes a first semiconductor layer 10a of a first conductivity type and a second semiconductor layer 10b of a second conductivity type. A pair of source trenches TS extending along the Y direction are formed in the semiconductor portion 10 of the source finger. The source trenches TS are formed in the shape of an elongated groove with a curved bottom, for example, but are not limited to this example. A field plate electrode 11 and a field plate contact 57 are disposed within the source trenches TS.

[0035] The field plate contact 57 is conductive and electrically connects the source electrode 42 to the second connecting portion 11a of the field plate electrode 11. This allows electricity to flow from the source electrode 42 to the field plate electrode 11. The field plate electrode 11 in the source finger portion is elongated vertically and curved along the cross-section of the source trench TS, forming a semicircular shape, and is positioned from a position facing the first semiconductor layer 10a to a position facing the second semiconductor layer 10b. A first insulating portion 30 is positioned around the field plate electrode 11.

[0036] As shown in Figures 9 and 10, the field plate electrode 11 is positioned in the source finger portion from a position facing the first semiconductor layer 10a to a position facing the second semiconductor layer 10b within the source trench TS, and in the cell portion and gate finger portion, it is positioned in the trench TR or gate trench TG facing the first semiconductor layer 10a. The gate electrode 12 is not positioned in the source finger portion. In the cell portion and gate finger portion, the gate electrode 12 is positioned in the trench TR or gate trench TG facing the second semiconductor layer 10b and the third semiconductor layer 10c.

[0037] (2. Method for manufacturing the semiconductor device 100) The manufacturing method of the semiconductor device 100 according to the embodiment will be described below with reference to Figures 11 to 21. In Figures 11 to 21, (a) shows the cell portion, (b) shows the gate finger portion, and (c) shows the source finger portion. In the following description, the trench TR in the cell portion, the gate trench TG in the gate finger portion, and the source trench TS in the source finger portion will be collectively referred to simply as trenches.

[0038] First, as shown in Figures 11(a) to (c), a trench is formed by a known method to prepare a structure Y which includes a semiconductor portion 10 of a first conductivity type containing silicon, a field plate electrode 11 and a gate electrode 12 provided in the trench, and a first insulating portion 30 disposed between the semiconductor portion 10 and the gate electrode 12, with a recessed portion C formed on the gate electrode 12. Then, a silicon nitride film 71 is deposited on the structure Y, for example by CVD (Chemical Vapor Deposition). This forms a recess C1 on the upper surface of the silicon nitride film 71 that reflects the recessed portion C.

[0039] Next, as shown in Figures 12(a) to (c), a silicon oxide film 72 is deposited on the silicon nitride film 71 by CVD. This creates a recess C2 on the upper surface of the silicon oxide film 72 that reflects the recess C1.

[0040] Next, as shown in Figures 13(a) to (c), the silicon oxide film 72 is removed in the region excluding the area directly above the depression C by a planarization treatment, for example, CMP (Chemical Mechanical Polishing). As a result, the silicon oxide film 72 remains only in the region directly above the depression C.

[0041] Next, as shown in Figures 14(a) to (c), the silicon nitride film 71 is etched using the silicon oxide film 72 above the depression C as a mask material. Anisotropic etching such as RIE (Reactive Ion Etching) may be used for the etching. As a result, the silicon nitride film 71 remains only in the area directly above the depression C, excluding the peripheral area.

[0042] Next, as shown in Figures 15(a) to (c), the silicon oxide film 72 formed on the silicon nitride film 71 is recessed by etching. Here, the etching may be isotropic etching such as wet etching. As a result, the length of the trench in the silicon oxide film 72 formed on the silicon nitride film 71 in the width direction becomes shorter than the length of the silicon nitride film 71 in the same width direction. In addition, the peripheral edge of the upper surface of the gate electrode 12 is exposed in the cell portion and the gate finger portion.

[0043] Next, as shown in Figures 16(a) to (c), the gate electrode 12 is subjected to an oxidation treatment. As a result, the exposed portions of the gate electrode 12 in the cell portion and gate finger portion are oxidized and become part of the first insulating portion 30. Consequently, at the ends of the gate electrode 12 in the cell portion and gate finger portion, opposing surfaces 13 are formed that move away from the semiconductor portion 10 as they extend upward.

[0044] Next, as shown in Figures 17(a) to (c), impurities are injected into the upper part of the semiconductor portion 10 in the cell portion, gate finger portion, and source finger portion to form a second semiconductor layer 10b of the second conductivity type. Furthermore, impurities are injected into the upper part of the second semiconductor layer 10b in the cell portion to form a third semiconductor layer 10c of the first conductivity type. As a result, in the cell portion, the opposing surface 13, which is the oxidized portion of the gate electrode 12, and the third semiconductor layer 10c of the first conductivity type face each other.

[0045] Next, as shown in Figures 18(a) to (c), a silicon oxide film 73 is formed on the third semiconductor layer 10c of the cell portion and on the second semiconductor layer 10b of the gate finger portion and source finger portion, for example, by CVD.

[0046] Next, as shown in Figures 19(a) to (c), the silicon oxide film 73 is removed by planarization treatment using CMP, exposing the upper surface of the silicon nitride film 71 located above the field plate electrode 11 or gate electrode 12.

[0047] Next, as shown in Figures 20(a) to (c), a resist pattern 74 in which a first opening P1 is formed between a plurality of trenches TR is formed on the silicon oxide film 73. In the gate finger portion, the gate electrode 12 has a first connecting portion 12a that connects to a gate wiring 62 provided on the upper surface of the semiconductor device 100, and the resist pattern 74 is formed without covering the first connecting portion 12a. In the source finger portion, the field plate electrode 11 has a second connecting portion 11a that connects to a source electrode 42 provided on the upper surface of the semiconductor device 100, and the resist pattern 74 is formed without covering the second connecting portion 11a.

[0048] Then, RIE is performed on the silicon nitride film 71 using the resist pattern 74 as a mask. This removes the silicon nitride film 71 placed on the first connecting portion 12a, forming a second opening P2 for placing the gate contact 55. Also, the silicon nitride film 71 placed on the second connecting portion 11a is removed, forming a third opening P3.

[0049] Next, as shown in Figures 21(a) to (c), RIE is performed on the silicon oxide film 73 using the resist pattern 74 as a mask. This creates a fourth opening P4 in the cell portion for positioning the source contact 51. In the source finger portion, the silicon oxide film 73 positioned on the second connecting portion 11a is removed, and a fifth opening P5 is formed for positioning the field plate contact 57.

[0050] Next, a source contact 51 is placed in the fourth aperture P4 of the cell. A drain electrode 41, serving as the first electrode, is provided on the lower surface of the semiconductor portion 10, and a source electrode 42, serving as the second electrode, is provided on the upper surface of the semiconductor portion 10. This completes the manufacturing of the semiconductor device 100.

[0051] (3.Summary) As described above, the semiconductor device 100 according to this embodiment has a drain electrode 41 as a first electrode, a first semiconductor layer 10a of a first conductivity type provided on the drain electrode 41 and connected to the drain electrode 41, a second semiconductor layer 10b of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer 10c of a first conductivity type provided on the second semiconductor layer, and a trench is formed along the first direction, the Y direction, and a semiconductor portion 10 containing silicon, and along the second direction, the X direction, which is perpendicular to the Y direction within the trench, the second semiconductor layer 10b and the third semiconductor layer 10 The device comprises a gate electrode having opposing surfaces 13 at both ends along the X direction, positioned opposite to c and facing the third semiconductor layer 10c, with the opposing surfaces 13 being formed to move away from the third semiconductor layer 10c as they extend upward; a first insulating portion 30 containing silicon oxide, provided in communication with the semiconductor portion 10 and the trench TR; a second insulating portion 31 provided on the gate electrode 12 and containing silicon nitride, which is made of a different material than the first insulating portion 30; and a source electrode 42 as a second electrode provided on the semiconductor portion 10 and connected to the second semiconductor layer 10b and the third semiconductor layer 10c.

[0052] This configuration allows for a height H1 between the third semiconductor layer 10c and the gate electrode 12 that is opposite each other, while simultaneously increasing the distance in the Y direction between the third semiconductor layer 10c and the gate electrode 12. This ensures that the gate electrode 12 has control over the second semiconductor layer 10b while reducing the parasitic capacitance between the third semiconductor layer 10c and the gate electrode 12. As a result, it becomes possible to reduce Qg while suppressing the increase in Ron.

[0053] Furthermore, the manufacturing method of the semiconductor device 100 includes a trench TR extending along the Y direction, a semiconductor portion 10 containing silicon, a gate electrode 12 containing silicon provided in the trench TR, and a first insulating portion 30 disposed between the semiconductor portion 10 and the gate electrode 12, and a recessed portion C formed on the gate electrode 12, a step of forming a silicon nitride film 71 on a structure Y, a step of forming a silicon oxide film 72 on the silicon nitride film 71, and a planarization treatment, thereby forming silicon oxide in the region excluding the area directly above the recessed portion C The steps include: removing the silicon oxide film 72; etching the silicon nitride film 71 using the silicon oxide film 72 on the recessed portion C as a mask; etching the silicon oxide film 72; oxidizing the gate electrode 12; injecting impurities into the semiconductor portion 10 to make the upper part of the semiconductor portion 10 a second semiconductor layer 10b of the second conductivity type; injecting impurities into the semiconductor portion 10 to make the upper part of the second semiconductor layer 10b, which faces the oxidized portion of the gate electrode 12, a third semiconductor layer 10c of the first conductivity type; and 3 The process includes the steps of forming a silicon oxide film 73 on a semiconductor layer 10c, exposing a silicon nitride film 71 by performing a planarization process, forming a resist pattern 74 in which a first opening P1 is formed between a plurality of trenches TR, etching the silicon oxide film 73 using the resist pattern 74 as a mask, in the step of forming the resist pattern 74, the resist pattern 74 does not cover the first connecting portion 12a, and after the step of forming the resist pattern 74, the silicon nitride film 71 placed on the first connecting portion 12a is removed, in the step of forming the resist pattern 74, the resist pattern does not cover the second connecting portion 11a, and in the step of removing the silicon nitride film 71, the silicon nitride film 71 placed on the second connecting portion 11a is also removed, and after the step of removing the silicon nitride film 71, the silicon oxide film 73 placed on the second connecting portion 11a is removed, and providing a drain electrode 41 as a first electrode on the lower surface of the semiconductor portion 10, and providing a source electrode 42 as a second electrode on the upper surface of the semiconductor portion 10.

[0054] By using this process, the silicon nitride film 71 is used as a stopper film in the planarization process by CMP, thereby improving the flatness of the interlayer film, miniaturization of the semiconductor device 100 is achieved, and an increase in Ron is suppressed.

[0055] Specifically, by adopting the above configuration, the focus margin can be improved in the process of forming the resist pattern 74, and the width of the fourth aperture P4 for positioning the source contact 51 can be narrowed, thereby enabling miniaturization of the semiconductor device 100. Furthermore, by adopting the above configuration, the fourth aperture P4 for positioning the source contact 51, the second aperture P2 for positioning the gate contact 55, and the fifth aperture P5 for positioning the field plate contact 57 can be formed in the same process. In addition, since the first aperture P1 is formed between multiple trenches TR by forming the resist pattern 74, misalignment due to self-alignment of the first aperture P1 can be prevented.

[0056] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0057] The present invention includes the following embodiments. (Note 1) First electrode and, A semiconductor portion having a first semiconductor layer of a first conductivity type provided on and connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, wherein a trench extending along a first direction is formed, Displaced within the trench along a second direction perpendicular to the first direction, facing the second semiconductor layer and the third semiconductor layer, and having a gate electrode at a position facing the third semiconductor layer, with a facing surface formed so as to move away from the third semiconductor layer as it extends upward, A first insulating portion is provided continuously on the semiconductor portion and inside the trench, A second insulating portion is provided on the gate electrode and is made of a different material from the first insulating portion, A second electrode is provided on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer, A semiconductor device equipped with the following features. (Note 2) The semiconductor device according to Appendix 1, wherein the gate electrode has the opposing surfaces at both ends along the second direction. (Note 3) The semiconductor part includes silicon, The first insulating portion contains silicon oxide, The semiconductor device described in Appendix 1, wherein the second insulating portion includes silicon nitride. (Note 4) A step of forming a silicon nitride film on a structure having a trench extending along a first direction, a semiconductor portion containing silicon, a gate electrode provided in the trench and containing silicon, and an insulating portion disposed between the semiconductor portion and the gate electrode, wherein a recessed portion is formed on the gate electrode. The steps include forming a silicon oxide film on the silicon nitride film, The process involves removing the silicon oxide film in the region excluding the area directly above the depression by applying a flattening treatment, The process involves etching the silicon nitride film using the silicon oxide film on the recessed portion as a mask, A step of applying an oxidation treatment to the gate electrode, A method for manufacturing a semiconductor device, comprising: (Note 5) The method for manufacturing a semiconductor device according to Appendix 4, further comprising the step of etching the silicon oxide film after the step of etching the silicon nitride film. (Note 6) The semiconductor part is of the first conductivity type, After the step of applying an oxidation treatment to the gate electrode, A step of injecting impurities into the semiconductor portion to form a second semiconductor layer of a second conductivity type on the upper part of the semiconductor portion, A step of injecting impurities into the semiconductor portion to form a third semiconductor layer of the first conductivity type in the upper part of the second semiconductor layer, which is opposite to the oxidized portion of the gate electrode. A step of forming a silicon oxide film on the aforementioned third semiconductor layer, The process involves a step of exposing the silicon nitride film by applying a planarization treatment, A method for manufacturing a semiconductor device as described in Appendix 4 or 5, further comprising: (Note 7) After the exposure step, A step of forming a resist pattern in which openings are formed between a plurality of trenches, A step of etching the silicon oxide film using the resist pattern as a mask, Further preparations are made for the method of manufacturing a semiconductor device as described in Appendix 6. (Note 8) The gate electrode has a first connecting portion that connects to a gate wiring provided on the upper surface of the semiconductor device. In the step of forming the resist pattern, the resist pattern does not cover the first connecting portion. The method for manufacturing a semiconductor device according to Appendix 7, further comprising the step of removing the silicon nitride film disposed on the first connecting portion after the step of forming the resist pattern. (Note 9) A field plate electrode is provided below the gate electrode in the trench. The field plate electrode has a second connecting portion that connects to a source electrode provided on the upper surface of the semiconductor device. In the step of forming the resist pattern, the resist pattern does not cover the second connecting portion. In the step of removing the silicon nitride film, the silicon nitride film placed on the second connecting portion is also removed. The method for manufacturing a semiconductor device according to Appendix 8, further comprising the step of removing the silicon oxide film disposed on the second connecting portion after the step of removing the silicon nitride film. (Note 10) The steps include providing a first electrode on the lower surface of the semiconductor portion, The step of providing a second electrode on the upper surface of the semiconductor part, A method for manufacturing a semiconductor device as described in any one of appendices 4 to 9, further comprising: [Explanation of Symbols]

[0058] 10: Semiconductor part, 10a: First semiconductor layer, 10b: Second semiconductor layer, 10c: Third semiconductor layer, 10d: Fourth semiconductor layer, 11: Field plate electrode, 11a: Second connection part, 12: Gate electrode, 12a: First connection part, 13: Opposing surface, 30: First insulating part, 30a: Field plate insulating part, 30b: Interlayer part, 30c: Gate insulating part, 30d: Upper part of layer, 31: Second insulating part, 41: Drain electrode, 42: Source electrode, 51: Source contact, 55: Gate contact, 57: Field plate contact, 61: Gate pad, 62: Gate wiring, 71: Silicon nitride film, 72: Silicon oxide film, 73: Silicon oxide film, 74: Resist pattern, 100: Semiconductor device

Claims

1. First electrode and, A semiconductor portion having a first semiconductor layer of a first conductivity type provided on and connected to the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer, wherein a trench extending along a first direction is formed, Displaced within the trench along a second direction perpendicular to the first direction, facing the second semiconductor layer and the third semiconductor layer, and having a gate electrode with a facing surface formed so as to move away from the third semiconductor layer upward, A first insulating portion is provided continuously on the semiconductor portion and inside the trench, A second insulating portion is provided on the gate electrode and is made of a different material from the first insulating portion, A second electrode is provided on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the gate electrode has the opposing surfaces at both ends along the second direction.

3. The semiconductor part includes silicon, The first insulating portion contains silicon oxide, The semiconductor device according to claim 1, wherein the second insulating portion includes silicon nitride.

4. A step of forming a silicon nitride film on a structure having a trench formed along a first direction, a semiconductor portion containing silicon, a gate electrode provided in the trench and containing silicon, and an insulating portion disposed between the semiconductor portion and the gate electrode, wherein a recessed portion is formed on the gate electrode. The steps include forming a silicon oxide film on the silicon nitride film, The process involves removing the silicon oxide film in the region excluding the area directly above the depression by applying a flattening treatment, The process involves etching the silicon nitride film using the silicon oxide film on the recessed portion as a mask, A step of applying an oxidation treatment to the gate electrode, A method for manufacturing a semiconductor device, comprising:

5. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of etching the silicon oxide film after the step of etching the silicon nitride film.

6. The semiconductor part is of the first conductivity type, After the step of applying an oxidation treatment to the gate electrode, A step of injecting impurities into the semiconductor portion to form a second semiconductor layer of a second conductivity type on the upper part of the semiconductor portion, A step of injecting impurities into the semiconductor portion to form a third semiconductor layer of the first conductivity type in the upper part of the second semiconductor layer, which is opposite to the oxidized portion of the gate electrode. A step of forming a silicon oxide film on the aforementioned third semiconductor layer, The process involves a step of exposing the silicon nitride film by applying a planarization treatment, A method for manufacturing a semiconductor device according to claim 4, further comprising:

7. After the exposure step, A step of forming a resist pattern in which openings are formed between a plurality of trenches, A step of etching the silicon oxide film using the resist pattern as a mask, A method for manufacturing a semiconductor device according to claim 6, further comprising:

8. The gate electrode has a first connecting portion that connects to a gate wiring provided on the upper surface of the semiconductor device. In the step of forming the resist pattern, the resist pattern does not cover the first connecting portion. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of removing the silicon nitride film disposed on the first connecting portion after the step of forming the resist pattern.

9. A field plate electrode is provided below the gate electrode in the trench. The field plate electrode has a second connecting portion that connects to a source electrode provided on the upper surface of the semiconductor device. In the step of forming the resist pattern, the resist pattern does not cover the second connecting portion. In the step of removing the silicon nitride film, the silicon nitride film placed on the second connecting portion is also removed. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of removing the silicon oxide film disposed on the second connecting portion after the step of removing the silicon nitride film.

10. The steps include providing a first electrode on the lower surface of the semiconductor portion, The step of providing a second electrode on the upper surface of the semiconductor part, The method for manufacturing a semiconductor device according to claim 4, further comprising

Images