Semiconductor equipment

Abstract

Improve the trade-off between on-resistance and safe operating area. [Solution] The semiconductor device according to this embodiment comprises a first electrode, a second electrode, a semiconductor layer, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, and a third semiconductor region of a first conductivity type. The semiconductor layer is provided between the first electrode and the second electrode. The first semiconductor region is provided within the semiconductor layer. The second semiconductor region is located above the first semiconductor region. The third electrode is provided within the second semiconductor region via a first insulating region. The third semiconductor region is located between the second semiconductor region and the second electrode. The semiconductor layer comprises a first portion in which the third electrode extends in a second direction with a first width, and a second portion in which the third electrode is configured with a second width greater than the first width, wherein the length of the second portion in the second direction is smaller than that of the first portion.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] In semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), low on-resistance is desirable. However, when reducing on-resistance by, for example, miniaturizing the cell pitch or shortening the channel length, the transconductance of the semiconductor device increases, potentially narrowing the safe operating area (SOA). In other words, there is a trade-off between on-resistance and the safe operating area. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-65766 [Patent Document 2] Japanese Patent Publication No. 2019-161103 [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device that can improve the trade-off between on-resistance and safe operating area. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment comprises a first electrode, a second electrode, a semiconductor layer, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, and a third semiconductor region of a first conductivity type. The semiconductor layer is provided between the first electrode and the second electrode. The first semiconductor region is provided within the semiconductor layer and located above the first electrode. The second semiconductor region is provided within the semiconductor layer and located above the first semiconductor region. The third electrode is provided within the second semiconductor region via a first insulating region and extends in a second direction perpendicular to a first direction from the first electrode to the second electrode. The third semiconductor region is provided within the semiconductor layer and located between the second semiconductor region and the second electrode. The semiconductor layer comprises a first portion in which the third electrode extends in the second direction with a first width, and a second portion in which the third electrode is configured with a second width greater than the first width. The length of the second portion in the second direction is smaller than the length of the first portion in the second direction. [Brief explanation of the drawing]

[0006] [Figure 1] This is a plan view of a semiconductor device according to an embodiment. [Figure 2A] This is a cross-sectional view of the gate of the semiconductor device according to the embodiment. [Figure 2B] This is a cross-sectional view of the wide gate portion in the semiconductor device according to the embodiment. [Figure 3] This is a graph of simulation results showing the relationship between mesa width and threshold voltage in a semiconductor device according to the embodiment. [Figure 4] These are cross-sectional views of a normal gate width portion and a wide gate width portion to illustrate an example of the manufacturing process of a semiconductor device according to the embodiment. [Figure 5] Figure 4 is a cross-sectional view of the normal gate width portion and the wide gate width portion, illustrating an example of the manufacturing process of a semiconductor device according to the embodiment. [Figure 6A] Figure 5 is a cross-sectional view of the gate normal width portion illustrating an example of the manufacturing process of a semiconductor device according to the embodiment. [Figure 6B]It is a cross-sectional view of a wide gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 5. [Figure 7A] It is a cross-sectional view of a normal gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 6A. [Figure 7B] It is a cross-sectional view of a wide gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 6B. [Figure 8A] It is a cross-sectional view of a normal gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 7A. [Figure 8B] It is a cross-sectional view of a wide gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 7B. [Figure 9A] It is a cross-sectional view of a normal gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 8A. [Figure 9B] It is a cross-sectional view of a wide gate width portion for explaining an example of a manufacturing process of a semiconductor device according to an embodiment, following FIG. 8B. [Figure 10] It is a plan view of a semiconductor device according to Modification 1. [Figure 11] It is a plan view of a semiconductor device according to Modification 2.

BEST MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and the drawings, elements similar to those described above with respect to the previous drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] For convenience of explanation, as shown in FIG. 1 and the like, an XYZ orthogonal coordinate system is adopted. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Also, in the Z-axis direction, the source electrode side is also referred to as "up", and the drain electrode side is also referred to as "down". However, this expression is for convenience and has nothing to do with the direction of gravity. The Z-axis direction is the first direction in the claims. The Y-axis direction is the second direction in the claims. The X-axis direction is the third direction in the claims.

[0009] Also, in the following description, in order to represent the relative high and low of the impurity concentration in each conductivity type, n + , n, n - , and p + , p, p - may be used in the notation. That is, n + indicates that the n-type impurity concentration is relatively higher than n, and n - indicates that the n-type impurity concentration is relatively lower than n. Also, p + indicates that the p-type impurity concentration is relatively higher than p, and p - indicates that the p-type impurity concentration is relatively lower than p. These notations represent the relative high and low of the net impurity concentration after these impurities compensate for each other when both p-type and n-type impurities are included in each region. The n-type, n + type and n - type are an example of the first conductivity type in the claims. The p-type, p + type and p - type are an example of the second conductivity type in the claims. Note that in the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be p-type.

[0010] Also, the impurity concentration of the semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS). Also, the relative high and low of the impurity concentration can be determined, for example, from the high and low of the carrier concentration obtained by scanning capacitance microscopy (SCM).

[0011] Furthermore, dimensions such as the width of the semiconductor region can be measured, for example, by surface and / or cross-sectional analysis using a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscope (SEM).

[0012] In this specification, terms such as "identical," "same," and "equal," as well as dimensions and physical property values ​​used to specify shape, geometric conditions, physical properties, and their degrees, shall not be strictly interpreted, but shall be interpreted to include a range that allows for the expectation of similar functionality.

[0013] The semiconductor device 1 according to the embodiment will be described with reference to Figures 1, 2A, and 2B. Figure 1 is a plan view of the semiconductor device 1 according to the embodiment, and is a plan view at height position I in Figures 2A and 2B. Figure 2A is a cross-sectional view of the gate normal width portion 3 in the semiconductor device 1 according to the embodiment, and is a cross-sectional view along line AA in Figure 1. Figure 2B is a cross-sectional view of the gate wide portion 4 in the semiconductor device 1 according to the embodiment, and is a cross-sectional view along line BB in Figure 1.

[0014] The semiconductor device 1 is, for example, a vertical MOSFET. More specifically, the semiconductor device 1 is a vertical MOSFET having a structure in which the field plate electrode (FP electrode) and the gate electrode are embedded in the same trench. Alternatively, the semiconductor device 1 may be a vertical MOSFET having a structure in which the FP electrode and the gate electrode are embedded in different trenches. Or, the semiconductor device 1 may be a vertical transistor such as an IGBT (Insulated Gate Bipolar Transistor).

[0015] As shown in Figures 2A and 2B, the semiconductor device 1 according to this embodiment comprises a semiconductor layer 2, a drain electrode 11, a source electrode 12, a gate electrode 13, an FP electrode 14, an insulating region (gate insulating film) 51, an insulating region (interlayer insulating film) 52, an insulating region (FP insulating film) 53, a conductive portion 61, and a conductive portion 62.

[0016] The semiconductor layer 2 is provided between the drain electrode 11 and the source electrode 12. The semiconductor layer 2 has a lower surface 2a and an upper surface 2b opposite to the lower surface 2a.

[0017] Furthermore, as shown in Figure 1, the semiconductor layer 2 has a gate normal width portion 3 and a gate wide portion 4. The gate normal width portion 3 is the portion in which the gate electrode 13 extends in the Y-axis direction with a width (first width) w1. The gate wide portion 4 is the portion in which the gate electrode 13 is composed of a width (second width) w2. Width w2 is greater than width w1. That is, the length of the gate electrode 13 in the X-axis direction in the gate wide portion 4 is greater than the length of the gate electrode 13 in the X-axis direction in the gate normal width portion 3. The gate normal width portion 3 is an example of the first portion in the claims. The gate wide portion 4 is an example of the second portion in the claims. As shown in Figure 1, the gate normal width portion 3 and the gate wide portion 4 are arranged alternately along the Y-axis direction.

[0018] Furthermore, the length of the gate wide portion 4 in the Y-axis direction is smaller than the length of the gate normal width portion 3 in the Y-axis direction. That is, the gate electrode 13 is locally wider in the gate wide portion 4. Also, in the gate wide portion 4, the gate electrode 13 has a protruding portion 13a that protrudes into the base region 23 via the insulating region 51. Note that the ratio of the gate wide portion 4 to the gate normal width portion 3 in the Y-axis direction is not limited to the example in Figure 1. For example, the ratio of the gate wide portion 4 to the gate normal width portion 3 in the Y-axis direction may be larger or smaller than in the example in Figure 1. Alternatively, the gate wide portion 4 may be provided more densely or more sparsely than in the example in Figure 1.

[0019] As shown in Figure 1, multiple gate electrodes 13 are provided, each extending in the Y-axis direction. That is, the semiconductor device 1 has a so-called stripe structure. In this embodiment, the Y-axis center of the gate normal width portion 3 between adjacent gate electrodes 13 is aligned with the X-axis direction, and the Y-axis center of the gate wide portion 4 between adjacent gate electrodes 13 is aligned with the X-axis direction. That is, multiple gate normal width portions 3 are provided continuously along the X-axis direction, and multiple gate wide portions 4 are provided continuously along the X-axis direction.

[0020] The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity, and for example, boron (B) can be used as the p-type impurity. The semiconductor layer 2 may also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0021] As shown in Figures 2A and 2B, the semiconductor layer 2 contains, for example, a drift region 21, a drain region 22, a base region 23, a source region 24, and a high-concentration region 25. Details of these regions will be described later.

[0022] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is provided on the lower surface 2a of the semiconductor layer 2. The drain electrode 11 is in contact with the drain region 22 and is electrically connected to the drain region 22. The drain electrode 11 is an example of the first electrode in the claims. The drain electrode 11 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc.

[0023] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is provided on the upper surface 2b of the semiconductor layer 2 via an insulating region 52. As shown in Figure 2A, the source electrode 12 is electrically connected to the source region 24 and the high-density region 25 via a conductive portion 61 in the gate normal width portion 3. Also, as shown in Figure 2B, the source electrode 12 is electrically connected to the source region 24 via a conductive portion 62 in the gate wide portion 4. The source electrode 12 is an example of the second electrode in the claims. The source electrode 12 is made of, for example, copper (Cu), titanium (Ti), tungsten (W), aluminum (Al), etc. The insulating region 52 includes, for example, silicon oxide or silicon nitride.

[0024] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is located within the base region 23 via an insulating region 51. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the insulating region 51. The gate electrode 13 is an example of the third electrode in the claims. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the base region 23, and carriers flow between the drift region 21 and the source region 24. This turns the MOSFET ON.

[0025] As shown in Figures 2A and 2B, in this embodiment, the distance d1 between the gate electrode 13 and the base region 23 along the X-axis direction in the normal width portion 3 of the gate is equal to the distance d2 between the gate electrode 13 and the base region 23 along the X-axis direction in the wide portion 4 of the gate. Here, distance d1 corresponds to the thickness of the insulating region 51 in the normal width portion 3, and distance d2 corresponds to the thickness of the insulating region 51 in the wide portion 4 of the gate. Note that distance d1 may be different from distance d2.

[0026] The FP electrode 14 is provided within the gate normal width portion 3 and gate wide portion 4 of the semiconductor layer 2 via an insulating region 53. The FP electrode 14 is electrically insulated from the semiconductor layer 2 by the insulating region 53 and is electrically connected to the source electrode 12, for example, at the Y-axis end of the semiconductor layer 2 (not shown). The FP electrode 14 is an example of the fourth electrode in the claims. In this embodiment, the FP electrode 14 is located below the gate electrode 13 and extends in the Y-axis direction. The FP electrode 14 is made of polysilicon containing, for example, p-type or n-type impurities. The FP electrode 14 may also be provided within the semiconductor layer 2 via an insulating region other than the insulating region 53. Furthermore, the FP electrode 14 may be provided to extend in a direction other than the Y-axis direction (for example, the X-axis direction).

[0027] As shown in Figures 2A and 2B, the FP electrode 14 has a width w3 in the gate normal width portion 3 and a width w4 in the gate wide portion 4. In this embodiment, width w3 is equal to width w4. However, width w3 may be different from width w4.

[0028] The insulating region 51 and insulating region 53 are provided to cover the side walls of a plurality of trenches provided on the upper surface 2b of the semiconductor layer 2. The insulating region 51 and insulating region 53 are examples of the first insulating region and the second insulating region in the claims, respectively. The insulating region 51 and insulating region 53 each contain, for example, silicon oxide or silicon nitride.

[0029] The conductive portion 61 is provided in the gate normal width portion 3, penetrates the source region 24, and electrically connects the source region 24 and the high-concentration region 25 to the source electrode 12. The conductive portion 61 is an example of the first conductive portion in the claims. The conductive portion 61 is made of the same material as the source electrode 12, for example. However, the conductive portion 61 may be made of a different material from the source electrode 12.

[0030] The conductive portion 62 is provided in the gate wide portion 4 and electrically connects the source region 24 and the source electrode 12. The lower end of the conductive portion 62 is located above the upper end of the base region 23. In this embodiment, the conductive portion 62 does not penetrate the source region 24. More specifically, in this embodiment, the lower end of the conductive portion 62 is located at the same height as the upper surface 2b of the semiconductor layer 2. The conductive portion 62 is an example of the second conductive portion in the claims. The conductive portion 62 is made of the same material as the source electrode 12, for example. However, the conductive portion 62 may be made of a different material than the source electrode 12.

[0031] Next, we will describe the details of each region within semiconductor layer 2.

[0032] The drift region 21 functions as the drift region of the MOSFET. The drift region 21 is provided within the gate normal width portion 3 and gate wide portion 4 of the semiconductor layer 2 and is located above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, n - This is a semiconductor region of a certain shape. The n-type impurity concentration in the drift region 21 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 16 cm -3 The following applies:

[0033] The drain region 22 functions as the drain region of the MOSFET. The drain region 22 is located within the gate normal width portion 3 and gate wide portion 4 of the semiconductor layer 2, above the drain electrode 11, and positioned between the drift region 21 and the drain electrode 11. The drain region 22 is in contact with the drain electrode 11 and is in ohmic contact with the drain electrode 11. The drain region 22 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0034] The drift region 21 and the drain region 22 are both examples of the first semiconductor region in the claims. The drain region 22 is optional. In this case, the drift region 21 is provided directly on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 is also optional. In this case, for example, the drain region 22 may also be provided at the location of the drift region 21.

[0035] The base region 23 functions as the base region of the MOSFET. The base region 23 is located within the gate normal width portion 3 and the gate wide portion 4 of the semiconductor layer 2, and is situated above the drift region 21. As shown in Figure 1, the base region 23 extends in the Y-axis direction. As shown in Figures 2A and 2B, the base region 23 has a width w5 in the gate normal width portion 3 and a width w6 in the gate wide portion 4. Widths w5 and w6 are so-called mesa widths. In this embodiment, width w6 is smaller than width w5. Width w6 is, for example, 0.1 μm or less. The base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the base region 23 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 The following applies: Base region 23 is an example of a second semiconductor region in the claims.

[0036] The source region 24 functions as the source region of the MOSFET. The source region 24 is located within the gate normal width portion 3 and gate wide portion 4 of the semiconductor layer 2, and is situated between the base region 23 and the source electrode 12. The source region 24 is in ohmic contact with the conductive portions 61 and 62. The source region 24 extends in the Y-axis direction. The source region 24 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the source region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following is true: Source region 24 is an example of a third semiconductor region in the claims.

[0037] As shown in Figure 2A, the high-concentration region 25 is provided within the base region 23 in the gate normal width portion 3. The high-concentration region 25 is electrically connected to the source electrode 12 via the conductive portion 61. The high-concentration region 25 is, for example, p + This is a semiconductor region of a certain type. That is, the impurity concentration in the high-concentration region 25 is higher than the impurity concentration in the base region 23. The p-type impurity concentration in the high-concentration region 25 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies: The high-concentration region 25 is an example of the fourth semiconductor region in the claims.

[0038] As shown in Figure 1, the high-concentration region 25 does not extend into the wide gate portion 4. That is, the high-concentration region 25 is not provided within the wide gate portion 4. In this embodiment, the high-concentration region 25 is not provided at the boundary between the normal gate portion 3 and the wide gate portion 4. Furthermore, the high-concentration region 25 is provided away from this boundary. In the example in Figure 1, the length l1 of the base region 23 between the high-concentration region 25 and the insulating region 51 in the X-axis direction is equal to the length l2 of the base region 23 between the high-concentration region 25 and the insulating region 51 in the Y-axis direction. Note that length l1 may be different from length l2. Also, the high-concentration region 25 may extend to the boundary between the normal gate portion 3 and the wide gate portion 4.

[0039] As described above, the semiconductor device 1 according to the embodiment includes a drain electrode 11, a source electrode 12, a semiconductor layer 2, a drift region 21 and a drain region 22 of a first conductivity type, a base region 23 of a second conductivity type, a gate electrode 13, and a source region 24 of a first conductivity type. The semiconductor layer 2 is provided between the drain electrode 11 and the source electrode 12. The drift region 21 and the drain region 22 are provided within the semiconductor layer 2 and are located above the drain electrode 11. The base region 23 is provided within the semiconductor layer 2 and is located above the drift region 21. The gate electrode 13 is provided within the base region 23 via an insulating region 51 and extends in the Y-axis direction perpendicular to the Z-axis direction from the drain electrode 11 to the source electrode 12. The source region 24 is provided within the semiconductor layer 2 and is located between the base region 23 and the source electrode 12. The semiconductor layer 2 comprises a gate normal width portion 3 in which the gate electrode 13 extends in the Y-axis direction with a width w1, and a gate wide portion 4 in which the gate electrode 13 is composed of a width w2 greater than the width w1. The length of the gate wide portion 4 in the Y-axis direction is smaller than the length of the gate normal width portion 3 in the Y-axis direction.

[0040] In this embodiment, in the wide gate portion 4, the gate electrodes 13 flanking the base region 23 are closer together compared to the normal gate width portion 3. Therefore, an inversion layer is more easily formed in the base region 23 in the wide gate portion 4. As a result, the threshold voltage of the wide gate portion 4 is lower than the threshold voltage of the normal gate width portion 3. For example, when a drive voltage is applied to the gate electrodes 13, the channels in the wide gate portion 4 turn on first when the voltage is low, while the channels in the normal gate width portion 3 remain off. Subsequently, as the voltage increases, the channels in the normal gate width portion 3 also turn on. This reduces the transconductance of the semiconductor device 1, so that a safe operating region can be secured even if the on-resistance is reduced. For example, even when the cell pitch of the semiconductor device 1 is miniaturized or the channel length is shortened to reduce the on-resistance, a safe operating region can be secured. Thus, according to this embodiment, the trade-off between on-resistance and the safe operating region can be improved.

[0041] Furthermore, in this embodiment, the width w6 of the base region 23 in the wide gate portion 4 is smaller than the width w5 of the base region 23 in the normal gate portion 3. As a result, the channel mobility in the base region 23 of the wide gate portion 4 is improved, and the on-resistance of the semiconductor device 1 can be reduced compared to the case where the wide gate portion 4 is not provided.

[0042] Furthermore, in this embodiment, the gate electrode 13 has a protrusion 13a that protrudes into the base region 23. As shown in Figure 1, in the base region 23 of the gate normal width portion 3, the region near the protrusion 13a (gate corner region) is approached by the gate electrode 13 from two directions (X-axis direction and Y-axis direction), and the gate electric field is applied from two directions. As a result, the inversion layer is more easily formed in this gate corner region. This makes it possible to further reduce the transconductance of the semiconductor device 1.

[0043] Furthermore, according to this embodiment, the on-resistance and transconductance of the semiconductor device 1 can be controlled by increasing or decreasing the number of protrusions 13a, thereby improving the design flexibility of the semiconductor device 1.

[0044] Furthermore, the semiconductor device 1 according to this embodiment further includes a high-density region 25 provided within the base region 23 in the normal gate width portion 3 and electrically connected to the source electrode 12 via a conductive portion 61. On the other hand, the high-density region 25 does not extend into the wide gate portion 4. This makes it possible to improve the avalanche withstand capability of the semiconductor device 1 while maintaining the channel mobility in the wide gate portion 4.

[0045] Furthermore, in this embodiment, the high-concentration region 25 is provided away from the boundary between the gate normal-width portion 3 and the gate wide portion 4. This promotes the formation of an inversion layer near the boundary, further reducing the transconductance of the semiconductor device 1. The high-concentration region 25 may also be provided up to the boundary between the gate normal-width portion 3 and the gate wide portion 4. In this case, the avalanche tolerance of the semiconductor device 1 can be further improved.

[0046] Furthermore, the semiconductor device 1 according to this embodiment further includes a conductive portion 62 provided in the gate wide portion 4 for electrically connecting the source region 24 and the source electrode 12. This ensures a contact area with the source region 24 even in the gate wide portion 4, further reducing the on-resistance of the semiconductor device 1. In addition, the lower end of the conductive portion 62 is located above the upper end of the base region 23. As a result, the base region 23 is not eroded by the conductive portion 62 in the gate wide portion 4, thereby suppressing an increase in the threshold voltage of the gate wide portion 4.

[0047] Furthermore, the semiconductor device 1 according to this embodiment further includes an FP electrode 14 provided within the semiconductor layer 2 via an insulating region 53 and electrically connected to the source electrode 12. As a result, when the MOSFET is in the off state, a depletion layer extends from the FP electrode 14 to the surrounding drift region 21 due to the voltage applied between the drain electrode 11 and the source electrode 12. This depletion layer connects with the depletion layer of the adjacent FP electrode 14, thereby improving the breakdown voltage of the semiconductor device 1.

[0048] In this embodiment, the width w6 of the base region 23 in the gate wide portion 4 may be 0.1 μm or less. This allows for a further reduction in the threshold voltage of the gate wide portion 4. This will be explained in detail with reference to Figure 3. Figure 3 is a graph of simulation results showing the relationship between the mesa width (w6) and the threshold voltage (Vth) in the semiconductor device 1 according to the embodiment.

[0049] As shown in Figure 3, when the width w6 is 0.1 μm or less, the threshold voltage decreases significantly compared to when the width w6 is greater than 0.1 μm. Therefore, by setting the width w6 to 0.1 μm or less, the threshold voltage of the wide gate portion 4 can be significantly reduced. Furthermore, since the threshold voltage of the wide gate portion 4 can be controlled by adjusting the width w6, the design flexibility of the semiconductor device 1 can be improved.

[0050] <Manufacturing method for semiconductor device 1> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to Figures 4 to 9B. Figures 4 and 5 are cross-sectional views of the gate normal width portion 3 and the gate wide portion 4 to illustrate an example of the manufacturing process of the semiconductor device 1 according to this embodiment. Figures 6A, 7A, 8A, and 9A are cross-sectional views of the gate normal width portion 3 to illustrate an example of the manufacturing process of the semiconductor device 1 according to this embodiment. Figures 6B, 7B, 8B, and 9B are cross-sectional views of the gate wide portion 4 to illustrate an example of the manufacturing process of the semiconductor device 1 according to this embodiment.

[0051] First, as shown in Figure 4, a semiconductor layer is prepared having a lower surface 2a and an upper surface 2b opposite to the lower surface 2a. The semiconductor layer is, for example, an n-type semiconductor substrate. A drift region 21 is provided within the semiconductor layer. In addition, a trench T1 is formed on the upper surface 2b of the semiconductor layer by reactive ion etching (RIE) or the like.

[0052] Next, as shown in Figure 5, an FP electrode 14 and an insulating region 53 are formed in the trench T1. More specifically, first, an insulating region is formed covering the inner wall of the trench T1 and the upper surface 2b of the semiconductor layer by thermal oxidation or the like. Then, a conductive material such as polysilicon is deposited in the insulating region by chemical vapor deposition (CVD) or the like to form the FP electrode 14. After that, the portion of the insulating region located above the FP electrode 14 is removed. Then, silicon oxide or the like is deposited on the upper surface of the FP electrode 14 by CVD or the like to form an insulating region 53a (buried film). In the following explanation, the insulating region 53a is considered to be part of the insulating region 53.

[0053] Next, as shown in Figures 6A and 6B, a resist 70 is formed in the gate normal width portion 3 to cover the upper surface 2b of the semiconductor layer and fill the trench T1. Note that the resist 70 is not formed in the gate wide portion 4. Subsequently, the upper sidewall portion of the semiconductor layer in the gate wide portion 4 above the trench T1 is removed by chemical dry etching (CDE) or the like. As a result, the trench T1 in the gate wide portion 4 is widened, and a trench T2 wider than trench T1 is formed. After that, the resist 70 in the gate normal width portion 3 is removed.

[0054] Next, as shown in Figures 7A and 7B, the gate electrode 13, base region 23, and insulating region 51 are formed. More specifically, first, insulating regions are formed by thermal oxidation or the like to cover the side walls of trench T1 in the normal-width gate portion 3, the side walls of trench T2 in the wide-width gate portion 4, and the upper surface 2b of the semiconductor layer in both the normal-width gate portion 3 and the wide-width gate portion 4. Then, conductive material such as polysilicon is deposited within the insulating region by CVD or the like to form the gate electrode 13. The width of the gate electrode 13 in the wide-width gate portion 4 is greater than the width of the gate electrode 13 in the normal-width gate portion 3. After that, p-type impurities are ion-implanted into the upper surface 2b of the semiconductor layer to form the base region 23. Then, an insulating region 51a is formed on the upper surface of the gate electrode 13. In the following explanation, the insulating region 51a is considered to be part of the insulating region 51. Also, the portion of the insulating region formed on the upper surface 2b of the semiconductor layer (insulating region 51b) is considered to be part of the insulating region 52 after its formation, as described later.

[0055] Next, as shown in Figures 8A and 8B, a source region 24 and an insulating region 52 are formed. More specifically, first, n-type impurities are ion-implanted into the upper surface 2b of the semiconductor layer to form the source region 24. Then, silicon oxide or the like is deposited on the upper surface 2b of the semiconductor layer by CVD or the like to form the insulating region 52.

[0056] Next, as shown in Figures 9A and 9B, a high-concentration region 25, opening H1, and opening H2 are formed. More specifically, first, an opening reaching the upper end of the source region 24 is formed in the normal-width gate portion 3 and the wide-width gate portion 4 using RIE or the like. This forms the upper part of opening H1 in the normal-width gate portion 3 and opening H2 in the wide-width gate portion 4. Subsequently, a resist is formed in the wide-width gate portion 4 that covers the upper surface 2b of the semiconductor layer and fills at least a portion of opening H2. This resist is not formed in the normal-width gate portion 3. Then, a trench is formed in the normal-width gate portion 3 that penetrates the source region 24 and reaches the base region 23 using silicon RIE or the like. This forms the lower part of opening H1 in the normal-width gate portion 3. Then, p-type impurities are ion-implanted into the upper surface 2b of the semiconductor layer to form a high-concentration region 25 at the bottom of opening H1. Finally, the resist formed in the wide-width gate portion 4 is removed.

[0057] Subsequently, although not shown in the diagram, n-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer to form a drain region 22. Then, conductive portions 61, 62, and a source electrode 12 are formed on the upper surface 2b of the semiconductor layer, and a drain electrode 11 is formed on the lower surface 2a of the conductive layer. The opening H1 of conductive portion 61 is filled, and the opening H2 of conductive portion 62 is filled.

[0058] The semiconductor device 1 is manufactured through the above process.

[0059] According to the manufacturing method of this embodiment, the FP electrode 14 can be formed simultaneously in the gate normal width portion 3 and the gate wide portion 4. In this case, the width w3 of the FP electrode 14 in the gate normal width portion 3 is equal to the width w4 of the FP electrode 14 in the gate wide portion 4.

[0060] Furthermore, according to the manufacturing method of this embodiment, the insulating region 51 covering the side wall of the trench T1 in the normal width portion 3 of the gate and the insulating region 51 covering the side wall of the trench T2 in the wide portion 4 of the gate can be formed at the same time. In this case, the distance d1 between the gate electrode 13 and the base region 23 along the X-axis direction in the normal width portion 3 is equal to the distance d2 between the gate electrode 13 and the base region 23 along the X-axis direction in the wide portion 4 of the gate.

[0061] Below, we will describe some modifications of the above-described embodiment, focusing on the differences from the embodiment. Each of the modifications described below, like the embodiment, can improve the trade-off between the on-resistance and the safe operating area of ​​the semiconductor device.

[0062] (Variation 1) Referring to Figure 10, a semiconductor device 1A according to Modification 1 of the embodiment will be described. Figure 10 is a plan view of the semiconductor device 1A according to Modification 1.

[0063] As shown in Figure 10, in this modified example, the gate normal width portion 3 and the gate wide portion 4 are alternately provided along the X-axis direction. In the example in Figure 10, the gate wide portion 4 is arranged in a staggered pattern within the semiconductor layer 2. More specifically, the Y-axis center of the gate normal width portion 3 in one gate electrode 13 and the Y-axis center of the gate wide portion 4 in the adjacent gate electrode 13 are aligned along the X-axis direction. In other words, the position of the Y-axis center of the gate wide portion 4 is shifted in the Y-axis direction by half the Y-axis length of the gate normal width portion 3 between adjacent gate electrodes 13. However, it is not limited to this, and the position of the Y-axis center of the gate wide portion 4 may be shifted in the Y-axis direction by, for example, one-third the Y-axis length of the gate normal width portion 3 between adjacent gate electrodes 13.

[0064] According to this modified example, since the gate-wide portion 4 with a low threshold voltage is more evenly distributed within the semiconductor device 1A, the current that starts to flow through the semiconductor device 1A can be made more uniform when, for example, a drive voltage is applied to the gate electrode 13.

[0065] (Modification 2) Referring to Figure 11, a semiconductor device 1B according to a modified example 2 of the embodiment will be described. Figure 11 is a plan view of the semiconductor device 1B according to the modified example 2.

[0066] As shown in Figure 11, in this modified example, the gate electrode 13 has a protrusion 13b instead of a protrusion 13a. The protrusion 13b has a rounded shape at its tip and base. Depending on the manufacturing method of the semiconductor device 1B, the protrusion 13b may have this shape.

[0067] This modified example can improve the degree of freedom in the manufacturing process of semiconductor device 1B.

[0068] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0069] 1 Semiconductor device 11 Drain electrode 12 Source electrodes 13 gates 14 FP electrode 2 Semiconductor layers 21 Drift Region 22 Drain region 23 Base area 24 Source Area 25 High concentration area 3 Gate normal width section 4. Wide section of gate 51, 52, 53 Insulated areas 61,62 Conductive parts

Claims

1. First electrode and, The second electrode and A semiconductor layer provided between the first electrode and the second electrode, A first semiconductor region of a first conductivity type is provided within the semiconductor layer and located above the first electrode, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and located above the first semiconductor region, A third electrode is provided within the second semiconductor region via a first insulating region, and extends in a second direction perpendicular to the first direction toward the second electrode, A third semiconductor region of a first conductivity type is provided within the semiconductor layer and located between the second semiconductor region and the second electrode, A semiconductor device equipped with, The semiconductor layer comprises a first portion in which the third electrode extends in the second direction with a first width, and a second portion in which the third electrode is configured with a second width greater than the first width. The length of the second portion in the second direction is smaller than the length of the first portion in the second direction. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein in the second part, the third electrode has a protrusion that protrudes into the second semiconductor region.

3. The first portion further comprises a fourth semiconductor region provided within the second semiconductor region, electrically connected to the second electrode via a first conductive portion, and having a higher impurity concentration than the second semiconductor region. The semiconductor device according to claim 1, wherein the fourth semiconductor region does not extend to the second portion.

4. The semiconductor device according to claim 3, wherein the fourth semiconductor region is provided away from the boundary between the first and second portions.

5. The second portion further comprises a second conductive portion provided for electrically connecting the third semiconductor region and the second electrode, The semiconductor device according to claim 3, wherein the lower end of the second conductive portion is located above the upper end of the second semiconductor region.

6. The semiconductor layer is provided via a second insulating region and further comprises a fourth electrode electrically connected to the second electrode, The semiconductor device according to claim 1, wherein the width of the fourth electrode in the first portion is equal to the width of the fourth electrode in the second portion.

7. The semiconductor device according to claim 1, wherein the width of the second semiconductor region in the second portion is smaller than the width of the second semiconductor region in the first portion.

8. The semiconductor device according to claim 7, wherein the width of the second semiconductor region in the second portion is 0.1 μm or less.

9. The semiconductor device according to claim 1, wherein the distance between the third electrode and the second semiconductor region in the first portion along a third direction perpendicular to the first and second directions is equal to the distance between the third electrode and the second semiconductor region in the second portion along the third direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein the center of the second portion in the second direction between adjacent third electrodes is along a third direction perpendicular to the first and second directions.

11. The semiconductor device according to any one of claims 1 to 9, wherein the first portion and the second portion are alternately provided along a third direction perpendicular to the first and second directions.

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