Semiconductor equipment

Abstract

To provide a semiconductor device with a structure that can be manufactured using a simple manufacturing process. [Solution] A semiconductor device provided on a semiconductor substrate having a first main surface and a second main surface and containing a bulk dopant, wherein the semiconductor substrate comprises a first low-concentration region of a first conductivity type having a carrier concentration lower than the bulk concentration which is the concentration of the bulk dopant, and a first high-concentration region of a first conductivity type having a first carrier concentration peak at a position in contact with the first low-concentration region on the first main surface side, and having a carrier concentration higher than the bulk concentration, and no hydrogen concentration peak is provided at a position overlapping with the first carrier concentration peak.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device in which the carrier lifetime is adjusted by irradiating with a charged particle beam such as helium is known (see, for example, Patent Document 1). Patent Document 1 International Publication No. 2020 / 100995

Summary of the Invention

Problems to be Solved by the Invention

[0003] In a semiconductor device, it is preferable to have a structure that can improve electrical characteristics or simplify the manufacturing process.

Means for Solving the Problems

[0008] In any of the above semiconductor devices, the width of the helium concentration peak in the depth direction may be smaller than the width of the first low concentration region in the depth direction.

[0009] Any of the above semiconductor devices may include a second high-concentration region of a first conductivity type having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration.

[0010] In any of the above semiconductor devices, the hydrogen concentration peak does not need to be located at a position that overlaps with the second carrier concentration peak.

[0011] In any of the above semiconductor devices, the second carrier concentration peak may be the concentration peak of a hydrogen-related donor.

[0012] In any of the above semiconductor devices, the first carrier concentration peak and the second carrier concentration peak may have a higher concentration closer to the hydrogen concentration peak than the other.

[0013] In any of the above semiconductor devices, the carrier concentration peak closer to the first main surface or the second main surface may have a higher concentration than the other of the first and second carrier concentration peaks.

[0014] In any of the above semiconductor devices, the value obtained by dividing the higher of the concentrations of the first carrier concentration peak and the second carrier concentration peak by the lower concentration may be 1.1 or less.

[0015] Any of the above semiconductor devices may have a second high-concentration region of a first conductivity type, having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration. In any of the above semiconductor devices, the first low-concentration region may have a helium concentration peak in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, the concentration of the first carrier concentration peak and the concentration of the second carrier concentration peak may be lower in the one closer to the helium concentration peak than in the other.

[0016] Any of the above semiconductor devices may have a second high-concentration region of a first conductivity type, having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration. In any of the above semiconductor devices, the first low-concentration region may have a helium concentration peak in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, the first carrier concentration peak and the second carrier concentration peak may each have an outer tail on the side opposite to the helium concentration peak. In any of the above semiconductor devices, the outer tail of the first carrier concentration peak and the second carrier concentration peak that is closer to the helium concentration peak may be steeper than the outer tail of the other outer tail.

[0017] Any of the above semiconductor devices may include a second low-concentration region having a carrier concentration valley at a position in contact with the second high-concentration region on the second main surface side.

[0018] Any of the above semiconductor devices may have the hydrogen concentration peak on the second main surface side of the second carrier concentration peak.

[0019] In any of the above semiconductor devices, the distance between the hydrogen concentration peak and the second carrier concentration peak in the depth direction of the semiconductor substrate may be 1 / 4 or more of the thickness of the semiconductor substrate in the depth direction.

[0020] In any of the above semiconductor devices, the hydrogen concentration of the hydrogen concentration peak is 1 × 10 16 / cm 3 That's all.

[0021] Any of the above semiconductor devices may have a constant lifetime region between the second carrier concentration peak and the hydrogen concentration peak, in which the carrier lifetime is constant in the depth direction of the semiconductor substrate.

[0022] Any of the above semiconductor devices may include a hydrogen concentration flat region between the first carrier concentration peak and the hydrogen concentration peak, where the hydrogen concentration is flat in the depth direction of the semiconductor substrate.

[0023] Any of the above semiconductor devices may include a drift region of a first conductivity type provided on the semiconductor substrate. Any of the above semiconductor devices may include a base region of a second conductivity type provided between the drift region and the first main surface. Any of the above semiconductor devices may include a trench portion provided from the first main surface down to below the base region. Any of the above semiconductor devices may include a storage region provided between the drift region and the base region, having a carrier concentration higher than that of the drift region. Any of the above semiconductor devices may include a lifetime adjustment region provided below the trench portion, where the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate. Any of the above semiconductor devices may have the first high-concentration region and the storage region overlapping. Any of the above semiconductor devices may have the first low-concentration region and the lifetime adjustment region overlapping.

[0024] Any of the above semiconductor devices may include a buffer region of a first conductivity type, provided between the drift region and the lower surface, and having a carrier concentration higher than that of the drift region. In any of the above semiconductor devices, the hydrogen concentration peak may be located in the buffer region.

[0025] Any of the above semiconductor devices may include a drift region of a first conductivity type provided on the semiconductor substrate. Any of the above semiconductor devices may include a base region of a second conductivity type provided between the drift region and the first main surface. Any of the above semiconductor devices may include a trench portion provided from the first main surface down to below the base region. Any of the above semiconductor devices may include a lifetime adjustment region provided below the trench portion, where the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate. Any of the above semiconductor devices may have the first low-concentration region and the lifetime adjustment region overlapping. Any of the above semiconductor devices may have the second high-concentration region and the drift region overlapping.

[0026] The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0027] [Figure 1] This is a cross-sectional view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] Figure 1 shows an example of the distribution of carrier concentration, helium chemical concentration, hydrogen chemical concentration, and oxygen chemical concentration along the AA line. [Figure 3] This is a cross-sectional view showing another example of the semiconductor device 100. [Figure 4] This figure shows an example of the carrier concentration distribution along the BB line in Figure 3. [Figure 5] This is a cross-sectional view showing another example of the semiconductor device 100. [Figure 6] This figure shows an example of the carrier concentration distribution along the CC line in Figure 5. [Figure 7] This is a cross-sectional view showing another example of the semiconductor device 100. [Figure 8A] Figure 7 shows an example of the distribution of carrier concentration, carrier mobility or carrier lifetime, helium chemical concentration, defect density, and hydrogen chemical concentration along the DD line. [Figure 8B] Figure 8A shows the relationship between L (μm) and Np / L (atoms / cm4). [Figure 9] This figure shows examples of carrier concentration distributions in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. [Figure 10] This figure shows examples of carrier concentration distributions in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. [Figure 11] This figure shows examples of carrier concentration distributions in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. [Figure 12] This is a diagram illustrating a more specific embodiment of the semiconductor device 100. [Figure 13] This is a magnified view of region A in Figure 12. [Figure 14] Figure 13 shows an example of an ee cross-section. [Modes for carrying out the invention]

[0028] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0029] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0030] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0031] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0032] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0033] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0034] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0035] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0036] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, where a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as an electron-supplying donor. A hydrogen-related donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, interstitial Si-H, where interstitial silicon (Si-i) and hydrogen are bonded in a silicon semiconductor, and CiOi-H, where interstitial carbon (Ci) and interstitial oxygen (Oi) and hydrogen are bonded, also function as electron-supplying donors. In this specification, VOH defects, CiOi-H, or interstitial Si-H may be referred to as hydrogen-related donors.

[0037] In this specification, the semiconductor substrate has N-type bulk donors uniformly distributed throughout. The bulk donors are donors due to dopants that were contained substantially uniformly in the ingot when the ingot from which the semiconductor substrate is derived was manufactured. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any one of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . A higher oxygen concentration tends to more easily generate hydrogen-related donors. The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Incidentally, each concentration in the present invention may be a value at room temperature. The value at room temperature may use, as an example, the value at 300 K (Kelvin) (about 26.9 °C).

[0038] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0039] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0040] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0041] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0042] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0043] Figure 1 is a cross-sectional view showing an example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 has a first main surface and a second main surface and is provided on a semiconductor substrate 10 containing a bulk dopant. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a substrate formed of another semiconductor material. The first main surface and the second main surface are the two surfaces of the semiconductor substrate 10 with the largest area. The first main surface and the second main surface are surfaces facing each other. In the example of Figure 1, the upper surface 21 of the semiconductor substrate 10 is the first main surface and the lower surface 23 is the second main surface. However, the upper surface 21 may be the second main surface and the lower surface 23 may be the first main surface.

[0044] In this specification, the two axes parallel to the upper surface 21 of the semiconductor substrate 10 are defined as the X-axis and Y-axis, and the axis perpendicular to the upper surface 21 is defined as the Z-axis. The X-axis, Y-axis, and Z-axis are orthogonal to each other. The direction parallel to the Z-axis is sometimes referred to as the depth direction.

[0045] The bulk dopant is an N-type or P-type dopant distributed throughout the semiconductor substrate 10. The bulk dopant may be a dopant that is substantially uniformly contained within the ingot during the manufacturing of the ingot that forms the basis of the semiconductor substrate 10. The bulk dopant in this specification is, for example, a bulk donor such as phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The semiconductor substrate 10 may be an N-type substrate.

[0046] The semiconductor device 100 includes a first low-concentration region 211 and a first high-concentration region 231 in the semiconductor substrate 10. The first low-concentration region 211 is a region of a first conductivity type having a carrier concentration lower than the bulk concentration, which is the concentration of the bulk dopant. In this specification, N-type is referred to as the first conductivity type and P-type as the second conductivity type. The concentration of the bulk dopant may be the average value of the bulk dopant concentration in the entire semiconductor substrate 10. If an element of the same type as the bulk dopant is locally injected into the semiconductor substrate 10, the average value of the bulk dopant concentration in the regions other than the locally injected region may be used as the bulk dopant concentration. For example, if the concentration of an element of the same type as the bulk dopant shows a peak, the average value of the bulk dopant may be calculated by excluding that peak portion. In another example, the minimum value of the bulk dopant concentration in the semiconductor substrate 10 may be used as the bulk dopant concentration.

[0047] The first low-concentration region 211 can be formed by irradiating the inside of the semiconductor substrate 10 with charged particles such as helium ions. The charged particles such as helium ions cause disturbances in the crystal structure, such as lattice defects, inside the semiconductor substrate 10, which reduces carrier mobility and carrier lifetime. As a result, the carrier concentration measured by methods such as SR decreases.

[0048] The first high-concentration region 231 is located in contact with the first low-concentration region 211 on the upper surface 21 side, and is an N-type region in which the carrier concentration is higher than the bulk concentration. The first high-concentration region 231 and the first low-concentration region 211 may be located on the upper surface 21 side or on the lower surface 23 side of the semiconductor substrate 10.

[0049] The first high-concentration region 231 may contain hydrogen-related donors. As described above, hydrogen-related donors are one or more of the following: VOH defects, CiOi-H, or interstitial Si-H. By irradiating the vicinity of the hydrogen-containing region with charged particles, or by having charged particles pass through the hydrogen-containing region, the aforementioned disorder in the crystal structure can be caused, thereby generating hydrogen-related donors.

[0050] Figure 2 shows an example of the distribution of carrier concentration, helium chemical concentration, hydrogen chemical concentration, and oxygen chemical concentration along line AA in Figure 1. Line AA is a line parallel to the Z axis that passes through a portion of the first high-concentration region 231 and the first low-concentration region 211. In each example herein, helium ions are used as an example of charged particles, but other charged particles may be used. In this case, the helium chemical concentration herein can be replaced with the concentration of other charged particles.

[0051] As described above, the first low-concentration region 211 is the bulk concentration N D This is a region with a lower carrier concentration than the first low-concentration region 211. The first low-concentration region 211 has a first valley 221 where the carrier concentration shows a minimum value V1. The minimum value V1 is the bulk concentration N DIt may be 90% or less, 70% or less, 50% or less, or 10% or less. The concentration trough may have a base portion from a position where the carrier concentration shows a minimum value toward the upper surface 21 in which the carrier concentration monotonically increases to a predetermined concentration (e.g., bulk concentration), and a base portion toward the lower surface 23 in which the carrier concentration monotonically increases to a predetermined concentration (e.g., bulk concentration). In this specification, monotonically increasing concentration toward a predetermined direction means that as you move toward the predetermined direction, the concentration increases or is maintained and there are no regions where the concentration decreases. Also, monotonically decreasing concentration toward a predetermined direction means that as you move toward the predetermined direction, the concentration decreases or is maintained and there are no regions where the concentration increases.

[0052] As described above, the first high-concentration region 231 is the bulk concentration N D This is a region with a higher carrier concentration than the first high-concentration region 231. The first high-concentration region 231 has a first carrier concentration peak 241 at a position where it is in contact with the first low-concentration region 211 on the upper surface 21 side. At the first carrier concentration peak 241, the carrier concentration shows a maximum value P1. The maximum value P1 is equal to the bulk concentration N D It may be 1.1 times or more, 1.5 times or more, 2 times or more, or 10 times or more. The concentration peak may have a base portion from the position where the carrier concentration shows a maximum value toward the upper surface 21 where the carrier concentration monotonically decreases to a predetermined concentration (e.g., bulk concentration), and a base portion toward the lower surface 23 where the carrier concentration monotonically decreases to a predetermined concentration (e.g., bulk concentration).

[0053] The phrase "the first carrier concentration peak 241 touching the first low-concentration region 211" may mean that the tail of the first carrier concentration peak 241 and the tail of the first trough 221 are continuous. Alternatively, the phrase "the first carrier concentration peak 241 touching the first low-concentration region 211" may mean that there is no region with a constant carrier concentration between the first carrier concentration peak 241 and the first low-concentration region 211. Alternatively, the phrase "the first carrier concentration peak 241 touching the first low-concentration region 211" may mean that the carrier concentration continues to increase from the position where the carrier concentration shows a minimum value V1 to the position where the carrier concentration shows a maximum value P1.

[0054] In this example, the first low-concentration region 211 has a helium concentration peak 261 where the helium chemical concentration shows a maximum value of PH. In this example, helium ions are implanted from the lower surface 23 of the semiconductor substrate 10 to position Z1, which is included in the first low-concentration region 211. The helium ions may also be implanted from the upper surface 21 of the semiconductor substrate 10. In the vicinity of the helium ion implantation position Z1, many disturbances in the crystal structure, such as crystal defects, occur. As a result, the carrier concentration decreases and the first low-concentration region 211 is formed.

[0055] In this example, the hydrogen chemical concentration of the semiconductor substrate 10 decreases monotonically as you move away from the top surface 21. For example, when the semiconductor substrate 10 is annealed in a hydrogen-containing atmosphere, hydrogen diffuses from the top surface 21 of the semiconductor substrate 10 towards the interior of the semiconductor substrate 10. Alternatively, hydrogen contained in the interlayer insulating film formed on the top surface 21 of the semiconductor substrate 10 diffuses from the top surface 21 towards the interior of the semiconductor substrate 10. In this case, as shown in Figure 2, the hydrogen chemical concentration decreases as you move away from the top surface 21.

[0056] The first high-concentration region 231 includes hydrogen-related donors formed by hydrogen present in the semiconductor substrate 10. Hydrogen-related donors are formed by hydrogen and disturbances in the crystal structure caused by the implantation of charged particles such as helium ions. For example, as shown by the dashed line 263, hydrogen-related donors are also formed in the first low-concentration region 211 near the helium ion implantation site Z1. However, since the density of crystal defects etc. is high in the first low-concentration region 211, the carrier concentration is the bulk concentration N D It is lower than that.

[0057] On the other hand, in the first high-concentration region 231, which is far from the helium ion implantation site Z1, the density of crystal defects is relatively low, and the hydrogen concentration is relatively high. Therefore, the concentration of hydrogen-related donors becomes relatively high compared to the remaining crystal defects, and the carrier concentration becomes the bulk concentration N D It is higher than [previous value]. In this example, the first carrier concentration peak 241 is the peak for hydrogen-related donors. When a carrier concentration peaks in a region where hydrogen is present and there are no peaks for N-type dopants other than hydrogen, that carrier concentration peak can be considered the peak for hydrogen-related donors.

[0058] In this example, the first carrier concentration peak 241 is formed without implanting hydrogen ions into the first high-concentration region 231. Therefore, no hydrogen concentration peak is provided at a position that overlaps with the first carrier concentration peak 241. In this specification, "concentration peaks do not overlap" may mean that the position of the peak of the other peak is not included in the depth range of the full width at half maximum of one peak. Alternatively, it may mean that the ranges of the full widths at half maximum of the two peaks do not overlap at all. The semiconductor substrate 10 does not need to have any hydrogen concentration peaks in the depth direction. In other examples of the semiconductor substrate 10, a hydrogen concentration peak may be provided at a position that does not overlap with the first carrier concentration peak 241.

[0059] In this example, since it is not necessary to implant hydrogen ions into the first high-concentration region 231, both the first low-concentration region 211 and the first high-concentration region 231 can be formed by a simple manufacturing process. The first low-concentration region 211 can be used, for example, as a lifetime adjustment region in a semiconductor device 100 to reduce the carrier lifetime. For example, if the semiconductor device 100 has transistors such as IGBTs (Insulated Gate Bipolar Transistors) and diodes, a lifetime adjustment region with reduced carrier lifetime may be formed to shorten the reverse recovery time of the diode. A lifetime adjustment region can also be formed in transistors adjacent to diodes.

[0060] The first high-concentration region 231 can be used as a storage region adjacent to the lifetime adjustment region. For example, in transistors such as IGBTs, an N+ type storage region may be formed below the P-type base layer to promote carrier accumulation and lower the on-resistance. In this case, the lifetime adjustment region and the storage region can be formed using a simple manufacturing process.

[0061] However, the applications of the first low-concentration region 211 and the first high-concentration region 231 are not limited to combinations of lifetime adjustment region and accumulation region. D Lower regions and bulk concentration N D If the structure is arranged so that higher concentration regions are adjacent to each other, then the first low-concentration region 211 and the first high-concentration region 231 can be used.

[0062] The oxygen chemical concentration may decrease monotonically as you move away from the top surface 21. However, annealing the semiconductor substrate 10 may cause oxygen near the top surface 21 of the semiconductor substrate 10 to be released outside the semiconductor substrate 10. The oxygen chemical concentration may have an oxygen concentration peak 262 near the top surface 21 of the semiconductor substrate 10, and may decrease monotonically at positions deeper than the oxygen concentration peak 262. The oxygen concentration peak 262 may be located on the top surface 21 side of the first low concentration region 211. The oxygen concentration peak 262 may be located in the first high concentration region 231. The oxygen concentration peak 262 may be located in a position that overlaps with the first carrier concentration peak 241. The higher the oxygen chemical concentration, the more the formation of hydrogen-related donors is promoted, making it easier to form the first carrier concentration peak 241.

[0063] Let W1 be the width in the depth direction of the helium concentration peak 261, and W2 be the width in the depth direction of the first low concentration region 211. Width W1 may be the width of the region in the helium concentration peak 261 where the helium chemical concentration is more than half of the maximum value PH (i.e., the full width at half maximum). In this case, width W2 may be the width of the region in the first low concentration region 211 where the carrier concentration is more than twice the minimum value V1. Alternatively, width W2 may be the width of the region in the first low concentration region 211 where the carrier concentration is the bulk concentration N D The width of the region may be less than half of the value. The width W1 may be the width of the region where the helium chemical concentration at the helium concentration peak 261 is 10% or more of the maximum value PH. In this case, the width W2 may be the width of the region where the carrier concentration at the first low concentration region 211 is 9 times or less of the minimum value V1, and the bulk concentration N D The width of the area may be less than 90% of the total area.

[0064] The width W1 may be smaller than the width W2. The width W1 may be less than half of the width W2, or less than one-quarter. By reducing the width W1, the position of the region forming the first low-concentration region 211 can be controlled with high precision. In other examples, the width W1 may be larger than the width W2. The width W1 varies depending on the type of device used to accelerate the helium ions. For example, by using a cyclotron-type accelerator, the width W1 can be made larger than the width W2. In this case, crystal defects can be formed over a wide area.

[0065] Bulk Plain N D And the difference between the maximum value P1 of the first carrier concentration peak 241 (P1-N) D ) is bulk concentration N D The difference between this value and the local minimum V1 of the first valley 221 (N D It can be smaller than -V1). Difference (P1-N D ) is the difference (N D -V1) may be less than half, or less than 1 / 4. D ) is the difference (N D -V1) may be greater than -V1.

[0066] In the depth direction, the width of the first high-concentration region 231 may be smaller than the width of the first low-concentration region 211. The width of the first high-concentration region 231 may be half or less of the width of the first low-concentration region 211, and may also be one-quarter or less.

[0067] Figure 3 is a cross-sectional view showing another example of the semiconductor device 100. In this example, the first high-concentration region 231 is provided in contact with the first low-concentration region 211 on the lower surface 23 side of the semiconductor substrate 10. The other structures are the same as those described in Figures 1 and 2. In this example, the lower surface 23 is the first main surface, and the upper surface 21 is the second main surface. The first high-concentration region 231 and the first low-concentration region 211 are provided on the upper surface 21 side of the semiconductor substrate 10.

[0068] Figure 4 shows an example of the carrier concentration distribution along the BB line in Figure 3. The BB line is a line parallel to the Z axis that passes through the first high-concentration region 231 and the first low-concentration region 211.

[0069] The carrier concentration distribution in this example may have a shape that is the inverse of the carrier concentration distribution in the example shown in Figure 2 in the depth direction. For example, the first carrier concentration peak 241 is in contact with the first low-concentration region 211 on the lower surface 23 side.

[0070] The distributions of helium, hydrogen, and oxygen chemical concentrations may be the same as or different from the example in Figure 2. Helium ions may be injected from the top surface 21 or from the bottom surface 23.

[0071] In this example, the hydrogen concentration in the first high-concentration region 231 may be higher than the hydrogen concentration in the first low-concentration region 211. For example, by implanting and diffusing hydrogen ions on the lower surface 23 side of the first high-concentration region 231, the hydrogen concentration in the first high-concentration region 231 becomes higher than the hydrogen concentration in the first low-concentration region 211. The semiconductor substrate 10 may have a concentration peak of hydrogen concentration on the lower surface 23 side of the first high-concentration region 231. With the configuration in this example, it is possible to suppress the expansion of the space charge region or depletion layer of, for example, IGBTs or diodes, and improve switching characteristics.

[0072] Figure 5 is a cross-sectional view showing another example of the semiconductor device 100. The semiconductor device 100 in this example further comprises a second high-concentration region 232 compared to the example described in Figures 1 and 2. The semiconductor device 100 may further comprise a second low-concentration region 212. The semiconductor device 100 does not necessarily have to have a second low-concentration region 212. The other structures are the same as those described in Figures 1 and 2.

[0073] The second high-concentration region 232 is located in a position where it is in contact with the first low-concentration region 211 on the lower surface 23 side, and the carrier concentration is the bulk concentration N D This is an N-type region with a higher concentration than the first. The second high-concentration region 232 may contain hydrogen-related donors.

[0074] The second low-concentration region 212 is an N-shaped region located at a position where it is in contact with the second high-concentration region 232 on the lower surface 23 side. The carrier concentration in the second low-concentration region 212 is the bulk concentration N D It can be even lower.

[0075] Figure 6 shows an example of the carrier concentration distribution along the CC line in Figure 5. The CC line is a line parallel to the Z-axis that passes through a part of the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. The distributions of helium chemical concentration, hydrogen chemical concentration, and oxygen chemical concentration may be the same as or different from the example in Figure 2.

[0076] The carrier concentration distribution in the first low-concentration region 211 and the first high-concentration region 231 is the same as in the example in Figure 2. As mentioned above, the second high-concentration region 232 is the bulk concentration N D This is a region with a higher carrier concentration than the first low-concentration region 211. The second high-concentration region 232 has a second carrier concentration peak 242 at a position where it is in contact with the first low-concentration region 211 on the lower surface 23 side. At the second carrier concentration peak 242, the carrier concentration shows a maximum value P2. The maximum value P2 is equal to the bulk concentration N D It may be 1.1 times or more, 1.5 times or more, 2 times or more, or 10 times or more.

[0077] The statement that the second carrier concentration peak 242 is in contact with the first low-concentration region 211 may mean that the tail of the second carrier concentration peak 242 and the tail of the first trough 221 are continuous. Alternatively, the statement that the second carrier concentration peak 242 is in contact with the first low-concentration region 211 may mean that there is no region with a constant carrier concentration between the second carrier concentration peak 242 and the first low-concentration region 211. Alternatively, the statement that the second carrier concentration peak 242 is in contact with the first low-concentration region 211 may mean that the carrier concentration continues to increase from the position where the carrier concentration shows a minimum value V1 to the position where the carrier concentration shows a maximum value P2.

[0078] In this example, as in the example in Figure 2, the first low-concentration region 211 has a helium concentration peak 261. Helium ions may be injected from the bottom surface 23 or from the top surface 21.

[0079] In this example, the hydrogen chemical concentration of the semiconductor substrate 10 may decrease monotonically as it moves away from the top surface 21. However, in this example, hydrogen is present in the second high-concentration region 232 to the extent that a second carrier concentration peak 242 can be formed. The second carrier concentration peak 242 may be a peak of hydrogen-related donors. The second carrier concentration peak 242 may be formed by the hydrogen present in the semiconductor substrate 10 and the disruption of the crystal structure caused by the implantation of charged particles such as helium ions. The maximum value P2 of the second carrier concentration peak 242 may be smaller than the maximum value P1 of the first carrier concentration peak 241. The hydrogen chemical concentration at the second carrier concentration peak 242 may be lower than the hydrogen chemical concentration at the first carrier concentration peak 241.

[0080] In other examples, the hydrogen concentration at the second carrier concentration peak 242 may be higher than the hydrogen concentration at the first carrier concentration peak 241. For example, by injecting and diffusing hydrogen ions below the second carrier concentration peak 242 on the lower surface 23 side, the hydrogen concentration at the second carrier concentration peak 242 becomes higher than the hydrogen concentration at the first carrier concentration peak 241. In this case, the maximum value P2 of the second carrier concentration peak 242 may be higher than the maximum value P1 of the first carrier concentration peak 241. Furthermore, there may be a concentration peak of hydrogen concentration below the second carrier concentration peak 242 on the lower surface 23 side.

[0081] In this example, the first carrier concentration peak 241 and the second carrier concentration peak 242 are formed without implanting hydrogen ions into either the first high-concentration region 231 or the second high-concentration region 232. A hydrogen concentration peak does not need to be located in a position that overlaps with the second carrier concentration peak 242. Therefore, the first low-concentration region 211, the first high-concentration region 231, and the second high-concentration region 232 can be formed by a simple manufacturing process. The second high-concentration region 232 may be used, for example, as part of the drift region in an IGBT or the like.

[0082] Bulk Plain N D And the difference between the second carrier concentration peak 242 and the maximum value P2 (P2-N) D ) is bulk concentration N D The difference between this value and the local minimum V1 of the first valley 221 (N D It can be smaller than -V1). Difference (P2-N D ) is the difference (N D -V1) may be less than half, or less than 1 / 4. D ) is the difference (N D -V1) may be greater than -V1.

[0083] In the depth direction, the width of the second high-concentration region 232 may be smaller than the width of the first low-concentration region 211. The width of the second high-concentration region 232 may be half or less of the width of the first low-concentration region 211, and may also be one-quarter or less.

[0084] The second low-concentration region 212 has a second valley 222 of carrier concentration at a position where it is in contact with the second high-concentration region 232 on the lower surface 23 side. The second valley 222 indicates a minimum value V2 of carrier concentration. The minimum value V2 is equal to the bulk concentration N D Lower is fine, bulk concentration N D It may be the same as the following. The entire second low-concentration region 212 is the bulk concentration N DIt may have a lower carrier concentration. The second low-concentration region 212 may or may not have hydrogen-related donors. For example, in the second low-concentration region 212, there are relatively few hydrogen-related donors and a relatively large number of remaining crystal defects, so the carrier concentration is relatively lower. Below the second low-concentration region 212, on the surface 23 side, the carrier concentration is the bulk concentration N D The same region may be provided. With the configuration of this example, for example, the expansion of the depletion layer can be suppressed in the second high-concentration region 232, and then the expansion of the depletion layer can be mitigated by the second low-concentration region 212, thereby suppressing the occurrence of avalanche yielding.

[0085] Figure 7 is a cross-sectional view showing another example of the semiconductor device 100. This example of the semiconductor device 100 further includes a hydrogen peak region 250 compared to any of the examples described in Figures 1 to 6. The other structures are the same as those described in any of the examples in Figures 1 to 6. Figure 7 shows an example in which the hydrogen peak region 250 has been added to the example shown in Figure 5.

[0086] The hydrogen peak region 250 is a region containing one or more hydrogen concentration peaks in the depth direction. The hydrogen peak region 250 is located on the lower surface 23 side of the first low concentration region 211. The hydrogen peak region 250 may be located on the lower surface 23 side of the second high concentration region 232. The hydrogen peak region 250 may be located on the lower surface 23 side of the second low concentration region 212. The hydrogen peak region 250 may be located in the region on the lower surface 23 side of the semiconductor substrate 10 (i.e., the region on the lower surface 23 side of the center in the depth direction).

[0087] Figure 8A shows an example of the distribution of carrier concentration, carrier mobility or carrier lifetime, helium chemical concentration, defect density, and hydrogen chemical concentration along the DD line in Figure 7. The DD line is a line parallel to the Z axis, passing through the first high-concentration region 231 to the hydrogen peak region 250. The distribution of oxygen chemical concentration may be the same as or different from the example in Figure 2.

[0088] As described above, the hydrogen peak region 250 has one or more hydrogen concentration peaks 251. At each hydrogen concentration peak 251, the hydrogen chemical concentration shows a maximum value Np. Each hydrogen concentration peak 251 is located on the lower side 23 of the second carrier concentration peak 242.

[0089] In the depth direction of the semiconductor substrate 10, the distance L between the hydrogen concentration peak 251 and the second carrier concentration peak 242 may be 1 / 4 or more of the thickness of the semiconductor substrate 10 in the depth direction. The distance L may be 1 / 2 or more of the thickness of the semiconductor substrate 10, or 3 / 4 or more. Even if the distance L is large, the hydrogen injected at the position of the hydrogen concentration peak 251 can diffuse to the position of the second carrier concentration peak 242 by increasing the dose of hydrogen ions, increasing the annealing temperature of the semiconductor substrate 10, or lengthening the annealing time. If there are multiple hydrogen concentration peaks 251, the distance L may be the distance between the hydrogen concentration peak 251 closest to the second carrier concentration peak 242 and the second carrier concentration peak 242. The distance L may also be the distance between the hydrogen concentration peak 251 with the highest hydrogen chemical concentration and the second carrier concentration peak 242.

[0090] The hydrogen concentration at hydrogen concentration peak 251 is 1 × 10⁻¹⁰ 16 / cm 3 The above is sufficient. If multiple hydrogen concentration peaks 251 are provided, the hydrogen concentration of at least one hydrogen concentration peak 251 is 1 × 10⁻⁶. 16 / cm 3 The above conditions are sufficient, and the hydrogen concentration at hydrogen concentration peak 251, which is closest to the second carrier concentration peak 242, is 1 × 10⁻⁶. 16 / cm 3 The above is sufficient, and the hydrogen concentration of all hydrogen concentration peaks 251 is 1 × 10⁻¹⁶ 16 / cm 3 That's fine too.

[0091] By annealing the semiconductor substrate 10, hydrogen diffuses from the hydrogen concentration peak 251 toward the upper surface 21. Between the first carrier concentration peak 241 and the hydrogen concentration peak 251, a hydrogen concentration flat region 252 may be provided in the depth direction of the semiconductor substrate 10, where the hydrogen concentration is flat. A flat hydrogen concentration means that the hydrogen concentration does not have any maximum or minimum values. In the hydrogen concentration flat region 252, the hydrogen chemical concentration may decrease monotonically from the hydrogen concentration peak 251 toward the upper surface 21. If a second high-concentration region 232 is provided, the hydrogen concentration flat region 252 is provided between the hydrogen concentration peak 251 and the second carrier concentration peak 242.

[0092] The hydrogen concentration flat region 252 may be provided over more than half of the region between the hydrogen peak region 250 and the first carrier concentration peak 241, and may be provided over more than three-quarters of the region. The distribution of hydrogen chemical concentration may have a fourth valley 266 between the first carrier concentration peak 241 and the hydrogen peak region 250 where the hydrogen chemical concentration is at its minimum value. The fourth valley 266 may be located in the first low-concentration region 211. The fourth valley 266 may be formed by hydrogen diffusing from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10 and hydrogen diffusing from the hydrogen peak region 250 to the upper surface 21. By having the fourth valley 266, a first high-concentration region 231 and a second high-concentration region 232 can be easily formed so as to sandwich the first low-concentration region 211.

[0093] The carrier mobility shows a minimum value near the helium ion implantation site Z1. The carrier lifetime is similar. The semiconductor substrate 10 may have a third valley 264 where the carrier mobility and carrier lifetime show minimum values. The third valley 264 may overlap with the first low-concentration region 211.

[0094] The semiconductor substrate 10 may have a constant lifetime region 260 between the second carrier concentration peak 242 and the hydrogen concentration peak 251. The constant lifetime region 260 is a region where the carrier lifetime is constant in the depth direction. A constant carrier lifetime means a region where the maximum value of the carrier lifetime is 1.1 times or less of the minimum value. The constant lifetime region 260 may be provided in a range of more than half of the range between the second carrier concentration peak 242 and the hydrogen concentration peak 251, and may also be provided in a range of more than three-quarters of the range. The constant lifetime region 260 may be provided in the entire range from the second low concentration region 212 to the hydrogen concentration peak 251. The constant lifetime region 260 may be a region where the carrier mobility is equal to the mobility in the semiconductor substrate 10 material (for example, the mobility μ0 in silicon). By injecting helium ions from the upper surface 21 side, the constant lifetime region 260 can be easily formed in regions where helium ions have not passed.

[0095] Similar to the example in Figure 2, the helium concentration peak 261 may be located in the first low-concentration region 211. The helium concentration peak 261 may have a smaller width in the depth direction than the first low-concentration region 211, as shown by the solid line in Figure 8A, or it may have a wider width in the depth direction than the first low-concentration region 211, as shown by the dashed line.

[0096] Of the concentrations P1 at the first carrier concentration peak 241 and P2 at the second carrier concentration peak 242, the concentration closer to the helium concentration peak 261 may be lower than the other. In the example in Figure 8A, the second carrier concentration peak 242 is located closer to the helium concentration peak 261 than the first carrier concentration peak 241. Since the defect density is higher closer to the helium concentration peak 261, the carrier concentration tends to be lower. In the example in Figure 8A, concentration P2 is lower than concentration P1. Concentration P1 may be 1.2 times or more, 1.5 times or more, or 2 times or more than concentration P2.

[0097] The defect density distribution has a defect density peak 265 in the depth direction. The defect density peak 265 overlaps with the helium concentration peak 261. In this example, the defect density peak 265 overlaps with the first high-concentration region 231 and the first low-concentration region 211. The defect density peak 265 may also overlap with the second high-concentration region 232, and may also overlap with the second low-concentration region 212 (see Figure 6).

[0098] Figure 8B shows L (μm) and Np / L (atoms / cm) in Figure 8A. 4 This figure shows the relationship between the two. For example, let Np be the hydrogen peak concentration of the hydrogen concentration peak 251 closest to the upper surface 21. The hydrogen peak concentration is, as an example, 1 × 10⁻⁶. 16 (atoms / cm 3 ) Above, 5 x 10 16 (atoms / cm 3 ) Below, but not limited to. For example, 1 × 10 15 (atoms / cm 3 ) Above, 1 x 10 17 (atoms / cm 3 ) may be less than or equal to 1 × 10⁻⁶. Np / L is 1 × 17 (atoms / cm 4 ) Above, 2 x 10 19 (atoms / cm 4 ) or less. In this case, for example, the expansion of the depletion layer can be suppressed in the second high-concentration region 232, and then the expansion of the depletion layer can be mitigated by the second low-concentration region 212, thereby suppressing the occurrence of avalanche yielding.

[0099] Figure 9 shows an example of carrier concentration distribution in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. The second low-concentration region 212 is optional.

[0100] Of the first carrier concentration peak 241 and the second carrier concentration peak 242, the one closer to either the upper surface 21 or the lower surface 23 may have a higher concentration than the other. In this example, both the first carrier concentration peak 241 and the second carrier concentration peak 242 are located on the upper surface 21 side of the semiconductor substrate 10, and the first carrier concentration peak 241 is located closer to the upper surface 21 than the second carrier concentration peak 242. In other words, the first carrier concentration peak 241 is located closer to the main surface than the second carrier concentration peak 242. In this example, the maximum value P1 at the first carrier concentration peak 241 may be greater than the maximum value P2 at the second carrier concentration peak 242. For example, by having a hydrogen chemical concentration distribution similar to the example described in Figure 2, the hydrogen chemical concentration in the first high-concentration region 231 can be made higher than the hydrogen chemical concentration in the second high-concentration region 232, making the maximum value P1 greater than the maximum value P2. The concentration P1 may be 1.2 times or more, 1.5 times or more, or 2 times or more than the concentration P2.

[0101] As explained in Figure 8A, the helium concentration peak 261 may be located at the injection position Z1 of the first low-concentration region 211. The first carrier concentration peak 241 and the second carrier concentration peak 242 each have an outer base on the opposite side from the helium concentration peak 261. In the example of Figure 9, the first carrier concentration peak 241 has an outer base 271, and the second carrier concentration peak 242 has an outer base 272. The outer base 271 is the portion where the carrier concentration monotonically decreases toward the upper surface 21 from the position where the carrier concentration shows a maximum value P1. The outer base 272 is the portion where the carrier concentration monotonically decreases toward the lower surface 23 from the position where the carrier concentration shows a maximum value P2.

[0102] Of the first carrier concentration peak 241 and the second carrier concentration peak 242, the outer tail closer to the helium concentration peak 261 may be steeper than the other outer tail. In the example in Figure 9, the outer tail 272 is steeper than the outer tail 271. A steep tail means that the absolute value of the slope of the carrier concentration distribution is large. In other examples, of the first carrier concentration peak 241 and the second carrier concentration peak 242, the outer tail further from the helium concentration peak 261 may be steeper than the other outer tail.

[0103] Figure 10 shows an example of carrier concentration distribution in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. The second low-concentration region 212 is optional.

[0104] In this example, similar to the example shown in Figure 8A, the hydrogen concentration peak 251 is located on the lower surface 23 side of the second high-concentration region 232. Of the first carrier concentration peak 241 and the second carrier concentration peak 242, the one closer to the hydrogen concentration peak 251 may have a higher concentration than the other. In this example, the second carrier concentration peak 242 is closer to the hydrogen concentration peak 251 than the first carrier concentration peak 241. By ensuring a sufficiently large amount of hydrogen diffuses from the hydrogen concentration peak 251 to the second carrier concentration peak 242, the maximum value P2 at the second carrier concentration peak 242 can be made larger than the maximum value P1 at the first carrier concentration peak 241. The amount of hydrogen that diffuses from the hydrogen concentration peak 251 to the second carrier concentration peak 242 can be adjusted by the dose of hydrogen ions injected at the position of the hydrogen concentration peak 251, the distance L from the hydrogen concentration peak 251 to the second carrier concentration peak 242, the annealing conditions of the semiconductor substrate 10, etc. The concentration P2 may be 1.2 times or more, 1.5 times or more, or 2 times or more than the concentration P1.

[0105] Figure 11 shows an example of carrier concentration distribution in the first high-concentration region 231, the first low-concentration region 211, the second high-concentration region 232, and the second low-concentration region 212. The second low-concentration region 212 is optional.

[0106] In this example, similar to the example shown in Figure 8A, the hydrogen concentration peak 251 may be located on the lower side 23 of the second high-concentration region 232. In this example, the value obtained by dividing the higher of the two concentrations, P1 of the first carrier concentration peak 241 and P2 of the second carrier concentration peak 242, by the lower concentration is 1.1 or less. In other words, concentrations P1 and P2 are approximately the same. Concentration P1 may be higher than concentration P2, and concentration P2 may be higher than concentration P1.

[0107] By making the hydrogen chemical concentration in the first high-concentration region 231 and the hydrogen chemical concentration in the second high-concentration region 232 approximately the same, concentrations P1 and P2 can be made approximately the same. The hydrogen chemical concentration in each region can be adjusted by, for example, the dose of hydrogen ions injected at the position of the hydrogen concentration peak 251, the distance L from the hydrogen concentration peak 251 to the second carrier concentration peak 242, and the annealing conditions of the semiconductor substrate 10.

[0108] Figure 12 illustrates a more specific embodiment of the semiconductor device 100. In Figure 12, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 12, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0109] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "viewed from above," it means viewed from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 12, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0110] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 12. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0111] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 12, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0112] In Figure 12, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 12). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0113] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0114] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0115] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0116] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 12, the gate wiring is hatched with diagonal lines.

[0117] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0118] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0119] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0120] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities.

[0121] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0122] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0123] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0124] Figure 13 is an enlarged view of region A in Figure 12. Region A is the region including the transistor section 70, the diode section 80, and the active gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active gate wiring 131 are provided separately from each other.

[0125] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 13. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 13, each contact hole 54 is hatched with diagonal lines.

[0126] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0127] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0128] The emitter electrode 52 is formed from a material containing metal. Figure 13 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like.

[0129] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0130] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0131] The gate trench portion 40 in this example may have two linear portions 39 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the alignment direction, and a tip portion 41 that connects the two linear portions 39. In Figure 13, the extension direction is the Y-axis direction.

[0132] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0133] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in the extension direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 13 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0134] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0135] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0136] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 13 shows the base region 14-e located at one end of each mesa portion in the extending direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0137] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0138] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the extension direction (Y-axis direction) of the trench portion.

[0139] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0140] The mesa portion 61 of the diode portion 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0141] A contact hole 54 is provided above each mesa portion. The contact holes 54 are located in the region sandwiched between the base region 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the region corresponding to the base region 14-e and the well region 11. The contact holes 54 may be located in the center of the mesa portion 60 in the alignment direction (X-axis direction).

[0142] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 13, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0143] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54.

[0144] Figure 14 shows an example of the ee cross-section in Figure 13. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0145] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 13.

[0146] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0147] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80.

[0148] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. The base region 14 is provided between the drift region 18 and the upper surface 21. An N+ type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18.

[0149] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0150] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0151] The accumulation region 16 is located between the drift region 18 and the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0152] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa portion 61.

[0153] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. In this example, the buffer section 20 is provided between the drift section 18 and the lower surface 23 of the semiconductor substrate 10. The doping concentration of the buffer section 20 is higher than the doping concentration of the drift section 18. The buffer section 20 may have a concentration peak with a higher doping concentration than the drift section 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. Furthermore, the doping concentration of the drift section 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately constant.

[0154] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0155] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0156] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0157] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0158] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0159] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0160] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0161] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0162] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0163] Below the gate trench 40 and the dummy trench 30, a lifetime adjustment region 141 is provided in which the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate 10. A portion of the lifetime adjustment region 141 may be located above the lower ends of the gate trench 40 and the dummy trench 30.

[0164] The first high-concentration region 231 and the accumulation region 16 described in Figures 1 to 11 may overlap. The entire first high-concentration region 231 may function as the accumulation region 16. Also, the first low-concentration region 211 and the lifetime adjustment region 141 described in Figures 1 to 11 may overlap. The entire first low-concentration region 211 may function as the lifetime adjustment region 141. According to this example, the accumulation region 16 and the lifetime adjustment region 141 can be formed in a simple manufacturing process.

[0165] The hydrogen concentration peak 251, as described in Figures 1 to 11, may be located in the buffer region 20. The buffer region 20 overlaps with the hydrogen concentration peak 251 and has a carrier concentration peak. This carrier concentration peak is the peak of the hydrogen-related donor. In this example, the storage region 16, the lifetime adjustment region 141, and the buffer region 20 can be formed in a simple manufacturing process.

[0166] The second high-concentration region 232 described in Figures 1 to 11 may overlap with the drift region 18. In this case, at least a portion of the drift region 18 can be made highly concentrated using a simple manufacturing process. The second low-concentration region 212 described in Figures 1 to 11 may also overlap with the drift region.

[0167] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0168] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0169] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulation Film, 34...Dummy conductive part, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive part, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa section, 70...Transistor section, 80...Diode section, 81...Extended region, 82...Cathode region, 90...Edge Terminal structure, 100... Semiconductor device, 130... Outer periphery gate wiring, 131... Active side gate wiring, 141... Lifetime adjustment region, 160... Active region, 162... Edge, 164... Gate pad, 211... First low concentration region, 212... Second low concentration region, 221... First valley, 222... Second valley, 231... First high concentration region, 232... Second high concentration region, 2 41...First carrier concentration peak, 242...Second carrier concentration peak, 250...Hydrogen peak region, 251...Hydrogen concentration peak, 252...Hydrogen concentration flat region, 260...Constant region, 261...Helium concentration peak, 262...Oxygen concentration peak, 263...Dashed line, 264...Third valley region, 265...Defect density peak, 266...Fourth valley region, 271, 272...Outer base region

Claims

1. A semiconductor device having a first main surface and a second main surface, provided on a semiconductor substrate containing a bulk dopant, In the semiconductor substrate, a first low-concentration region of a first conductivity type is provided, having a carrier concentration lower than the bulk concentration, which is the concentration of the bulk dopant. A first high-concentration region of a first conductivity type has a first carrier concentration peak at a position in contact with the first low-concentration region and the first main surface side, and the carrier concentration is higher than the bulk concentration. Equipped with, A hydrogen concentration peak is not located at a position that overlaps with the first carrier concentration peak. Semiconductor equipment.

2. The first high-concentration region includes hydrogen-related donors. The semiconductor device according to claim 1.

3. The aforementioned first carrier concentration peak is the concentration peak of the hydrogen-related donor. The semiconductor device according to claim 2.

4. The first low-concentration region has a helium concentration peak in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1.

5. The width of the helium concentration peak in the depth direction is smaller than the width of the first low concentration region in the depth direction. The semiconductor device according to claim 4.

6. The material further comprises a second high-concentration region of the first conductivity type, having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration. The semiconductor device according to any one of claims 1 to 5.

7. The hydrogen concentration peak is not located at a position that overlaps with the second carrier concentration peak. The semiconductor device according to claim 6.

8. The aforementioned second carrier concentration peak is the concentration peak of the hydrogen-related donor. The semiconductor device according to claim 7.

9. Of the first carrier concentration peak and the second carrier concentration peak, the one closer to the hydrogen concentration peak has a higher concentration than the other. The semiconductor device according to claim 6.

10. Of the first carrier concentration peak and the second carrier concentration peak, the one closer to the first principal surface or the second principal surface has a higher concentration than the other. The semiconductor device according to claim 6.

11. The value obtained by dividing the higher of the two carrier concentration peaks (the first carrier concentration peak and the second carrier concentration peak) by the lower of the two carrier concentration peaks is 1.1 or less. The semiconductor device according to claim 6.

12. The first conductivity type further comprises a second high-concentration region having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration. The first low-concentration region has a helium concentration peak in the depth direction of the semiconductor substrate. Of the concentrations of the first carrier concentration peak and the second carrier concentration peak, the one closer to the helium concentration peak is lower than the other. The semiconductor device according to any one of claims 1 to 3.

13. The first conductivity type further comprises a second high-concentration region having a second carrier concentration peak at a position in contact with the first low-concentration region and the second main surface side, and having a carrier concentration higher than the bulk concentration. The first low-concentration region has a helium concentration peak in the depth direction of the semiconductor substrate. The first carrier concentration peak and the second carrier concentration peak each have an outer tail on the side opposite to the helium concentration peak. Of the first carrier concentration peak and the second carrier concentration peak, the outer base of the peak closer to the helium concentration peak is steeper than the outer base of the other peak. The semiconductor device according to any one of claims 1 to 3.

14. The second low-concentration region further comprises a second low-concentration region having a carrier concentration valley at a position in contact with the second high-concentration region on the second main surface side. The semiconductor device according to claim 6.

15. The hydrogen concentration peak is located on the second main surface side of the second carrier concentration peak. The semiconductor device according to claim 6.

16. In the depth direction of the semiconductor substrate, the distance between the hydrogen concentration peak and the second carrier concentration peak is 1 / 4 or more of the thickness of the semiconductor substrate in the depth direction. The semiconductor device according to claim 15.

17. The hydrogen concentration at the aforementioned hydrogen concentration peak is 1 × 10 １６ / cm ３ That's all. The semiconductor device according to claim 15.

18. Between the second carrier concentration peak and the hydrogen concentration peak, the semiconductor substrate has a constant lifetime region in the depth direction where the carrier lifetime is constant. The semiconductor device according to claim 6.

19. Between the first carrier concentration peak and the hydrogen concentration peak, the semiconductor substrate is provided with a hydrogen concentration flat region in the depth direction where the hydrogen concentration is flat. The semiconductor device according to claim 18.

20. A first conductivity type drift region provided on the semiconductor substrate, A second conductive base region is provided between the drift region and the first main surface, A trench portion is provided from the first main surface down to below the base region, A storage region is provided between the drift region and the base region, and has a carrier concentration higher than that of the drift region. A lifetime adjustment region is provided below the trench portion, in which the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate. Equipped with, The aforementioned first high-concentration region and the accumulation region overlap, The first low-concentration region and the lifetime adjustment region overlap. The semiconductor device according to any one of claims 1 to 5.

21. The system further comprises a buffer region of a first conductivity type, provided between the drift region and the second main surface, having a carrier concentration higher than that of the drift region. The hydrogen concentration peak is located in the buffer region. The semiconductor device according to claim 20.

22. A first conductivity type drift region provided on the semiconductor substrate, A second conductive base region is provided between the drift region and the first main surface, A trench portion is provided from the first main surface down to below the base region, A lifetime adjustment region is provided below the trench portion, in which the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate. Equipped with, The aforementioned first low-concentration region and the aforementioned lifetime adjustment region overlap, The second high-concentration region and the drift region overlap. The semiconductor device according to claim 6.

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