Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device with reduced on-resistance. [Solution] The embodiment includes a first electrode, a semiconductor layer, and a second electrode. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a structure, and a gate electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. Multiple structures are provided in a second direction corresponding to the [100] direction of the silicon crystal plane and in a third direction inclined from the second direction. The gate electrode faces the second semiconductor region. Each of the multiple structures includes an insulating portion and a conductive portion. The second semiconductor region has a higher impurity concentration of the second conductivity type in the first plane perpendicular to the second direction than in the third plane perpendicular to the third direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are used for power conversion and the like. It is desirable that the on-resistance of the semiconductor device be low.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment of the present invention aims to provide a semiconductor device with reduced on-resistance.

Means for Solving the Problems

[0005] A semiconductor device according to an embodiment includes a first electrode, a semiconductor layer disposed on the first electrode, and a second electrode disposed on the semiconductor layer. The semiconductor layer includes a first semiconductor region of a first conductivity type electrically connected to the first electrode, a second semiconductor region of a second conductivity type disposed on the first semiconductor region and electrically connected to the second electrode, a third semiconductor region of the first conductivity type disposed on the second semiconductor region and electrically connected to the second electrode, a plurality of structures arranged side by side in a second direction perpendicular to a first direction toward the semiconductor layer from the first electrode and corresponding to the

[0100] direction of the silicon crystal plane, and a third direction orthogonal to the first direction and inclined with respect to the second direction at an angle greater than 0° and less than 90°, and a gate electrode disposed opposite the second semiconductor region via an oxide film in the second and third directions. Each of the plurality of structures includes an insulating portion containing an oxide, which is arranged alongside a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region in the second and third directions, and a conductive portion provided within the insulating portion, which includes a portion facing the first semiconductor region in the second and third directions, and which is electrically connected to the second electrode. The second semiconductor region has a first surface perpendicular to the second direction and forming an interface with the oxide film, a second surface located opposite the first surface, a third surface perpendicular to the third direction and forming an interface with the oxide film, and a fourth surface located opposite the third surface. The impurity concentration of the second conductivity type on the first surface is higher than the impurity concentration of the second conductivity type on the third surface. [Brief explanation of the drawing]

[0006] [Figure 1] This is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] This is an enlarged view of section II in Figure 1. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] This is a cross-sectional view along line IV-IV in Figure 2. [Figure 5]This is a plan view illustrating a part of a semiconductor device according to the first embodiment. [Figure 6] This is a plan view illustrating a part of a semiconductor device according to a modified example of the first embodiment. [Figure 7] This is a cross-sectional view along the line VI-VI in Figure 4. [Figure 8] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 9] This is a plan view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 12] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 14] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 15] This is a plan view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 16] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 17] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to the first embodiment. [Figure 18] This is a cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 19] Figure 18 is a cross-sectional view along the XIX-XIX line. [Figure 20] Figure 18 shows a cross-sectional view along the line XX-XX. [Modes for carrying out the invention]

[0007] Each embodiment of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] (First embodiment) Figure 1 is a plan view representing a semiconductor device according to an embodiment. Figure 2 is an enlarged view of section II in Figure 1. Figure 3 is a cross-sectional view taken along the line III-III in Figure 2. Figure 4 is a cross-sectional view along the line IV-IV in Figure 2. Figure 2 is a cross-sectional view along the VV line in Figure 3.

[0009] As shown in Figures 1 to 4, the semiconductor device 100 according to the embodiment includes a drain electrode (first electrode) E1, a semiconductor layer SL, and a source electrode (second electrode) E2. A structure 20 is provided on the semiconductor layer SL. The structure 20 includes a gate electrode 10 and a gate insulating layer 11. The semiconductor device 100 according to the embodiment is a MOSFET having a drain electrode E1, a source electrode E2, and a gate electrode 10.

[0010] In the following specific examples, the first direction D1, the second direction D2, and the third direction D3 may be used for explanation. The first direction D1 is the direction from the drain electrode E1 toward the semiconductor layer SL. The second direction D2 and the third direction D3 are perpendicular to the first direction D1. The third direction D3 is a direction tilted from the second direction D2, and the angle of tilt is greater than 0° and less than 90°. In the following explanation, the direction from the drain electrode E1 toward the semiconductor layer SL will be referred to as "up" or "upward," and the opposite direction will be referred to as "down" or "downward." These directions are based on the relative positional relationship between the drain electrode E1 and the semiconductor layer SL, and are unrelated to the direction of gravity.

[0011] As shown in Figure 1, a source electrode E2 and a gate pad E3 are provided on the upper surface of the semiconductor device 100. The source electrode E2 and the gate pad E3 are electrically isolated from each other.

[0012] As shown in Figure 2, the structure 20 is aligned along a second direction D2. The structure 20 is aligned along a third direction D3. The structure 20 includes an insulating portion 21 and a conductive portion 22, and the structure 20 is provided with a gate electrode 10 and a gate insulating layer 11. The insulating portion 21 surrounds the conductive portion 22 along a plane including the second direction D2 and the third direction D3. The gate electrode 10 also surrounds the insulating portion 21 along a plane including the second direction D2 and the third direction D3. The gate insulating layer 11 surrounds the gate electrode 10 along a plane including the second direction D2 and the third direction D3. The gate insulating layer 11 contains an oxide, for example, a layer containing SiO2. For ease of understanding, in this embodiment, the structure 20 is described as a single unit including the insulating portion 21, the conductive portion 22, the gate electrode 10 and the gate insulating layer 11.

[0013] As shown in FIGS. 3 and 4, the drain electrode E1 is provided on the lower surface of the semiconductor device 100. The semiconductor layer SL is provided on the drain electrode E1. The semiconductor layer SL contains single crystal silicon. The second direction D2 corresponds to the

[0100] direction of the crystal plane of silicon. The source electrode E2 and the gate pad E3 are provided on the semiconductor layer SL.

[0014] The semiconductor layer SL is an n - -type (first conductivity type) drift region (first semiconductor region) 1, a p-type (second conductivity type) base region (second semiconductor region) 2, an n + -type source region (third semiconductor region) 3 and an n + -type drain region 5.

[0015] The n + -type drain region 5 is provided on the drain electrode E1. The n + -type drain region 5 is electrically connected to the drain electrode E1. The n - -type drift region 1 is provided on the n + -type drain region 5. The n - -type drift region 1 is electrically connected to the drain electrode E1 through the n + -type drain region 5. The p-type base region 2 is provided on the n - -type drift region 1. On the p-type base region 2, an n + -type source region 3 and a p + -type contact region 4 are provided. The p + -type contact region 4 is provided between adjacent n + -type source regions 3 along the second direction D2. The source electrode E2 is provided on the n + -type source region 3 and the p-type contact region 4, and is electrically connected to the p + -type contact region and the n + -type source region 3.

[0016] The structure 20 includes a part of the n - -type drift region 1, the p-type base region 2 and an n +The shapes are aligned along the second direction D2 via the source region 3. Structure 20 is n - Part of the shape drift region 1, p-shaped base region 2 and n + They are aligned along the third direction D3 via the shape source region 3. More specifically, as will be described later in relation to Figures 5 and 7, the structure 20 is part of the first part 2a and n which are part of the p-shaped base region 2. - It is aligned along the second direction D2 via the fourth part 1a, which is part of the shape drift region 1. Also, the structure 20 is aligned along the second direction D2 via parts 2b1 and n of the other parts 2b of the p-shaped base region 2 other than the first part 2a. - The drift region 1 is aligned along the third direction D3 via at least a portion 1b1 of the other portions 1b, excluding the fourth portion 1a.

[0017] The conductive part 22 is provided within the insulating part 21. At least a portion of the conductive part 22 is connected to the insulating part 21 and n - They are aligned along the second direction D2 through a portion of the shaped drift region 1. At least a portion of the conductive portion 22 is connected to the insulating portion 21 and n - The components are aligned along the third direction D3 through a portion of the shape drift region 1. The insulating portion 21 contains an oxide, for example, SiO2. The conductive portion 22 is electrically connected to the source electrode E2.

[0018] The gate electrode 10 faces the p-type base region 2 via the gate insulating layer 11 in the second direction D2 and the third direction D3. The gate electrode 10 is connected to the p-type base region 2 via the gate insulating layer 11. - Shape drift regions 1 and n + It faces the p-type source region 3. The gate electrode 10 is electrically connected to the gate pad E3. More specifically, as will be described later in relation to Figure 5, the gate electrode 10 faces the first portion 2a of the p-type base region 2 via the gate insulating layer 11 in the second direction D2. Also, the gate electrode 10 faces the second portion 2b1 of the p-type base region 2 via the gate insulating layer 11 in the third direction D3.

[0019] As shown in Figures 2 to 4, the p-shaped base region 2 surrounds the gate insulating layer 11 along a plane that includes the second direction D2 and the third direction D3.

[0020] Viewed from the first direction D1, the boundaries of the insulating portion 21, the conductive portion 22, the gate electrode 10, the gate insulating layer 11, and the p-type base region 2 are hexagonal. These boundaries are approximately parallel in each of the insulating portion 21, the conductive portion 22, the gate electrode 10, the gate insulating layer 11, and the p-type base region 2.

[0021] The p-type base region 2 includes a first portion 2a and other portions 2b. The first portion 2a is a region having a higher concentration of p-type impurities than the p-type impurities in the other portions 2b.

[0022] The p-shaped base region 2 has a first surface S1 perpendicular to the second direction D2. The p-shaped base region 2 also has a second surface S2 located opposite the first surface S1 in the second direction D2. The second surface S2 is perpendicular to the second direction D2. The first surface S1 and the second surface S2 are surfaces that form the interface with the gate insulating layer 11. The first portion 2a is the region between the first surface S1 and the second surface S2, and includes the first surface S1 and the second surface S2. The other portion 2b is the region of the p-shaped base region 2 other than the first portion 2a.

[0023] The remaining portion 2b has a surface in contact with the first portion 2a and a third surface S3 perpendicular to the third direction D3. The third surface S3 is adjacent to the first surface S1. The remaining portion 2b has a fourth surface S4 located opposite the third surface S3 in the third direction D3. The fourth surface S4 is perpendicular to the third direction D3. The third surface S3 and the fourth surface S4 are surfaces that form an interface with the gate insulating layer 11. The remaining portion 2b includes a second portion 2b1. The second portion 2b1 is not in contact with the first portion 2a and is a region between the third surface S3 and the fourth surface S4, and is a region that includes the third surface S3 and the fourth surface S4.

[0024] The arrangement of the gate electrode 10, gate insulating layer 11, and p-type base region 2 will be described in more detail. Figure 5 is a plan view illustrating a part of a semiconductor device according to the embodiment. In Figure 5, the structures 20 shown in Figure 2 have been given different symbols to distinguish them from one another. Also, in Figure 5, only three adjacent structures 20 from the multiple structures 20 shown in Figure 2 are shown, and the surrounding structures are omitted. Furthermore, the first part 2a and the second part 2b1 are shown with dashed lines to indicate the interface with the surrounding part. The same applies to Figures 6, 7, and 18. The configurations of the first structure 20a, the second structure 20b, and the third structure 20c shown in Figure 5 are the same as those of the structure 20 shown in Figure 2. That is, the first structure 20a includes the first gate electrode 10a, the first gate insulating layer 11a, the first insulating part 21a, and the first conductive part 22a; the second structure 20b includes the second gate electrode 10b, the second gate insulating layer 11b, the second insulating part 21b, and the second conductive part 22b; and the third structure 20c includes the third gate electrode 10c, the third gate insulating layer 11c, the third insulating part 21c, and the third conductive part 22c. The first gate electrode 10a, the second gate electrode 10b, and the third gate electrode 10c correspond to the gate electrode 10 shown in Figure 2. The first gate insulating layer 11a, the second gate insulating layer 11b, and the third gate insulating layer 11c correspond to the gate insulating layer 11 shown in Figure 2. The first insulating portion 21a, the second insulating portion 21b, and the second insulating portion 21c correspond to the insulating portion 21 shown in Figure 2. The first conductive portion 22a, the second conductive portion 22b, and the third conductive portion 22c correspond to the conductive portion 22 shown in Figure 2.

[0025] As shown in Figure 5, the pair of second gate electrode 10b and gate insulating layer 11b included in the second structure 20b is adjacent to the pair of first gate electrode 10a and gate insulating layer 11a included in the first structure 20a along the second direction D2. The pair of third gate electrode 10c and gate insulating layer 11c included in the third structure 20c is adjacent to the pair of first gate electrode 10a and gate insulating layer 11a included in the first structure 20a along the third direction D3.

[0026] The first gate electrode 10a is positioned opposite the first surface S1 of the first portion 2a via a gate insulating layer 11a. The second gate electrode 10b is positioned opposite the second surface S2 of the first portion 2a via a gate insulating layer 11b. With respect to the second direction D2, the first gate electrode 10a and the second gate electrode 10b are positioned side by side along the second direction D2.

[0027] The first gate electrode 10a is positioned facing the third surface S3 of the second portion 2b1 via a gate insulating layer 11a. The third gate electrode 10c is positioned facing the fourth surface S4 of the second portion 2b1 via a gate insulating layer 11c. The first gate electrode 10a and the third gate electrode 10c are positioned side by side along the third direction D3.

[0028] The thickness tox1 of the gate insulating layer 11a in contact with the first surface S1 is approximately equal to the thickness tox2 of the gate insulating layer 11b in contact with the second surface S2. The thickness tox3 of the gate insulating layer 11a in contact with the third surface S3 is approximately equal to the thickness tox4 of the gate insulating layer 11c in contact with the fourth surface S4. Thicknesses tox1 and tox2 are thinner than thicknesses tox3 and tox4. Although not indicated by a sign, the thicknesses of other gate insulating layers not in contact with the first surface S1 and the second surface S2 are thicker than thicknesses tox1 and tox2.

[0029] Distance d1 is the distance between the first surface S1 and the second surface S2. Distance d2 is the distance between the third surface S3 and the fourth surface S4. Distances d1 and d2 can be set arbitrarily, but as will be described later in relation to Figure 7, in order to reduce the element size while ensuring the drain-source breakdown voltage of the semiconductor device 100, it is preferable to set d1=d2 and make the values ​​of d1 and d2 smaller. The pitch P2, which represents the distance between structures in the second direction D2, is the distance between the centroids G1 and G2 of hexagons adjacent in the second direction D2 that include the first surface S1 and the third surface S3. The pitch P3, which represents the distance between structures in the third direction D3, is the distance between the centroids G1 and G3 of hexagons adjacent in the third direction D3 that include the first surface S1 and the third surface S3. Each side of the hexagon including the first surface S1 and the third surface S3 forms a channel of the MOSFET, and the length of the side of the hexagon corresponds to the channel width. Therefore, it is preferable to make the pitches P2 and P3 approximately equal and shorten their respective lengths, as this contributes to increasing the channel width.

[0030] The gate threshold voltage of a MOSFET increases with increasing thickness of the gate insulating layer. Therefore, if the impurity concentration of the p-type base region 2 in contact with the gate insulating layer is the same, the gate threshold voltage of the portion of the gate insulating layer in contact with the first surface S1 and the second surface S2 will be lower than the gate threshold voltage of other portions. As a result, the gate threshold voltage of the MOSFET will vary depending on the direction within the plane including the second direction D2 and the third direction D3, increasing the overall on-resistance of the MOSFET.

[0031] The gate threshold voltage of a MOSFET can be adjusted by controlling the impurity concentration of the p-type base region 2. In the semiconductor device 100 according to this embodiment, the impurity concentration of the other portion 2b is lower than that of the first portion 2a extending from the first surface S1 to the second surface S2. Therefore, by appropriately setting the impurity concentration of the first portion 2a and the impurity concentration of the other portion 2b, the gate threshold voltage can be made uniform regardless of the difference in the thickness of the gate insulating layer. By making the gate threshold voltage uniform for the gate insulating layer 11 in contact with the p-type base region 2 and the gate electrode 10 arranged via the gate insulating layer 11, a semiconductor device 100 with lower on-resistance can be realized. Since the gate threshold voltage of a MOSFET is adjusted by the impurity concentration of the p-type base region 2 in contact with the gate insulating layer, it is preferable that the impurity concentration of the second portion 2b1 is set lower than that of the first portion 2a.

[0032] Figure 6 is a plan view illustrating a part of a semiconductor device according to a modified embodiment. In Figure 6, as in Figure 2, adjacent structures in the second direction D2 are indicated by different reference numerals to illustrate the arrangement of the gate electrode 10, gate insulating layer 11, and p-type base region 2. Furthermore, in Figure 6, only two adjacent structures 20 from the multiple structures 20 shown in Figures 2 and 5 are represented, and the surrounding structures are omitted. The gate threshold voltage can be controlled by adjusting the concentration of p-type impurities in the p-type base region 2 at and near the interface with the gate insulating layer 11. Therefore, the portion of the p-type base region 2 in which the concentration of p-type impurities is higher than in other parts is not limited to the case shown in Figure 6, etc., but may be limited to the region close to the gate insulating layer 11.

[0033] As shown in Figure 6, the second structure 20b is aligned adjacent to the first structure 20a along the second direction D2. The third structure 20c and other structures aligned adjacent in the third direction are the same as in Figure 5, and their explanation is omitted.

[0034] The p-type base region 2 includes a first portion 2a and a third portion 2b2. The first portion 2a is divided into two portions 2a1 and 2a2. One portion 2a1 has a first surface S1. The other portion 2a2 has a second surface S2. The first gate electrode 10a is positioned opposite the first surface S1 of one portion 2a1 via a gate insulating layer 11. The second gate electrode 10b is positioned opposite the second surface S2 of the other portion 2a2 via a gate insulating layer 11. The third portion 2b2 is a region sandwiched between the first portions 2a1 and 2a2. The remaining portion 2b includes the third portion 2b2, and one portion 2a1 and the other portion 2a2 have impurity concentrations higher than the impurity concentration of the third portion 2b2.

[0035] Even with this configuration, as explained in relation to Figure 3, it becomes possible to equalize the gate threshold voltages on each of the first surface S1 to the fourth surface S4, thereby reducing the variation in the resistance of the channel formed in the p-type base region 2 of the semiconductor device 100 and enabling a stable low on-resistance.

[0036] As shown in Figures 3, 4, and 7, n - The drift region 1 surrounds the insulating portion 21. Note that in Figure 7, only three adjacent structures 20 out of the multiple structures 20 exemplified in Figure 2 are shown, and the surrounding structures are omitted.

[0037] Viewed from the first direction D1, the shape of the boundary between the insulating portion 21 and the conductive portion 22 is hexagonal. Also, n - The shape of the boundary between the drift region 1 and the insulating portion 21 is also hexagonal.

[0038] n - The shape drift region 1 includes a fourth portion 1a and a fifth portion 1b. The fifth portion 1b is a region having an impurity concentration lower than that of the fourth portion 1a.

[0039] n - The fourth portion 1a of the shaped drift region 1 has a fifth surface S5 that is perpendicular to the second direction D2. -The fourth portion 1a of the drift region 1 has a sixth surface S6 located opposite the fifth surface S5 in the second direction D2. The sixth surface S6 is perpendicular to the second direction D2. The fifth surface S5 and the sixth surface S6 are surfaces that form the interface with the insulating portions 21a and 21b. The fourth portion 1a is the region between the fifth surface S5 and the sixth surface S6, and is the region that includes the fifth surface S5 and the sixth surface S6. The fifth portion 1b is n - This is the region of shape drift region 1 excluding the fourth part 1a.

[0040] The fifth portion 1b has a surface in contact with the fourth portion 1a and a seventh surface S7 perpendicular to the third direction D3. The seventh surface S7 is adjacent to the fifth surface S5. The fifth portion 1b has an eighth surface S8 located opposite the seventh surface S7 in the third direction D3. The eighth surface S8 is perpendicular to the third direction D3. The seventh surface S7 and the eighth surface S8 are surfaces that form interfaces with the insulating portions 21a and 21c. The fifth portion 1b includes other portions 1b1 that are not in contact with the fourth portion 1a. The other portions 1b1 are the region of the fifth portion 1b between the seventh surface S7 and the eighth surface S8, and include the seventh surface S7 and the eighth surface S8.

[0041] The fifth surface S5 is continuous with the first surface S1 of the p-shaped base region 2, and the sixth surface S6 is continuous with the second surface S2 of the p-shaped base region 2. Also, the seventh surface S7 is continuous with the third surface S3 of the p-shaped base region 2, and the eighth surface S8 is continuous with the fourth surface S4 of the p-shaped base region 2.

[0042] The thickness tox5 of the insulating portion 21a in contact with the fifth surface S5 is approximately equal to the thickness tox6 of the insulating portion 21b in contact with the sixth surface S6. The thickness tox7 of the insulating portion 21a in contact with the seventh surface S7 is approximately equal to the thickness tox8 of the insulating portion 21c in contact with the eighth surface S8. Thicknesses tox5 and tox6 are thinner than thicknesses tox7 and tox8. Although not indicated by a sign, the thicknesses of other insulating portions not in contact with the fifth surface S5 and the sixth surface S6 are thicker than thicknesses tox5 and tox6.

[0043] Distance d3 is the distance between the fifth face S5 and the sixth face S6. Distance d4 is the distance between the seventh face S7 and the eighth face S8. Distance d3 can be approximately equal to distance d4. As explained in relation to Figure 5, from the viewpoint of arranging the structures 20 most densely and reducing on-resistance, it is preferable that the pitch P2 in the second direction D2 of adjacent structures is equal to the pitch P3 in the third direction D3 of adjacent structures.

[0044] n - When the impurity concentration in the shape drift region 1 is the same, two adjacent conductive parts 22 and n - When a voltage is applied between the shaped drift region 1 and the insulating portion 21, the thicker the insulating portion 21, the n - The depletion layer within the shape drift region 1 does not extend easily. Therefore, the distance d3 between adjacent structures 20a and 20b is n - Within the drift region 1, it is necessary to bring the depletion layer close enough to extend and connect. On the other hand, if the thickness of the insulating part 21 is thin, the n in contact with the structures 20a and 20b - The depletion layer within the shape drift region 1 extends sufficiently. Applying this to the case in Figure 6, n - If the impurity concentration in shape drift region 1 is the same in all regions, the distance between structures 20a and 20b must be longer than the distance between structures 20a and 20c, and the pitch at which the structures are arranged will differ between the second direction D2 and the third direction D3.

[0045] Here, if the thickness of the insulating part is the same, then the adjacent conductive part and n - When a voltage is applied between the drift region 1 and the other region, n - The higher the impurity concentration in the drift region 1, the less likely the depletion layer is to elongate, allowing the distance between adjacent conductive parts to be reduced. Therefore, in the semiconductor device 100 according to this embodiment, by providing a fourth part 1a with a high n-type impurity concentration between structures 20a and 20b, the distance d3 between structures 20a and 20b can be reduced while making the breakdown voltage between structures 20a and 20b and the fourth part 1a equal to the breakdown voltage between structures 20a and 20c and the other parts 1b1.

[0046] When the thicknesses tox5 and tox6 of the insulating parts 21a and 21b are thinner than the thicknesses tox7 and tox8 of the insulating parts 21a and 21c, the impurity concentration of the fourth part 1a is set to the other n including the fifth part 1b. - By increasing the impurity concentration in the drift region 1, the on-resistance of the semiconductor device 100 can be reduced. Furthermore, by doing so, the arrangement of the structures can be aligned in all directions, and by improving the density of the arrangement of structures in the semiconductor device 100, the on-resistance can be reduced.

[0047] A method for manufacturing the semiconductor device 100 according to an embodiment will be described. Figures 8, 10-14, 16, and 17 are cross-sectional views illustrating the manufacturing process of a semiconductor device according to an embodiment. Figures 9 and 15 are plan views illustrating the manufacturing process of a semiconductor device according to an embodiment. Figures 8, 10, 11, 13, 14, and 16 show cross-sections at the positions corresponding to line III-III in Figure 2. Figures 12 and 17 show cross-sections at the locations corresponding to the line IV-IV in Figure 2. Figures 9 and 15 are shown as plan views corresponding to Figure 2.

[0048] As shown in Figure 8, a semiconductor substrate S is prepared in which an aperture OP1 is formed. The semiconductor substrate S is n + Semiconductor layer 5s and n - It includes a semiconductor layer 1s. The aperture OP1 is n - These are bottomed trenches (holes) formed in the semiconductor layer 1s. As will be described later in relation to Figure 9, the shape of the periphery of the opening OP1 is hexagonal when viewed from the first direction D1, which is perpendicular to the second direction D2 and the third direction D3. The openings OP1 are arranged at approximately equal intervals along the second direction D2 and along the third direction D3.

[0049] As shown in Figure 9, a mask M1 is placed on the semiconductor substrate S. The mask M1 is positioned to expose the fifth surface S5 and the sixth surface S6 of the opening OP1. The fifth surface S5 and the sixth surface S6 are the inner wall surfaces of the opening OP1, and n - This plane corresponds to the silicon crystal plane

[0100] of the semiconductor layer 1s. The fifth plane S5 and the sixth plane S6 are planes perpendicular to the second direction D2. On the inner wall surface of the opening OP1, the other planes adjacent to the fifth plane S5 and the sixth plane S6 are covered by the mask M1.

[0050] As shown in Figure 10, impurities are implanted into the inner wall of the opening OP1 by ion implantation through the mask M1. When implanting impurities, the implantation direction is tilted by an angle θ from the first direction D1. Preferably, the angle θ is set as an angle from the first direction D1 in a plane that includes the first direction D1 and the second direction D2. This allows n to enter from the opening OP1. - Impurities can be implanted into the fifth surface S5 of the semiconductor layer 1s. - A high-concentration region 1sa is formed. - The high-concentration region 1sa is formed from the fifth surface S5 toward the second direction D2. By adjusting the injection energy of n-type impurities, the n-type impurities are injected to a depth of at least half the distance d3 between the fifth surface S5 and the sixth surface S6.

[0051] As shown in Figure 11, impurities are implanted into the aperture OP1 via the mask M1 by ion implantation. When implanting impurities, the irradiation direction is tilted by an angle -θ from the first direction D1. Preferably, the angle -θ is set as an angle from the first direction D1 within a plane containing the first direction D1 and the second direction D2. This allows impurities to be implanted from the aperture OP1 into the sixth surface S6. - A high-concentration region 1sa is formed. -The n-type high-concentration region 1sa is formed from the sixth surface S6 in the direction opposite to the second direction D2. By adjusting the injection energy of the n-type impurities, the n-type impurities are injected to a depth of at least half the distance d3 between the fifth surface S5 and the sixth surface S6. In this way, n - The high-concentration region 1sa is formed from the bottom to the upper end of the opening OP1. In other words, n - The high-concentration region 1sa is formed with a nearly uniform impurity concentration in the region extending over a distance d3 between the fifth surface S5 and the sixth surface S6. For the purposes of understanding, the impurity introduction depth during ion implantation is given as n. - The length of the high-concentration region 1sa in the second direction D2, which is distance d3, was set to half of this value. More specifically, it can be appropriately set by adjusting the ion implantation energy. For example, if ion implantation is performed from both sides, the fifth surface S5 and the sixth surface S6, and the impurity distribution after implantation is a Gaussian distribution, the ion implantation energy can be set such that the impurity concentration becomes nearly constant over the entire distance d3 as a result of the overlapping impurity distributions on both sides.

[0052] Figure 12 shows the introduction of impurities to surfaces other than the fifth surface S5 and the sixth surface S6 of the opening OP1 during the ion implantation process described in relation to Figures 10 and 11. As shown in Figure 12, the implantation of impurities in the opening OP1 is almost completely shielded by the mask M1, and the introduction of impurities to surfaces other than the fifth surface S5 and the sixth surface S6 is almost suppressed. Therefore, the region from the seventh surface S7 to the eighth surface S8 is n - The impurity concentration is lower than in the high-concentration region 1sa.

[0053] In the ion implantation process described in relation to Figures 10 and 11, the implantation energy for impurities on the fifth surface S5 side is set to be approximately equal to the implantation energy on the sixth surface S6 side. By appropriately setting the impurity implantation energy, a sufficient impurity introduction distance in the second direction D2 can be ensured.

[0054] The ion implantation angle θ is greater than 0° and less than 50°, and is appropriately set according to the aperture diameter and depth of the opening OP1 and the depth to which the impurities are introduced.

[0055] In the ion implantation process, impurity implantation may be repeated in multiple steps depending on the withstand voltage between the drain and source of the semiconductor device 100.

[0056] As explained in relation to Figure 9, a mask M1 is placed to cover all surfaces except the 5th surface S5 and the 6th surface S6, and impurities are removed by tilting it from the first direction D1. - By injecting impurities into the semiconductor layer, it is possible to accurately introduce impurities from the fifth surface S5 and the sixth surface S6.

[0057] Subsequently, the mask M1 is removed, and an insulating portion 21 is formed on the wall surface of the opening OP1 by thermal oxidation, and a conductive portion 22 is formed within the insulating portion 21. Furthermore, a gate insulating layer 11 and a gate electrode 10 are formed to create an intermediate member I1 having a fourth portion 1a, as shown in Figure 13.

[0058] When the insulating portion 21 and the gate insulating layer 11 are formed by thermal oxidation, differences in oxidation rates occur depending on the crystal orientation of the silicon. Specifically, the plane perpendicular to the second direction D2 corresponds to the silicon crystal plane

[0100] , and the oxidation rate of this plane is slower than the oxidation rate of the plane tilted with respect to the

[0100] direction. In single-crystal silicon, the

[0010] direction is equivalent to the

[0100] direction. In the following explanation, the

[0100] direction and the

[0010] direction will be collectively referred to as the

[0100] direction.

[0059] Due to these differences in oxidation rates, as explained in relation to Figure 5, the thickness of the gate insulating layer 11 formed on the fifth surface S5 and the sixth surface S6 is thinner than the thickness of the gate insulating layer 11 formed on the other surfaces. Also, as explained in relation to Figure 7, the thickness of the insulating portion 21 formed on the fifth surface S5 and the sixth surface S6 is thinner than the thickness of the insulating portion 21 formed on the other surfaces.

[0060] As shown in Figure 14, n of the intermediate member I1 shown in Figure 13 - P-type impurities are ion-implanted into the surface of the fourth portion 1a of the p-type semiconductor layer 1s and the surface of the fifth portion 1b shown in Figure 4 to form a p-type semiconductor layer 2s and then an intermediate member I2. At this point, the p-type semiconductor layer 2s is formed with a nearly uniform impurity concentration throughout the intermediate member I2.

[0061] Furthermore, by forming the p-type semiconductor layer 2s, the region corresponding to the p-type semiconductor layer 2s is as shown in Figures 11 and 12. - The fifth surface S5 of the high-concentration region 1sa will be called the first surface S1, and the sixth surface S6 will be called the second surface S2.

[0062] Subsequently, as shown in Figure 15, a mask M2 is placed on the intermediate member I2 on which the p-type semiconductor layer 2s is formed. The mask M2 is positioned similarly to the mask M1 described in relation to Figure 9. That is, the mask M2 is positioned so as to expose the region of the p-type semiconductor layer 2s from the first surface S1 to the second surface S2, and cover the remaining region.

[0063] As shown in Figures 16 and 17, p-type impurities are implanted from above the intermediate member I2 on which the mask M2 is placed. In this case, the implantation angle can be 0° from the first direction D1. However, from the viewpoint of preventing channeling during ion implantation, it is preferable to implant at an angle of several degrees from the first direction D1. In the region where the mask M2 is not placed, a high-concentration p-type region 2sa is formed, and the impurity concentration of the p-type semiconductor layer 2s in the region where the mask M2 is formed remains almost the same as before impurity implantation.

[0064] Subsequently, the n shown in Figures 1 to 4 is applied to the p-type semiconductor layer 2s and the p-type high-density region 2sa. + Shape source region 3 and p + Contact region 4 is formed sequentially. Then, n + Drain electrodes E1 and n connected to the drain region 5 +A source electrode E2 connected to the p-type source region 3 and the p-type contact region 4, and a gate pad E3 connected to the gate electrode 10 are formed, respectively. In this way, the semiconductor device 100 according to the embodiment is manufactured.

[0065] The effects of the semiconductor device 100 according to this embodiment will be described. In the semiconductor device 100 according to the embodiment, the p-type base region 2 forms the channel of the MOSFET. The gate insulating layer 11 is formed by thermal oxidation, and on the silicon crystal plane corresponding to the

[0100] direction, the thickness of the gate insulating layer 11 due to thermal oxidation is thinner than the thickness of the gate insulating layer 11 corresponding to other directions. Therefore, the thickness of the gate insulating layer 11 in contact with the first plane S1 and the second plane S2, respectively, which are orthogonal to the second direction D2 corresponding to the

[0100] direction, is thinner than the thickness of the gate insulating layer 11 in contact with planes orthogonal to other directions. In the semiconductor device 100 according to the embodiment, the p-type impurity concentration in the first portion 2a, which is the region containing the first plane S1 and the second plane S2, is higher than the p-type impurity concentration in other portions. In the p-type base region 2, if the p-type impurity concentration is the same, the thinner the thickness of the gate insulating layer 11, the lower the gate threshold voltage. In the semiconductor device 100 according to this embodiment, the p-type impurity concentration in the first portion 1a is increased to compensate for the decrease in gate threshold voltage due to the reduction in the thickness of the gate insulating layer 11. As a result, the gate threshold voltage can be aligned in all directions of the p-type base region 2 that forms the channel, and the variation in resistance values ​​can be reduced in all channels of the semiconductor device 100, thereby reducing the on-resistance.

[0066] The gate threshold voltage can be made to match the gate threshold voltage on planes perpendicular to other directions if the impurity concentration near the first surface S1 and the second surface S2 in contact with the gate insulating layer 11 within the p-type base region 2 is higher than elsewhere.

[0067] When viewed from a first direction D1, the p-shaped base region 2, which includes the first surface S1 and the third surface S3 adjacent to the first surface S1, preferably has trenches (holes) with hexagonal walls. By making the opening shape of the trenches in the p-shaped base region 2 hexagonal, the shape of the gate electrode 10, which is positioned opposite the walls of the trenches, when viewed from the first direction D1, can be made hexagonal. By making the shape of the trenches in the p-shaped base region 2 forming the gate electrode 10 hexagonal, the trenches can be arranged to be as dense as possible. By arranging the trenches densely, the channel width per unit area can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0068] In the semiconductor device 100 according to the embodiment, one of the factors determining the withstand voltage between the drain and source is the conductive part 22 of the structure 20 and n - This is the pressure resistance between the drift region 1 and the structure 20. - In the shape drift region 1, the thickness of the insulating portion 21 in contact with the fifth surface S5 and the sixth surface S6, which are perpendicular to the second direction D2 corresponding to the silicon crystal plane

[0100] , is thinner than the thickness of the insulating portion 21 in contact with the surfaces perpendicular to the other directions. In the semiconductor device 100 according to the embodiment, n - Within the shape drift region 1, the impurity concentration in all regions except for the fourth portion 1a, which spans from the fifth surface S5 to the sixth surface S6, is lower than that of the fourth portion 1a. Therefore, the depletion layers on the fifth surface S5 and the sixth surface S6 can extend to a similar extent as can the depletion layers on the other surfaces, and the distance between the fifth surface S5 and the sixth surface S6 can be made approximately equal to the distance between the two surfaces in the other direction.

[0069] n - In the shaped drift region 1, a hexagonal trench is formed that is continuous with the p-shaped base region 2. In other words, the fifth surface S5 and the sixth surface S6 are the walls of the trenches that are continuous with the first surface S1 and the second surface S2, respectively. - By making the shape of the trench in the drift region 1 a hexagon, n - The distance between two faces located on opposite sides of the shaped drift region 1 is made approximately equal in each direction, n- The structures 20 provided in the trenches formed in the drift region 1 can be arranged most densely. As a result, a semiconductor device 100 with low on-resistance can be realized while achieving sufficient withstand voltage between the drain and source.

[0070] In the manufacturing method of the semiconductor device 100 according to the embodiment, impurities are injected into the fifth surface S1 of the semiconductor substrate S on which the aperture OP1 is formed, at an angle θ from the first direction D1 within a plane including the first direction D1 and the second direction D2. Furthermore, impurities are injected into the sixth surface S1 of the semiconductor substrate S on which the aperture OP1 is formed, at an angle -θ from the first direction D1 within a plane including the first direction D1 and the second direction D2. As a result, n - In the semiconductor layer 1s, the impurity concentration in the fourth portion 1a, which includes the fifth surface S5 and the sixth surface S6, can be made higher than the impurity concentration in the regions other than the fourth portion 1a.

[0071] Before the impurity injection step, the fifth surface S5 and the sixth surface S6 of the inner wall surface of the opening OP1 can be exposed, and a mask M1 can be placed to cover the surfaces other than the fifth surface S5 and the sixth surface S6. By placing the mask M1 in this way, a region with a high impurity concentration, including the fifth surface S5 and the sixth surface S6 corresponding to the silicon crystal plane

[0100] , can be stably and reliably formed.

[0072] (Second embodiment) Figure 18 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. Figure 19 is a cross-sectional view of the line XIX-XIX in Figure 18. Figure 20 is a cross-sectional view along the line XX-XX in Figure 18. Figure 18 shows a cross-section along the line XVIII-XVIII in Figure 19. As shown in Figures 18 to 20, the semiconductor device 200 according to this embodiment includes a structure 220 that is different from the semiconductor device 100 shown in Figure 1, etc. In this embodiment, the gate electrode 10 is provided separately from the structure 220. That is, the structure 220 does not include the gate electrode 10 and the gate insulating layer 11. The same reference numerals are used for identical components, and detailed descriptions are omitted.

[0073] As shown in Figures 18 to 20, the p-shaped base region 2 surrounds the structure 220. On the p-shaped base region 2, n + Shape source region 3 and p + Each of the contact regions 4 is provided. + Contact area 4 surrounds structure 220. + The shape source region 3 is p + It surrounds the contact area 4. + Shape source region 3 and p + A source electrode E2 is provided on the contact region 4, n + Shape source region 3 and p + The contact region 4 is electrically connected to the source electrode E2. The source electrode E2 is also provided on the structure 220 and is electrically connected to the conductive portion 22 of the structure 220. The gate insulating layer 11 is n - Part of the shape drift region 1, p-shaped base region 2 and n + It surrounds the source region 3. The gate electrode 10 is connected via the gate insulating layer 11, n - Part of the shape drift region 1, p-shaped base region 2 and n + It surrounds source region 3.

[0074] Similar to the first embodiment, the structures 220 are aligned along the second direction D2 and along the third direction D3. The conductive portion 22 of the structure 220 extends along the first direction D1, and the insulating portion 21 extends along the first direction D1, surrounding the conductive portion 22.

[0075] In the semiconductor device 200 according to this embodiment, a trench for the gate electrode 10 surrounds a hexagonal trench that houses the structure 220.

[0076] As shown in Figures 18 to 20, the p-shaped base region 2 includes a first portion 2a. The first portion 2a has a first surface S1a and a second surface S2a that are perpendicular to the second direction D2. The first surface S1a is the interface of the first portion 2a with the gate insulating layer 11. The second surface S2a is the surface located on the opposite side of the first surface S1a. The second surface S2a faces the insulating portion 21 and forms the interface with the insulating portion 21. The first portion 2a is the region between the first surface S1a and the second surface S2a within the p-shaped base region 2 surrounding the structure 220, and includes the first surface S1a and the second surface S2a.

[0077] Of the p-shaped base region 2, the region other than the first portion 2a is the other portion (second portion) 2b. The other portion 2b has, for example, a third surface S3a and a fourth surface S4a that are perpendicular to the third direction D3. The third surface S3a is the interface between the other portion 2b and the gate insulating layer 11. The fourth surface S4a is the surface located on the opposite side of the third surface S3a. The fourth surface S4a is the surface that faces the conductive portion 22 of the structure 220 and forms the interface with the insulating portion 21. The other portion 2b is the region of the p-shaped base region 2 between the third surface S3a and the fourth surface S4a, and includes the third surface S3a and the fourth surface S4a.

[0078] n deeper than gate electrode 10 and gate insulating layer 11 - In the shape drift region 1, the configuration is the same as in the first embodiment described above, and a detailed explanation is omitted.

[0079] The thickness of the gate insulating layer 11 formed on the first surface S1a of the first portion 2a is thinner than the thickness of the gate insulating layer 11 formed at the interface with the other portion 2b. Therefore, in the semiconductor device 200 according to this embodiment, similar to the first embodiment, the first portion 2a has a higher p-type impurity concentration than the p-type impurity concentration of the other portion 2b. As a result, the gate threshold voltage can be equalized in the p-type base region 2, reducing variations in channel resistance, thereby reducing the channel resistance in the p-type base region 2 and reducing the on-resistance.

[0080] Furthermore, as in the first embodiment, the insulating portion 21 becomes thinner in the second direction D2, so the depletion layer tends to spread. Therefore, by that amount n - The concentration of n-type impurities in the portion of the drift region 1 that is in contact with the insulating portion 21 can be increased, - The on-resistance in the drift region 1 can be reduced.

[0081] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0082] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0083] The embodiments include the following aspects:

[0084] (Note 1) First electrode and, A semiconductor layer disposed on the first electrode, A second electrode disposed on the semiconductor layer, Equipped with, The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type electrically connected to the first electrode, A second semiconductor region of a second conductivity type is disposed on the first semiconductor region and electrically connected to the second electrode, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region and electrically connected to the second electrode, A plurality of structures are arranged side by side in a second direction perpendicular to the first direction toward the semiconductor layer from the first electrode and corresponding to the

[0100] direction of the silicon crystal plane, and in a third direction perpendicular to the first direction and tilted with respect to the second direction at an angle greater than 0° and less than 90°, A plurality of gate electrodes are arranged opposite the second semiconductor region via an oxide film in the second and third directions, Includes, Each of the plurality of structures is arranged in the second and third directions alongside a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region. An insulating part containing oxides, A conductive portion is provided in the insulating portion, including a portion facing the first semiconductor region in the second and third directions, and electrically connected to the second electrode, Includes, The second semiconductor region has a first surface perpendicular to the second direction and forming an interface with the oxide film, a second surface located opposite the first surface, a third surface perpendicular to the third direction and forming an interface with the oxide film, and a fourth surface located opposite the third surface. A semiconductor device in which the impurity concentration of the second conductivity type on the first surface is higher than the impurity concentration of the second conductivity type on the third surface.

[0085] (Note 2) The plurality of structures include a first structure, a second structure, and a third structure, The second structure is aligned with the first structure in the second direction, The third structure is aligned with the first structure in the third direction, The plurality of gate electrodes include a first gate electrode, a second gate electrode, and a third gate electrode that are electrically connected to each other. The first gate electrode surrounds at least a portion of the first structure and faces the first and third surfaces, The second gate electrode surrounds at least a portion of the second structure and faces the second surface, The third gate electrode surrounds at least a portion of the third structure and faces the fourth surface, The semiconductor device according to Appendix 1, wherein the impurity concentration of the second conductivity type in the first portion of the second semiconductor region having the first and second surfaces is higher than the impurity concentration of the second conductivity type in the second portion of the second semiconductor region having the third and fourth surfaces.

[0086] (Note 3) The first part comprises one portion having the first surface and the other portion having the second surface. The semiconductor device according to Appendix 2, wherein the impurity concentration of the second conductivity type in the third portion between the one portion and the other portion is lower than the impurity concentration of the second conductivity type in either the one portion or the other portion.

[0087] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein, when viewed from the first direction, the shape of the outer periphery of the oxide film adjacent to the first surface and the third surface is hexagonal.

[0088] (Note 5) The semiconductor device described in any one of the appendices 1 to 4, wherein the distance between the first surface and the second surface is equal to the distance between the third surface and the fourth surface.

[0089] (Note 6) The conductive portion includes a first conductive portion included in the first structure, a second conductive portion included in the second structure, and a third conductive portion included in the third structure. The first semiconductor region is, A fifth surface facing the first conductive portion and perpendicular to the second direction, A sixth surface located on the opposite side of the fifth surface, facing the second conductive portion, and perpendicular to the second direction, A seventh surface facing the first conductive portion and perpendicular to the third direction, An eighth surface located on the opposite side of the seventh surface, facing the third conductive portion, and perpendicular to the third direction, Includes, The semiconductor device according to Appendix 2 or 3, wherein the carrier concentration of the first conductivity type in the fifth part, which is the other part of the fourth part including the fifth and sixth surfaces, is lower than the carrier concentration of the first conductivity type in the fourth part.

[0090] (Note 7) The semiconductor device according to Appendix 6, wherein, when viewed from the first direction, the shape of the outer periphery of the oxide film adjacent to the fifth and seventh surfaces is hexagonal.

[0091] (Note 8) The semiconductor device according to Appendix 6 or 7, wherein the distance between the fifth surface and the sixth surface is equal to the distance between the seventh surface and the eighth surface.

[0092] (Note 9) Each of the plurality of gate electrodes surrounds each of the plurality of structures, The second semiconductor region is provided between the gate electrode and the plurality of structures, The second and fourth surfaces face the insulating portion, The semiconductor device according to Appendix 1, wherein the impurity concentration of the second conductivity type in the first portion including the first and second surfaces is higher than the impurity concentration of the second conductivity type in the second portion including the third and fourth surfaces.

[0093] (Note 10) An intermediate member having a semiconductor layer containing an impurity of a first conductivity type, wherein the semiconductor layer has a plurality of openings, each having a first surface extending in the thickness direction and a second surface facing the first surface as side walls, and the plurality of openings are filled with an insulator and a conductor, a step of preparing an intermediate member, The intermediate member comprises the step of injecting the second conductivity type impurity from the first direction, which is the thickness direction of the semiconductor layer, A step of placing a first mask that covers the other surfaces that constitute the side walls of the opening, other than the first and second surfaces when viewed from the first direction, After positioning the first mask, a step is taken to further inject the impurity of the second conductivity type from the first direction, A method for manufacturing a semiconductor device equipped with [the specified features].

[0094] (Note 11) The step of preparing the intermediate member is: A step of preparing a semiconductor substrate having a plurality of openings each having a first surface perpendicular to the first direction and corresponding to the

[0100] direction of the crystal plane of silicon, and a second surface disposed opposite to the first surface, and a third direction orthogonal to the first direction and inclined at an angle greater than 0° and less than 90° with respect to the second direction; A step of disposing a second mask that covers the other surfaces constituting the side walls of the openings other than the first surface and the second surface when viewed from the first direction; After disposing the second mask, a step of implanting impurities of the first conductivity type toward the first surface at an angle greater than 0° and less than 50° from the first direction in a plane including the first direction and the second direction; After disposing the second mask, a step of implanting impurities of the first conductivity type toward the second surface at an angle greater than -50° and less than 0° from the first direction in the plane including the first direction and the second direction; The method of manufacturing a semiconductor device according to Appendix 10, including the above steps.

Explanation of Symbols

[0095] 1…n - Shape drift region 1a…Fourth part 1b…Fifth part 1s…n - Shape semiconductor layer 1sa…n - Shape high-concentration region 2…p-type base region 2a…First part 2b…Other parts 2b1…Second part 3…n + Shape source region 10…Gate electrode 10a…First gate electrode 10b…Second gate electrode 10c…Third gate electrode 11…Gate insulating layer 11a…First gate insulating layer 11b...Second gate insulating layer, 11c...Third gate insulating layer, 20, 220...Structure, 20a...First structure, 20b...Second structure, 20c...Third structure, 21...Insulating part, 21a...First insulating section, 21b...Second insulating section, 21c...Third insulating section, 22...Conductive part, 22a...First conductive part, 22b...second conductive part, 22c...Third conductive part, 100, 200... Semiconductor equipment

Claims

1. First electrode and, A semiconductor layer disposed on the first electrode, A second electrode disposed on the semiconductor layer, Equipped with, The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type electrically connected to the first electrode, A second semiconductor region of a second conductivity type is disposed on the first semiconductor region and electrically connected to the second electrode, A third semiconductor region of a first conductivity type is disposed on the second semiconductor region and electrically connected to the second electrode, A plurality of structures are arranged side by side in a second direction perpendicular to the first direction toward the semiconductor layer from the first electrode and corresponding to the [100] direction of the silicon crystal plane, and in a third direction perpendicular to the first direction and inclined with respect to the second direction at an angle greater than 0° and less than 90°, A gate electrode positioned opposite the second semiconductor region via an oxide film in the second and third directions, Includes, Each of the plurality of structures is arranged in the second and third directions alongside a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region. An insulating part containing oxides, A conductive portion is provided in the insulating portion, including a portion facing the first semiconductor region in the second and third directions, and electrically connected to the second electrode, Includes, The second semiconductor region has a first surface perpendicular to the second direction and forming an interface with the oxide film, a second surface located opposite the first surface, a third surface perpendicular to the third direction and forming an interface with the oxide film, and a fourth surface located opposite the third surface. A semiconductor device in which the impurity concentration of the second conductivity type on the first surface is higher than the impurity concentration of the second conductivity type on the third surface.

2. The plurality of structures include a first structure, a second structure, and a third structure, The second structure is aligned with the first structure in the second direction, The third structure is aligned with the first structure in the third direction, The gate electrode includes a first gate electrode, a second gate electrode, and a third gate electrode that are electrically connected to each other. The first gate electrode surrounds at least a portion of the first structure and faces the first and third surfaces, The second gate electrode surrounds at least a portion of the second structure and faces the second surface, The third gate electrode surrounds at least a portion of the third structure and faces the fourth surface, The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type in the first portion having the first surface and the second surface is higher than the impurity concentration of the second conductivity type in the second portion having the third surface and the fourth surface.

3. The first part comprises one portion having a first surface and the other portion having a second surface. The semiconductor device according to claim 2, wherein the impurity concentration of the second conductivity type in the third portion between the one portion and the other portion is lower than the impurity concentration of the second conductivity type in either the one portion or the other portion.

4. The semiconductor device according to claim 1, wherein, when viewed from the first direction, the peripheral shape including the first surface and the third surface is hexagonal.

5. The semiconductor device according to claim 1, wherein the distance between the first surface and the second surface is equal to the distance between the third surface and the fourth surface.

6. The conductive portion includes a first conductive portion, a second conductive portion, and a third conductive portion. The first semiconductor region is, A fifth surface facing the first conductive portion and perpendicular to the second direction, A sixth surface located on the opposite side of the fifth surface, facing the second conductive portion, and perpendicular to the second direction, A seventh surface facing the first conductive portion and perpendicular to the third direction, An eighth surface located on the opposite side of the seventh surface, facing the third conductive portion, and perpendicular to the third direction, Includes, The semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type in the fifth portion, which is the other portion of the fourth portion including the fifth and sixth surfaces, is lower than the impurity concentration of the first conductivity type in the fourth portion.

7. The semiconductor device according to claim 6, wherein, when viewed from the first direction, the peripheral shape including the fifth and seventh surfaces is hexagonal.

8. The semiconductor device according to claim 6, wherein the distance between the fifth surface and the sixth surface is equal to the distance between the seventh surface and the eighth surface.

9. The gate electrode surrounds each of the plurality of structures, The second semiconductor region is provided between the gate electrode and the plurality of structures, The second and fourth surfaces face the insulating portion, The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type in the first portion including the first and second surfaces is higher than the impurity concentration of the second conductivity type in the second portion including the third and fourth surfaces.

10. The intermediate member having a semiconductor layer containing an impurity of a first conductivity type, wherein the semiconductor layer is a semiconductor layer having a plurality of openings, each having a first surface extending in the thickness direction and a second surface facing the first surface, and the plurality of openings are filled with an insulator and a conductor, the step of preparing the intermediate member, The intermediate member comprises the step of injecting the second conductivity type of impurity from the first direction, which is the thickness direction of the semiconductor layer, A step of arranging a mask that covers the other surfaces of the first and second surfaces that face the opening when viewed from the first direction, After placing the mask, the process involves further injecting the impurity of the second conductivity type from the first direction, A method for manufacturing a semiconductor device equipped with [the specified features].

11. The step of preparing the intermediate member is: A step of preparing a semiconductor substrate having a plurality of openings, each having a first surface perpendicular to the second direction and a second surface positioned opposite the first surface, which is formed in a second direction perpendicular to the first direction and corresponding to the [100] direction of the silicon crystal plane, and a third direction perpendicular to the first direction and inclined with respect to the second direction at an angle greater than 0° and less than 90°, the first surface perpendicular to the second direction and the second surface positioned opposite the first surface, A step of injecting an impurity of a first conductivity type toward the first plane at an angle greater than 0° and less than 90° from the first direction within a plane including the first and second directions, A step of injecting an impurity of the first conductivity type toward the second surface at an angle greater than -90° and less than 0° from the first direction within the plane including the first and second directions, A method for manufacturing a semiconductor device according to claim 10, including the following:

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