Semiconductor memory device and method for manufacturing a semiconductor memory device

Abstract

To reduce the dummy area at the edge of the laminate. [Solution] The semiconductor memory device of the embodiment comprises a laminate including a plurality of conductive layers and a plurality of first insulating layers stacked alternately one layer at a time; a plurality of slits extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction; and a plurality of pillars arranged between the plurality of slits and extending within the laminate in the stacking direction, wherein the entire upper end of the first slit located closest to the edge of the laminate in the second direction is covered with the first material, and a portion of the upper end of each of the plurality of second slits, excluding the first slit, is covered with the first material.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

Background Art

[0002] A semiconductor memory device such as a three-dimensional non-volatile memory includes, for example, a stacked body in which a plurality of conductive layers are stacked, and memory cells are three-dimensionally arranged at the height positions of the individual conductive layers. In order to suppress variations in the characteristics of the memory cells, the vicinity of the end of the stacked body is a dummy region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can reduce the dummy region at the end of the stacked body.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a laminate including a plurality of conductive layers and a plurality of first insulating layers stacked alternately one layer at a time; a plurality of slits extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction; and a plurality of pillars arranged between the plurality of slits and extending within the laminate in the stacking direction, wherein the entire upper end of the first slit located closest to the edge of the laminate in the second direction is covered with a first material, and a portion of the upper end of each of the plurality of second slits, excluding the first slit, is covered with the first material. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing a schematic example of the configuration of a semiconductor memory device according to an embodiment. [Figure 2] A schematic diagram showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 3] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 5] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 9] A diagram illustrating, in order, some of the steps of a semiconductor memory manufacturing method according to an embodiment. [Figure 10] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to a modified embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0008] (Example of semiconductor memory device configuration) Figure 1 is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, Figure 1(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction, and Figure 1(b) is a schematic plan view showing the layout of the semiconductor memory device 1.

[0009] However, in Figure 1(a), hatching is omitted for the sake of readability. Also, in Figure 1(a), components that do not necessarily exist in the same cross-section are shown, and some upper-level wiring, etc., are omitted.

[0010] Furthermore, in this specification, both the X and Y directions are directions along the orientation of the surface of the word line WL, and the X and Y directions are orthogonal to each other. The electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is along the X direction. The direction intersecting the first direction may be referred to as the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing tolerances, the first direction and the second direction are not necessarily orthogonal.

[0011] As shown in Figure 1(a), the semiconductor memory device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, one or more selection gate lines SGS, multiple word lines WL, one or more selection gate lines SGD, and a semiconductor substrate SB on which peripheral circuits CBA are provided.

[0012] A source wire SL is arranged on the electrode film EL via an insulating layer 60. Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film EL via the plugs PG. Although not shown in the diagram, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are provided in the same layer as the electrode film EL. A selection gate wire SGS, multiple word wires WL, and a selection gate wire SGD are stacked on the source wire SL in this order.

[0013] As shown in Figures 1(a) and 1(b), a memory area MR is located in the center of multiple word lines WL in the X direction, and stepped areas SR are located at both ends of the multiple word lines WL in the X direction. These memory areas MR and stepped areas SR are divided into multiple regions by multiple plate-like portions LI that penetrate the multiple word lines WL and extend in a direction along the X direction.

[0014] Furthermore, the area located between adjacent plate-shaped sections LI in the Y direction, and including the memory area MR and the step area SR, is called the block area BLK. As will be described later, the memory area MR contains multiple memory cells that hold data non-volatilely, and the block area BLK described above serves as the unit for erasing this data.

[0015] Furthermore, between adjacent plate-like portions LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the selected gate line SGD. These multiple isolation layers SHE extend in the direction along the X direction throughout the entire memory area MR, and also reach a portion of the stepped area SR at both ends in the X direction.

[0016] In the memory region MR, multiple pillars PL are arranged that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction. The lower end of each pillar PL reaches the source line SL. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR. Therefore, the semiconductor memory device 1 of this embodiment is also a semiconductor memory device.

[0017] In the staircase region SR, a plurality of word lines WL and selection gate lines SGD, SGS are processed in a staircase shape and terminated. At this time, as moving away from the memory region MR in the X direction, since the plurality of word lines WL and selection gate lines SGD, SGS constituting the terrace portion move from the upper layer side to the lower layer side, the height position of the terrace portion goes down toward the source line SL side.

[0018] In this specification, the direction in which the terrace surfaces of the plurality of word lines WL and selection gate lines SGD, SGS face is defined as the upper side of the semiconductor memory device 1.

[0019] The above-described isolation layer SHE extends from the memory region MR to the portion where the selection gate line SGD of the staircase region SR is processed in a staircase shape. Thereby, within one block region BLK, the selection gate line SGD is separated into a plurality of regions. In other words, by the isolation layer SHE penetrating the upper layer portion of the plurality of word lines WL, these upper layer portions are partitioned into the patterns of the plurality of selection gate lines SGD.

[0020] Contact CCs connected to the word lines WL and selection gate lines SGD, SGS of each layer are respectively arranged in each terrace portion constituted by the plurality of word lines WL and selection gate lines SGD, SGS. In the word line WL and the selection gate line SGS, one contact CC is connected for each layer. In the selection gate line SGD, one contact CC is connected for each partition separated by the isolation layer SHE for each layer.

[0021] Here, within one block region BLK, the plurality of contact CCs are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, for example, the plurality of contact CCs are arranged for every two block regions BLK.

[0022] In other words, in the example shown in Figure 1(b), in the block region BLK at the very top of the page, multiple contact CCs are located in the stair region SR on the left side of the page, among the stair regions SR at both ends in the X direction. Furthermore, in the block region BLK one level below and two levels below the above block region BLK, multiple contact CCs are located in the stair region SR on the right side of the page, among the stair regions SR at both ends in the X direction. Moreover, in the block region BLK at the very bottom of the page, multiple contact CCs are again located in the stair region SR on the left side of the page.

[0023] Therefore, as shown in Figure 1(a), the respective contact CCs of the stair region SR at both ends in the X direction belong to different block regions BLK and are not actually located in the same cross-section.

[0024] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells included in the memory region MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells.

[0025] Multiple word lines WL, selection gate lines SGD, SGS, pillar PL, and contact CC are covered by an insulating layer 50. The insulating layer 50 also extends around these components, including the multiple word lines WL, etc.

[0026] The semiconductor substrate SB above the insulating layer 50 covering the above configuration is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0027] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers multiple word lines WL, etc., a semiconductor memory device 1 is formed that includes multiple word lines WL, selection gate lines SGD, SGS, pillar PL, contact CC, etc., and the peripheral circuit CBA.

[0028] Next, we will describe a detailed configuration example of the semiconductor memory device 1 using Figures 2 and 3.

[0029] Figure 2 is a schematic diagram showing an example of the configuration of a semiconductor memory device 1 according to an embodiment. More specifically, Figure 2 is an XY cross-sectional view of the semiconductor memory device 1 at the height position of the selected gate line SGD, showing the vicinity of the end position in the Y direction of the laminate LM, which includes the above-mentioned plurality of word lines WL and selected gate lines SGD,SGS.

[0030] As shown in Figure 2, multiple pillars PL are arranged in a periodic pattern within each block region BLK sandwiched between multiple plate-like sections LI. In the example in Figure 2, these pillars PL are arranged in a staggered pattern when viewed from above. However, these pillars PL may have other periodic arrangements, such as a grid pattern.

[0031] Furthermore, within one block region BLK between adjacent plate-like portions LI in the Y direction, multiple separation layers SHE, which separate the selected gate line SGD into multiple sections, extend in the direction along the X direction, as described above. In this case, in order to maintain a periodic arrangement in the multiple pillars PL, the separation layers SHE may overlap with some of the arrangements of the multiple pillars PL extending in the direction along the X direction when viewed from above.

[0032] In this way, by maintaining a periodic arrangement in multiple pillars PL, individual pillars PL can be formed more precisely and with reduced processing errors during the manufacturing process of the semiconductor memory device 1 described later.

[0033] Furthermore, as described above, stair regions SR (see Figure 1(b)) are arranged on both sides in the X direction of each block region BLK. The stair regions SR are exclusively filled with contact CCs connected to each layer, such as word lines WL. Therefore, dummy pillars (not shown) that follow the periodic arrangement of the multiple pillars PL described above are placed in the surplus space in the stair regions SR. This makes it possible to form individual pillars PL at both ends in the X direction of the memory region MR with greater precision and while suppressing machining errors.

[0034] On the other hand, a dummy block region BLKd is positioned at the Y-direction end of the laminate LM. The dummy block region BLKd is positioned adjacent to the multiple block regions BLK aligned in the Y-direction, further outward in the Y-direction, and is the region between the dummy plate-like portion LId on the outward Y-direction and the plate-like portion LI adjacent to this dummy plate-like portion LId in the Y-direction.

[0035] In other words, the dummy plate-like portion LId is positioned furthest outward in the Y direction among the multiple plate-like portions LI,LId. One difference between the dummy plate-like portion LId and the multiple plate-like portions LI mentioned above is that the shapes of the bridging portions BR and BRw at the upper ends of the plate-like portions LI,LId are different.

[0036] Each of the multiple plate-like portions LI has multiple bridging portions BR at its upper end, arranged along the X direction at predetermined intervals. These multiple bridging portions BR of each plate-like portion LI may be positioned approximately equal to each other in the X direction and aligned in the Y direction between the multiple plate-like portions LI, as shown in the example in Figure 2. Alternatively, these bridging portions BR may be positioned at different locations in the X direction between the multiple plate-like portions LI and may not be aligned in the Y direction.

[0037] In the dummy block region BLKd, multiple dummy pillars PLd are arranged in place of the multiple pillars PL described above. These dummy pillars PLd do not contribute to the function of the semiconductor memory device 1 and are provided at both ends of the stacked body LM in the Y direction to suppress variations in memory cell characteristics at both ends of the stacked body LM in the Y direction. Furthermore, the region between the plate-like parts LI and LId where these pillars PLd are arranged also becomes a dummy block region BLKd that does not contribute to the function of the semiconductor memory device 1.

[0038] Furthermore, the arrangement of pillars PLd in the dummy block region BLKd follows the periodic arrangement of pillars PL in the block region BLK described above. That is, in the example in Figure 2, the dummy pillars PLd are also arranged in a staggered pattern, and in order to maintain the periodicity of these pillar PLd arrangements, some of the pillar PLd arrangements may overlap with the separation layer SHE.

[0039] In this way, by providing dummy pillar PLd, it becomes possible to form multiple pillar PLs that contribute to the function of the semiconductor memory device 1 with greater precision at both ends in the Y direction, while suppressing processing errors.

[0040] Furthermore, beyond a predetermined position in the Y direction between the plate-like sections LI and LId, and further outside the plate-like section LId, the laminated body LM is transformed into laminated body LMs, in which multiple sacrificial layers are laminated in place of the multiple word lines WL and the like that provided by the laminated body LM. Further outside the plate-like section LId in the Y direction, a dummy step region SRd is positioned, and each layer of the laminated body LMs is processed into a step shape extending in the Y direction and terminates there.

[0041] As will be described later, the dummy step region SRd is a step-shaped region that is secondarily formed when the step region SR is formed during the manufacturing of the semiconductor memory device 1. For this reason, unlike the aforementioned step region SR (see Figure 1(b)) which is located on both sides of the stacked body LM in the X direction, the step region SRd does not function as a word line WL lead-out region, and contacts CC, etc., are not placed there. Furthermore, since the step region SRd is an inactive region that does not contribute to the function of the semiconductor memory device 1, the area of ​​the step region SRd in the semiconductor memory device 1 is smaller than that of the aforementioned step region SR.

[0042] Although not shown in Figure 2, the dummy stair region SRd and the area outside the stair region SRd in the Y direction are also covered by the insulating layer 50 described above (see Figure 1(a)).

[0043] Figure 3 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 1 according to an embodiment.

[0044] More specifically, Figures 3(a) and 3(b) are cross-sectional views along the Y direction in the memory region MR of the semiconductor memory device 1. Of these, Figure 3(a) shows a cross-section of the block region BLK described above, and Figure 3(b) shows a cross-section of the dummy block region BLKd described above. Note that in Figures 3(a) and 3(b), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0045] Figure 3(c) is an enlarged cross-sectional view of pillar PL in the selected gate lines SGD and SGS. Figure 3(d) is an enlarged cross-sectional view of pillar PL at the height of the word line WL.

[0046] As shown in Figure 3(a), in the block region BLK, the source wire SL has a multilayer structure in which, for example, a lower source wire DSLa, an intermediate source wire BSL, and an upper source wire DSLb are stacked on the insulating layer 60 in this order. The lower source wire DSLa, the intermediate source wire BSL, and the upper source wire DSLb are, for example, polysilicon layers. Of these, at least the intermediate source wire BSL may be a conductive polysilicon layer with diffused impurities.

[0047] The source wire SL is connected to the peripheral circuit CBA via the electrode film EL through a through-contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA, within the aforementioned insulating layer 50 on the outside of the laminate LM.

[0048] A laminate LM is placed on the source line SL. The laminate LM comprises laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time.

[0049] The LMa laminate is positioned above the source line SL. Below the bottommost word line WL of the LMa laminate, multiple selectable gate lines SGS0 and SGS1 are arranged in this order from the top of the LMa laminate, via an insulating layer OL. The LMb laminate is positioned on top of the LMa laminate. Above the topmost word line WL of the LMB laminate, multiple selectable gate lines SGD0 and SGD1 are arranged in this order from the top of the LMB laminate, via an insulating layer OL.

[0050] However, the number of layers of these word lines WL and selective gate lines SGD,SGS in the laminate LM is arbitrary. The word lines WL and selective gate lines SGD,SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0051] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53 each constitute a part of the insulating layer 50 in Figure 1.

[0052] As described above, the laminate LM is divided in the Y direction by multiple plate-like portions LI. That is, each of the plate-like portions LI is aligned with each other in the Y direction and extends in a direction along the stacking direction and the X direction of the laminate LM.

[0053] Thus, the plate-like portion LI extends continuously within the laminate LM from one end in the X direction to the other end. Furthermore, the plate-like portion LI penetrates the laminate LM and the upper source line DSLb to reach the intermediate source line BSL.

[0054] The plate-like portion LI has a tapered shape in which its width in the Y direction decreases from the upper end to the lower end, for example. Alternatively, the plate-like portion LI has a bowing shape in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end, for example.

[0055] Each plate-shaped portion LI includes an insulating layer 54, a conductive layer 24, and a cross-linking portion BR. The insulating layer 54 is, for example, a silicon oxide layer. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer. The cross-linking portion BR is, like the insulating layer 54, for example, a silicon oxide layer. The cross-linking portion BR may also be a polysilicon layer or the like.

[0056] The insulating layer 54 covers the side walls of the plate-shaped portion LI facing in the Y direction. The conductive layer 24 is filled inside the insulating layer 54. As shown in Figure 2 above, the cross-linked portion BR covers a portion of the upper end of the conductive layer 24 in the plate-shaped portion LI that extends in the direction along the X direction.

[0057] In the example shown in Figure 2 above, the bridging portions BR are arranged in the Y direction between multiple plate-like portions LI. In Figure 3(a), however, the plate-like portions LI with and without bridging portions BR are shown separately. The left side of the paper shows the cross-section of the plate-like portion LI with bridging portions BR, and the right side shows the cross-section of the plate-like portion LI without bridging portions BR.

[0058] Between adjacent plate-like portions LI in the Y direction, multiple isolation layers SHE are arranged, extending in the direction along the X direction and penetrating the upper portion of the laminate LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the selection gate lines SGD0 and SGD1 and reach the insulating layer OL directly below the selection gate line SGD1.

[0059] In other words, these separation layers SHE, which penetrate the upper portion of the laminated LMb, extend in the X direction between the plate-like portions LI, dividing the upper portion of the laminated LMb into the aforementioned selected gate lines SGD0 and SGD1.

[0060] In the memory region MR, multiple pillars PL are distributed and penetrate the stacked structure LM, the upper source line DSLb, and the intermediate source line BSL, reaching the lower source line DSLa. Each pillar PL has a cross-sectional shape in the direction along the layer direction of the stacked structure LM, i.e., along the XY plane, such as a circular, elliptical, or oval shape.

[0061] Furthermore, the pillar PL has a tapered shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area decrease from the upper layer side to the lower layer side. Alternatively, the pillar PL has a bowing shape in the portion that penetrates the laminate LMa and the portion that penetrates the laminate LMb, where the diameter and cross-sectional area are maximized at a predetermined position between the upper and lower layers, for example.

[0062] Each of the multiple pillar PLs has a memory layer ME extending in the stacking direction within the laminate LM, a channel layer CN penetrating the laminate LM and connecting to the intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0063] More specifically, the channel layer CN is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. That is, the memory layer ME is located on the side of the pillar PL, excluding the depth of the intermediate source line BSL. The memory layer ME is also located on the bottom surface of the pillar PL, which extends to the depth of the lower source line DSLa.

[0064] As described above, the channel layer CN further penetrates the stack LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa, and is in contact with the intermediate source line BSL on its side. This electrically connects the channel layer CN to the source line SL, including the intermediate source line BSL.

[0065] Furthermore, the cap layer CP is positioned at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. In addition, the cap layer CP is connected to the bit wire BL, which is located in the insulating layer 53, via a plug CH located in the insulating layer 52. The bit wire BL extends above the laminate LM in a direction along the Y direction so as to intersect with the drawing direction of the word wire WL.

[0066] In Figure 3(a), the separation layer SHE is positioned between multiple adjacent pillars PL in the Y direction. However, as shown in the example in Figure 2, the separation layer SHE may be positioned to overlap with several pillars PL in the stacking direction of the laminate LM. In this case, since the separation layer SHE penetrates the upper end of the pillars PL up to the height of the selected gate line SGD, these pillars PL may be treated as dummy pillars.

[0067] Furthermore, in Figure 3(a), plug CH is connected only to three of the six pillar PLs, each of which is electrically connected to the bit line BL shown in Figure 3(a) and passes through the three separated selection gate lines SGD. The other pillar PLs are connected to other bit lines BL that extend parallel to the bit line BL shown in Figure 3(a) in the Y direction, at positions different from the cross-section shown in Figure 3(a), via plug CH, which is not shown in Figure 3(a).

[0068] As shown in Figures 3(c) and 3(d), the memory layer ME has a stacked structure including a block insulating layer BK, a tunnel insulating layer TN, and a charge storage layer CT.

[0069] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer. The channel layer CN and cap layer CP are semiconductor layers, for example, polysilicon layers or amorphous silicon layers.

[0070] As shown in Figure 3(d), with the above configuration, memory cells MC are formed in the portions of the pillar PL side surface that face each word line WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL.

[0071] As shown in Figure 3(c), selection gate STD is formed on the side of pillar PL where it faces the selection gate lines SGD0 and SGD1 which are above the word line WL. Also, selection gate STS is formed on the side of pillar PL where it faces the selection gate lines SGS0 and SGS1 which are below the word line WL.

[0072] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS can be turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong.

[0073] As shown in Figure 3(b), the dummy block region BLKd is positioned between the plate-like portion LI, which is located on the block layer BLK side adjacent to the block region BLKd in the Y direction, and the dummy plate-like portion LId, which is further outside the block region BLKd in the Y direction and separates the block region BLKd from the area where the aforementioned dummy stair region SRd etc. are located.

[0074] In the Y-direction outward region of the dummy block region BLKd, that is, the region on the right side of the plane of the dummy plate-like portion LId, an intermediate sacrificial layer SCN is placed in place of the intermediate source line BSL of the source line SL.

[0075] In other words, corresponding to the lower source line DSLa, intermediate source line BSL, and upper source line DSLb located in the block region BLKd, the lower source line DSLa, intermediate sacrificial layer SCN, and upper source line DSLb are arranged in the block region BLKd in that order from the insulating layer 60 side.

[0076] The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and functions as a sacrificial layer when forming an intermediate source line BSL in the block region BLK during the manufacturing process of the semiconductor memory device 1 described later. In the block region BLKd, the intermediate source line BSL is not formed from the intermediate sacrificial layer SCN, and the sacrificial layer SCN remains as is.

[0077] Furthermore, in block region BLKd, above the upper source line DSLb, multiple word lines WL and selection gate lines SGD and SGS are stacked, and instead of the stacked LM having stacked LMa and LMb, multiple insulating layers NL are stacked, and a stacked LMs having stacked LMsa and LMsb is arranged.

[0078] In other words, the laminate LMs consists of multiple insulating layers NL and multiple insulating layers OL stacked alternately, forming laminates LMsa and LMsb. Laminate LMsa corresponds to laminate LMa in block region BLK and is located above the upper source line DSLb. Laminate LMsb corresponds to laminate LMb in block region BLK and is located on top of laminate LMsa.

[0079] The multiple insulating layers NL contained in the laminates LMsa and LMsb are, for example, silicon nitride layers, and function as sacrificial layers when forming word lines WL of the laminate LM in the manufacturing process of the semiconductor memory device 1 described later. In the block region BLKd, word lines WL are not formed from the insulating layers NL, and the sacrificial insulating layers NL remain as they are.

[0080] Furthermore, the number of insulating layers NL contained in the laminate LMsa is equal to the total number of word lines WL and select gate lines SGS contained in the laminate LMa of the block region BLK. Similarly, the number of insulating layers NL contained in the laminate LMsb is equal to the total number of word lines WL and select gate lines SGD contained in the laminate LMb of the block region BLK. In addition, insulating layers 52 and 53 covering the upper surface of the laminate LM also cover the upper surface of the laminate LMs.

[0081] The laminated LMs configured in this way, and the intermediate sacrificial layer SCN interposed between the lower source line DSLa and the upper source line DSLb, may also be arranged in a portion of the block region BLKd. That is, in this case, the laminated LMs and the intermediate sacrificial layer SCN are arranged on both sides in the Y direction, flanking the dummy plate-like portion LId, as shown in Figure 2 above.

[0082] Therefore, within the dummy block region BLKd, the laminate LM and intermediate source line BSL may be arranged within a predetermined distance in the Y direction from the plate-like portion LI on one side in the Y direction, and the laminate LMs and intermediate sacrificial layer SCN may be arranged within a predetermined distance in the Y direction from the plate-like portion LId on the other side in the Y direction.

[0083] In this case, the laminate LM and the laminate LMs do not necessarily have a clear boundary, and the laminate LM may gradually be replaced by the laminate LMs as metal atoms such as tungsten contained in the word line WL of the laminate LM are gradually replaced by molecules such as silicon nitride contained in the insulating layer NL of the laminate LMs.

[0084] Furthermore, there does not necessarily have to be a clear boundary between the intermediate source line (BSL) and the intermediate sacrificial layer (SCN). The intermediate source line (BSL) may gradually be replaced by the intermediate sacrificial layer (SCN) as atoms such as silicon contained in the intermediate source line (BSL) are gradually replaced by molecules such as silicon nitride contained in the intermediate sacrificial layer (SCN).

[0085] The laminated LM and intermediate source wire BSL may occupy at least half of the block region BLKd. However, the volume occupied by the laminated LM and intermediate source wire BSL within the block region BLKd may vary depending on the conditions in the manufacturing process of the semiconductor memory device 1 described later. Therefore, the laminated LM and intermediate source wire BSL may occupy more than half of the volume within the block region BLKd, or they may occupy the entire block region BLKd.

[0086] Furthermore, in the example shown in Figure 3(b), the boundary between the laminate LM and the laminate LMs, and the boundary between the intermediate source line BSL and the intermediate sacrificial layer SCN are located approximately equal in distance from the plate-like portion LI on one side of the block region BLKd. However, these boundaries may be located at different distances from the plate-like portion LI on one side of the block region BLKd. For example, the distance from the plate-like portion LI of the boundary between the laminate LM and the laminate LMs may be shorter than the distance from the plate-like portion LI of the boundary between the intermediate source line BSL and the intermediate sacrificial layer SCN.

[0087] The dummy plate-like portion LId is positioned on one side of the block region BLKd in the Y direction and extends continuously within the laminate LMs from one end to the other in the X direction, along the stacking direction and the X direction of the laminate LMs. Furthermore, the plate-like portion LId penetrates the laminate LMs and the upper source line DSLb to reach the intermediate sacrificial layer SCN.

[0088] The plate-like portion LId has a tapered shape, for example, in which its width in the Y direction decreases from the upper end to the lower end. Alternatively, the plate-like portion LId has a bowing shape, for example, in which its width in the Y direction is maximum at a predetermined position between the upper end and the lower end.

[0089] Furthermore, the plate-like portion LId includes an insulating layer 54, a sacrificial layer 25, and a crosslinking portion BRw. The sacrificial layer 25 is, for example, an amorphous silicon layer, and functions as a sacrificial layer until the conductive layer 24 is formed on the plate-like portion LI during the manufacturing process of the semiconductor memory device 1, which will be described later. In the plate-like portion LId, the conductive layer 24 is not formed, and the sacrificial layer 25 remains as is. The crosslinking portion BRw is, like the insulating layer 54 and the crosslinking portion BR of the plate-like portion LI, for example, a silicon oxide layer. The crosslinking portion BRw may also be a polysilicon layer or the like.

[0090] The insulating layer 54 also covers the side walls facing in the Y direction in the plate-like portion LId. The sacrificial layer 25 is filled inside the insulating layer 54. As shown in Figure 2 above, the bridging portion BRw covers the entire upper end of the sacrificial layer 25 in the plate-like portion LId that extends in the direction along the X direction.

[0091] In the dummy block region BLKd, multiple separation layers SHE are arranged between adjacent plate-like sections LI and LId in the Y direction, penetrating the upper layer of the laminate LMsb and extending along the X direction. The penetration depth of the separation layers SHE within the block region BLKd corresponds to the depth of the selected gate line SGD within the block region BLK.

[0092] In the block region BLKd, multiple dummy pillars PLd are distributed and penetrate the laminate LM or laminate LMs, the upper source line DSLb, and the intermediate source line BSL or intermediate sacrificial layer SCN, reaching the lower source line DSLa.

[0093] Each pillar PLd has the same configuration as the pillar PL described above. That is, each of the multiple pillar PLd has a dummy layer MEd extending in the lamination direction within the laminate LM or laminate LMs, a dummy layer CNd penetrating within the laminate LM or laminate LMs, a dummy layer CPd covering the upper surface of the dummy layer CNd, and a dummy layer CRd that serves as the core material of the pillar PLd.

[0094] In pillar PLd located within the laminate LM, the dummy layer CNd penetrates the laminate LM and is in direct contact with the intermediate source line BSL at the depth of the intermediate source line BSL. On the other hand, in pillar PLd located within the laminate LMs, a dummy layer MEd is placed around the dummy layer CNd that penetrates the laminate LMs, and the dummy layer CNd is not in direct contact with the intermediate sacrificial layer SCN. In both cases, the dummy layer MEd is also placed on the bottom surface of pillar PLd that reaches the depth of the lower source line DSLa.

[0095] Furthermore, the dummy layer CPd is positioned on the upper end of the pillar PLd so as to cover at least the upper end of the dummy layer CNd and is connected to the dummy layer CNd. In addition, the dummy layer CPd is connected to the dummy bit wire BLd located in the insulating layer 53 via the dummy plug CHd located in the insulating layer 52.

[0096] However, while the bit line BL to which the pillar PL of block region BLK is connected via plug CH is electrically connected to the peripheral circuit CBA, the bit line BLd to which the dummy pillar PLd in block region BLKd is connected is not connected to the peripheral circuit CBA. This is because the dummy pillar PLd does not contribute to the function of the semiconductor memory device 1 and does not need to be electrically operated.

[0097] (Method of manufacturing semiconductor memory devices) Next, the manufacturing method of the semiconductor memory device 1 according to the embodiment will be described using Figures 4 to 9. Figures 4 to 9 are diagrams illustrating, in order, some of the steps of the manufacturing method of the semiconductor memory device 1 according to the embodiment. Figures 4 to 9 show a cross-section along the Y direction of the region that will later become the memory region MR.

[0098] As shown in Figure 4(a), the lower source line DSLa, the intermediate sacrificial layer SCN, and the upper source line DSLb are formed on the support substrate SS in this order.

[0099] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The insulating layer 60 (see Figure 2, etc.) described above may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and as described above, is a layer that will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0100] On the upper source line DSLb, a laminate LMsa is formed by alternately stacking multiple insulating layers NL and multiple insulating layers OL, one layer at a time. The insulating layer NL is, for example, a silicon nitride layer, and as described above, functions as a sacrificial layer that will later be replaced by a conductive material to become the word line WL or the selected gate line SGS.

[0101] Although not shown in the diagram, the insulating layer NL and insulating layer OL at both ends of the laminate LMsa in the X direction are processed in a stepped manner. This processing can be achieved by repeatedly slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsa.

[0102] Specifically, a mask pattern is formed on the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL in the exposed areas are etched away one layer at a time. Then, the edges of the mask pattern are receded by treatment with oxygen plasma or the like, exposing the upper surface of the laminated LMsa, and the insulating layer NL and insulating layer OL are etched away one layer at a time again. By repeating this process multiple times, a laminated LMsa with a stepped shape at both ends in the X direction is formed.

[0103] At this time, both ends of the laminate LMsa in the Y direction are similarly processed into a stepped shape, forming a structure that will later become part of the dummy stepped region SRd. The stepped structures at both ends in the X and Y directions are then covered by the insulating layer 50 (see Figure 1(a)) described above.

[0104] As shown in Figure 4(b), the laminate LMsa forms multiple memory holes MHa extending in the stacking direction. These multiple memory holes MHa penetrate the laminate LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory holes MHa later become the substructure of pillar PL or pillar PLd.

[0105] These memory holes MHa have wide gaps in two locations on the paper, where plate-like sections LI and LId will later be provided. Therefore, the two memory holes MHa on the left side of the paper will later become the lower structure of pillar PL, and the six memory holes MHa in the center of the paper will later become the lower structure of pillar PLd.

[0106] As shown in Figure 4(c), these memory holes MHa are filled with a sacrificial layer 27, such as an amorphous silicon layer or a CVD-carbon layer. This forms a pillar PLc in which multiple memory holes MHa are filled with the sacrificial layer 27.

[0107] As shown in Figure 4(d), the laminate LMsa is covered, forming a laminate LMsb in which multiple insulating layers NL and multiple insulating layers OL are alternately stacked one layer at a time. The insulating layers NL of the laminate LMsb function as sacrificial layers that are later replaced by conductive layers to become word lines WL or selected gate lines SGD.

[0108] Although not shown in the diagram, a portion of the laminate LMsb is processed in a stepwise manner, altering the insulating layer NL and insulating layer OL. This processing can be achieved by repeatedly performing the same steps as the processing for the laminate LMsa described above: slimming the mask pattern of the photoresist layer, etc., and etching the insulating layer NL and insulating layer OL of the laminate LMsb.

[0109] At this time, the uppermost step of the stair section formed on the laminated LMsa and the lowermost step of the stair section formed on the laminated LMsb are brought into close proximity to form a stair shape that extends continuously from the lower layer of the laminated LMsa to the upper layer of the laminated LMsb. As a result, the laminated LMsa and LMsb are formed with a stair region SR having a stair shape extending from the laminated LMsa to the laminated LMsb, with the stair region SR formed at both ends in the X direction.

[0110] At this time, both ends of the laminate LMsb in the Y direction are similarly processed into a stepped shape, forming a structure that will later become part of the dummy stepped region SRd. The stepped structures at both ends in the X and Y directions are then further covered by the insulating layer 50 (see Figure 1(a)) described above.

[0111] As shown in Figure 5(a), multiple memory holes MHb are formed that penetrate the laminate LMsb and connect to multiple pillars PLc that have already been formed within the laminate LMsa. The memory holes MHb are the parts that will later become the superstructure of pillar PL or pillar PLd.

[0112] As shown in Figure 5(b), the sacrificial layer 27 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, multiple memory holes MHa open at the bottom of multiple memory holes MHb, and multiple memory holes MH are formed that penetrate the laminate LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0113] Furthermore, the two memory holes MH on the left side of the page will later become pillar PL, and the six memory holes MH in the center of the page will later become pillar PLd.

[0114] Furthermore, if the sacrificial layer 27 filled inside the pillar PLc is a CVD-carbon layer or the like, the sacrificial layer 27 can be removed from these pillar PLc all at once when the mask pattern used to form the memory holes MHb in Figure 5(a) above is removed by ashing using oxygen plasma or the like.

[0115] As shown in Figure 5(c), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order within the memory hole MH. As a result, the multilayer insulating layer MEb and the semiconductor layer CNb are formed on the side surface and the bottom surface where the lower source line DSLa is exposed within the memory hole MH, and the insulating layer CRb is filled into the center of the memory hole MH. The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb correspond to the memory layer ME, the channel layer CN, and the core layer CR, or the dummy layers CRd, CNd, MEd, respectively. The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminate LMsb.

[0116] As shown in Figure 5(d), the insulating layer CRb, semiconductor layer CNb, and multilayer insulating layer MEb on the upper surface of the laminate LMsb are sequentially removed, leaving these as separate layers for each individual memory hole MH. As a result, the core layer CR, channel layer CN, and memory layer ME are formed within the memory hole MH that will become pillar PL at the rear left of the page. Additionally, dummy layers CRd, CNd, and MEd are formed within the memory hole MH that will become pillar PLd at the rear center of the page.

[0117] Furthermore, when removing the insulating layer CRb, semiconductor layer CNb, and multilayer insulating layer MEb from the upper surface of the laminate LMsb, the upper ends of the core layer CR and channel layer CN, and the upper ends of the dummy layers CRd and CNd are recessed from the upper surface of the memory hole MH, thereby forming a recess DN at the upper end of the memory hole MH.

[0118] As shown in Figure 6(a), a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP or the dummy layer CPd, and is also formed on the upper surface of the laminate LMsb.

[0119] As shown in Figure 6(b), the semiconductor layer CPb on the upper surface of the laminate LMsb is removed by CMP (Chemical Mechanical Polishing) or the like, and a cap layer CP or dummy layer CPd is formed to be placed at the upper end of the memory hole MH. At this time, the insulating layer OL on the uppermost layer of the laminate LMsb is also removed by a predetermined thickness.

[0120] As shown in Figure 6(c), the insulating layer OL on the top layer of the laminated LMsb, which has been thinned by CMP or the like, is stacked up. This creates pillars PL in which the cap layer CP is embedded in the insulating layer OL on the top layer, and pillars PLd in which the dummy layer CPd is embedded in the insulating layer OL on the top layer.

[0121] However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and no part of the side of the channel layer CN is exposed from the memory layer ME. This is also true for the dummy pillar PLd.

[0122] As shown in Figure 7(a), a slit ST is formed that penetrates the laminates LMsb and LMsa, and the upper source line DSLb, and reaches the intermediate sacrificial layer SCN. The slit ST also extends along the X direction within the laminates LMsa and LMsb.

[0123] As shown in Figure 7(b), an insulating layer 54 is formed on the side walls of the slit ST facing each other in the Y direction. In addition, a sacrificial layer 25, such as an amorphous silicon layer, is filled inside the insulating layer 54 that covers the side walls of the slit ST.

[0124] As shown in Figure 7(c), the upper end of the sacrificial layer 25 filled in the slit ST is removed. At this time, in the case of slit ST that will become a plate-like portion LI later on the left side of the paper, a portion of the sacrificial layer 25 in the slit ST that extends in the direction along the X direction is intermittently removed. On the other hand, in the case of slit ST that will become a plate-like portion LId later on the right side of the paper, the entire upper end of the sacrificial layer 25 that extends in the direction along the X direction is removed.

[0125] As shown in Figure 7(d), a silicon oxide layer or polysilicon layer is formed to cover the portion where the sacrificial layer 25 has been removed from the upper end of the slit ST. As a result, a crosslinked portion BR is formed in the slit ST on the left side of the paper, and a crosslinked portion BRw is formed in the slit ST on the right side of the paper. In addition, a dummy plate-like portion LId, comprising an insulating layer 54, a sacrificial layer 25, and a crosslinked portion BRw, is formed on the right side of the paper.

[0126] As shown in Figure 8(a), the sacrificial layer within the slit ST is removed from between the intermittently formed cross-linking portions BR at the upper ends of multiple slit STs, including the slit ST on the left side of the paper. At this time, a cross-linking portion BRw covering the entire upper surface is formed on the plate-like portion LId on the right side of the paper. Therefore, the sacrificial layer 25 is not removed from the plate-like portion LId.

[0127] As shown in Figure 8(b), the sacrificial layer 25 is removed, such as in the slit ST on the left side of the paper, and a removal solution for the intermediate sacrificial layer SCN, such as thermal phosphoric acid, is introduced through multiple slit STs whose sidewalls are protected by the insulating layer 54, thereby removing the intermediate sacrificial layer SCN sandwiched between the lower source wire DSLa and the upper source wire DSLb. However, since the sidewalls of these slit STs are protected by the insulating layer 54, the removal of the insulating layer NL within the laminates LMsa and LMsb is suppressed.

[0128] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. In addition, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the gap layer GPs.

[0129] In this case, the treatment time with the removal solution such as hot phosphoric acid is determined based on the time required to remove all of the intermediate sacrificial layer SCN within a region corresponding to one block region BLK when the removal solution is introduced from both sides in the Y direction using adjacent slits ST in the Y direction.

[0130] On the other hand, since the sacrificial layer 25 remains filled in the plate-like portion LId on the right side of the paper, the removal liquid does not flow in from this plate-like portion LId. Therefore, in the region where the six pillars PLd in the center of the paper are located, the removal process of the intermediate sacrificial layer SCN proceeds only from the slit ST on the left side of the paper, and the intermediate sacrificial layer SCN may remain in the region closer to the plate-like portion LId on the right side of the paper without being completely removed.

[0131] In this case, in some pillars PLd located near the slit ST on the left side of the paper, the dummy layer MEd is exposed within the gap layer GPs formed between the lower source line DSLa and the upper source line DSLb, while in some pillars PLd located near the plate-like section LId on the right side of the paper, the dummy layer MEd remains covered by the intermediate sacrificial layer SCN.

[0132] As shown in Figure 8(c), chemical solutions are introduced into the gap layer GPs through multiple slits ST as needed, sequentially removing the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see Figures 2(c) and 2(d)) of the memory layer ME exposed within the gap layer GPs. As a result, the memory layer ME is removed from a portion of the side wall of the pillar PL, and a portion of the inner channel layer CN is exposed within the gap layer GPs.

[0133] In this case, in the region where the six pillars PLd in the center of the paper are arranged, the dummy layer MEd of some of the pillars PLd in the region where the gap layers GPs are formed may be removed, similar to the multiple pillars PL described above, so that the dummy layer CNd is exposed within the gap layers GPs.

[0134] As shown in Figure 8(d), a raw material gas, such as amorphous silicon, is injected through multiple slits ST whose sidewalls are protected by an insulating layer 54, and the gap layers GPs are filled with amorphous silicon or the like. The support substrate SS is then heat-treated to polycrystallize the amorphous silicon filled in the gap layers GPs, forming an intermediate source wire BSL containing polysilicon or the like.

[0135] As a result, a portion of the channel layer CN of the pillar PL is connected laterally to the source line SL via the intermediate source line BSL. Similarly, some of the exposed dummy layer CNd of the pillar PLd may be connected laterally to the source line SL via the intermediate source line BSL.

[0136] As shown in Figure 9(a), the insulating layer 54 on the side walls of multiple slits ST from which the sacrificial layer 25 has been removed is temporarily removed. At this time, if the crosslinked portion BR is formed from a material such as polysilicon different from the insulating layer 54, it is possible to suppress damage to the crosslinked portion BR when the insulating layer 54 is removed.

[0137] As shown in Figure 9(b), a removal solution for the insulating layer NL, such as thermal phosphoric acid, is introduced into the interior of the laminates LMsa and LMsb through multiple slits ST to remove the insulating layer NL of the laminates LMsa and LMsb.

[0138] In this case, the treatment time with the removal solution such as hot phosphoric acid is determined based on the time required to remove all the insulating layer NL within a region corresponding to one block region BLK when the removal solution is introduced from both sides in the Y direction using adjacent slits ST in the Y direction.

[0139] On the other hand, since the sacrificial layer 25 remains filled in the plate-like portion LId on the right side of the paper, the removal liquid does not flow in from this plate-like portion LId. Therefore, in the region where the six pillars PLd in the center of the paper are located, the removal process of the insulating layer NL proceeds only from the slit ST on the left side of the paper, and the insulating layer NL may remain in the region closer to the plate-like portion LId on the right side of the paper without being completely removed.

[0140] As a result, laminates LMga and LMgb are formed, having multiple gap layers GP in which the insulating layer NL between insulating layers OL has been removed, in the spaces between multiple slits ST, including the slit ST on the left side of the paper, from which the sacrificial layer 25 has been removed, and in a portion of the area between the plate-like portion LId on the right side of the paper, which is filled with the sacrificial layer 25, and the slit ST on the left side of the paper from which the sacrificial layer 25 has been removed.

[0141] Laminates LMga and LMgb, which contain multiple gap layers GP, have a fragile structure. Multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layer OL remaining in the laminate from bending, and prevents the laminate LMga and LMgb from deforming or collapsing.

[0142] However, the dummy step regions SRd at both ends of the laminate LMga,LMgb in the Y direction and the insulating layer 50 covering them (see Figure 1(a)) generate expansion stress (tensile stress) that expands outward from the center of the insulating layer 50. As a result, the laminate LMga,LMgb is subjected to contraction stress directed toward the center of the laminate LMga,LMgb in the Y direction.

[0143] This could cause multiple pillars PL formed on the laminates LMga and LMgb to become misaligned in the Y direction. If multiple pillars PL become misaligned, it could lead to misalignment with the subsequently formed plugs CH, potentially resulting in poor connection between the pillars PL and the plugs CH.

[0144] Furthermore, multiple slits ST may be compressed in the Y direction by shrinkage stress in the laminates LMga and LMgb, potentially reducing their width in the Y direction. This could cause multiple slits ST to become blocked, hindering subsequent processing. Such deformation of the slit ST width could also further exacerbate misalignment of multiple pillars PL in the Y direction.

[0145] The positional misalignment described above becomes more pronounced closer to the Y-direction end of the laminate LM. This is one of the reasons for placing dummy pillars PLd at the end of the laminate LM. In other words, in the region where positional misalignment due to stress in the insulating layer 50 may occur, dummy pillars PLd are placed in place of pillars PL that contribute to the function of the semiconductor memory device 1.

[0146] In the semiconductor memory device 1 of this embodiment, in addition to the above countermeasures, a dummy plate-shaped portion Lid is placed at the ends of the laminates LMga and LMgb in the Y direction, leaving laminates LMsa and LMsb with the insulating layer NL not removed at the Y-direction ends of the laminates LMga and LMgb. As a result, the laminates LMga and LMgb located on the Y-direction inside the laminates LMsa and LMsb are separated from the insulating layer 50 located on the Y-direction outside, thereby suppressing the influence of stress generated by the insulating layer 50 on the laminates LMga and LMgb.

[0147] Therefore, displacement of pillar PL and deformation of slit ST width due to shrinkage stress in laminates LMga and LMgb are suppressed.

[0148] Furthermore, multiple slits ST are equipped with a bridging section BR at their upper end. This relieves stress on both sides of the slit ST in the Y direction, further suppressing deformation of the slit ST width.

[0149] As shown in Figure 9(c), a raw material gas of a conductive material, such as tungsten or molybdenum, is injected into the interior of the laminates LMga and LMgb through the slit ST, and the gap layer GP of the laminates LMga and LMgb is filled with the conductive material to form multiple word lines WL, etc.

[0150] As a result, a laminate LM is formed, which includes laminates LMa and LMb, in which multiple word lines WL and multiple insulating layers OL are alternately stacked one layer at a time. As described above, in this case, the laminates LMs remain in place in some regions at both ends of the laminate LM in the Y direction.

[0151] As described above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN, and the process of forming the word line WL from the insulating layer NL, are also called replacement processes.

[0152] Subsequently, an insulating layer 54 is formed on the side wall of the slit ST, and a conductive layer 24 is filled into the insulating layer 54 to form a plate-like portion LI.

[0153] Furthermore, by forming grooves that penetrate one or more conductive layers, including the uppermost conductive layer of the laminated LMb, and filling the grooves with an insulating layer 56, an isolation layer SHE is formed that partitions these conductive layers into a pattern of selected gate lines SGD.

[0154] Furthermore, multiple contact points CC are formed from the upper side of the staircase area SR, reaching the word lines WL and selection gate lines SGD and SGS that constitute each step of the staircase structure of the staircase area SR.

[0155] Furthermore, an insulating layer 52 is formed on the upper surface of the laminate LM, and plugs CH are formed that penetrate the insulating layer 52 and are connected to each of the pillars PL, and plugs are formed that are connected to contact CC. In addition, an insulating layer 53 is formed on the insulating layer 52, and bit wires BL are formed that are connected to plugs CH, and upper layer wiring etc. are formed that are connected to contact CC via the plugs of contact CC. Also, electrode pads etc. are formed on the upper surface of the insulating layer 53 to establish electrical conductivity with the surrounding circuit CBA.

[0156] Furthermore, in the above, the plug CH and bit wire BL may be formed collectively by using, for example, the dual damascene method.

[0157] In addition, the formation of dummy plugs CHd and dummy bit wires BLd are carried out on the dummy pillar PLd in parallel with the above process.

[0158] On the other hand, peripheral circuits CBA are formed on a semiconductor substrate SB, which is separate from the support substrate SS on which the laminated structure LM is formed, and covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to bring the peripheral circuits CBA to the surface of the insulating layer 40 and connect them to electrode pads etc. formed on the upper surface of the insulating layer 40.

[0159] Next, the support substrate SS and the semiconductor substrate SB are bonded together by their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. After that, the support substrate SS is removed to expose the source wire SL, and the electrode film EL is connected via the insulating layer 60 on which the plug PG is formed.

[0160] The semiconductor memory device 1 of the embodiment is manufactured as described above.

[0161] (Overview) In semiconductor memory devices such as 3D non-volatile memory, the periodic arrangement of pillars terminates at both ends in the Y direction of the stack, making it prone to processing errors during pillar formation. Furthermore, only relatively small dummy step regions are placed at both ends in the Y direction of the stack, making it easy for pillar displacement to occur due to stress from the outside of the stack when the stack is replaced. For this reason, pillars near both ends in the Y direction of the stack are designated as dummy pillars, and the regions where these dummy pillars are placed are designated as dummy blocks.

[0162] Considering the effects of misalignment in the pillars near both ends of the laminate in the Y direction, it is preferable to place multiple dummy blocks at each end of the laminate in the Y direction. However, this increases the area occupied by the dummy blocks in the semiconductor memory device, making it difficult to increase the storage capacity of the semiconductor memory device and to miniaturize it.

[0163] According to the semiconductor memory device 1 of this embodiment, the entire upper end of the plate-shaped portion LId, which is located closest to the edge of the stacked bodies LM,LMs in the Y direction, is covered by the bridged portion BRw.

[0164] In this way, by covering the entire plate-like portion LId at the ends of the laminated LMs with the bridging portion BRw, the replacement of the laminated LMs near the ends in the Y direction can be inhibited, and the shrinkage stress on the laminated LM that forms on the Y-side of the laminated LMs can be suppressed.

[0165] This reduces the range from the end positions of the laminates LM,LMs where pillar PL misalignment may occur, eliminating the need to place multiple dummy blocks, for example, and thus reducing the dummy block area BLKd.

[0166] Furthermore, by simply changing the shape of the cross-linking portion BRw, two different types of plate-like portions LI and LId can be formed. This allows for the formation of plate-like portions LI, which are used to replace laminates such as LM, and plate-like portions LId, which are not used to replace laminates such as LM, without increasing the number of manufacturing steps.

[0167] In the semiconductor memory device 1 of this embodiment, a sacrificial layer 25 is filled into the plate-shaped portion LId located closest to the edge of the stacked LM,LMs in the Y direction. By leaving the sacrificial layer 25 in the plate-shaped portion LId at the edge of the stacked LM,LMs in this way, the replacement of the stacked LMs near the edge in the Y direction can be inhibited.

[0168] According to the semiconductor memory device 1 of this embodiment, the laminated LMs are located outside the plate-shaped portion LId, which is positioned closest to the edge of the laminated LMs LM and LMs in the Y direction. Instead of multiple word lines WL, multiple insulating layers NL are alternately stacked one layer at a time with multiple insulating layers OL. By leaving laminated LMs at the edges of the laminated LM in this way, shrinkage stress on the laminated LM formed on the Y-direction side of the laminated LMs can be suppressed.

[0169] According to the semiconductor memory device 1 of the embodiment, the multiple pillars PL and PLd are selectively arranged in the region between plate-shaped parts LId and LI and the region between plate-shaped parts LI and LI, from among the region between plate-shaped parts LId and LI adjacent to each other in the Y direction and the region between plate-shaped parts LId and LI adjacent to each other in the Y direction.

[0170] As described above, since the laminated LMs located at least outside the plate-like portion LId in the Y direction are not replaced, they do not need to be supported by multiple pillars PL and PLd. Therefore, multiple pillars PL and PLd are not placed in the region outside the plate-like portion LId in the Y direction, which further reduces the dummy block region BLKd.

[0171] In the semiconductor memory device 1 of this embodiment, the pillar PLd positioned in the region between the plate-shaped parts LId and LI is a dummy pillar. By making the pillar PLd, which is prone to misalignment due to processing errors and stress, a dummy pillar that does not contribute to the function of the semiconductor memory device 1, the quality of the semiconductor memory device 1 can be improved.

[0172] (modified version) Next, a modified semiconductor memory device 2 of the embodiment will be described using Figure 10. The modified semiconductor memory device 2 differs from the above-described embodiment in that the multiple plate-like portions LI2 do not have a conductive layer 24.

[0173] Figure 10 is a cross-sectional view showing an example of the configuration of a semiconductor memory device 2 according to a modified embodiment.

[0174] More specifically, Figure 10(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 2, showing a cross-section in the Y direction in the block region BLK, and Figure 10(b) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 2, showing a cross-section in the dummy block region BLKd. Note that in Figures 10(a) and (b), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0175] In Figure 10, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0176] As shown in Figure 10, the modified semiconductor memory device 2 has a plurality of plate-like portions LI2 that penetrate the laminate LM in the stacking direction and extend in a direction along the X direction, instead of the plate-like portions LI of the semiconductor memory device 1 of the above embodiment.

[0177] Each plate-shaped portion LI2 has an insulating layer 55, such as a silicon oxide layer, instead of the conductive layer 24 that the plate-shaped portion LI of the above-described embodiment has. That is, an insulating layer 54 is arranged on the side walls of the plate-shaped portion LI2 facing each other in the Y direction, and an insulating layer 55 is filled inside the insulating layer 54. In addition, a plurality of cross-linking portions BR are arranged at predetermined intervals in the X direction at the upper end of the insulating layer 55.

[0178] These plate-like portions LI2 are formed by replacing the intermediate source wire BSL and the laminate LM with an insulating layer 55 in place of the conductive layer 24 within the aforementioned slit ST. Since the insulating layers 54 and 55 are made of the same material, such as a silicon oxide layer, their boundaries may be indistinguishable. Furthermore, if the cross-linked portion BR is a silicon oxide layer or the like, the boundary between the cross-linked portion BR and the insulating layers 54 and 55 may also be indistinguishable.

[0179] In the modified semiconductor memory device 2, the plate-like portion LI is filled with an insulating layer 55. This configuration also provides the same effects as the embodiment described above.

[0180] In the embodiments and modifications described above, the semiconductor memory devices 1 and 2 are provided with a 2-tier stacked structure LM, etc., in which two stacked structures LMa and LMb are stacked vertically. However, the configuration of the stacked structure is not limited to 2 tiers; it may be 1 tier or 3 tiers or more.

[0181] Furthermore, in the embodiments and modifications described above, the pillar PL is connected to the source line SL on the side of the channel layer CN, but this is not limited to this configuration. For example, the pillar may be configured such that the memory layer on the bottom surface of the pillar is removed and the source line is connected at the lower end of the channel layer.

[0182] Furthermore, in the embodiments and modifications described above, the peripheral circuit CBA is positioned above the laminate LM. However, the peripheral circuit may be positioned below the laminate, or on the same layer as the laminate. When the peripheral circuit is positioned below the laminate, the laminate can be formed further above the semiconductor substrate on which the peripheral circuit is formed. When the peripheral circuit is positioned on the same layer as the laminate, the laminate can be formed at a different location on the semiconductor substrate from where the peripheral circuit is formed.

[0183] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0184] 1,2...semiconductor memory device, 24...conductive layer, 25...sacrificial layer, 54,55...insulating layer, BLK,BLKd...block region, BR,BRw...bridged region, LI,LI2,LId...plate-like region, LM,LMs...laminated structure, MC...memory cell, MR...memory region, NL,OL...insulating layer, PL,PLd...pillar, SR,SRd...stair region, SGD,SGS...selection gate line, ST...slit, WL...word line.

Claims

1. A laminate comprising multiple conductive layers and multiple first insulating layers stacked alternately one layer at a time, A plurality of slits extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction, The laminate comprises a plurality of pillars arranged between the plurality of slits and extending in the stacking direction within the laminate, Of the plurality of slits, the entire upper end of the first slit, which is located closest to the edge of the laminate in the second direction, is covered with the first material. Of the plurality of slits, a portion of the upper end of each of the plurality of second slits, excluding the first slit, is covered with the first material. Semiconductor memory device.

2. The first slit is filled with the second material. The plurality of second slits are filled with a third material different from the second material. The semiconductor memory device according to claim 1.

3. The laminated body is A first laminate is arranged between the plurality of second slits, and the plurality of conductive layers and the plurality of first insulating layers are alternately stacked one layer at a time. The present invention includes a second laminate disposed between the end of the laminate in the second direction and the first slit, wherein a plurality of second insulating layers are laminated alternately with the plurality of first insulating layers, one layer at a time, instead of the plurality of conductive layers, The semiconductor memory device according to claim 1.

4. Of the plurality of second slits, the first and second laminates are both disposed between the first slit and the second slit adjacent to the first slit in the second direction, The semiconductor memory device according to claim 3.

5. Between the first and second slits, The first laminate is arranged in the region near the second slit, The second laminate is located in the region near the first slit. The semiconductor memory device according to claim 4.

6. A laminate comprising multiple conductive layers and multiple first insulating layers stacked alternately one layer at a time, A plurality of slits extending within the laminate in a first direction intersecting the stacking direction and the stacking direction, and dividing the laminate in a second direction intersecting the first direction and the stacking direction, The laminate comprises a plurality of pillars arranged between the plurality of slits and extending in the stacking direction within the laminate, Of the plurality of slits, the first slit located closest to the edge of the laminate in the second direction and the plurality of second slits excluding the first slit contain different materials and have different layer structures. Semiconductor memory device.

7. A laminate is formed in which multiple first insulating layers and multiple second insulating layers are alternately stacked one layer at a time. A plurality of pillars are formed in the laminate in the stacking direction of the laminate, Multiple slits are formed that extend within the laminate in a first direction intersecting the stacking direction and in the stacking direction, and divide the laminate in a second direction intersecting the first direction and the stacking direction. A first bridging portion is formed that covers the entire upper end of the first slit, which is located closest to the edge of the laminate in the second direction, among the plurality of slits, and a second bridging portion is formed that covers a part of the upper end of each of the plurality of second slits excluding the first slit. The plurality of second insulating layers are replaced by a plurality of conductive layers through the plurality of second slits. A method for manufacturing semiconductor memory devices.

8. The formation of the first and second bridging portions is as follows: Filling the first slit and the plurality of second slits with a sacrificial layer, This includes forming recesses at the upper end of the sacrificial layer for forming the first and second bridging portions, The method for manufacturing a semiconductor memory device according to claim 7.

9. The substitution of the plurality of second insulating layers with the plurality of conductive layers is This includes removing the sacrificial layer filled in the second slits from between the second bridging portions that cover a portion of each of the plurality of second slits, The method for manufacturing a semiconductor memory device according to claim 8.

10. After replacing the plurality of second insulating layers with the plurality of conductive layers, a material different from the sacrificial layer is filled into the plurality of second slits. A method for manufacturing a semiconductor memory device according to claim 9.

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