Manufacturing method for multilayer substrates and semiconductor devices

Abstract

To minimize damage to the support substrate when removing it. [Solution] The laminated substrate of the embodiment is a laminated substrate for peeling using thermal expansion by laser light, comprising: a semiconductor substrate; a first insulating layer disposed above the semiconductor substrate; and a phosphorus-doped polysilicon layer disposed in contact with the first insulating layer, having a portion whose thickness in the direction perpendicular to the surface of the semiconductor substrate is greater than that of the first insulating layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a laminated substrate and a semiconductor device.

Background Art

[0002] A semiconductor device such as a three-dimensional nonvolatile memory may be manufactured by bonding a support substrate on which a plurality of memory pillars are formed and a semiconductor substrate on which a peripheral circuit is formed. After bonding with the semiconductor substrate, the support substrate is peeled off and reused.

[0003] An insulating layer or the like for protecting the support substrate is formed on the support substrate, and the support substrate on the insulating layer side is thermally expanded by irradiation with laser light or the like. Thereby, the support substrate and the insulating layer can be cleaved to peel off the support substrate. At this time, damage such as lattice defects may occur in the support substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a method for manufacturing a laminated substrate and a semiconductor device capable of suppressing damage to the support substrate when peeling off the support substrate.

Means for Solving the Problems

[0006] The laminated substrate of the embodiment is a laminated substrate for peeling using thermal expansion by laser light, comprising: a semiconductor substrate; a first insulating layer disposed above the semiconductor substrate; and a phosphorus-doped polysilicon layer disposed in contact with the first insulating layer, having a portion whose thickness in the direction perpendicular to the surface of the semiconductor substrate is greater than that of the first insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example configuration of a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 5] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 9] A cross-sectional view illustrating a part of the procedure for the regeneration process of the support substrate according to the embodiment. [Figure 10] A schematic cross-sectional view showing the delamination of the support substrate in the comparative example. [Figure 11] A schematic cross-sectional view showing the delamination of the support substrate in the comparative example. [Figure 12] A cross-sectional view showing an example of the configuration of a support substrate according to a modified example 1 of the embodiment. [Figure 13] A cross-sectional view showing an example of the configuration of a support substrate according to a modified example 2 of the embodiment. [Figure 14]A schematic cross-sectional view showing the peeling of the support substrate according to a modified example 2 of the embodiment. [Figure 15] A schematic cross-sectional view showing the peeling of the support substrate according to a modified example 2 of the embodiment. [Figure 16] A schematic diagram showing the measurement substrate and absorption rate measurement method according to the example. [Figure 17] A schematic diagram illustrating a method for calculating the absorption rate of the polysilicon layer in a measurement substrate according to the embodiment. [Figure 18] A schematic diagram illustrating a method for calculating the absorption rate of the polysilicon layer in a measurement substrate according to the embodiment. [Figure 19] A graph showing the absorption rate of the polysilicon layer in the measurement substrate according to the example. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0009] (Example of semiconductor device configuration) Figure 1 is a cross-sectional view showing an example configuration of the semiconductor device 1 according to an embodiment. However, hatching is omitted in Figure 1 for the sake of readability.

[0010] As shown in Figure 1, the semiconductor device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, and a laminate LM in which multiple word lines WL are stacked. The semiconductor device 1 also includes a peripheral circuit CBA provided on a semiconductor substrate SB above the laminate LM.

[0011] A source wire SL is arranged on the electrode film EL via an insulating layer 60. The source wire SL is, for example, a polysilicon layer.

[0012] Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film EL via the plugs PG. This allows a source potential to be applied to the source wire SL from outside the semiconductor device 1 via the electrode film EL and the plugs PG.

[0013] A stacked structure LM, consisting of multiple word lines WL stacked on top of each other, is arranged on the source line SL. A memory area MR is located in the center of the stacked structure LM, and contact areas ER are located at both ends of the stacked structure LM.

[0014] In the memory region MR, multiple pillars PL, which serve as memory pillars, are arranged, penetrating the word line WL in the stacking direction. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. As a result, the semiconductor device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0015] Multiple contacts CC are arranged in the contact region ER, each connected to a multiple word line WL. In this specification, in the extending direction of the contact CC, the end of the contact CC that connects to the word line WL is considered to be on the lower side of the semiconductor device 1.

[0016] From the contact CC, write voltage and read voltage are applied to memory cells contained in the memory area MR in the center of the stacked LM, via word lines WL located at the same height as the memory cells. In this way, these contact CCs individually draw out the word lines WL that are stacked in multiple layers.

[0017] Multiple word wires WL, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around the multiple word wires WL.

[0018] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0019] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with the insulating layer 50 covering the laminate LM, a semiconductor device 1 is formed that includes multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0020] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 1 of the embodiment will be described with reference to Figures 2 to 9. The method for manufacturing the semiconductor device 1 may include, in part, a method for manufacturing the support substrate SS, a method for peeling off the support substrate SS, and a method for regenerating the support substrate SS.

[0021] Figures 2 to 8 illustrate, in order, a part of the procedure for manufacturing the semiconductor device 1 according to an embodiment. Unless otherwise specified, Figures 2 to 8 are cross-sectional views of the semiconductor device 1 during the manufacturing process.

[0022] As shown in Figure 2(a), a semiconductor substrate 30 such as a silicon substrate is prepared. After cleaning both sides of the semiconductor substrate 30, an insulating layer 91 such as a silicon nitride layer is formed.

[0023] The insulating layer 91 is formed on both sides of the semiconductor substrate 30 using, for example, CVD (Chemical Vapor Deposition), with a thickness of 50 nm to 100 nm, for example, 70 nm. However, as will be described later, in this embodiment, damage to the semiconductor substrate 30 during the peeling process of the support substrate SS, which will be described later, is suppressed. Therefore, the insulating layer 91 used for surface protection does not need to be formed.

[0024] Furthermore, for example, on a semiconductor substrate 30 covered with an insulating layer 91, an insulating layer 92 and a polysilicon layer 93 are formed in this order, starting from the semiconductor substrate 30 side.

[0025] The insulating layer 92 is a silicon oxide layer or the like, and has a layer thickness of, for example, 20 nm to 50 nm. The insulating layer 92 functions as an insulating layer that insulates the semiconductor substrate 30 from the heat of the polysilicon layer 93, which is a heat source, during the peeling process of the support substrate SS described later.

[0026] The polysilicon layer 93 is formed to be thicker than the insulating layer 92, for example, having a layer thickness of 100 nm to 300 nm. Furthermore, the polysilicon layer 93 is doped with phosphorus. Doping the polysilicon layer 93 with phosphorus increases the absorption rate of light with wavelengths of 9 μm to 10 μm, allowing the polysilicon layer 93 to expand thermally during the peeling process of the support substrate SS described later, thereby separating the insulating layer 92 from the polysilicon layer 93.

[0027] The phosphorus concentration in the polysilicon layer 93 is, for example, 1.5 × 10⁻⁶. 20 atom / cm 3 The above is more preferable, 3.0 × 10 20 atom / cm 3 This concludes the explanation. As a result, while the absorption rate of light with wavelengths between 9 μm and 10 μm is 0% in the undoped polysilicon layer, the absorption rate of the polysilicon layer 93 with the above phosphorus concentration can be increased to, for example, 50% or more, more preferably 75% or more.

[0028] As a result, the polysilicon layer 93 can be heated and thermally expanded by light of the above wavelength. The thermal conductivity of the polysilicon layer 93 is more than 10 times that of the insulating layer 92, which is a silicon oxide layer or the like. In addition, when comparing the thermal conductivity of each layer of the support substrate SS, the thermal conductivity of the insulating layer 91, which is a silicon nitride layer or the like, and the thermal conductivity of the semiconductor substrate 30, which is a silicon substrate or the like, are both more than 10 times that of the insulating layer 92, which is a silicon oxide layer or the like.

[0029] As described above, a support substrate SS is manufactured in which a multilayer structure 90 including insulating layers 91, 92 and a polysilicon layer 93 is formed on a semiconductor substrate 30. Thus, the support substrate SS is configured as a laminated substrate in which multiple layers are formed on the semiconductor substrate 30.

[0030] As shown in Figure 2(b), a conductive layer SLb is formed on the multilayer structure 90 of the support substrate SS. The conductive layer SLb is, for example, a polysilicon layer, and later becomes the source line SL of the semiconductor device 1. However, when forming the conductive layer SLb on the multilayer structure 90, the conductive layer SLb may be formed via other layers such as a silicon oxide layer or a polysilicon layer. The layer interposed between the multilayer structure 90 and the conductive layer SLb may be a single-layer structure, a multilayer structure of the same type of layer, or a multilayer structure of different types of layers.

[0031] Furthermore, the conductive layer SLb does not necessarily have to be formed on the support substrate SS at this stage. In that case, for example, the conductive layer SLb can be formed after bonding with the semiconductor substrate SB, as described later, and then processed into a source wire SL.

[0032] As shown in Figure 2(c), multiple laminates LM are formed on the conductive layer SLb by stacking multiple word lines WL spaced apart from each other. As shown in the enlarged cross-sectional view in Figure 2(d), multiple pillars PL and multiple contacts CC are formed on each individual laminate LM.

[0033] The laminate LM on which pillars PL and contacts CC are formed is formed as follows: On a conductive layer SLb formed on a support substrate SS, a laminate is formed in which multiple silicon nitride layers and multiple silicon oxide layers are alternately stacked one layer at a time.

[0034] Furthermore, multiple contact holes reaching individual silicon nitride layers are formed in a portion of this laminate. Memory holes are also formed that penetrate the laminate and reach the conductive layer SLb, and memory layers and semiconductor layers are filled into these memory holes. At this time, a portion of the memory layer on the side of the semiconductor layer is removed to electrically connect the semiconductor layer and the conductive layer SLb.

[0035] Subsequently, a process called replacement is performed to replace multiple silicon nitride layers of the laminate with conductive layers to form word lines (WL). In addition, multiple contact holes are filled with conductive layers to form contacts (CC), and upper layer wiring is formed on the upper layer of the laminate (LM).

[0036] As shown in Figure 2(d), an insulating layer 50 is formed to cover multiple laminates LM, each having multiple pillars PL and multiple contacts CC formed as described above. Electrode pads are formed on the surface of the insulating layer 50, which are electrically connected to the pillars PL and contacts CC of the laminates LM.

[0037] The insulating layer 50, which includes multiple laminates LM on which multiple pillars PL are formed, is an example of a device layer that includes at least a part of the configuration of the semiconductor device 1.

[0038] As shown in Figure 3(a), multiple peripheral circuits CBA, including transistors TR, are formed on a semiconductor substrate SB, which is separate from the support substrate SS. The multiple peripheral circuits CBA are formed to correspond to, for example, each of the multiple laminates LM. An insulating layer 40 is also formed to cover the peripheral circuits CBA. Electrode pads are formed on the surface of the insulating layer 40 that are electrically connected to the transistors TR and other components of the peripheral circuits CBA.

[0039] As shown in Figure 3(b), the side of the support substrate SS on which the laminate LM etc. is formed is placed opposite the side of the semiconductor substrate SB on which the peripheral circuit CBA etc. is formed, and the insulating layer 50 on the support substrate SS side and the insulating layer 40 on the semiconductor substrate SB side are joined together to bond the support substrate SS and the semiconductor substrate SB.

[0040] These insulating layers 50 and 40 can be joined by, for example, activating their surfaces in advance through plasma treatment. When joining the insulating layers 50 and 40, the support substrate SS and the semiconductor substrate SB are aligned so that the electrode pads formed on the insulating layer 50 and the electrode pads formed on the insulating layer 40 overlap.

[0041] After bonding the insulating layers 50 and 40, an annealing process is performed to bond the two electrode pads together, for example, by a Cu-Cu bond. This electrically connects the corresponding laminate LM and peripheral circuit CBA, and also bonds the support substrate SS and semiconductor substrate SB together.

[0042] As shown in Figure 4, a laser beam having a wavelength of, for example, 9 μm to 10 μm is irradiated onto the bonded material of the support substrate SS and the semiconductor substrate SB from the support substrate SS side. For example, a carbon dioxide (CO2) laser with a wavelength of 9.6 μm can be used as the laser beam. However, the wavelength of the laser beam may also be, for example, 9.25 μm or 10.6 μm. Furthermore, it is preferable to irradiate the laser beam in a pulsed manner. This allows the entire surface of the support substrate SS to be irradiated with laser light.

[0043] As shown in the top view of Figure 5, when irradiating the entire surface of the support substrate SS with a pulsed laser, for example, the bonded material of the support substrate SS and the semiconductor substrate SB can be placed on a stage RT that is capable of rotational and horizontal drive, and while rotating the stage RT, the laser beam can be sequentially irradiated in a pulsed manner from the laser oscillator OSC.

[0044] In other words, by rotating the stage RT once to irradiate the support substrate SS with laser light in a circular pattern, and then moving the stage RT horizontally to shift the irradiation position, and then rotating the stage RT again, the entire surface of the support substrate SS can be irradiated with laser light in a concentric pattern.

[0045] In this case, the laser beam may be irradiated in a concentric circle from the outer periphery of the support substrate SS toward the center, as shown in the example in Figure 5, or, not according to the example in Figure 5, the laser beam may be irradiated in a concentric circle from the center toward the outer periphery of the support substrate SS.

[0046] The pitch of the laser beam irradiation positions can be, for example, several tens of micrometers apart, and the pulse frequency can be, for example, between 10 kHz and 100 kHz.

[0047] As described above, when the support substrate SS is irradiated with laser light, the polysilicon layer 93 of the multilayer structure 90 formed on the semiconductor substrate 30 undergoes thermal expansion, causing the polysilicon layer 93 and the insulating layer 92 to cleave apart. This process is shown in Figure 6.

[0048] As shown in Figure 6(a), when irradiated with laser light, the phosphorus-doped polysilicon layer 93, which has a higher laser light absorption rate than the insulating layer 92, absorbs the laser light and generates heat.

[0049] As shown in Figure 6(b), the insulating layer 92 also generates some heat when irradiated with laser light, but the amount of heat generated by the insulating layer 92 is lower than that of the polysilicon layer 93. Furthermore, as mentioned above, the thermal conductivity of the insulating layer 92 is less than one-tenth that of the polysilicon layer 93. For this reason, the insulating layer 92 can function as an insulating layer that suppresses the transfer of heat from the polysilicon layer 93 to the semiconductor substrate 30.

[0050] Furthermore, when the insulating layer 92 is to function as a heat insulating layer, it is preferable that the insulating layer 92 has a thickness of, for example, 20 nm to 50 nm, as described above. If the insulating layer 92 is too thick, the insulating layer 92 itself becomes a heat source, weakening its heat insulating effect, and heat may be transferred to the semiconductor substrate 30. When heat is transferred to the semiconductor substrate 30, the semiconductor substrate 30 itself expands due to heat, which may cause damage such as lattice defects in the crystal of the semiconductor substrate 30.

[0051] On the other hand, if an insulating layer 92 is not provided on the support substrate SS, the heat from the polysilicon layer 93 is transferred to the semiconductor substrate 30 and dissipated, causing the stress generated by the thermal expansion of the polysilicon layer 93 to be dispersed, making it difficult to peel off the support substrate SS.

[0052] As shown in Figure 6(c), the polysilicon layer 93 undergoes thermal expansion. This creates stress between the polysilicon layer 93 and the insulating layer 92.

[0053] As shown in Figure 6(d), the stress on the thermally expanded polysilicon layer 93 pushes up the insulating layer 92, causing the interface between the polysilicon layer 93 and the insulating layer 92 to crack.

[0054] As shown in Figure 6(e), the support substrate SS is peeled off with the insulating layers 92 and 91 attached to the semiconductor substrate 30 due to a crack that occurs at the interface between the polysilicon layer 93 and the insulating layer 92. At this time, the portion of the polysilicon layer 93 that has expanded due to heat peels off together with the insulating layer 92 and 91.

[0055] In this way, by utilizing the thermal expansion of the polysilicon layer 93 to cleave the polysilicon layer 93 and the insulating layer 92, the support substrate SS can be removed at a relatively low temperature. Therefore, the support substrate SS can be removed without the need to thermal spray or melt the polysilicon layer 93 and the insulating layer 92, or to cause a chemical change in the components that serve as the starting point for the cleavage.

[0056] As shown in Figure 7, when the support substrate SS, which has become a semiconductor substrate 30 having only a part of the multilayer structure 90 such as insulating layers 92 and 91, is peeled off, the semiconductor substrate SB side will be left with peripheral circuits CBA including transistors TR etc. formed on the semiconductor substrate SB, and a laminate LM which is bonded above the peripheral circuits CBA via insulating layers 40 and 50 and includes pillars PL etc.

[0057] As shown in Figure 8(a), the multilayer structure 90 remaining on the conductive layer SLb side of the laminate LM bonded to the semiconductor substrate SB is removed by polishing using a polishing pad PD with CMP (Chemical Mechanical Polishing) or the like.

[0058] As shown in Figure 8(b), the multilayer structure 90 is removed, exposing the conductive layer SLb on the upper surface of the semiconductor substrate SB.

[0059] As shown in Figure 8(c), a resist pattern 21 having a pattern that matches the arrangement of each laminate LM is formed on the conductive layer SLb.

[0060] As shown in Figure 8(d), the conductive layer SLb is etched through the resist pattern 21 to form a pattern of multiple source lines SL separated for each individual laminate LM.

[0061] As shown in the top view of Figure 8(e), the source line SL is also formed in a grid-like pattern, for example, to match the arrangement of multiple laminates LM arranged in a grid pattern within the plane of the semiconductor substrate SB.

[0062] After the source line SL is formed in multiple patterns, the resist pattern 21 is removed by ashing using oxygen plasma or the like.

[0063] Subsequently, an electrode film EL is formed that connects to a source wire SL via a plug PG formed in the insulating layer 60, and the semiconductor substrate SB is sectionalized to include at least one laminate LM, thereby manufacturing the semiconductor device 1 of the embodiment.

[0064] On the other hand, the support substrate SS, which is peeled off from the semiconductor substrate SB, undergoes the regeneration process described below and is reused as a support substrate SS for the manufacture of a new semiconductor device 1.

[0065] Figure 9 is a cross-sectional view illustrating a part of the procedure for the regeneration process of the support substrate SS according to the embodiment.

[0066] As shown in Figure 9(a), the multilayer structure 90 remaining on the support substrate SS side due to the cracking is removed by grinding with a polishing pad PD. The multilayer structure 90 may also be removed by wet etching or the like.

[0067] As shown in Figure 9(b), the multilayer structure 90 is removed, and the semiconductor substrate 30 is obtained in approximately its original state.

[0068] From this point onward, the semiconductor substrate 30 is subjected to the process shown in Figure 2(a) above.

[0069] Specifically, as shown in Figure 9(c), after cleaning the semiconductor substrate 30, both sides of the semiconductor substrate 30 are covered with, for example, an insulating layer 91. Furthermore, an insulating layer 92 and a phosphorus-doped polysilicon layer 93 are formed on the semiconductor substrate 30 in this order, starting from the semiconductor substrate 30 side.

[0070] As described above, a support substrate SS is regenerated from a used semiconductor substrate 30. The regeneration process for the support substrate SS shown in Figure 9 above may also be included in the method for manufacturing the support substrate SS.

[0071] (Overview) Semiconductor devices such as three-dimensional non-volatile memory may be manufactured by forming a laminate containing multiple pillars on a support substrate, and then bonding it to a semiconductor substrate on which peripheral circuits are formed separately. The support substrate is peeled off after being bonded to the semiconductor substrate and reused repeatedly.

[0072] The support substrate is delaminated by, for example, irradiating it with laser light, causing thermal expansion of the semiconductor substrate that constitutes the support substrate, which leads to a cleavage between the semiconductor substrate and other components on its surface. This process is shown in Figure 10. Figure 10 is a schematic cross-sectional view showing the delamination of the support substrate SSx according to a comparative example.

[0073] As shown in Figure 10(a), the support substrate SSx comprises a semiconductor substrate 30 and an insulating layer 91, such as a silicon nitride layer, that protects the semiconductor substrate 30. An insulating layer 50, which is a device layer, is formed on the insulating layer 91 of the support substrate SSx, and the insulating layer 50 is joined to an insulating layer 40 that covers peripheral circuits, etc.

[0074] The laminated material described above is irradiated from the support substrate SSx side with laser light having a wavelength of, for example, 9 μm to 10 μm. As a result, the insulating layer 50 generates heat. Here, as mentioned above, the thermal conductivity of the insulating layer 91, which is a silicon nitride layer, and the thermal conductivity of the semiconductor substrate 30, which is a silicon substrate, are 10 times or more compared to the insulating layer 50, which is a silicon oxide layer, etc.

[0075] As shown in Figure 10(b), the heat from the insulating layer 50 is transferred to the semiconductor substrate 30, which also has high thermal conductivity, via the insulating layer 91, which has higher thermal conductivity than the insulating layer 50.

[0076] As shown in Figure 10(c), the insulating layer 91 side of the semiconductor substrate 30 undergoes thermal expansion.

[0077] As shown in Figure 10(d), the thermally expanded portion of the semiconductor substrate 30 pushes down the insulating layer 91, causing the interface between the semiconductor substrate 30 and the insulating layer 91 to crack.

[0078] As shown in Figure 10(e), the support substrate SSx, which is now just the semiconductor substrate 30, is peeled off due to a crack that occurs at the interface between the semiconductor substrate 30 and the insulating layer 91. At this time, the portion of the semiconductor substrate 30 that has undergone thermal expansion remains attached to the insulating layer 91 and is left on the insulating layer 40, 50 side.

[0079] Thus, when the support substrate SSx is peeled off by utilizing the thermal expansion of the semiconductor substrate 30 itself, damage such as lattice defects occurs in the thermally expanded semiconductor substrate 30. Furthermore, if the thermally expanded portion of the semiconductor substrate 30 remains on the insulating layer 40, 50 side, further damage such as irregularities occurs on the surface of the semiconductor substrate 30.

[0080] If damage such as lattice defects and irregularities occurs in the semiconductor substrate 30, when the support substrate SSx is regenerated, not only the insulating layer 91 on the semiconductor substrate 30 but also the damaged portion of the semiconductor substrate 30 must be removed. As a result, the semiconductor substrate 30 becomes thinner with each regeneration, and the number of times the support substrate SSx can be regenerated decreases.

[0081] According to the support substrate SS of the embodiment, it comprises an insulating layer 92 disposed above the semiconductor substrate 30, and a phosphorus-doped polysilicon layer 93 disposed above the insulating layer 92.

[0082] As described above, the phosphorus-doped polysilicon layer 93 has the property of absorbing laser light and acts as a starting point for cleavage in the multilayer structure 90. The insulating layer 92 absorbs laser light less readily than the polysilicon layer 93 and suppresses the transfer of heat generated in the polysilicon layer 93 to the semiconductor substrate 30. This makes it possible to suppress damage to the semiconductor substrate 30 when peeling off the support substrate SS.

[0083] According to the support substrate SS of the embodiment, the polysilicon layer 93 is 1.5 × 10 20 atom / cm 3 More preferably, 3.0 × 10 20 atom / cm 3 The above phosphorus concentration is achieved. This makes it possible to increase the absorption rate of light with wavelengths between 9 μm and 10 μm in the polysilicon layer 93.

[0084] According to the support substrate SS of the embodiment, the polysilicon layer 93 has an absorption rate of 50% or more, more preferably 75% or more, for light with a wavelength of 9 μm to 10 μm. As a result, laser light of the above wavelength is absorbed by the polysilicon layer 93, causing the polysilicon layer 93 to undergo thermal expansion.

[0085] According to the support substrate SS of this embodiment, the polysilicon layer 93 has a thermal conductivity 10 times or more that of the insulating layer 92. This allows the polysilicon layer 93 to expand thermally efficiently.

[0086] In the support substrate SS of this embodiment, the thickness of the insulating layer 92 between the semiconductor substrate 30 and the polysilicon layer 93 is 20 nm to 50 nm. This allows the insulating layer 92 to function as a heat insulating layer. Therefore, heat transfer from the polysilicon layer 93 to the semiconductor substrate 30 is suppressed, and damage to the semiconductor substrate 30 is prevented.

[0087] Here, Figure 11 shows the case where a comparative example support substrate SSz having an insulating layer 92z thicker than the insulating layer 92 of the embodiment is used. Figure 11 is a schematic cross-sectional view showing the peeling of the support substrate SSz according to the comparative example.

[0088] As shown in Figure 11(a), the support substrate SSz comprises a semiconductor substrate 30, an insulating layer 91, an insulating layer 92z which is a silicon oxide layer or the like, and a phosphorus-doped polysilicon layer 93. The insulating layer 92z of the support substrate SSz has a layer thickness of, for example, 200 nm.

[0089] An insulating layer 50, which is a device layer, is formed on the polysilicon layer 93 of the support substrate SSz, and the insulating layer 50 is bonded to an insulating layer 40 that covers the surrounding circuits, etc.

[0090] The laminated material described above is irradiated from the support substrate SSz side with laser light having a wavelength of, for example, 9 μm to 10 μm. As a result, the polysilicon layer 93 generates heat.

[0091] As shown in Figure 11(b), the insulating layer 92z, which has a thickness of, for example, 200 nm, also generates heat at this time. The heat from the insulating layer 92z is transferred to the semiconductor substrate 30 via the insulating layer 91.

[0092] As shown in Figure 11(c), the insulating layer 92z side of the polysilicon layer 93 undergoes thermal expansion, and the insulating layer 91 side of the semiconductor substrate 30 also undergoes thermal expansion.

[0093] As shown in Figure 11(d), when the semiconductor substrate 30 expands due to heat, the expanded portion of the semiconductor substrate 30 pushes down the insulating layer 91, causing cracks to occur at two locations: the interface between the semiconductor substrate 30 and the insulating layer 91, and the interface between the insulating layer 92z and the polysilicon layer 93.

[0094] As shown in Figure 11(e), the thermally expanded portion of the polysilicon layer 93 adheres to the insulating layer 92z, and furthermore, the insulating layer 92z with the thermally expanded portion of the polysilicon layer 93 and the insulating layer 91 adhere to the thermally expanded portion of the semiconductor substrate 30, causing the support substrate SSz to be peeled off.

[0095] In the exfoliation method described above, heat is transferred to the semiconductor substrate 30, which can cause lattice defects and other defects in the crystal of the semiconductor substrate 30.

[0096] In the support substrate SS of this embodiment, as described above, by appropriately adjusting the thickness of the insulating layer 92, it is possible to suppress the insulating layer 92 itself from becoming a heat source, while suppressing heat transfer to the semiconductor substrate 30 through the heat insulation effect of the insulating layer 92, thereby suppressing damage to the semiconductor substrate 30.

[0097] In the support substrate SS of this embodiment, the thickness of the polysilicon layer 93 is 100 nm or more and 300 nm or less. By forming the polysilicon layer 93 thicker than the insulating layer 92 in this way, stress is generated by the thermal expansion of the polysilicon layer 93, causing the interface with the insulating layer 92 to crack.

[0098] (Variation 1) Next, the support substrate SSa of the modified embodiment 1 will be described with reference to Figure 12. The support substrate SSa of the modified embodiment 1 differs from the above embodiment in that, in addition to the above-described layers, it has a metal layer 94.

[0099] Figure 12 is a cross-sectional view showing an example of the configuration of the support substrate SSa according to a modified example 1 of the embodiment. In the following drawings, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0100] As shown in Figure 12, the support substrate SSa of the modified example 1 has a configuration in which a multilayer structure 90a is formed on a semiconductor substrate 30. The multilayer structure 90a includes an insulating layer 91 that covers both sides of the semiconductor substrate 30, and further includes an insulating layer 92, a polysilicon layer 93, and a metal layer 94 in this order from the semiconductor substrate 30 side.

[0101] The metal layer 94 may be, for example, a transition metal layer such as a titanium layer, tantalum layer, tungsten layer, molybdenum layer, copper layer, platinum layer, or gold layer, or it may be an oxide layer of these transition metals.

[0102] As a result, when the support substrate SSa is peeled off, the metal layer 94, which has a higher reflectivity than the polysilicon layer 93 for light with wavelengths of 9 μm to 10 μm, can reflect the laser light that has passed through the polysilicon layer 93 back to the polysilicon layer 93. Therefore, the absorption efficiency of laser light in the polysilicon layer 93 can be further increased, and the thermal expansion of the polysilicon layer 93 can be further promoted.

[0103] Furthermore, the layer provided on the polysilicon layer 93 and functioning as a reflective layer does not need to contain metal, as long as it has a higher reflectivity than the polysilicon layer 93. For example, it may be a polysilicon layer with an even higher phosphorus concentration than the polysilicon layer 93.

[0104] The support substrate SSa of the modified example 1 also provides the same effects as the support substrate SS of the above-described embodiment.

[0105] (Modification 2) Next, the support substrate SSb of the modified embodiment 2 will be described with reference to Figures 13 to 15. The support substrate SSb of the modified embodiment 2 differs from the above-described embodiment in that it comprises a polysilicon layer 93b divided into multiple patterns.

[0106] In the following drawings, components similar to those in the embodiments described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0107] Figure 13 is a cross-sectional view showing an example of the configuration of a support substrate SSb according to a modified example 2 of the embodiment. As shown in Figure 13, the support substrate SSb of modified example 2 has a configuration in which a multilayer structure 90b is formed on a semiconductor substrate 30. The multilayer structure 90b includes an insulating layer 92b and a polysilicon layer 93b.

[0108] However, the support substrate SSb may have an insulating layer 91 such as a silicon nitride layer that covers both surfaces of the semiconductor substrate 30, similar to the above-described embodiment. That is, the multilayer structure 90b of the second modification may further include an insulating layer 91.

[0109] The insulating layer 92b is, for example, a silicon oxide layer or the like disposed on the semiconductor substrate 30, and a part thereof reaches the height position of the upper surface of the polysilicon layer 93b. The layer thickness of the insulating layer 92b between the lower end portion of the polysilicon layer 93b and the upper surface of the semiconductor substrate 30 is, for example, 20 nm or more and 50 nm or less.

[0110] The polysilicon layer 93b is, for example, doped with phosphorus at 1.5×10 20 atom / cm 3 or more, more preferably 3.0×10 20 atom / cm 3 or more, and has a layer thickness of, for example, 100 nm or more and 3 nm or less.

[0111] Further, the polysilicon layer 93b is divided into a plurality of patterns when viewed from the stacking direction of the insulating layer 92b and the polysilicon layer 93b, and a part thereof is buried in the insulating layer 92b that reaches the height position of the upper surface of the polysilicon layer 93b. More specifically, the upper end portion of the polysilicon layer 93b is exposed on the upper surface of the insulating layer 92b, and the lower end portion is located at a predetermined depth in the insulating layer 92b.

[0112] The shape of each of the polysilicon layers 93b divided into a plurality of patterns is, for example, rectangular when viewed from the stacking direction of the insulating layer 92b and the polysilicon layer 93b. However, the shape of the polysilicon layer 93b is not limited to a rectangle, and may be, for example, a polygon, a circle, an ellipse, or the like.

[0113] The size of the upper surface of each of the polysilicon layers 93b is, for example, 100 nm or more and 1000 nm or less. Here, the upper surface size of the polysilicon layer 93b is the maximum width when the polysilicon layer 93b is a polygon such as a rectangle, and can be the maximum diameter when the polysilicon layer 93b is a circle or the like.

[0114] The polysilicon layer 93b, which is divided into multiple patterns, is dispersed within the insulating layer 92b in a grid-like manner, for example, when viewed from the stacking direction between the insulating layer 92b and the polysilicon layer 93b. However, the arrangement of the polysilicon layer 93b is not limited to a grid shape; the polysilicon layer 93b may be arranged, for example, in a staggered pattern, or radially or concentrically on a circular semiconductor substrate 30.

[0115] When the pitch of the polysilicon layer 93b is defined as the distance between the center points of the upper surface shape of the polysilicon layer 93b, the polysilicon layer 93b has a pitch of, for example, 100 nm or more and 1000 nm or less.

[0116] The support substrate SSb described above can be manufactured as follows.

[0117] Specifically, an insulating layer 92b having a thickness equal to or greater than the thickness of the polysilicon layer 93b in addition to the thickness between the polysilicon layer 93b and the semiconductor substrate 30 is formed on the semiconductor substrate 30. Multiple recesses having the pattern of the polysilicon layer 93b are then formed in the insulating layer 92b by reactive ion etching (RIE) or the like. Subsequently, the above-mentioned support substrate SSb is manufactured by filling the recesses with phosphorus-doped polysilicon layer 93b.

[0118] Next, Figures 14 and 15 show how the support substrate SSb, configured as described above, is peeled off. Figures 14 and 15 are schematic cross-sectional views showing the peeling of the support substrate SSb according to a modified example 2 of the embodiment.

[0119] As shown in Figure 14(a), the support substrate SSb of the modified example 2 and the semiconductor substrate SB on which the peripheral circuit CBA is formed are also bonded together by bonding an insulating layer 50 formed on the support substrate SSb, which includes pillars PL and laminates LM, etc., and an insulating layer 40 that covers the peripheral circuit CBA of the semiconductor substrate SB.

[0120] A laser beam having a wavelength of, for example, 9 μm to 10 μm is irradiated onto the bonded material of the support substrate SSb and the semiconductor substrate SB from the support substrate SSb side. At this time, it is preferable to use, for example, a carbon dioxide laser having a wavelength of 10.6 μm with a larger spot diameter than in the above embodiment. The laser beam may be irradiated continuously or in a pulsed manner. When the laser beam is irradiated in a pulsed manner, the pitch of the laser beam irradiation positions can be, for example, 15 μm or less, more preferably 5 μm or less.

[0121] As a result, the polysilicon layer 93b, which is divided into multiple patterns, generates heat. At the same time, the insulating layer 92b interposed between the upper end of the polysilicon layer 93b and the semiconductor substrate 30 suppresses the transfer of heat from the polysilicon layer 93b to the semiconductor substrate 30. In addition, the insulating layer 92b interposed between the polysilicon layers 93b, which are divided into multiple patterns, suppresses the transfer of heat between the polysilicon layers 93b.

[0122] As shown in Figure 14(b), each of the polysilicon layers 93b, which are divided into multiple patterns, undergoes thermal expansion.

[0123] As shown in Figure 15(a), the thermal expansion of the polysilicon layer 93b pushes up the insulating layer 92b interposed between the upper end of the polysilicon layer 93b and the semiconductor substrate 30, causing the insulating layer 92b to rupture at a height near the upper end of the polysilicon layer 93b.

[0124] As shown in Figure 15(b), a crack occurs within the insulating layer 92b at a height near the upper end of the polysilicon layer 93b, causing the insulating layer 91b above the polysilicon layer 93b to peel off the support substrate SSb in conjunction with the semiconductor substrate 30.

[0125] As mentioned above, by making the pitch of the laser beam irradiation positions finer and irradiating the laser beam in a pulsed manner, or by irradiating the laser beam continuously, the number of cracks due to thermal expansion of the polysilicon layer increases. Therefore, the stress applied to the semiconductor substrate when the support substrate is peeled off can be further reduced, and damage to the semiconductor substrate can be further reduced.

[0126] However, if, for example, the polysilicon layer is formed as a continuous layer, increasing the area of ​​laser irradiation will cause the entire polysilicon layer to expand due to thermal expansion. The stress that causes cracking at the interface with the insulating layer arises from the coexistence of areas in the polysilicon layer that expand due to thermal expansion and areas that do not. Therefore, if the entire polysilicon layer expands due to thermal expansion, it becomes difficult to detach it from the support substrate.

[0127] In the support substrate SSb of the modified example 2, the polysilicon layer 93b is divided into multiple patterns when viewed from the stacking direction of the insulating layer 92b and the polysilicon layer 93b.

[0128] According to the above configuration, when a pulsed laser with a finer pitch of laser beam irradiation positions is used, or when continuous laser irradiation is used, the polysilicon layer 93b undergoes thermal expansion in each of the multiple divided patterns. In addition, the insulating layer 92b filling the gaps between the multiple patterns of the polysilicon layer 93b functions as a heat insulating layer, suppressing heat transfer between the polysilicon layers 93b.

[0129] Therefore, stress can be generated in the insulating layer 92b interposed between the polysilicon layer 93b and the semiconductor substrate 30, causing it to cleave and allowing the support substrate SSb to be peeled off.

[0130] Furthermore, by using pulsed lasers with a finer pitch, or by continuous irradiation of laser light, the number of cracks in the insulating layer 92b increases, reducing the stress applied to the semiconductor substrate 30 and further suppressing damage to the semiconductor substrate 30.

[0131] The support substrate SSb of the modified example 2 also provides the same effects as the support substrate SS of the above-described embodiment. [Examples]

[0132] The following describes the embodiments in detail with reference to the drawings. The embodiments show the method and results for measuring the absorption rate of light at each wavelength in the polysilicon layer, which functions as a thermal expansion layer.

[0133] Figure 16 is a schematic diagram showing the measurement substrate SSex and the method for measuring absorption rate according to the embodiment.

[0134] As shown in Figure 16, the measurement substrate SSex is a semiconductor substrate 30e with an anti-reflective layer AR formed on its back surface and a polysilicon layer 93e, etc., which is the target of absorption rate measurement, formed on its front surface.

[0135] Light is obliquely incident on the measurement substrate SSex from the light emitter PR, and the light reflected from the measurement target, such as the polysilicon layer 93e, is detected by the light receiver RC.

[0136] The wavelength of the light emitted from the light emitter PR can be changed, for example, within the range of 3.0 μm to 12 μm. The light is multiple-reflected by the upper and lower surfaces of the polysilicon layer 93e, etc., and the light reflected back to the light receiver RC is detected. At this time, by obliquely incidenting the light onto the measurement substrate SSex, these multiple-reflected lights can be separated and detected individually.

[0137] Such measurements can be performed using a spectroscopic ellipsometer or similar device equipped with a light emitter PR and a light receiver RC.

[0138] Figures 17 and 18 are schematic diagrams illustrating the method for calculating the absorption rate of the polysilicon layer 93e in the measurement substrate SSex according to the embodiment.

[0139] As shown in Figure 17, light of wavelength λ is obliquely incident on the measurement substrate SSex from the light source PR. The angle of incidence at this time is assumed to be φ0 with respect to a perpendicular line drawn from the upper surface of the polysilicon layer 93e on the measurement substrate SSex.

[0140] A portion of the light that reaches the polysilicon layer 93e from the light source PR is reflected from the upper surface of the polysilicon layer 93e and detected by the light receiver RC. The incident light from the light source PR and the reflected light from the polysilicon layer 93e each contain p-polarized and s-polarized components, respectively.

[0141] The p-polarization component is the polarization component parallel to the incident plane from the light source PR, and the s-polarization component is the polarization component perpendicular to the incident plane of light from the light source PR. The incident plane of light is the plane that includes both the incident light from the light source PR and the reflected light from the polysilicon layer 93e. The p-polarization component and the s-polarization component affect the reflectance of light of wavelength λ in the polysilicon layer 93e.

[0142] A portion of the light that reaches the polysilicon layer 93e from the floodlight PR is incident into the polysilicon layer 93e at an angle φ1 with respect to the thickness direction of the polysilicon layer 93e. A portion of the light incident into the polysilicon layer 93e is reflected by the lower surface of the polysilicon layer 93e, and another portion is transmitted to the semiconductor substrate 30e side at an angle φ2 with respect to the thickness direction of the polysilicon layer 93e.

[0143] A portion of the light reflected from the lower surface of the polysilicon layer 93e is transmitted through the upper surface of the polysilicon layer 93e and detected by the photodetector RC. Another portion of the light reflected from the lower surface of the polysilicon layer 93e is further reflected from the upper surface of the polysilicon layer 93e. A portion of the light reflected from the upper surface of the polysilicon layer 93e is reflected from the lower surface of the polysilicon layer 93e, and another portion is transmitted to the semiconductor substrate 30e.

[0144] In this way, the light reflected from the surface of the polysilicon layer 93e, and the light that undergoes multiple reflections within the polysilicon layer 93e and is finally transmitted to the photodetector RC are detected by the photodetector RC. Furthermore, based on the information about this light detected by the photodetector RC, the n / k value is determined using the following equations (1) to (8). n is the refractive index of the polysilicon layer 93e, and k is the extinction coefficient of the polysilicon layer 93e.

[0145] The intensity reflectance of the p-polarization component Rp = r p ·r p ...(1) The intensity reflectance of the s-polarization component Rs = r s ·r s ...(2) r p : Amplitude reflectance of the p-polarization component r s :s polarization component amplitude reflectance

[0146] r p =(r 1p +r 2p ×e -iδ ) / (1+r 1p ·r 2p ×e -iδ )···(3) r s =(r 1s +r 2s ×e -iδ ) / (1+r 1s ·r 2s ×e -iδ )···(4) δ=(4π / λ)nd·cosφ1···(5) i: Imaginary number δ: Phase difference when light of wavelength λ makes one round trip within the polysilicon layer 93e. n: Refractive index of polysilicon layer 93e d: Thickness of polysilicon layer 93e

[0147] Reflection Fresnel coefficient r of the p-polarized component ip = (n i · cosφ i-1 -n i-1 · cosφ i ) / (ni · cosφ i―1 +n i-1 · cosφ i )···(6) r of the reflection Fresnel coefficient of the s-polarization component is = (n i-1 · cosφ i -n i · cosφ i-1 ) / (n i-1 · cosφ i +n i · cosφ i-1 )···(7) n i : Complex refractive index of polysilicon layer 93e

[0148] n=n i -ik···(8)

[0149] Here, the refractive index and thickness of the polysilicon layer 93e are known. Therefore, the n / k value can be determined using equations (1) to (8) above.

[0150] As shown in Figure 18, when light of wavelength λ is incident on the polysilicon layer 93e with intensity I0, the wavelength of the light in the polysilicon layer 93e becomes wavelength λ / n1 depending on the refractive index n1 of the polysilicon layer 93e, and the intensity I of the light transmitted through the polysilicon layer 93e with thickness d is expressed by the following equation (9).

[0151] I=I0×exp((-4πk / λ)·d)···(9)

[0152] Furthermore, the absorption rate A of light with wavelength λ in the polysilicon layer 93e can be obtained from the following equation (10).

[0153] Absorption rate A = (I0 - I) / I0 = 1 - e -αx ...(10) α: Absorption coefficient

[0154] Figure 19 is a graph showing the absorption rate of the polysilicon layer 93e of the measurement substrate SSex according to the embodiment. In the graph of Figure 19, the horizontal axis represents the wavelength λ (nm) of light irradiated onto the polysilicon layer 93e, and the vertical axis represents the absorption rate (%) of light at each wavelength λ in the polysilicon layer 93e.

[0155] Furthermore, as shown in Figure 16, the polysilicon layer 93e consists of an undoped polysilicon layer and a 1.5 × 10 20 atom / cm 3 A phosphorus-doped polysilicon layer and 3.0 × 10 20 atom / cm 3 The phosphorus-doped polysilicon layers were used as the measurement targets. The thickness of these polysilicon layers was set to 200 nm. For comparison, the absorption rate of a silicon oxide layer with a thickness of 200 nm, which was used in the aforementioned insulating layer 92, was also measured.

[0156] Furthermore, for reference, the graph in Figure 19 shows a dashed line representing the wavelength of the carbon dioxide laser light, 9.6 μm, which was used when peeling off the support substrate SS in the above-described embodiment.

[0157] As shown in Figure 19, the light absorption rate in the silicon oxide layer with a thickness of 200 nm was approximately 45% at a wavelength λ of around 9 μm, while the light absorption rate in the undoped polysilicon layer 93e was consistently 0% over wavelengths from 3.0 μm to 12 μm.

[0158] In contrast, the absorption rate in the phosphorus-doped polysilicon layer 93e increased as the wavelength λ of light increased up to around 7.0 μm, and the increase in absorption rate was greater with increasing phosphorus concentration.

[0159] More details: 3.0×10 20 atom / cm 3 In the phosphorus-doped polysilicon layer, the absorption rate at wavelengths λ of 9 μm or greater is 75% or greater, and 1.5 × 10⁻⁶ 20 atom / cm 3 The phosphorus content was also over 50% in the phosphorus-doped polysilicon layer.

[0160] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0161] 1... Semiconductor device, 30, SB... Semiconductor substrate, 40, 50, 60, 91, 92, 92b... Insulating layer, 90, 90a, 90b... Multilayer structure, 93, 93b... Polysilicon layer, 94... Metal layer, CBA... Peripheral circuit, LM... Laminate, PL... Pillar, SS, SSa, SSb... Support substrate, WL... Word line.

Claims

1. A laminated substrate for delamination using thermal expansion by laser light, Semiconductor substrate and A first insulating layer is disposed above the semiconductor substrate, The present invention comprises a phosphorus-doped polysilicon layer disposed in contact with the first insulating layer, having a portion of which has a thickness in the direction perpendicular to the surface of the semiconductor substrate greater than that of the first insulating layer, Multilayer substrate.

2. The aforementioned polysilicon layer is 1.5 x 10 ２０ atom / cm ３ Having the above phosphorus concentration, The laminated substrate according to claim 1.

3. The aforementioned polysilicon layer is 3.0 x 10 ２０ atom / cm ３ Having the above phosphorus concentration, The laminated substrate according to claim 1.

4. In the aforementioned polysilicon layer, The absorption rate of light with wavelengths between 9 μm and 10 μm is 50% or less. The laminated substrate according to claim 1.

5. The aforementioned polysilicon layer is Viewed from the lamination direction of the first insulating layer and the polysilicon layer, it is divided into multiple patterns. The laminated substrate according to claim 1.

6. The first insulating layer is Also arranged between the plurality of patterns of the polysilicon layer, The laminated substrate according to claim 5.

7. The polysilicon layer further comprises a device layer including at least a portion of the components of a semiconductor device. The laminated substrate according to claim 1.

8. The thickness of the first insulating layer between the semiconductor substrate and the polysilicon layer is 20 nm or more and 50 nm or less. The thickness of the polysilicon layer is 100 nm or more and 300 nm or less. The thickness of the device layer is 500 nm or more. The laminated substrate according to claim 7.

9. A first insulating layer and a phosphorus-doped polysilicon layer are formed in this order above the first semiconductor substrate. A device layer including at least a portion of the components of a semiconductor device is formed above the polysilicon layer. The polysilicon layer is irradiated with laser light to cleave the first insulating layer and the polysilicon layer and remove the first semiconductor substrate. A method for manufacturing a semiconductor device.

10. The formation of the device layer is A laminate is formed on top of the polysilicon layer, in which multiple conductive layers are stacked spaced apart from each other. This includes forming a memory pillar that penetrates the laminate, The method for manufacturing a semiconductor device according to claim 9.

11. Before removing the first semiconductor substrate, Forming peripheral circuits including transistors on a second semiconductor substrate, The method further includes bonding the surface of the first semiconductor substrate on which the device layer is formed with the surface of the second semiconductor substrate on which the peripheral circuit is formed. A method for manufacturing a semiconductor device according to claim 10.

12. The formation of the aforementioned polysilicon layer is Forming a plurality of recess patterns in the first insulating layer, This includes filling the plurality of recessed patterns with the polysilicon layer. The method for manufacturing a semiconductor device according to claim 9.

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