Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can suppress current degradation caused by the operation of an internal diode. [Solution] The second semiconductor layer 7 (SiC epitaxial layer) of the semiconductor device 1 includes a first region 7A, a second region 7B, and a third region 7C in the surface layer portion of the first main surface 3. The first region 7A is a region in which point defects are distributed in a first density range. The second region 7B is located on the main surface side relative to the first region 7A and is a region in which point defects are distributed in a second density range lower than the first density range. The third region 7C is located on the SiC substrate side relative to the first region 7A and is a region in which point defects are distributed in a third density range lower than the first density range.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a SiC semiconductor device comprising an n-type SiC epitaxial layer, a source metal on the SiC epitaxial layer, a passivation film made of an organic insulator arranged to cover the source metal, an end insulating film extending from a dicing region set at the end of the SiC epitaxial layer toward the source metal and positioned below the passivation film, and a metal-under insulating film positioned below the source metal, wherein the distance from the end of the dicing region in the end insulating film toward the passivation film is longer than the distance from the end of the passivation film in the end insulating film toward the source metal. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-093209

[0004] [overview] One embodiment of this disclosure provides a semiconductor device and a method for manufacturing the same that can suppress current degradation caused by the operation of an internal diode. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a perspective view showing an example of a chip layout. [Figure 4] Figure 4 is a plan view showing the main part of the active region. [Figure 5]Figure 5 is a perspective view showing the main part of the active region. [Figure 6] Figure 6 is a perspective view showing the main part of the active region. [Figure 7] Figure 7 is a cross-sectional view showing the main part of the active region. [Figure 8] Figure 8 shows the relationship between the density of the Z1 / 2 center and the depth of the chip. [Figure 9A] Figure 9A shows a part of the manufacturing process for the semiconductor device. [Figure 9B] Figure 9B shows the process after Figure 9A. [Figure 9C] Figure 9C shows the process after Figure 9B. [Figure 9D] Figure 9D shows the process after Figure 9C. [Figure 9E] Figure 9E shows the process after Figure 9D. [Figure 9F] Figure 9F shows the process after Figure 9E. [Figure 9G] Figure 9G shows the process after Figure 9F. [Figure 10] Figure 10 shows a modified example of the point defect introduction process. [Figure 11] Figure 11 shows a modified example of the point defect introduction process. [Figure 12] Figure 12 is a perspective view showing a first modified example of the semiconductor device. [Figure 13] Figure 13 is a perspective view showing a second modified example of the semiconductor device.

[0006] [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily correspond. Corresponding structures in the attached drawings are denoted by the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0008] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "1st," "2nd," and "3rd" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is the conductivity type due to trivalent elements, and "n-type" is the conductivity type due to pentavalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] (1) Overall configuration of semiconductor device 1 Figure 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a perspective view showing an example of the layout of the chip 2.

[0011] Referring to Figures 1 to 3, the semiconductor device 1 includes a chip 2 containing a SiC single crystal. The chip 2 may also be referred to as a "SiC chip" or "semiconductor chip". In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of other polytypes.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0014] With respect to the circumferential direction of the chip 2, starting from the first side surface 5A (counterclockwise in Figure 1), the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in the first direction X along the first main surface 3 and face the second direction Y which intersects (specifically orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0015] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0017] Referring to Figure 3, the chip 2 (first main surface 3 and second main surface 4) has an off-angle θoff tilted at a predetermined angle in the predetermined off-direction Doff with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is tilted by an off-angle θoff from the vertical axis toward the off-direction Doff. Also, the c-plane of the SiC single crystal is tilted by an off-angle θoff with respect to the horizontal plane.

[0018] The off-direction Doff is preferably the a-axis direction (second direction Y) of the SiC single crystal. The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0019] The off-angle θoff is preferably 5° or less. The off-angle θoff is particularly preferably 2° or more and 4.5° or less. The off-angle θoff is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the form in which the off-angle θoff is 0° (i.e., the form in which the first principal surface 3 is a just plane with respect to the c surface).

[0020] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed on the surface of the second main surface 4. The first semiconductor layer 6 is given a drain potential as a first potential (high potential). The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)", "base region (layer)", "drain region (layer)", etc.

[0021] The first semiconductor layer 6 extends in layers along the second main surface 4, forming the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 consists of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 consists of a substrate containing a SiC single crystal (semiconductor single crystal) (SiC substrate), and has a second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 consists of a substrate made of a SiC single crystal (i.e., a SiC substrate). The first semiconductor layer 6 has the aforementioned off-direction Do and off-angle θo.

[0022] The first semiconductor layer 6 is 1 × 10 18 cm -3 The above 1 x 10 21 cm -3 The following n-type impurity concentrations may be present as peak values. Preferably, the first semiconductor layer 6 has a nearly constant n-type impurity concentration in the thickness direction.

[0023] The first semiconductor layer 6 may have a first thickness T1 of 10 μm or more and 500 μm or less. The first thickness T1 may have a value that falls within at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or more and 500 μm or less.

[0024] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed on the surface layer of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," etc. The second semiconductor layer 7 extends in layers along the first main surface 3 and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0025] In this configuration, the second semiconductor layer 7 consists of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 consists of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the aforementioned off-direction Do and off-angle θo. The second semiconductor layer 7 consists of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized starting from the first semiconductor layer 6.

[0026] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the crystal growth starting point, and the upper end of the second semiconductor layer 7 is the crystal growth ending point. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0027] The second semiconductor layer 7 includes an n-type drift region 8, which is an example of a first impurity region. In this configuration, the drift region 8 is formed by a portion (n-type portion) of the second semiconductor layer 7.

[0028] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The second semiconductor layer 7 has an off-direction Do and off-angle θo that substantially coincide with the off-direction Do and off-angle θo of the first semiconductor layer 6.

[0029] The n-type impurity concentration in the second semiconductor layer 7 (drift region 8) is preferably less than the n-type impurity concentration in the first semiconductor layer 6. The second semiconductor layer 7 is 1 × 10 15 cm -3 The above 5 x 10 16 cm -3 The n-type impurity concentration may have the following peak values. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the second semiconductor layer 7 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0030] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that falls within at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0031] The semiconductor device 1 includes an active region 9 set on the chip 2. The active region 9 is set in the inner part of the chip 2, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. Preferably, the planar area of ​​the active region 9 is 50% to 90% of the planar area of ​​the first main surface 3.

[0032] The semiconductor device 1 includes an outer peripheral region 10 set outside the active region 9 in the chip 2. The outer peripheral region 10 is located in the area between the periphery of the chip 2 and the active region 9 in a plan view. In a plan view, the outer peripheral region 10 extends in a band shape along the active region 9 and is set in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 9.

[0033] Referring to Figures 2 and 3, the semiconductor device 1 includes a plurality of trench electrode-type trench structures 11 formed on the first main surface 3 in the active region 9. The trench structures 11 may also be referred to as "gate structures," "trench gate structures," etc. A gate potential is applied to the plurality of trench structures 11 as a control potential. The plurality of trench structures 11 provide an MIS (Metal Insulator Semiconductor) structure in the active region 9.

[0034] The multiple trench structures 11 are arranged at intervals from the periphery of the active region 9 inward. In this configuration, the multiple trench structures 11 are arranged at intervals in the second direction Y and each is formed in a strip shape extending in the first direction X. In other words, the multiple trench structures 11 are arranged at intervals in the a-axis direction and each extends in the m-axis direction.

[0035] Furthermore, in this configuration, the multiple trench structures 11 are arranged in a stripe-like pattern extending in the m-axis direction (first direction X). The multiple trench structures 11 are formed with gaps between them, extending from the lower end of the second semiconductor layer 7 (first semiconductor layer 6) towards the first main surface 3, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between.

[0036] The semiconductor device 1 includes a plurality of p-type bottom wells 12 formed horizontally spaced apart within the second semiconductor layer 7 of the active region 9. Specifically, each of the plurality of bottom wells 12 is formed at the bottom of the trench structure 11.

[0037] The semiconductor device 1 includes p-type field relaxation rings 15 formed on the surface layer of the first main surface 3 in the outer peripheral region 10 (periphery of the first main surface 3). The number of field relaxation rings 15 is typically between 3 and 8. The multiple field relaxation rings 15 are formed in an electrically floating state and relax the electric field within the chip 2 at the peripheral edge of the first main surface 3. The number, width, depth, and p-type impurity concentration of the field relaxation rings 15 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field relaxation rings 15 may also be referred to as "field regions," "field rings," "guard rings," etc.

[0038] Referring to Figure 3, the multiple field relaxation rings 15 are formed at intervals in the region between the periphery of the tip 2 and the active region 9. The multiple field relaxation rings 15 are formed in a band shape extending along the active region 9 in a plan view. In this embodiment, the multiple field relaxation rings 15 are formed in an annular shape (specifically, a square annular shape) surrounding the active region 9 in a plan view.

[0039] The semiconductor device 1 includes an interlayer insulating film 16 that covers the first main surface 3. The interlayer insulating film 16 may also be referred to as an "insulating film," "interlayer film," or "intermediate insulating film." The interlayer insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0040] Referring to Figure 1, the semiconductor device 1 includes a gate pad 17 disposed on an interlayer insulating film 16. The gate pad 17 is an electrode to which a gate potential is applied from the outside. The gate pad 17 may also be referred to as a "gate pad electrode," "first pad electrode," etc. The gate pad 17 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0041] In this embodiment, the gate pad 17 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The gate pad 17 may be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the gate pad 17 is positioned at the periphery of the active region 9 in a plan view.

[0042] Figure 1 shows an example where the gate pad 17 is positioned in a region along the center of the second side surface 5B at the periphery of the active region 9. The gate pad 17 may also be positioned in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad 17 may be positioned at any corner of the active region 9 in a plan view. Alternatively, the gate pad 17 may be positioned in the center of the active region 9 in a plan view. In this embodiment, the gate pad 17 is formed in a rectangular shape in a plan view.

[0043] The semiconductor device 1 includes at least one (or more in this embodiment) gate wiring 18 drawn from a gate pad 17 onto an interlayer insulating film 16. The gate wiring 18 may be referred to as "wiring," "wiring electrode," "finger electrode," "gate finger," etc. The plurality of gate wirings 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side. In this embodiment, the plurality of gate wirings 18 include a first gate wiring 18A and a second gate wiring 18B.

[0044] The first gate wiring 18A is drawn out from the gate pad 17 toward the first side surface 5A and extends in a linear fashion along the periphery of the active region 9. The first gate wiring 18A is electrically connected to one end of a plurality of trench structures 11.

[0045] The second gate wiring 18B is drawn out from the gate pad 17 toward the third side surface 5C and extends in a line along the periphery of the active region 9. The second gate wiring 18B is electrically connected to the other ends of the multiple trench structures 11.

[0046] The semiconductor device 1 includes a source pad 19 disposed on the interlayer insulating film 16 at a distance from the gate pad 17 and gate wiring 18. The source pad 19 is an electrode to which a source potential is applied from the outside. The source pad 19 may also be referred to as a "source pad electrode," "second pad electrode," etc. The source pad 19 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0047] The source pad 19 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The source pad 19 may be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the source pad 19 is formed in a polygonal shape with a recess that is recessed along the gate pad 17 in a plan view. Of course, the source pad 19 may be formed in a rectangular shape in a plan view.

[0048] The semiconductor device 1 includes a drain pad 20 covering the second main surface 4. The drain pad 20 is an electrode to which a drain potential is applied from the outside. The drain pad 20 may also be referred to as the "drain pad electrode," "third pad electrode," etc. The drain pad 20 forms ohmic contact with the first semiconductor layer 6 exposed from the second main surface 4. In other words, the drain pad 20 is electrically connected to the drift region 8 via the first semiconductor layer 6.

[0049] The drain pad 20 may cover the entire second main surface 4 so as to be continuous with the peripheral edge (the first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 20 may cover the second main surface 4 at a distance inward from the peripheral edge of the chip 2 so as to expose the peripheral edge portion of the chip 2.

[0050] The breakdown voltage that can be applied between the source pad 19 and the drain pad 20 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0051] (2) Detailed structure of the active region 9 and the outer peripheral region 10 of the semiconductor device 1 FIG. 4 is a plan view showing the main part of the active region 9. FIGS. 5 and 6 are perspective views showing the main part of the active region 9. FIG. 5 shows a cross-section appearing near the center in the extending direction of the trench 22, and FIG. 6 shows a cross-section appearing near the end 61 in the extending direction of the trench 22. FIG. 7 is a cross-sectional view showing the main part of the active region 9 and corresponds to the perspective view of FIG. 5.

[0052] Referring to FIGS. 5 to 7, the semiconductor device 1 includes a p-type body region 21 formed in the surface layer portion of the drift region 8. The body region 21 as an example of the second impurity region is formed in a layer shape extending along the first main surface 3 in this form. The body region 21 may be formed over the entire surface layer portion of the drift region 8 and may be exposed from the first to fourth side surfaces 5A to 5D. The body region 21 is formed at a distance from the lower end of the second semiconductor layer 7 toward the first main surface 3 side.

[0053] The body region 21 is 1×10 15 cm -3 or more and 1×10 18 cm -3The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the body region 21 is adjusted by at least one trivalent element. The trivalent element in the body region 21 may be at least one of boron, aluminum, gallium, and indium.

[0054] As described above, the semiconductor device 1 includes trench structures 11. Referring to Figure 4, each trench structure 11 has a trench width WT in the direction of arrangement. Preferably, the trench width WT is less than the second thickness T2 of the second semiconductor layer 7 (see Figure 3). The trench width WT may be 0.2 μm or more and 1.5 μm or less.

[0055] The trench structure 11 has a trench depth DT in the vertical direction Z. Preferably, the trench depth DT is less than the second thickness T2 of the second semiconductor layer 7. Preferably, the trench depth DT is greater than the trench width WT. In other words, it is preferable that each of the multiple trench structures 11 has an aspect ratio DT / WT that extends in a vertical columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and preferably 1 or more and 3 or less. The trench depth DT may be 0.5 μm or more and 3.0 μm or less.

[0056] Referring to Figures 5 and 6, the multiple trench structures 11 are arranged in the second direction Y with a trench pitch PT spacing between them. Preferably, the trench pitch PT is less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT may be 0.5 μm or more and 6.0 μm or less.

[0057] Each trench structure 11 includes a trench 22, a trench insulating film 23, and an embedded conductive layer 24. The trench 22 may be referred to as an "element trench," "gate trench," etc. The trench insulating film 23 may be referred to as an "element insulating film," "gate insulating film," etc. The embedded conductive layer 24 may be referred to as an "embedded electrode," "gate electrode," etc.

[0058] The trenches 22 are formed on the first main surface 3 and define the inner surface of the trench structure 11 (the side surfaces 25 and bottom surface 26 shown in Figures 5 to 7). Preferably, the bottom surface 26 of the trenches 22 has a flat, extending portion. Between adjacent trenches 22, a mesa portion 27 is formed by a part of the second semiconductor layer 7. The mesa portion 27 provides a unit cell UC of the trench gate type transistor. The mesa portion 27 may also be referred to as the "element mesa portion".

[0059] As shown in Figure 4, the multiple trench structures 11 (multiple trenches 22) and multiple mesa portions 27 are strip-shaped extending along the first direction X and are arranged alternately in the second direction Y. The multiple trenches 22 and multiple mesa portions 27 are arranged in a stripe pattern as a whole. The mesa width WM of the mesa portions 27 is preferably wider than the trench width WT. The mesa width WM may be 0.4 μm or more and 3.0 μm or less.

[0060] The trench insulating film 23 coats the inner surface of the trench 22. The trench insulating film 23 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 23 has a single-layer structure consisting of a silicon oxide film. It is particularly preferable that the trench insulating film 23 contains a silicon oxide film made of the oxide of the chip 2.

[0061] The embedded conductive layer 24 is embedded in the trench 22 and faces the channel across the trench insulating film 23. In this embodiment, the embedded conductive layer 24 faces the body region 21 across the trench insulating film 23. The embedded conductive layer 24 may contain p-type or n-type conductive polysilicon.

[0062] As described above, the semiconductor device 1 includes a bottom well 12. The bottom well 12 is formed at the bottom of the trench structure 11. More specifically, the bottom well 12 is formed at the bottom of the trench 22. The bottom well 12 is exposed from the bottom surface 26 of the trench 22 and is in contact with the trench insulating film 23. Therefore, the upper end of the bottom well 12 is exposed to the bottom surface 26 of the trench structure 11 (trench 22). The bottom well 12 mitigates the electric field applied to the bottom of the trench 22. The bottom well 12 may also be referred to as an "electric field relaxation region," "electric field relaxation layer," "bottom electric field relaxation region," or "bottom electric field relaxation layer."

[0063] The bottom well 12 faces the embedded conductive layer 24 via the trench insulating film 23 in the depth direction of the trench 22. At the bottom of the trench 22, the trench insulating film 23 is sandwiched between the embedded conductive layer 24 and the bottom well 12.

[0064] The bottom well 12 is formed at the bottom of the trench 22 over its entire length in the direction of extension of the trench 22 and is formed in a strip shape extending in the direction of extension of the trench 22. Referring to Figure 7, the bottom well 12 is formed in the width direction of the trench 22, straddling one end of the trench 22 and the other end of the trench 22. In this embodiment, the bottom well 12 has one side formed substantially coplanar with one side 25 in the width direction of the trench 22 in the depth direction of the trench 22, and the other side formed substantially coplanar with the other side 25 in the width direction of the trench 22.

[0065] The bottom well 12 may have a higher impurity concentration than the body region 21. For example, the bottom well 12 may have a concentration of 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the bottom well 12 is adjusted by at least one trivalent element. The trivalent element in the bottom well 12 may be at least one of boron, aluminum, gallium, and indium.

[0066] Multiple bottom wells 12 overlap with multiple trench structures 11 in the depth direction of the trench 22. Specifically, multiple bottom wells 12 overlap with multiple trench structures 11 in a one-to-one correspondence in the thickness direction of the tip 2. In this configuration, each of the multiple bottom wells 12 is connected to the bottom surface 26 of the corresponding trench structure 11. Therefore, the multiple bottom wells 12 are arranged in the second direction Y with a spacing of trench pitch PT.

[0067] The bottom well 12 has a relaxation depth DR in the vertical direction Z. The relaxation depth DR is preferably 0.1 μm or more and 1.5 μm or less. Each of the multiple bottom wells 12 has a relaxation width WR in the alignment direction. The relaxation width WR may be 0.2 μm or more and 1.5 μm or less.

[0068] The semiconductor device 1 includes a source region 28 as an example of a third impurity region in the surface layer of the first main surface 3. The source region 28 is formed in the region between a plurality of trench structures 11. The source region 28 is formed in the surface layer of the body region 21.

[0069] In this configuration, multiple source regions 28 are formed across the width of the mesa portion 27, extending from one side 25 to the other side 25 (one side 25 and the other side 25 of the trench 22). The multiple source regions 28 are arranged at intervals along the extension direction of the trench 22 in each mesa portion 27. As a result, multiple channel sections CH are arranged at intervals in the second direction Y (the extension direction of the trench 22) in each mesa portion 27. In the channel sections CH, channels are formed on both sides of the trench 22's side 25 in the second direction Y of the mesa portion 27.

[0070] The source region 28 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). The source region 28 has a concentration of 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3The following n-type impurity concentrations may be present as peak values.

[0071] The semiconductor device 1 includes a body contact region 29 in the surface layer of the first main surface 3. The body contact region 29 is formed in the region between the plurality of trench structures 11. The body contact region 29 is formed adjacent to the source region 28 in the surface layer of the body region 21.

[0072] In this configuration, multiple body contact areas 29 are formed across the width of the mesa portion 27, extending from one side surface 25 to the other side surface 25 of the mesa portion 27. In each mesa portion 27, multiple source areas 28 and multiple body contact areas 29 are arranged alternately along the extending direction of the trench 22. Each source area 28 and each body contact area 29 is exposed from both sides 25 of the trench 22 (both sides 25 of the mesa portion 27).

[0073] Referring to Figure 6, the semiconductor device 1 further includes a contact well 62 and a connection region 63 near the end 61 of the trench 22.

[0074] The contact well 62 is a p-shaped region that extends in a line across multiple trenches 22 below the trench 22, connecting multiple bottom wells 12 to each other.

[0075] The impurity concentration in the contact well 62 may be equal to the impurity concentration in the bottom well 12. The impurity concentration in the contact well 62 may be higher than the impurity concentration in the body region 21. For example, the contact well 62 may have an impurity concentration of 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following p-type impurity concentrations may be present as peak values.

[0076] The connection region 63 is a p-type region that electrically connects the body region 21 and the bottom well 12 (contact well 62). The connection region 63 extends along the inner surface of the trench 22 from the body region 21 to the bottom well 12 (contact well 62). As a result, the bottom well 12 is electrically connected to the body region 21 via the contact well 62 and the connection region 63, and is fixed at the source potential. Therefore, as shown in Figure 7, the semiconductor device 1 includes a body diode 13 with the bottom well 12 as the anode and the second semiconductor layer 7 (drift region 8) as the cathode.

[0077] As described above, the semiconductor device 1 includes an interlayer insulating film 16 on the first main surface 3. Multiple contact openings 41 are formed in the interlayer insulating film 16. The multiple contact openings 41 include multiple contact openings 41 (not shown) that expose multiple trench structures 11 (embedded conductive layers 24), and multiple contact openings 41 that expose multiple source regions 28. The multiple contact openings 41 for the source regions 28 are formed in the regions between the multiple trench structures 11, exposing multiple source regions 28 and multiple body contact regions 29.

[0078] Referring to Figure 7, the semiconductor device 1 includes a main surface electrode 42. The main surface electrode 42 is formed on the first main surface 3 so as to cover the interlayer insulating film 16. The main surface electrode 42 has a laminated structure including a barrier layer 43 and a main body layer 44, which are stacked in this order from the first main surface 3 side.

[0079] The barrier layer 43 is formed in a film-like manner along the inner surfaces of the first main surface 3 and the contact opening 41. The barrier layer 43 is in ohmic contact with the first main surface 3. The barrier layer 43 may include at least one of the following: a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer.

[0080] The main body layer 44 is formed on the barrier layer 43. The main body layer 44 covers the entire main surface of the barrier layer 43. The main body layer 44 is electrically connected to the source region 28 and the body contact region 29 via the barrier layer 43. Therefore, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned source pad 19. Although not shown in the figures, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned gate pad 17 and gate wiring 18. The bottom well 12 is fixed to the source potential via the body contact region 29 and the body region 21.

[0081] The main body layer 44 includes at least one of the following: a pure Al layer (an Al layer consisting of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0082] The semiconductor device 1 includes a resin layer 45 that covers the main surface electrode 42. The resin layer 45 is formed in a film-like manner along the main surface of the main surface electrode 42. The resin layer 45 may contain a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 45 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 45 contains polybenzoxazole. A passivation film (not shown) made of an insulating film such as silicon nitride may be interposed between the resin layer 45 and the main surface electrode 42.

[0083] (3) Distribution of point defects in the second semiconductor layer 7 (SiC epitaxial layer) The SiC single crystal constituting the second semiconductor layer 7 contains various crystal defects. These crystal defects include, for example, basal plane dislocations. Basal plane dislocations are distributed, for example, in the first semiconductor layer 6 (SiC substrate) or near the interface between the first semiconductor layer 6 and the second semiconductor layer 7, and may stack and form stacking faults by expanding toward the first main surface 3. One example of a factor causing this expansion is the arrival of holes injected into the drift region 8 during the operation of a parasitic diode (in this embodiment, the body diode 13) at basal plane dislocations. Since stacking faults caused by the expansion of basal plane dislocations are one of the factors that cause current degradation of the MIS device (such as an increase in on-resistance), it is preferable to suppress their occurrence as much as possible.

[0084] Therefore, in this semiconductor device 1, many point defects known as carrier lifetime killers for SiC single crystals are distributed near the body diode 13 shown in Figure 7. This causes many holes to disappear through recombination within the drift region 8 near the body diode 13, reducing the number of holes that reach the basal plane dislocation. As a result, the basal plane dislocation becomes less likely to expand, and the current degradation of the MIS device is suppressed.

[0085] Referring to Figures 7 and 8, point defects (Z) in the second semiconductor layer 7. 1 / 2 Add an explanation about the distribution of the center. 1 / 2 The center is an example of a point defect within a SiC single crystal.

[0086] Referring to Figure 7, the second semiconductor layer 7 can be divided into a first region 7A, a second region 7B, and a third region 7C in the thickness direction of the chip 2. The first region 7A, the second region 7B, and the third region 7C are each layered regions that extend laterally along the first main surface 3, and can be divided in a manner that the second semiconductor layer 7 is sliced ​​laterally.

[0087] In the thickness direction of chip 2, the second region 7B and the third region 7C are arranged so as to sandwich the first region 7A. The second region 7B is located closer to the first main surface 3 than the first region 7A, and the third region 7C is located closer to the first semiconductor layer 6 than the first region 7A.

[0088] More specifically, the first region 7A is located on the side of the first semiconductor layer 6 that is below the bottom of the trench 22. The first region 7A may extend in the thickness direction of the chip 2 from the depth position of the bottom surface 26 of the trench 22 toward the first semiconductor layer 6 to a position below the bottom well 12. Therefore, the first region 7A may cover the bottom well 12 from two directions, the side and below. In other words, the bottom well 12 may be located within the first region 7A in the second semiconductor layer 7.

[0089] The first region 7A may be a part above the central position C in the thickness direction of the portion of the second semiconductor layer 7 from the lower end of the bottom well 12 to the first semiconductor layer 6. The thickness TA of the first region 7A may be 1 / 10 to 1 / 2 of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TA of the first region 7A may be 0.5 μm to 5 μm. For example, the lower end of the first region 7A in the thickness direction (the end on the first semiconductor layer 6 side) may be at a depth position from the lower end of the bottom well 12 that is 1 to 3 times the thickness of the bottom well 12.

[0090] The second region 7B may extend from the upper end of the first region 7A (the bottom surface 26 of the trench 22) in the thickness direction to the first main surface 3. The device structure, including the body region 21 and the source region 28, may be located within the second region 7B in the second semiconductor layer 7. In this embodiment, the second region 7B is located in the region between the multiple trenches 22.

[0091] The thickness TB of the second region 7B is greater than the thickness TA of the first region 7A. The thickness TB of the second region 7B may be between 1 / 10 and 1 / 2 of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TB of the second region 7B may be between 0.5 μm and 5 μm.

[0092] The third region 7C may extend from the lower end of the first region 7A to the first semiconductor layer 6 in the thickness direction. The third region 7C is a region exceeding half the thickness in the portion of the second semiconductor layer 7 from the lower end of the bottom well 12 to the first semiconductor layer 6. The entire third region 7C is formed by an n-type drift region 8. The thickness TC of the third region 7C is greater than the thickness TA of the first region 7A and the thickness TB of the second region 7B. The thickness TC of the third region 7C may be between 1 / 10 and 1 / 2 of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TC of the third region 7C may be between 0.5 μm and 5 μm.

[0093] Figure 8 shows Z 1 / 2 This figure shows the relationship between the density of the center and the depth of chip 2.

[0094] The solid line shown in Figure 8 represents the Z-axis in the depth direction of the chip 2. 1 / 2 Profile 14 shows an example of the gradient of the level density at the center. Z at each depth in Figure 8. 1 / 2 The level density of the center is based on results measured, for example, by DLTS (Deep Level Transient Spectroscopy). 1 / 2 The level density of the centers may be determined by assuming that it is the same as the concentration of carbon vacancies in the first semiconductor layer 6 and the second semiconductor layer 7 based on the results measured by the DLTS method.

[0095] In Figure 8, the vertical axis shows the depth of the second semiconductor layer 7 (drift region 8) and the first semiconductor layer 6, with the first main surface 3 as the reference (zero point). The horizontal axis is Z 1 / 2 This shows the energy level density at the center.

[0096] Referring to Figure 8, as shown in profile 14, Z in the second semiconductor layer 7 1 / 2 The energy level density at the center may be formed in a roughly mountain-like shape with a peak value P at a certain depth position. In this case, the profile 14 is Z from the first main surface 3 side toward the peak value P. 1 / 2 The region where the energy level density at the center gradually increases (gradual increase section 30), and the region where the Z energy level density increases from the peak value P towards the first semiconductor layer 6.1 / 2 The profile may have a portion (decrease portion 31) where the level density at the center gradually decreases. In other words, the profile 14 may gradually decrease from the peak value P toward both the first main surface 3 side and the first semiconductor layer 6 side.

[0097] In profile 14, the peak value P is surrounded by Z. 1 / 2 The convex portion containing a series of concentration changes (inflection points) where the level density of the center shifts from increasing (increasing trend) to decreasing (decreasing trend) is the concentration transition section 32.

[0098] The peak value P is Z 1 / 2 This is the maximum value of the level density at the center. In this embodiment, the peak value P is located in the first region 7A. More specifically, the concentration transition region 32 containing the peak value P may coincide with the first region 7A. The concentration transition region 32 (first region 7A) may be in a range of 0.5 μm to 5 μm that straddles the peak value P above and below in the thickness direction of the second semiconductor layer 7.

[0099] Therefore, Z of profile 14 1 / 2 The peak value P of the level density at the center is located on the first semiconductor layer 6 side of the bottom surface 26 of the trench 22 and the lower end of the bottom well 12. Z in the concentration transition region 32 (first region 7A) 1 / 2 The range of the level density at the center is 1 × 10⁻⁶. 14 cm -3 The above 1 x 10 16 cm -3 The following is also acceptable.

[0100] The gradually increasing portion 30 may coincide with the second region 7B. The gradually increasing portion 30 (second region 7B) may be in a range of 0.5 μm to 5 μm from the upper end of the first region 7A in the thickness direction of the second semiconductor layer 7. Z in the gradually increasing portion 30 (second region 7B) 1 / 2 The range of the center's energy level density is Z in the concentration transition section 32 (first region 7A). 1 / 2 It is smaller than the range of the center's energy level density.

[0101] Z in the gradually increasing section 30 (second region 7B) 1 / 2The range of the level density at the center is 1 × 10⁻⁶. 14 cm -3 The above 1 x 10 16 cm -3 The following may also apply: Z in the concentration transition region 32 (first region 7A) 1 / 2 The upper limit of the level density at the center (peak value P) and Z in the gradually increasing section 30 (second region 7B) 1 / 2 The difference between the center's level density and the upper limit of its range is 1 × 10⁻⁶ 13 cm -3 The above 1 x 10 15 cm -3 The following is also acceptable.

[0102] The tapering portion 31 may coincide with the third region 7C. The tapering portion 31 (third region 7C) may be in a range of 0.5 μm to 5 μm from the lower end of the first region 7A in the thickness direction of the second semiconductor layer 7. Z in the tapering portion 31 (third region 7C) 1 / 2 The range of the center's energy level density is Z in the concentration transition section 32 (first region 7A). 1 / 2 It is smaller than the range of the level density at the center. Furthermore, Z in the decreasing section 31 (third region 7C) 1 / 2 The range of the center's energy level density is Z in the gradually increasing section 30 (second region 7B). 1 / 2 It may be smaller than the range of the center's energy level density.

[0103] Z in the gradual decrease section 31 (third region 7C) 1 / 2 The range of the level density at the center is 1 × 10⁻⁶. 14 cm -3 The above 1 x 10 16 cm -3 The following may also apply: Z in the concentration transition region 32 (first region 7A) 1 / 2 The upper limit of the energy level density at the center (peak value P) and Z in the decreasing section 31 (third region 7C) 1 / 2 The difference between the center's level density and the upper limit of its range is 1 × 10⁻⁶ 14 cm -3 The above 1 x 10 15 cm -3 The following is also acceptable.

[0104] Profile 14 further shows Z in the first semiconductor layer 6.1 / 2 This includes a region (converging region 33) where the decrease in the level density at the center almost converges. Z in the convergeding region 33 (first semiconductor layer 6) 1 / 2 The range of the level density at the center may be smaller than that of the increasing section 30 and the decreasing section 31. Z in the converging section 33 1 / 2 The range of the level density at the center is 1 × 10⁻⁶. 10 cm -3 The above 1 x 10 14 cm -3 The following is also acceptable.

[0105] (4) Effects of semiconductor device 1 According to semiconductor device 1, the first region 7A is located near the bottom well 12 where the body diode 13 is located. In the region of the second semiconductor layer 7 (drift region 8) near the body diode 13, Z 1 / 2 The level density at the center is selectively increased. This allows more holes injected into the drift region 8 during the operation of the body diode 13 to be eliminated by recombination near the body diode 13. As a result, the number of holes reaching the basal plane dislocation can be reduced, making it more difficult for the basal plane dislocation to expand and suppressing the degradation of the current conduction of the MIS device. In addition, it is possible to prevent the basal plane dislocation from becoming a stacking fault and reaching the device structure, thus preventing the generation of leakage current caused by such stacking faults.

[0106] Furthermore, the Z region near the body diode 13 1 / 2 While selectively increasing the energy level density in the center, the region between adjacent trenches 22 is designated as the second region 7B, and its energy level density is kept lower than that of the first region 7A. This reduces interference with the on-current flowing longitudinally through the channel, and further reduces the on-resistance.

[0107] (5) Method for manufacturing semiconductor device 1 Figures 9A to 9G are diagrams showing a part of the manufacturing process of semiconductor device 1 in order of steps. Figures 9A to 9G show cross-sections corresponding to Figure 7.

[0108] To manufacture the semiconductor device 1, a SiC wafer is prepared to serve as the basis for the first semiconductor layer 6 (SiC substrate). The SiC wafer may contain basal plane dislocations. Referring to Figure 9A, SiC crystals are grown on the main surface (Si surface) of the first semiconductor layer 6 (SiC wafer) while doping with impurities using epitaxial growth methods such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), and MBE (Molecular Beam Epitaxy). As a result, n - A second semiconductor layer 7 (SiC epitaxial layer) of the same type is formed. During this process, the second semiconductor layer 7 undergoes epitaxial growth at a temperature of approximately 1600°C to 1800°C, causing some of the carbon vacancies 34 (see Figure 9B) contained in the first semiconductor layer 6 to diffuse almost uniformly into the interior of the second semiconductor layer 7.

[0109] Next, referring to Figure 9B, a point defect (in this embodiment, Z) is selectively identified in the surface layer of the first main surface 3 of the second semiconductor layer 7. 1 / 2 A center is introduced. As a result, the first region 7A, the second region 7B, and the third region 7C are formed in the second semiconductor layer 7. More specifically, when the SiC wafer on which the second semiconductor layer 7 has grown is heat-treated, the carbon vacancies 34 in the first semiconductor layer 6 diffuse into the second semiconductor layer 7.

[0110] By appropriately controlling the processing conditions (e.g., heating temperature, heating time, etc.), the carbon vacancies 34 diffuse in the desired manner. This allows Z 1 / 2 First region 7A, second region 7B, and third region 7C are formed in the second semiconductor layer 7, with centers distributed at the level density of profile 14 shown in Figure 8. The heating temperature at this time may be, for example, 1600°C to 2000°C, and the heating time may be 5 minutes to 120 minutes. The heating temperature and heating time are adjusted, for example, so that the diffusing carbon vacancies 34 do not reach the first main surface 3, and the vicinity of the bottom of the trench 22 formed in a later step becomes the destination of a large number of carbon vacancies 34.

[0111] Next, referring to Figure 9C, p-type and n-type impurity ions are sequentially implanted into the second semiconductor layer 7 via the first main surface 3. This forms a body region 21 and a source region 28 on the surface of the second semiconductor layer 7.

[0112] Next, referring to Figure 9D, the second semiconductor layer 7 is selectively dry-etched from the first main surface 3. This forms trenches 22 in the second semiconductor layer 7.

[0113] Next, referring to Figure 9E, p-type impurity ions are implanted toward the bottom surface 26 of the trench 22. This forms a bottom well 12 at the bottom of the trench 22.

[0114] Next, referring to Figure 9F, the trench insulating film 23 is formed by thermal oxidation of the inner surface (side surface 25 and bottom surface 26) of the trench 22. Then, doped polysilicon material is deposited on the second semiconductor layer 7, for example by CVD, and then etched back. This forms an embedded conductive layer 24 made of the polysilicon material remaining in the trench 22.

[0115] Next, referring to Figure 9G, the interlayer insulating film 16, the main surface electrode 42, and the resin layer 45 are formed. Subsequently, the SiC wafer is cut into individual chips to obtain the semiconductor device 1.

[0116] Note that the point defect (Z) shown in Figure 9B 1 / 2 The introduction process of the center can be replaced with the processes shown in Figures 10 and 11.

[0117] In Figure 10, point defects are introduced into the second semiconductor layer 7 by electron beam irradiation. For example, by irradiating the interior of the second semiconductor layer 7 with an electron beam from the first main surface 3 and causing damage, Z-axis defects are introduced inside the second semiconductor layer 7. 1 / 2 The level density of the center (density of carbon vacancies 34) may be selectively increased. This allows Z 1 / 2The first region 7A, the second region 7B, and the third region 7C are formed in the second semiconductor layer 7, with the centers distributed at the level density of profile 14 shown in Figure 8.

[0118] In Figure 11, during the growth of the second semiconductor layer 7 (SiC epitaxial layer) shown in Figure 9A, the distribution of the point defect level density in the second semiconductor layer 7 is adjusted by changing the supply ratio of Si introduction gas (silicon introduction gas) and C introduction gas (carbon introduction gas). For example, at the location of the first region 7A, the supply ratio of Si introduction gas is lowered compared to the locations of the second region 7B and the third region 7C. As a result, the density of carbon vacancies 34 in the first region 7A increases, so Z 1 / 2 The first region 7A, the second region 7B, and the third region 7C are formed in the second semiconductor layer 7, with the centers distributed at the level density of profile 14 shown in Figure 8.

[0119] (6) Modified example of semiconductor device 1 The following examples illustrate modifications applicable to the semiconductor device 1, with reference to Figures 12 and 13. Figures 12 and 13 show the first and second modifications of the semiconductor device 1, respectively.

[0120] Referring to Figure 12, the transistor structure Tr of this semiconductor device 1 has a planar gate type vertical structure.

[0121] The semiconductor device 1 includes a plurality of p-type body regions 76 formed in the active region 9. In this embodiment, the plurality of body regions 76, as an example of an element well, are arranged with spacing in the second direction Y and are each formed in a strip shape extending in the first direction X. The plurality of body regions 76 are arranged in a stripe shape as a whole. Each body region 76 provides a unit cell UC of a planar gate type transistor. Each unit cell UC may be the smallest unit that functions as an MIS transistor, comprising at least a body region 76 and a source region 77 (described later).

[0122] Multiple body regions 76 are, for example, 1 × 10 15 cm -31×10 or more above 18 cm -3 It may have the following p-type impurity concentration as a peak value.

[0123] The semiconductor device 1 includes one or more n-type source regions 77 formed in the surface layer portions of a plurality of body regions 76 in the active region 9. In this form, a plurality (two in this form) of source regions 77 are formed in the surface layer portion of each body region 76 with a space therebetween. The plurality of source regions 77 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The plurality of source regions 77 may have an n-type impurity concentration of 1×10 18 cm -3 1×10 or more above 21 cm -3 It may have the following n-type impurity concentration as a peak value.

[0124] The plurality of source regions 77 may each extend in a strip shape along the extending direction of the corresponding body region 76. Of course, the plurality of source regions 77 may be formed with a space therebetween along the extending direction of the corresponding body region 76. The plurality of source regions 77 are formed with a space from the bottom of the corresponding body region 76 toward the first main surface 3 side, and are formed with a space inward from the periphery of the corresponding body region 76. The plurality of source regions 77 define a channel region 78 along the first main surface 3 at the peripheral portion of the body region 76.

[0125] The semiconductor device 1 includes one or more p-type body contact regions 79 formed in the surface layer portions of a plurality of body regions 76 in the active region 9. In this form, one body contact region 79 is formed in the region between a plurality of adjacent source regions 77 in the surface layer portion of each body region 76.

[0126] The plurality of body contact regions 79 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 76. The plurality of body contact regions 79 may have a p-type impurity concentration of 1×10 18 cm -3 1×10 or more above 21 cm-3 The following p-type impurity concentrations may be present as peak values.

[0127] Multiple body contact regions 79 may each extend in a strip-like manner along the extending direction of the corresponding body region 76. Of course, multiple body contact regions 79 may be formed at intervals along the extending direction of the corresponding body region 76. Multiple body contact regions 79 may be formed at intervals from the bottom of the corresponding body region 76 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 76 toward the inward side.

[0128] The semiconductor device 1 includes a plurality of planar electrode type gate structures 80 arranged on the first main surface 3 in the active region 9. The gate structures 80 may also be referred to as "planar structures" or "planar gate structures". The plurality of gate structures 80 are spaced apart on the first main surface 3 so as to overlap at least one channel region 78 in the stacking direction. The plurality of gate structures 80 are assigned a gate potential as a control potential. The plurality of gate structures 80 control the inversion and non-inversion of channels (current paths) within the body region 76 in response to the gate potential.

[0129] In this embodiment, the multiple gate structures 80 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple gate structures 80 are each positioned to straddle two adjacent body regions 76 and cover multiple source regions 77 located within one and the other body region 76, respectively.

[0130] Each of the multiple gate structures 80 has a stacked structure including a gate insulating film 81 disposed on the first main surface 3 and a gate electrode 82 disposed on the gate insulating film 81. The gate insulating film 81 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 81 has a single-layer structure made of a silicon oxide film. The gate insulating film 81 may include a silicon oxide film made of the oxide of the chip 2. The gate electrode 82 may include p-type or n-type conductive polysilicon.

[0131] The contact opening 41 of the interlayer insulating film 16 exposes the source region 77 and the body contact region 79.

[0132] Referring to Figure 13, the bottom well 12 at the bottom of the trench 22 does not necessarily have to be formed. In this case, the body diode 13 is a body diode with the body region 21 as the anode and the second semiconductor layer 7 (drift region 8) as the cathode. Since the depth position of the body diode 13 is located closer to the first main surface 3 than in the case of Figure 7, the range of the second region 7B in Figure 7 may be the range of the first region 7A. For example, the first region 7A may be the range from the bottom surface 26 of the trench 22 to the first main surface 3 in the thickness direction.

[0133] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0134] For example, in each of the embodiments described above, trench-gate type MISFETs and planar-gate type MISFETs were shown as examples of device structures. The semiconductor device 1 may also include Schottky barrier diodes and JFETs (Junction Field Effect Transistors) as other device structures.

[0135] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0136] In each of the above-described embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0137] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0138] [Note 1-1] SiC substrate (6) and A first conductivity type SiC epitaxial layer (7) is laminated on the SiC substrate (6), A vertical element structure (Tr) is formed on the surface layer of the main surface (3) of the SiC epitaxial layer (7), and current flows in the vertical direction, which is the stacking direction of the SiC substrate (6) and the SiC epitaxial layer (7). The device structure (Tr) includes a diode (13) formed by a junction between a first impurity region (21,76) of a second conductivity type, which is part of the device structure (Tr), and the SiC epitaxial layer (7). The SiC epitaxial layer (7) includes a first region (7A), a second region (7B), and a third region (7C) in the surface portion of the main surface (3). The first region (7A) is a region in which point defects are distributed within a first density range. The second region (7B) is located on the main surface (3) side relative to the first region (7A), and is a region in which point defects are distributed in a second density range that is lower than the first density range. The semiconductor device (1) is a region where the third region (7C) is located on the SiC substrate (6) side relative to the first region (7A), and where point defects are distributed in a third density range lower than the first density range.

[0139] [Appendix 1-2] The semiconductor device (1) according to Appendix 1-1, wherein the density profile (14) of point defects in the longitudinal direction of the SiC epitaxial layer (7) has a peak (P) in the first region (7A) and gradually decreases from the peak (P) toward the second region (7B) and the third region (7C).

[0140] [Appendix 1-3] The first region (7A) is a range of 0.5 μm to 5 μm that spans above and below the peak (P) in the thickness direction of the SiC epitaxial layer (7). The second region (7B) is the range from 0.5 μm to 5 μm from the upper end of the first region (7A). The semiconductor device (1) as described in Appendix 1-2, wherein the third region (7C) is a range of 0.5 μm to 5 μm from the lower end of the first region (7A).

[0141] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein the element structure (Tr) includes a trench gate structure comprising a gate trench (22) formed on the main surface (3), a gate insulating film (23) formed on the inner surface of the gate trench (22), and a gate electrode (24) embedded in the gate trench (22) via the gate insulating film (23).

[0142] [Appendix 1-5] The gate trench (22) further includes a second conductive bottom well (12) at its bottom, The semiconductor device (1) described in Appendix 1-4, wherein the first region (7A) is located on the SiC substrate (6) side of the bottom well (12).

[0143] [Appendix 1-6] The gate trench (22) further includes a second conductive bottom well (12) at its bottom, The aforementioned point defect is Z 1 / 2 It is the center, The Z of the first region (7A) measured by the DLTS method 1 / 2 The semiconductor device (1) described in Appendix 1-4, wherein the peak (P) of the center level density is located on the SiC substrate (6) side rather than at the bottom of the gate trench (22).

[0144] [Appendix 1-7] The first region (7A) is selectively located below the bottom of the gate trench (22), The second region (7B) is located between a plurality of gate trenches (22) and is a semiconductor device (1) as described in any one of the appendices 1-4 to 1-6.

[0145] [Appendix 1-8] The device structure (Tr) includes a planar gate structure (80) comprising a gate insulating film (81) formed on the main surface (3) and a gate electrode (82) formed on the gate insulating film (81), as described in Appendix 1-2 or Appendix 1-3 (1).

[0146] [Appendix 1-9] The difference between the upper limit of the first density range and the upper limit of the third density range is 1 × 10⁻⁶ 14 cm -3 The above 1 x 10 15 cm -3 The semiconductor device (1) described in any one of the following appendices 1-1 to 1-8.

[0147] [Appendix 1-10] The aforementioned point defect is Z 1 / 2 The center is a semiconductor device (1) described in any one of the items from Appendix 1-1 to Appendix 1-9.

[0148] [Appendix 1-11] A step of growing a first-conductivity type SiC epitaxial layer (7) on a SiC substrate (6), A step of selectively introducing point defects into the surface layer of the main surface (3) of the SiC epitaxial layer (7) to form a first region (7A) in which point defects are distributed in a first density range, a second region (7B) in which point defects are distributed in a second density range smaller than the first density range on the main surface (3) side relative to the first region (7A), and a third region (7C) in which point defects are distributed in a third density range smaller than the first density range on the SiC substrate (6) side relative to the first region (7A), A method for manufacturing a semiconductor device (1), comprising the step of forming a vertical element structure (Tr) in which current flows in the vertical direction, which is the stacking direction of the SiC substrate (6) and the SiC epitaxial layer (7), having a first impurity region (21) of a second conductivity type in the surface layer portion of the main surface (3) of the SiC epitaxial layer (7) so as to form a diode (13) consisting of a junction with the SiC epitaxial layer (7).

[0149] [Appendix 1-12] The method for manufacturing a semiconductor device (1) as described in Appendix 1-11, wherein the step of introducing point defects includes a step of transferring carbon vacancies (34) in the SiC substrate (6) to the SiC epitaxial layer (7) by heat treatment.

[0150] [Appendix 1-13] The method for manufacturing a semiconductor device (1) as described in Appendix 1-11, wherein the step of introducing the point defect includes a step of introducing the point defect by electron beam irradiation.

[0151] [Appendix 1-14] The method for manufacturing a semiconductor device (1) as described in Appendix 1-11, wherein the step of introducing the point defects includes a step of introducing the point defects by changing the supply ratio of Si introduction gas and C introduction gas during the growth of the SiC epitaxial layer (7).

[0152] [Appendix 1-15] A method for manufacturing a semiconductor device (1) as described in Appendix 1-14, wherein the density of point defects in the third region (7C) and the first region (7A) is adjusted by reducing the C introduction gas during the growth of the SiC epitaxial layer (7) as the growth time progresses.

[0153] [Appendix 1-16] A method for manufacturing a semiconductor device (1) according to any one of the appendices 1-11 to 1-15, wherein the step of forming the element structure (Tr) is performed after the step of introducing the point defect. [Explanation of Symbols]

[0154] 1: Semiconductor device 2: Tip 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: First semiconductor layer 7: Second semiconductor layer 7A: 1st area 7B:Second area 7C: 3rd area 8: Drift region 9: Active area 10: Outer area 11: Trench structure 12: Bottom well 13: Body Diode 14: Profile 15: Field relaxation ring 16: Interlayer insulating film 17: Gate Pad 18: Gate wiring 18A: First gate wiring 18B: Second gate wiring 19: Sourcepad 20: Drain pad 21: Body area 22: Trench 23: Trench Insulation 24: Buried conductive layer 25: Side view 26: Bottom 27: Mesa Club 28: Source area 29: Body contact area 30: Gradual increase section 31: Decreasing section 32:Concentration transition part 33: Convergence section 34: Carbon vacancies 41: Contact opening 42: Main surface electrode 43: Barrier layer 44: Main layer 45: Resin layer 61: End 62: Contact Well 63: Connection area 76: Body area 77: Source area 78: Channel area 79: Body contact area 80: Gate structure 81: Gate Insulator 82: Guard gate C: Center position in the thickness direction

Claims

1. SiC substrate and A first conductivity type SiC epitaxial layer is laminated on the SiC substrate, A vertical element structure is formed on the surface layer of the main surface of the SiC epitaxial layer, and current flows in the vertical direction which is the stacking direction of the SiC substrate and the SiC epitaxial layer. The device includes a diode comprising a junction between a first impurity region of a second conductivity type, which is part of the device structure, and the SiC epitaxial layer. The SiC epitaxial layer includes a first region, a second region, and a third region in the surface portion of the main surface. The first region is a region in which point defects are distributed within a first density range. The second region is located on the main surface side relative to the first region, and is a region in which point defects are distributed in a second density range that is lower than the first density range. The semiconductor device is characterized in that the third region is located on the SiC substrate side relative to the first region, and point defects are distributed in a third density range lower than the first density range.

2. The semiconductor device according to claim 1, wherein the density profile of point defects in the longitudinal direction of the SiC epitaxial layer has a peak in the first region and gradually decreases from the peak toward the second and third regions.

3. The first region is a range of 0.5 μm to 5 μm that spans the peak vertically in the thickness direction of the SiC epitaxial layer. The second region is the range from 0.5 μm to 5 μm from the upper end of the first region. The semiconductor device according to claim 2, wherein the third region is a range of 0.5 μm or more and 5 μm or less from the lower end of the first region.

4. The semiconductor device according to claim 2, wherein the element structure includes a trench gate structure comprising a gate trench formed on the main surface, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film.

5. The gate trench further includes a second conductive bottom well located at the bottom of the gate trench, The semiconductor device according to claim 4, wherein the first region is located on the SiC substrate side of the bottom well.

6. The gate trench further includes a second conductive bottom well located at the bottom of the gate trench, The aforementioned point defect is Z １／２ It is the center, Z of the first region measured by the DLTS method １／２ The semiconductor device according to claim 4, wherein the peak of the center level density is located on the SiC substrate side of the bottom of the gate trench.

7. The first region is selectively located below the bottom of the gate trench, The semiconductor device according to claim 5, wherein the second region is located between a plurality of gate trenches.

8. The semiconductor device according to claim 2, wherein the element structure includes a planar gate structure comprising a gate insulating film formed on the main surface and a gate electrode formed on the gate insulating film.

9. The difference between the upper limit of the first density range and the upper limit of the third density range is 1 × 10⁻⁶ １４ cm －３ The above 1 x 10 １５ cm －３ The semiconductor device according to any one of claims 1 to 8, which is as follows:

10. The aforementioned point defect is Z １／２ The semiconductor device described in any one of claims 1 to 8, which is the center.

11. A process for growing a first-conductivity type SiC epitaxial layer on a SiC substrate, A step of selectively introducing point defects into the surface layer of the main surface of the SiC epitaxial layer to form a first region in which point defects are distributed in a first density range, a second region on the main surface side of the first region in which point defects are distributed in a second density range smaller than the first density range, and a third region on the SiC substrate side of the first region in which point defects are distributed in a third density range smaller than the first density range. A method for manufacturing a semiconductor device, comprising the step of forming a vertical element structure in which current flows in the vertical direction, which is the stacking direction of the SiC substrate and the SiC epitaxial layer, having a first impurity region of a second conductivity type so as to form a diode consisting of a junction with the SiC epitaxial layer on the surface layer portion of the main surface of the SiC epitaxial layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the step of introducing point defects includes a step of transferring carbon vacancies in the SiC substrate to the SiC epitaxial layer by heat treatment.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the step of introducing the point defect includes a step of introducing the point defect by electron beam irradiation.

14. The method for manufacturing a semiconductor device according to claim 11, wherein the step of introducing point defects includes a step of introducing point defects by changing the supply ratio of Si introduction gas and C introduction gas during the growth of the SiC epitaxial layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the density of point defects in the third region and the first region is adjusted by reducing the C introduction gas in accordance with the growth time during the growth of the SiC epitaxial layer.

16. The method for manufacturing a semiconductor device according to any one of claims 11 to 14, wherein the step of forming the element structure is performed after the step of introducing the point defect.

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