Semiconductor equipment

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that can suppress current degradation caused by the operation of an internal diode. [Solution] The semiconductor device 1 includes a first semiconductor layer 6, a second semiconductor layer 7 of a first conductivity type stacked on the first semiconductor layer 6, a vertical element structure formed on the surface of the first main surface 3 of the second semiconductor layer 7 through which current flows in the vertical direction which is the stacking direction of the first semiconductor layer 6 and the second semiconductor layer 7, a body diode 13 consisting of a junction between a body region 21 of a second conductivity type which is part of the element structure and the second semiconductor layer 7, and a first carrier inhibiting portion 34 formed on the surface of the first main surface 3 of the second semiconductor layer 7 and consisting of crystal defects 35 formed by the distribution of carrier lifetime killers, wherein the first carrier inhibiting portion 34 is uniformly distributed across the entire surface of the second semiconductor layer 7.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including an active cell portion and a peripheral portion on a semiconductor substrate (n-type base layer), a p-type body region selectively formed on the surface portion of the n-type base layer in the active cell portion, an n-type source region formed in the p-type body region, a gate electrode facing a channel region through a gate insulating film, a p-type column layer formed across the active cell portion and the peripheral portion inside the n-type base layer and disposed below the p-type body region in the active cell portion, a source electrode film electrically connected to the n-type source region, and a peripheral electrode film electrically connected to the p-type column layer in the peripheral portion. - - + + - - - - + + - -

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] One embodiment of this disclosure provides a semiconductor device capable of suppressing current-carrying degradation caused by the operation of a built-in diode.

Brief Description of the Drawings

[0005] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of this disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. [Figure 3] FIG. 3 is a perspective view showing a layout example of a chip. [Figure 4] Figure 4 is a plan view showing the main part of the active region. [Figure 5] Figure 5 is a perspective view showing the main part of the active region. [Figure 6] Figure 6 is a perspective view showing the main part of the active region. [Figure 7] Figure 7 is a cross-sectional view showing the main part of the active region. [Figure 8] Figure 8 shows the relationship between the concentration of protons and / or helium and the depth of tip 2. [Figure 9A] Figure 9A shows a part of the manufacturing process for the semiconductor device. [Figure 9B] Figure 9B shows the process after Figure 9A. [Figure 9C] Figure 9C shows the process after Figure 9B. [Figure 9D] Figure 9D shows the process after Figure 9C. [Figure 9E] Figure 9E shows the process after Figure 9D. [Figure 9F] Figure 9F shows the process after Figure 9E. [Figure 9G] Figure 9G shows the process after Figure 9F. [Figure 9H] Figure 9H shows the process after Figure 9G. [Figure 10] Figure 10 is a perspective view showing a first modified example of the semiconductor device. [Figure 11] Figure 11 is a perspective view showing a second modified example of the semiconductor device. [Figure 12] Figure 12 is a perspective view showing a third modified example of the semiconductor device. [Figure 13] Figure 13 shows the relationship between the concentration of protons and / or helium and the depth of the tip.

[0006] [Detailed explanation] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0007] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale, proportions, angles, etc., do not necessarily correspond. Corresponding structures in the attached drawings are denoted by the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0008] Where the word "substantially" is used in this specification, it includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% from the numerical value (form) being compared. In the following descriptions, words such as "1st," "2nd," and "3rd" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is the conductivity type due to trivalent elements, and "n-type" is the conductivity type due to pentavalent elements. Unless otherwise specified, trivalent elements are at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] (1) Overall configuration of semiconductor device 1 Figure 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a perspective view showing an example of the layout of the chip 2.

[0011] Referring to Figures 1 to 3, the semiconductor device 1 includes a chip 2 containing a SiC single crystal. The chip 2 may also be referred to as a "SiC chip" or "semiconductor chip". In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of other polytypes.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0014] With respect to the circumferential direction of the chip 2, starting from the first side surface 5A (counterclockwise in Figure 1), the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in the first direction X along the first main surface 3 and face the second direction Y which intersects (specifically orthogonal to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0015] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0017] Referring to Figure 3, the chip 2 (first main surface 3 and second main surface 4) has an off-angle θoff tilted at a predetermined angle in the predetermined off-direction Doff with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is tilted by an off-angle θoff from the vertical axis toward the off-direction Doff. Also, the c-plane of the SiC single crystal is tilted by an off-angle θoff with respect to the horizontal plane.

[0018] The off-direction Doff is preferably the a-axis direction (second direction Y) of the SiC single crystal. The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0019] The off-angle θoff is preferably 5° or less. The off-angle θoff is particularly preferably 2° or more and 4.5° or less. The off-angle θoff is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the form in which the off-angle θoff is 0° (i.e., the form in which the first principal surface 3 is a just plane with respect to the c surface).

[0020] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in the surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor layer 6. The first semiconductor layer 6 may be referred to as a "semiconductor region (layer)", a "base region (layer)", a "drain region (layer)", or the like.

[0021] The first semiconductor layer 6 extends in a layer shape along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 6 is composed of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this form, the first semiconductor layer 6 is made of a substrate made of a SiC single crystal (that is, a SiC substrate). The first semiconductor layer 6 has the aforementioned off-direction Do and off-angle θo.

[0022] The first semiconductor layer 6 may have a peak n-type impurity concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0023] The first semiconductor layer 6 may have a first thickness T1 of 10 μm or more and 500 μm or less. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0024] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in the surface layer portion of the first main surface 3. The second semiconductor layer 7 may be referred to as a "semiconductor region (layer)", a "drift region (layer)", or the like. The second semiconductor layer 7 extends in a layer shape along the first main surface 3 and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0025] In this configuration, the second semiconductor layer 7 consists of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 consists of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the aforementioned off-direction Do and off-angle θo. The second semiconductor layer 7 consists of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized starting from the first semiconductor layer 6.

[0026] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the crystal growth starting point, and the upper end of the second semiconductor layer 7 is the crystal growth ending point. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0027] The second semiconductor layer 7 includes an n-type drift region 8, which is an example of a first impurity region. In this configuration, the drift region 8 is formed by a portion (n-type portion) of the second semiconductor layer 7.

[0028] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The second semiconductor layer 7 has an off-direction Do and off-angle θo that substantially coincide with the off-direction Do and off-angle θo of the first semiconductor layer 6.

[0029] The n-type impurity concentration in the second semiconductor layer 7 (drift region 8) is preferably less than the n-type impurity concentration in the first semiconductor layer 6. The second semiconductor layer 7 is 1 × 10 15 cm -3 The above 5 x 10 16 cm -3 The n-type impurity concentration may have the following peak values. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the second semiconductor layer 7 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0030] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that falls within at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0031] The semiconductor device 1 includes an active region 9 set on the chip 2. The active region 9 is set in the inner part of the chip 2, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. Preferably, the planar area of ​​the active region 9 is 50% to 90% of the planar area of ​​the first main surface 3.

[0032] The semiconductor device 1 includes an outer peripheral region 10 set outside the active region 9 in the chip 2. The outer peripheral region 10 is located in the area between the periphery of the chip 2 and the active region 9 in a plan view. In a plan view, the outer peripheral region 10 extends in a band shape along the active region 9 and is set in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 9.

[0033] Referring to Figures 2 and 3, the semiconductor device 1 includes a plurality of trench electrode-type trench structures 11 formed on the first main surface 3 in the active region 9. The trench structures 11 may also be referred to as "gate structures," "trench gate structures," etc. A gate potential is applied to the plurality of trench structures 11 as a control potential. The plurality of trench structures 11 provide an MIS (Metal Insulator Semiconductor) structure in the active region 9.

[0034] The multiple trench structures 11 are arranged at intervals from the periphery of the active region 9 inward. In this configuration, the multiple trench structures 11 are arranged at intervals in the second direction Y and each is formed in a strip shape extending in the first direction X. In other words, the multiple trench structures 11 are arranged at intervals in the a-axis direction and each extends in the m-axis direction.

[0035] Furthermore, in this configuration, the multiple trench structures 11 are arranged in a stripe-like pattern extending in the m-axis direction (first direction X). The multiple trench structures 11 are formed with gaps between them, extending from the lower end of the second semiconductor layer 7 (first semiconductor layer 6) towards the first main surface 3, and face the first semiconductor layer 6 with a portion of the second semiconductor layer 7 in between.

[0036] The semiconductor device 1 includes a plurality of p-type bottom wells 12 formed horizontally spaced apart within the second semiconductor layer 7 of the active region 9. Specifically, each of the plurality of bottom wells 12 is formed at the bottom of the trench structure 11.

[0037] The semiconductor device 1 includes p-type field relaxation rings 15 formed on the surface layer of the first main surface 3 in the outer peripheral region 10 (periphery of the first main surface 3). The number of field relaxation rings 15 is typically between 3 and 8. The multiple field relaxation rings 15 are formed in an electrically floating state and relax the electric field within the chip 2 at the peripheral edge of the first main surface 3. The number, width, depth, and p-type impurity concentration of the field relaxation rings 15 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field relaxation rings 15 may also be referred to as "field regions," "field rings," "guard rings," etc.

[0038] Referring to Figure 3, the multiple field relaxation rings 15 are formed at intervals in the region between the periphery of the tip 2 and the active region 9. The multiple field relaxation rings 15 are formed in a band shape extending along the active region 9 in a plan view. In this embodiment, the multiple field relaxation rings 15 are formed in an annular shape (specifically, a square annular shape) surrounding the active region 9 in a plan view.

[0039] The semiconductor device 1 includes an interlayer insulating film 16 that covers the first main surface 3. The interlayer insulating film 16 may also be referred to as an "insulating film," "interlayer film," or "intermediate insulating film." The interlayer insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0040] Referring to Figure 1, the semiconductor device 1 includes a gate pad 17 disposed on an interlayer insulating film 16. The gate pad 17 is an electrode to which a gate potential is applied from the outside. The gate pad 17 may also be referred to as a "gate pad electrode," "first pad electrode," etc. The gate pad 17 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0041] In this embodiment, the gate pad 17 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The gate pad 17 may be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the gate pad 17 is positioned at the periphery of the active region 9 in a plan view.

[0042] Figure 1 shows an example where the gate pad 17 is positioned in a region along the center of the second side surface 5B at the periphery of the active region 9. The gate pad 17 may also be positioned in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad 17 may be positioned at any corner of the active region 9 in a plan view. Alternatively, the gate pad 17 may be positioned in the center of the active region 9 in a plan view. In this embodiment, the gate pad 17 is formed in a rectangular shape in a plan view.

[0043] The semiconductor device 1 includes at least one (or more in this embodiment) gate wiring 18 drawn from a gate pad 17 onto an interlayer insulating film 16. The gate wiring 18 may be referred to as "wiring," "wiring electrode," "finger electrode," "gate finger," etc. The plurality of gate wirings 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side. In this embodiment, the plurality of gate wirings 18 include a first gate wiring 18A and a second gate wiring 18B.

[0044] The first gate wiring 18A is drawn out from the gate pad 17 toward the first side surface 5A and extends in a linear fashion along the periphery of the active region 9. The first gate wiring 18A is electrically connected to one end of a plurality of trench structures 11.

[0045] The second gate wiring 18B is drawn out from the gate pad 17 toward the third side surface 5C and extends in a line along the periphery of the active region 9. The second gate wiring 18B is electrically connected to the other ends of the multiple trench structures 11.

[0046] The semiconductor device 1 includes a source pad 19 disposed on the interlayer insulating film 16 at a distance from the gate pad 17 and gate wiring 18. The source pad 19 is an electrode to which a source potential is applied from the outside. The source pad 19 may also be referred to as a "source pad electrode," "second pad electrode," etc. The source pad 19 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side.

[0047] The source pad 19 is positioned on the portion of the interlayer insulating film 16 that covers the active region 9. The source pad 19 may be positioned at a distance from the outer peripheral region 10 toward the active region 9. In this embodiment, the source pad 19 is formed in a polygonal shape with a recess that is recessed along the gate pad 17 in a plan view. Of course, the source pad 19 may be formed in a rectangular shape in a plan view.

[0048] The semiconductor device 1 includes a drain pad 20 covering the second main surface 4. The drain pad 20 is an electrode to which a drain potential is applied from the outside. The drain pad 20 may also be referred to as the "drain pad electrode," "third pad electrode," etc. The drain pad 20 forms ohmic contact with the first semiconductor layer 6 exposed from the second main surface 4. In other words, the drain pad 20 is electrically connected to the drift region 8 via the first semiconductor layer 6.

[0049] The drain pad 20 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Alternatively, the drain pad 20 may cover the second main surface 4 with a gap inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0050] The breakdown voltage that can be applied between the source pad 19 and the drain pad 20 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within any one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0051] (2) Detailed structure of the active region 9 and peripheral region 10 of the semiconductor device 1 Figure 4 is a plan view showing the main part of the active region 9. Figures 5 and 6 are perspective views showing the main part of the active region 9. Figure 5 shows a cross-section that appears near the center in the extending direction of the trench 22, and Figure 6 shows a cross-section that appears near the end 61 in the extending direction of the trench 22. Figure 7 is a cross-sectional view showing the main part of the active region 9, corresponding to the perspective view of Figure 5.

[0052] Referring to Figures 5 to 7, the semiconductor device 1 includes a p-type body region 21 formed on the surface of the drift region 8. In this embodiment, the body region 21, as an example of a second impurity region, is formed in layers extending along the first main surface 3. The body region 21 is formed over the entire surface of the drift region 8 and may be exposed from the first to fourth side surfaces 5A to 5D. The body region 21 is formed with a gap from the lower end of the second semiconductor layer 7 toward the first main surface 3.

[0053] Body region 21 is 1 × 10 15 cm -3 The above 1 x 10 18 cm -3The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the body region 21 is adjusted by at least one trivalent element. The trivalent element in the body region 21 may be at least one of boron, aluminum, gallium, and indium.

[0054] As described above, the semiconductor device 1 includes trench structures 11. Referring to Figure 4, each trench structure 11 has a trench width WT in the direction of arrangement. Preferably, the trench width WT is less than the second thickness T2 of the second semiconductor layer 7 (see Figure 3). The trench width WT may be 0.2 μm or more and 1.5 μm or less.

[0055] The trench structure 11 has a trench depth DT in the vertical direction Z. Preferably, the trench depth DT is less than the second thickness T2 of the second semiconductor layer 7. Preferably, the trench depth DT is greater than the trench width WT. In other words, it is preferable that each of the multiple trench structures 11 has an aspect ratio DT / WT that extends in a vertical columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and preferably 1 or more and 3 or less. The trench depth DT may be 0.5 μm or more and 3.0 μm or less.

[0056] Referring to Figures 5 and 6, the multiple trench structures 11 are arranged in the second direction Y with a trench pitch PT spacing between them. Preferably, the trench pitch PT is less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT may be 0.5 μm or more and 6.0 μm or less.

[0057] Each trench structure 11 includes a trench 22, a trench insulating film 23, and an embedded conductive layer 24. The trench 22 may be referred to as an "element trench," "gate trench," etc. The trench insulating film 23 may be referred to as an "element insulating film," "gate insulating film," etc. The embedded conductive layer 24 may be referred to as an "embedded electrode," "gate electrode," etc.

[0058] The trenches 22 are formed on the first main surface 3 and define the inner surface of the trench structure 11 (the side surfaces 25 and bottom surface 26 shown in Figures 5 to 7). Preferably, the bottom surface 26 of the trenches 22 has a flat, extending portion. Between adjacent trenches 22, a mesa portion 27 is formed by a part of the second semiconductor layer 7. The mesa portion 27 provides a unit cell UC of the trench gate type transistor. The mesa portion 27 may also be referred to as the "element mesa portion".

[0059] As shown in Figure 4, the multiple trench structures 11 (multiple trenches 22) and multiple mesa portions 27 are strip-shaped extending along the first direction X and are arranged alternately in the second direction Y. The multiple trenches 22 and multiple mesa portions 27 are arranged in a stripe pattern as a whole. The mesa width WM of the mesa portions 27 is preferably wider than the trench width WT. The mesa width WM may be 0.4 μm or more and 3.0 μm or less.

[0060] The trench insulating film 23 coats the inner surface of the trench 22. The trench insulating film 23 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 23 has a single-layer structure consisting of a silicon oxide film. It is particularly preferable that the trench insulating film 23 contains a silicon oxide film made of the oxide of the chip 2.

[0061] The embedded conductive layer 24 is embedded in the trench 22 and faces the channel across the trench insulating film 23. In this embodiment, the embedded conductive layer 24 faces the body region 21 across the trench insulating film 23. The embedded conductive layer 24 may contain p-type or n-type conductive polysilicon.

[0062] As described above, the semiconductor device 1 includes a bottom well 12. The bottom well 12 is formed at the bottom of the trench structure 11. More specifically, the bottom well 12 is formed at the bottom of the trench 22. The bottom well 12 is exposed from the bottom surface 26 of the trench 22 and is in contact with the trench insulating film 23. Therefore, the upper end of the bottom well 12 is exposed to the bottom surface 26 of the trench structure 11 (trench 22). The bottom well 12 mitigates the electric field applied to the bottom of the trench 22. The bottom well 12 may also be referred to as an "electric field relaxation region," "electric field relaxation layer," "bottom electric field relaxation region," or "bottom electric field relaxation layer."

[0063] The bottom well 12 faces the embedded conductive layer 24 via the trench insulating film 23 in the depth direction of the trench 22. At the bottom of the trench 22, the trench insulating film 23 is sandwiched between the embedded conductive layer 24 and the bottom well 12.

[0064] The bottom well 12 is formed at the bottom of the trench 22 over its entire length in the direction of extension of the trench 22 and is formed in a strip shape extending in the direction of extension of the trench 22. Referring to Figure 7, the bottom well 12 is formed in the width direction of the trench 22, straddling one end of the trench 22 and the other end of the trench 22. In this embodiment, the bottom well 12 has one side formed substantially coplanar with one side 25 in the width direction of the trench 22 in the depth direction of the trench 22, and the other side formed substantially coplanar with the other side 25 in the width direction of the trench 22.

[0065] The bottom well 12 may have a higher impurity concentration than the body region 21. For example, the bottom well 12 may have a concentration of 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following p-type impurity concentrations may be present as peak values. Preferably, the p-type impurity concentration in the bottom well 12 is adjusted by at least one trivalent element. The trivalent element in the bottom well 12 may be at least one of boron, aluminum, gallium, and indium.

[0066] Multiple bottom wells 12 overlap with multiple trench structures 11 in the depth direction of the trench 22. Specifically, multiple bottom wells 12 overlap with multiple trench structures 11 in a one-to-one correspondence in the thickness direction of the tip 2. In this configuration, each of the multiple bottom wells 12 is connected to the bottom surface 26 of the corresponding trench structure 11. Therefore, the multiple bottom wells 12 are arranged in the second direction Y with a spacing of trench pitch PT.

[0067] The bottom well 12 has a relaxation depth DR in the vertical direction Z. The relaxation depth DR is preferably 0.1 μm or more and 1.5 μm or less. Each of the multiple bottom wells 12 has a relaxation width WR in the alignment direction. The relaxation width WR may be 0.2 μm or more and 1.5 μm or less.

[0068] The semiconductor device 1 includes a source region 28 as an example of a third impurity region in the surface layer of the first main surface 3. The source region 28 is formed in the region between a plurality of trench structures 11. The source region 28 is formed in the surface layer of the body region 21.

[0069] In this configuration, multiple source regions 28 are formed across the width of the mesa portion 27, extending from one side 25 to the other side 25 (one side 25 and the other side 25 of the trench 22). The multiple source regions 28 are arranged at intervals along the extension direction of the trench 22 in each mesa portion 27. As a result, multiple channel sections CH are arranged at intervals in the second direction Y (the extension direction of the trench 22) in each mesa portion 27. In the channel sections CH, channels are formed on both sides of the trench 22's side 25 in the second direction Y of the mesa portion 27.

[0070] The source region 28 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). The source region 28 has a concentration of 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3The following n-type impurity concentrations may be present as peak values.

[0071] The semiconductor device 1 includes a body contact region 29 in the surface layer of the first main surface 3. The body contact region 29 is formed in the region between the plurality of trench structures 11. The body contact region 29 is formed adjacent to the source region 28 in the surface layer of the body region 21.

[0072] In this configuration, multiple body contact areas 29 are formed across the width of the mesa portion 27, extending from one side surface 25 to the other side surface 25 of the mesa portion 27. In each mesa portion 27, multiple source areas 28 and multiple body contact areas 29 are arranged alternately along the extending direction of the trench 22. Each source area 28 and each body contact area 29 is exposed from both sides 25 of the trench 22 (both sides 25 of the mesa portion 27).

[0073] Referring to Figure 6, the semiconductor device 1 further includes a contact well 62 and a connection region 63 near the end 61 of the trench 22.

[0074] The contact well 62 is a p-shaped region that extends in a line across multiple trenches 22 below the trench 22, connecting multiple bottom wells 12 to each other.

[0075] The impurity concentration in the contact well 62 may be equal to the impurity concentration in the bottom well 12. The impurity concentration in the contact well 62 may be higher than the impurity concentration in the body region 21. For example, the contact well 62 may have an impurity concentration of 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following p-type impurity concentrations may be present as peak values.

[0076] The connection region 63 is a p-type region that electrically connects the body region 21 and the bottom well 12 (contact well 62). The connection region 63 extends along the inner surface of the trench 22 from the body region 21 to the bottom well 12 (contact well 62). As a result, the bottom well 12 is electrically connected to the body region 21 via the contact well 62 and the connection region 63, and is fixed at the source potential. Therefore, as shown in Figure 7, the semiconductor device 1 includes a body diode 13 with the bottom well 12 as the anode and the second semiconductor layer 7 (drift region 8) as the cathode.

[0077] As described above, the semiconductor device 1 includes an interlayer insulating film 16 on the first main surface 3. Multiple contact openings 41 are formed in the interlayer insulating film 16. The multiple contact openings 41 include multiple contact openings 41 (not shown) that expose multiple trench structures 11 (embedded conductive layers 24), and multiple contact openings 41 that expose multiple source regions 28. The multiple contact openings 41 for the source regions 28 are formed in the regions between the multiple trench structures 11, exposing multiple source regions 28 and multiple body contact regions 29.

[0078] Referring to Figure 7, the semiconductor device 1 includes a main surface electrode 42. The main surface electrode 42 is formed on the first main surface 3 so as to cover the interlayer insulating film 16. The main surface electrode 42 has a laminated structure including a barrier layer 43 and a main body layer 44, which are stacked in this order from the first main surface 3 side.

[0079] The barrier layer 43 is formed in a film-like manner along the inner surfaces of the first main surface 3 and the contact opening 41. The barrier layer 43 is in ohmic contact with the first main surface 3. The barrier layer 43 may include at least one of the following: a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer.

[0080] The main body layer 44 is formed on the barrier layer 43. The main body layer 44 covers the entire main surface of the barrier layer 43. The main body layer 44 is electrically connected to the source region 28 and the body contact region 29 via the barrier layer 43. Therefore, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned source pad 19. Although not shown in the figures, the main surface electrode 42 in the semiconductor device 1 may include the aforementioned gate pad 17 and gate wiring 18. The bottom well 12 is fixed to the source potential via the body contact region 29 and the body region 21.

[0081] The main body layer 44 includes at least one of the following: a pure Al layer (an Al layer consisting of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0082] The semiconductor device 1 includes a resin layer 45 that covers the main surface electrode 42. The resin layer 45 is formed in a film-like manner along the main surface of the main surface electrode 42. The resin layer 45 may contain a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 45 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 45 contains polybenzoxazole. A passivation film (not shown) made of an insulating film such as silicon nitride may be interposed between the resin layer 45 and the main surface electrode 42.

[0083] (3) Distribution of carrier inhibition regions in the second semiconductor layer 7 (SiC epitaxial layer) The SiC single crystal constituting the second semiconductor layer 7 contains various crystal defects. These crystal defects include, for example, basal plane dislocations. Basal plane dislocations are distributed, for example, in the first semiconductor layer 6 (SiC substrate) or near the interface between the first semiconductor layer 6 and the second semiconductor layer 7, and may stack and form stacking faults by expanding toward the first main surface 3. One example of a factor causing this expansion is the arrival of holes injected into the drift region 8 during the operation of a parasitic diode (in this embodiment, the body diode 13) at basal plane dislocations. Since stacking faults caused by the expansion of basal plane dislocations are one of the factors that cause current degradation of the MIS device (such as an increase in on-resistance), it is preferable to suppress their occurrence as much as possible.

[0084] Therefore, in this semiconductor device 1, a large number of carrier lifetime killers for the SiC single crystal are distributed near the body diode 13 shown in Figure 7. A carrier inhibition region consisting of crystal defects formed by the distribution of these carrier lifetime killers can be placed near the body diode 13. This causes many holes to disappear through recombination within the drift region 8, reducing the number of holes that reach the basal plane dislocation. As a result, the basal plane dislocation becomes less likely to expand, and the degradation of the current-intensive device is suppressed.

[0085] Referring to Figures 7 and 8, the distribution of carrier inhibition regions in the second semiconductor layer 7 will be explained. In this configuration, the carrier inhibition regions consist of crystal defects formed by the introduction of protons or helium.

[0086] Referring to Figure 7, the second semiconductor layer 7 can be divided into a first region 7A, a second region 7B, a third region 7C, and a fourth region 7D in the thickness direction of the chip 2. The first region 7A, the second region 7B, the third region 7C, and the fourth region 7D are each layered regions that extend laterally along the first main surface 3, and can be divided in a manner that the second semiconductor layer 7 is sliced ​​laterally.

[0087] In the thickness direction of chip 2, the second region 7B and the third region 7C are arranged so as to sandwich the first region 7A. The second region 7B is located closer to the first main surface 3 than the first region 7A, and the third region 7C is located closer to the first semiconductor layer 6 than the first region 7A. The fourth region 7D is located even closer to the first semiconductor layer 6 than the third region 7C.

[0088] More specifically, the first region 7A is located on the side of the first semiconductor layer 6 that is below the bottom of the trench 22. The first region 7A may extend in the thickness direction of the chip 2 from the depth position of the bottom surface 26 of the trench 22 toward the first semiconductor layer 6 to a position below the bottom well 12. Therefore, the first region 7A may cover the bottom well 12 from two directions, the side and below. In other words, the bottom well 12 may be located within the first region 7A in the second semiconductor layer 7.

[0089] The first region 7A may be a part above the central position C in the thickness direction of the portion of the second semiconductor layer 7 from the lower end of the bottom well 12 to the first semiconductor layer 6. The thickness TA of the first region 7A may be 1 / 5 or more and 2 / 5 or less of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TA of the first region 7A may be 2 μm or more and 3 μm or less. For example, the lower end of the first region 7A in the thickness direction (the end on the first semiconductor layer 6 side) may be at a depth position from the lower end of the bottom well 12 that is 0.5 times or more and 5 times or less the thickness of the bottom well 12.

[0090] The second region 7B may extend from the upper end of the first region 7A (the bottom surface 26 of the trench 22) in the thickness direction to the first main surface 3. The device structure, including the body region 21 and the source region 28, may be located within the second region 7B in the second semiconductor layer 7. In this embodiment, the second region 7B is located in the region between the multiple trenches 22.

[0091] The thickness TB of the second region 7B is greater than the thickness TA of the first region 7A. The thickness TB of the second region 7B may be between 1 / 10 and 1 / 2 of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TB of the second region 7B may be between 0.5 μm and 5 μm.

[0092] The fourth region 7D may be the area from the lower end of the third region 7C in the thickness direction to the first semiconductor layer 6. The thickness TD of the fourth region 7D may be 1 / 5 or more and 2 / 5 or less of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TD of the fourth region 7D may be 2 μm or more and 3 μm or less. For example, the lower end of the fourth region 7D in the thickness direction (the end on the first semiconductor layer 6 side) may be the boundary portion 38 between the first semiconductor layer 6 and the second semiconductor layer 7.

[0093] The third region 7C may be the area between the first region 7A and the fourth region 7D in the thickness direction. The third region 7C is the region exceeding half the thickness in the portion of the second semiconductor layer 7 from the lower end of the bottom well 12 to the first semiconductor layer 6. The entire third region 7C is formed by an n-type drift region 8. The thickness TC of the third region 7C is greater than the thickness TA of the first region 7A, the thickness TB of the second region 7B, and the thickness TD of the fourth region 7D. The thickness TC of the third region 7C may be between 1 / 10 and 1 / 2 of the thickness T2 of the second semiconductor layer 7. Specifically, the thickness TC of the third region 7C may be between 0.5 μm and 5 μm.

[0094] Figure 8 shows the relationship between the concentration of protons and / or helium and the depth of tip 2.

[0095] The solid line shown in Figure 8 is profile 14, which represents an example of the proton and / or helium concentration gradient in the depth direction of tip 2. The proton and / or helium concentrations at each depth in Figure 8 are based on results measured, for example, by the SIMS (Secondary Ion Mass Spectrometry) method.

[0096] In Figure 8, the vertical axis shows the depth of the second semiconductor layer 7 (drift region 8) and the first semiconductor layer 6, with the first main surface 3 as the reference (zero point). The horizontal axis shows the concentration of protons and / or helium. If only one of the elements, protons or helium, is detected, the horizontal axis shows the concentration of that element; if both protons and helium are detected, it shows the total concentration of protons and helium.

[0097] Referring to Figure 8, as shown in profile 14, the concentration of protons and / or helium in the second semiconductor layer 7 may be formed in a roughly mountain shape with a first peak value P1 at a certain depth. In this case, profile 14 may have a portion (increasing portion 30) in which the concentration of protons and / or helium gradually increases from the first main surface 3 side toward the first peak value P1, and a portion (decreasing portion 31) in which the concentration of protons and / or helium gradually decreases from the first peak value P1 toward the first semiconductor layer 6. In other words, profile 14 may gradually decrease from the peak value P toward both the first main surface 3 side and the first semiconductor layer 6 side.

[0098] In profile 14, the convex portion containing a series of concentration changes (inflection points) where the proton and / or helium concentrations shift from increasing (increasing trend) to decreasing (decreasing trend) around the first peak value P1 is the first concentration transition section 32.

[0099] The first peak value P1 is the maximum value of the proton and / or helium concentration in the first concentration transition region 32. In this embodiment, the first peak value P1 is located in the first region 7A. More specifically, the first concentration transition region 32 containing the first peak value P1 may coincide with the first region 7A. The first concentration transition region 32 (first region 7A) may be a range of 0.5 μm to 5 μm that straddles the first peak value P1 above and below in the thickness direction of the second semiconductor layer 7.

[0100] Therefore, the first peak value P1 of the proton and / or helium concentration in profile 14 is located on the first semiconductor layer 6 side of the bottom surface 26 of the trench 22 and the lower end of the bottom well 12.

[0101] Referring to Figures 7 and 8, the first concentration transition region 32 is a first carrier inhibition region 34 in which a relatively large amount of protons and / or helium are introduced in the second semiconductor layer 7, and a quantity of crystal defects 35 that can promote hole recombination are distributed. Specifically, the range of proton and / or helium concentrations in the first concentration transition region 32 (first region 7A) is 1 × 10⁻⁶. 13 atoms / cm 3 The above is preferable to 1 × 10 14 atoms / cm 3 The above is preferable to 1 × 10 13 atoms / cm 3 The above 1 x 10 16 atoms / cm 3 The following is also acceptable.

[0102] Referring to Figure 7, the first carrier inhibitory portion 34 is uniformly distributed across the entire surface of the second semiconductor layer 7. "Uniformly distributed across the entire surface of the second semiconductor layer 7" may mean, for example, that it is uniformly distributed across the entire surface of the second semiconductor layer 7 in a plan view, as shown by dot hatching in Figure 3. More specifically, it may mean that the error in the range of proton and / or helium concentrations at multiple locations in the active region 9 in a plan view (for example, regions overlapping multiple mesa portions 27) is ±10% or less.

[0103] The gradually increasing portion 30 may coincide with the second region 7B. The gradually increasing portion 30 (second region 7B) may be in a range of 0.5 μm to 5 μm from the upper end of the first region 7A in the thickness direction of the second semiconductor layer 7. The concentration range of protons and / or helium in the gradually increasing portion 30 (second region 7B) is smaller than the concentration range of protons and / or helium in the first concentration transition portion 32 (first region 7A).

[0104] The concentration range of protons and / or helium in the gradually increasing section 30 (second region 7B) is 1 × 10⁻⁶. 16 atoms / cm 3 It is less than 1 × 10⁻⁶, preferably 1 × 10⁻⁶ 13 atoms / cm3 The above 1 x 10 15 atoms / cm 3 The following may also apply: The difference between the upper limit of the proton and / or helium concentration range (first peak value P1) in the first concentration transition section 32 (first region 7A) and the upper limit of the proton and / or helium concentration range in the gradual increase section 30 (second region 7B) is 1 × 10⁻⁶ 13 atoms / cm 3 The above 1 x 10 15 atoms / cm 3 The following is also acceptable.

[0105] The decreasing portion 31 may coincide with the third region 7C. The decreasing portion 31 (third region 7C) may be in the range of 0.5 μm to 5 μm from the lower end of the first region 7A in the thickness direction of the second semiconductor layer 7. The proton and / or helium concentration range in the decreasing portion 31 (third region 7C) is smaller than the proton and / or helium concentration range in the first concentration transition portion 32 (first region 7A). Furthermore, the proton and / or helium concentration range in the decreasing portion 31 (third region 7C) may be smaller than the proton and / or helium concentration range in the increasing portion 30 (second region 7B).

[0106] The concentration range of protons and / or helium in the decreasing region 31 (third region 7C) is 1 × 10⁻⁶. 16 atoms / cm 3 It is less than 1 × 10⁻⁶, preferably 1 × 10⁻⁶ 13 atoms / cm 3 The above 1 x 10 15 atoms / cm 3 The following may also apply: The difference between the upper limit of the proton and / or helium concentration range (first peak value P1) in the first concentration transition section 32 (first region 7A) and the upper limit of the proton and / or helium concentration range in the gradual decrease section 31 (third region 7C) is 1 × 10⁻⁶ 13 atoms / cm 3 The above 1 x 10 15 atoms / cm 3 The following is also acceptable.

[0107] Profile 14 further has a second peak value P2 near the boundary 38 between the first semiconductor layer 6 and the second semiconductor layer 7. In profile 14, the convex portion containing a series of concentration changes (inflection points) where the proton and / or helium concentrations change from increasing (increasing trend) to decreasing (decreasing trend) on either side of the second peak value P2 is the second concentration transition region 33.

[0108] The second peak value P2 is the maximum value of the proton and / or helium concentration in the second concentration transition region 33. In this embodiment, the second peak value P2 is located in the fourth region 7D. More specifically, the second concentration transition region 33 containing the second peak value P2 may coincide with the fourth region 7D. The second concentration transition region 33 (fourth region 7D) may be a range of 0.5 μm to 5 μm that straddles the second peak value P2 above and below it in the thickness direction of the second semiconductor layer 7. In this embodiment, the second peak value P2 is located within the second semiconductor layer 7.

[0109] Referring to Figures 7 and 8, the second concentration transition region 33 is a second carrier inhibitory region 36 in which a relatively large amount of protons and / or helium are introduced in the second semiconductor layer 7, and a quantity of crystal defects 37 that can promote hole recombination are distributed. Specifically, the range of proton and / or helium concentrations in the second concentration transition region 33 (fourth region 7D) is 1 × 10⁻⁶. 13 atoms / cm 3 The above is preferable to 1 × 10 14 atoms / cm 3 The above is preferable to 1 × 10 13 atoms / cm 3 The above 1 x 10 16 atoms / cm 3 The following is also acceptable.

[0110] Referring to Figure 7, the second carrier inhibitory region 36 is uniformly distributed across the entire surface of the second semiconductor layer 7. "Uniformly distributed across the entire surface of the second semiconductor layer 7" means, for example, that it may be uniformly distributed across the entire surface of the second semiconductor layer 7 in a plan view, similar to the first carrier inhibitory region 34 shown by dot hatching in Figure 3. More specifically, it may mean that the error in the range of proton and / or helium concentrations at multiple locations in the active region 9 in a plan view (for example, regions overlapping multiple mesa regions 27) is ±10% or less.

[0111] Therefore, the second carrier inhibiting portion 36 overlaps with the first carrier inhibiting portion 34 in the thickness direction of the second semiconductor layer 7. Furthermore, the second carrier inhibiting portion 36 is selectively arranged in the second semiconductor layer 7, out of the first semiconductor layer 6 and the second semiconductor layer 7.

[0112] (4) Effects of semiconductor device 1 In semiconductor device 1, a first region 7A is located near the bottom well 12 where the body diode 13 is positioned. In the region of the second semiconductor layer 7 (drift region 8) near the body diode 13, the concentration of protons and / or helium is selectively increased, and a first carrier inhibition region 34 is formed where crystal defects 35 are distributed. This allows many of the holes injected into the drift region 8 during the operation of the body diode 13 to be eliminated by recombination near the body diode 13. As a result, the number of holes that reach the basal plane dislocation can be reduced, making it more difficult for the basal plane dislocation to expand, and thus suppressing the degradation of the current conduction of the MIS device. Furthermore, it is possible to prevent the basal plane dislocation from becoming a stacking fault and reaching the device structure, thus preventing the generation of leakage current caused by such stacking faults.

[0113] Furthermore, while the concentration of protons and / or helium in the region near the body diode 13 is selectively increased, the region between adjacent trenches 22 is designated as the second region 7B, and the concentration of protons and / or helium is kept lower than that of the first region 7A. This reduces interference with the on-current flowing longitudinally through the channel, and further reduces the on-resistance.

[0114] Furthermore, a fourth region 7D is located near the boundary 38 between the first semiconductor layer 6 and the second semiconductor layer 7. In the region near the boundary 38, the concentration of protons and / or helium is selectively increased, and a second carrier inhibition region 36 is formed where crystal defects 37 are distributed. As a result, even if there are holes that pass through the first carrier inhibition region 34 toward the first semiconductor layer 6, hole recombination can be promoted in the second carrier inhibition region 36. Consequently, the expansion of basal plane dislocations can be further suppressed, and the degradation of the MIS device's electrical conductivity can be further suppressed.

[0115] (5) Method for manufacturing semiconductor device 1 Figures 9A to 9H are diagrams showing a part of the manufacturing process of semiconductor device 1 in order of steps. Figures 9A to 9H show cross-sections corresponding to Figure 7.

[0116] To manufacture the semiconductor device 1, a SiC wafer is prepared to serve as the basis for the first semiconductor layer 6 (SiC substrate). The SiC wafer may contain basal plane dislocations. Referring to Figure 9A, SiC crystals are grown on the main surface (Si surface) of the first semiconductor layer 6 (SiC wafer) while doping with impurities using epitaxial growth methods such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy), and MBE (Molecular Beam Epitaxy). As a result, n - A type 2 semiconductor layer 7 (SiC epitaxial layer) is formed.

[0117] Next, referring to Figure 9B, p-type and n-type impurity ions are sequentially implanted into the second semiconductor layer 7 via the first main surface 3. This forms a body region 21 and a source region 28 on the surface of the second semiconductor layer 7.

[0118] Next, referring to Figure 9C, the second semiconductor layer 7 is selectively dry-etched from the first main surface 3. This forms trenches 22 in the second semiconductor layer 7.

[0119] Next, referring to Figure 9D, p-type impurity ions are implanted toward the bottom surface 26 of the trench 22. This forms a bottom well 12 at the bottom of the trench 22.

[0120] Next, referring to Figure 9E, the entire surface of the first main surface 3 of the second semiconductor layer 7 is irradiated with at least one of protons and helium ions at a first energy. Either protons or helium ions may be irradiated alone, or they may be irradiated sequentially in separate steps. This introduces protons and / or helium to the position of the fourth region 7D.

[0121] Next, referring to Figure 9F, at least one of protons and helium ions is irradiated onto the entire surface of the first main surface 3 of the second semiconductor layer 7 at a second energy lower than the first energy. Either protons or helium ions may be irradiated alone, or they may be irradiated sequentially in separate steps. This introduces protons and / or helium into the first region 7A, which is shallower (on the first main surface 3 side) than the position of the fourth region 7D. After irradiation, annealing (for example, 300°C to 1200°C) is performed to form the crystal defects 35 and 37 caused by the irradiated particles as the first carrier inhibiting portion 34 and the second carrier inhibiting portion 36, respectively. Note that this annealing process at 300°C to 1200°C may be omitted.

[0122] Next, referring to Figure 9G, the trench insulating film 23 is formed by thermal oxidation of the inner surface (side surface 25 and bottom surface 26) of the trench 22. Then, doped polysilicon material is deposited on the second semiconductor layer 7, for example by CVD, and then etched back. This forms an embedded conductive layer 24 consisting of the polysilicon material remaining in the trench 22.

[0123] Next, referring to Figure 9H, the interlayer insulating film 16, the main surface electrode 42, and the resin layer 45 are formed. Subsequently, the SiC wafer is cut into individual chips to obtain the semiconductor device 1.

[0124] (6) Modified example of semiconductor device 1 The following shows modified examples of the semiconductor device 1 with reference to Figures 10 to 12. Figures 10 to 12 show the first to third modified examples of the semiconductor device 1, respectively.

[0125] Referring to Figure 10, the transistor structure Tr of this semiconductor device 1 has a planar gate type vertical structure.

[0126] The semiconductor device 1 includes a plurality of p-type body regions 76 formed in the active region 9. In this embodiment, the plurality of body regions 76, as an example of an element well, are arranged with spacing in the second direction Y and are each formed in a strip shape extending in the first direction X. The plurality of body regions 76 are arranged in a stripe shape as a whole. Each body region 76 provides a unit cell UC of a planar gate type transistor. Each unit cell UC may be the smallest unit that functions as an MIS transistor, comprising at least a body region 76 and a source region 77 (described later).

[0127] Multiple body regions 76 are, for example, 1 × 10 15 cm -3 The above 1 x 10 18 cm -3 The following p-type impurity concentrations may be present as peak values.

[0128] The semiconductor device 1 includes one or more n-type source regions 77 formed on the surface of each of the multiple body regions 76 in the active region 9. In this embodiment, multiple (two in this embodiment) source regions 77 are formed at intervals on the surface of each body region 76. The multiple source regions 77 have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 8. The multiple source regions 77 have a concentration of 1 × 10⁻¹⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following n-type impurity concentrations may be present as peak values.

[0129] Multiple source regions 77 may each extend in a strip-like manner along the extending direction of the corresponding body region 76. Of course, multiple source regions 77 may be formed at intervals along the extending direction of the corresponding body region 76. Multiple source regions 77 may be formed at intervals from the bottom of the corresponding body region 76 toward the first main surface 3, and at intervals from the periphery of the corresponding body region 76 toward the inward side. Multiple source regions 77 define channel regions 78 along the first main surface 3 at the periphery of the body region 76.

[0130] The semiconductor device 1 includes one or more p-type body contact regions 79 formed on the surface of each of the multiple body regions 76 in the active region 9. In this configuration, one body contact region 79 is formed in the region between multiple adjacent source regions 77 on the surface of each body region 76.

[0131] Multiple body contact regions 79 have a higher p-type impurity concentration (peak value) than multiple body regions 76. Multiple body contact regions 79 have a concentration of 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following p-type impurity concentrations may be present as peak values.

[0132] Multiple body contact regions 79 may each extend in a strip-like manner along the extending direction of the corresponding body region 76. Of course, multiple body contact regions 79 may be formed at intervals along the extending direction of the corresponding body region 76. Multiple body contact regions 79 may be formed at intervals from the bottom of the corresponding body region 76 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 76 toward the inward side.

[0133] The semiconductor device 1 includes a plurality of planar electrode type gate structures 80 arranged on the first main surface 3 in the active region 9. The gate structures 80 may also be referred to as "planar structures" or "planar gate structures". The plurality of gate structures 80 are spaced apart on the first main surface 3 so as to overlap at least one channel region 78 in the stacking direction. The plurality of gate structures 80 are assigned a gate potential as a control potential. The plurality of gate structures 80 control the inversion and non-inversion of channels (current paths) within the body region 76 in response to the gate potential.

[0134] In this embodiment, the multiple gate structures 80 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. In this embodiment, the multiple gate structures 80 are each positioned to straddle two adjacent body regions 76 and cover multiple source regions 77 located within one and the other body region 76, respectively.

[0135] Each of the multiple gate structures 80 has a stacked structure including a gate insulating film 81 disposed on the first main surface 3 and a gate electrode 82 disposed on the gate insulating film 81. The gate insulating film 81 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 81 has a single-layer structure made of a silicon oxide film. The gate insulating film 81 may include a silicon oxide film made of the oxide of the chip 2. The gate electrode 82 may include p-type or n-type conductive polysilicon.

[0136] The contact opening 41 of the interlayer insulating film 16 exposes the source region 77 and the body contact region 79.

[0137] Referring to Figure 11, the bottom well 12 at the bottom of the trench 22 does not necessarily have to be formed. In this case, the body diode 13 is a body diode with the body region 21 as the anode and the second semiconductor layer 7 (drift region 8) as the cathode. Since the depth position of the body diode 13 is located closer to the first main surface 3 than in the case of Figure 7, the range of the second region 7B in Figure 7 may be the range of the first region 7A. For example, the first region 7A may be the range from the bottom surface 26 of the trench 22 to the first main surface 3 in the thickness direction.

[0138] Referring to Figure 12, the second carrier inhibitor 36 may be arranged across the first semiconductor layer 6 and the second semiconductor layer 7. In this case, as shown in Figure 13, the proton and / or helium concentration range is 1 × 10⁻⁶. 13 atoms / cm 3 The above 1 x 10 16 atoms / cm 3 The second concentration transition region 33, as described below, may span the first semiconductor layer 6 and the second semiconductor layer 7. The second peak value P2 may be located in either the first semiconductor layer 6 or the second semiconductor layer 7.

[0139] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0140] For example, in each of the above embodiments, trench-gate type MISFETs and planar-gate type MISFETs were shown as examples of device structures. The semiconductor device 1 may also include Schottky barrier diodes and JFETs (Junction Field Effect Transistors) as other device structures.

[0141] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the "n-type" semiconductor region is inverted to "p-type," and the conductivity type of the "p-type" semiconductor region is inverted to "n-type." The specific configuration in this case can be obtained by replacing "n-type" with "p-type" and simultaneously replacing "p-type" with "n-type" in the above description and attached drawings.

[0142] In each of the above-described embodiments, a p-type collector region may be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0143] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0144] [Note 1-1] SiC substrate (6) and A first conductivity type SiC epitaxial layer (7) is laminated on the SiC substrate (6), A vertical element structure (Tr) is formed on the surface layer of the main surface (3) of the SiC epitaxial layer (7), and current flows in the vertical direction, which is the stacking direction of the SiC substrate (6) and the SiC epitaxial layer (7), A diode (13) consisting of a junction between a first impurity region (21,76) of a second conductivity type, which is part of the device structure (Tr), and the SiC epitaxial layer (7), The SiC epitaxial layer (7) includes a first carrier inhibiting portion (34) formed on the surface of the main surface (3) and consisting of crystal defects (35) formed by the distribution of carrier lifetime killers, The semiconductor device (1) is uniformly distributed across the entire surface of the SiC epitaxial layer (7) in the first carrier inhibiting portion (34).

[0145] [Appendix 1-2] The semiconductor device (1) described in Appendix 1-1, wherein the first carrier inhibiting portion (34) is located on the SiC substrate (6) side of the element structure (Tr).

[0146] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-1 or Appendix 1-2, wherein the first carrier inhibiting portion (34) is located on the side of the device structure (Tr) that is greater than the center (C) in the thickness direction of the SiC epitaxial layer (7).

[0147] [Appendix 1-4] The carrier lifetime killer is a proton or helium. The semiconductor device (1) according to any one of the appendices 1-1 to 1-3, wherein the profile (14) showing the concentration gradient of protons or helium in the depth direction of the SiC epitaxial layer (7) is on the SiC substrate (6) side rather than the device structure (Tr), and has a peak value (P1) on the device structure (Tr) side rather than the center (C) in the thickness direction of the SiC epitaxial layer (7).

[0148] [Appendix 1-5] The device structure (Tr) includes a trench gate structure (11) comprising a gate trench (22) formed on the main surface (3), a gate insulating film (23) formed on the inner surface of the gate trench (22), and a gate electrode (24) embedded in the gate trench (22) via the gate insulating film (23), as described in any one of the appendices 1-1 to 1-4.

[0149] [Appendix 1-6] The gate trench (22) further includes a second conductive bottom well (12) at its bottom, The semiconductor device (1) described in Appendix 1-5, wherein the first carrier inhibiting portion (34) is located on the SiC substrate (6) side of the bottom well (12).

[0150] [Appendix 1-7] The carrier lifetime killer is a proton or helium. The semiconductor device (1) according to Appendix 1-6, wherein the profile (14) showing the concentration gradient of protons or helium in the depth direction of the SiC epitaxial layer (7) has a peak value (P1) on the SiC substrate (6) side than the bottom well (12).

[0151] [Appendix 1-8] The gate trench (22) further includes a second conductive bottom well (12) at its bottom, The semiconductor device (1) according to Appendix 1-5, wherein the first carrier inhibiting portion (34) is located on the SiC substrate (6) side of the bottom well (12) and is located on the device structure (Tr) side of the center (C) in the thickness direction of the SiC epitaxial layer (7).

[0152] [Appendix 1-9] The device structure (Tr) includes a planar gate structure (80) comprising a gate insulating film (81) formed on the main surface (3) and a gate electrode (82) formed on the gate insulating film (81), as described in any one of the appendices 1-1 to 1-4.

[0153] [Appendix 1-10] The thickness (T2) of the SiC epitaxial layer (7) is 5 μm or more and 15 μm or less. The semiconductor device (1) described in any one of the appendices 1-1 to 1-9, wherein the thickness (TA) of the first carrier inhibiting portion (34) is 2 μm or more and 3 μm or less.

[0154] [Appendix 1-11] The carrier lifetime killer is a proton or helium, as described in any one of the appendices 1-1 to 1-10 (1).

[0155] [Appendix 1-12] A semiconductor device (1) according to any one of the appendices 1-1 to 1-11, further comprising a second carrier inhibiting portion (36) formed at the boundary portion (38) between the SiC substrate (6) and the SiC epitaxial layer (7), and consisting of crystal defects (37) formed by the distribution of carrier lifetime killers.

[0156] [Appendix 1-13] The semiconductor device (1) described in Appendix 1-12, wherein the second carrier inhibiting portion (36) is uniformly distributed across the entire surface of the SiC epitaxial layer (7).

[0157] [Appendix 1-14] In the thickness direction of the SiC epitaxial layer (7), the first carrier inhibiting portion (34) and the second carrier inhibiting portion (36) overlap each other, as described in Appendix 1-12 or Appendix 1-13, semiconductor device (1).

[0158] [Appendix 1-15] The semiconductor device (1) according to any one of the appendices 1-12 to 1-14, wherein the second carrier inhibitor (36) is selectively disposed on the SiC epitaxial layer (7) of the SiC substrate (6) and the SiC epitaxial layer (7).

[0159] [Appendix 1-16] The semiconductor device (1) described in any one of the appendices 1-12 to 1-14, wherein the second carrier inhibitor (36) is arranged across the SiC substrate (6) and the SiC epitaxial layer (7).

[0160] [Appendix 1-17] The semiconductor device (1) according to any one of the appendices 1-12 to 1-16, wherein the carrier lifetime killer constituting the first carrier inhibiting portion (34) and the second carrier inhibiting portion (36) is a proton or helium. [Explanation of symbols]

[0161] 1: Semiconductor device 2: Tip 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: First semiconductor layer 7: Second semiconductor layer 7A: 1st area 7B:Second area 7C: 3rd area 7D: 4th area 8: Drift region 9: Active area 10: Outer area 11: Trench structure 12: Bottom well 13: Body Diode 14: Profile 15: Field relaxation ring 16: Interlayer insulating film 17: Gate Pad 18: Gate wiring 18A: First gate wiring 18B: Second gate wiring 19: Sourcepad 20: Drain pad 21: Body area 22: Trench 23: Trench Insulation 24: Buried conductive layer 25: Side view 26: Bottom 27: Mesa Club 28: Source area 29: Body contact area 30: Gradual increase section 31: Decreasing section 32: 1st concentration transition part 33:Second concentration transition part 34: First Carrier Inhibition Unit 35: Crystal defect 36: Second carrier inhibition unit 37: Crystal defect 38: Boundary 41: Contact opening 42: Main surface electrode 43: Barrier layer 44: Main layer 45: Resin layer 61: End 62: Contact Well 63: Connection area 76: Body area 77: Source area 78: Channel area 79: Body contact area 80: Gate structure 81: Gate Insulator 82: Guard gate

Claims

1. SiC substrate and A first conductivity type SiC epitaxial layer is laminated on the SiC substrate, A vertical element structure is formed on the surface layer of the main surface of the SiC epitaxial layer, and current flows in the vertical direction which is the stacking direction of the SiC substrate and the SiC epitaxial layer. A diode comprising a junction between a first impurity region of a second conductivity type, which is part of the element structure, and the SiC epitaxial layer, The SiC epitaxial layer includes a first carrier inhibition portion formed on the surface of the main surface and consisting of crystal defects formed by the distribution of carrier lifetime killers, The semiconductor device wherein the first carrier inhibiting portion is uniformly distributed across the entire surface of the SiC epitaxial layer.

2. The semiconductor device according to claim 1, wherein the first carrier inhibiting portion is located on the SiC substrate side of the element structure.

3. The semiconductor device according to claim 2, wherein the first carrier inhibiting portion is located on the element structure side of the center in the thickness direction of the SiC epitaxial layer.

4. The carrier lifetime killer is a proton or helium. The semiconductor device according to claim 3, wherein the profile showing the concentration gradient of protons or helium in the depth direction of the SiC epitaxial layer is located on the SiC substrate side of the device structure and has a peak value on the device structure side of the center in the thickness direction of the SiC epitaxial layer.

5. The semiconductor device according to claim 2, wherein the element structure includes a trench gate structure comprising a gate trench formed on the main surface, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode embedded in the gate trench via the gate insulating film.

6. The gate trench further includes a second conductive bottom well located at the bottom of the gate trench, The semiconductor device according to claim 5, wherein the first carrier inhibiting portion is located on the SiC substrate side of the bottom well.

7. The carrier lifetime killer is a proton or helium. The semiconductor device according to claim 6, wherein the profile showing the proton or helium concentration gradient in the depth direction of the SiC epitaxial layer has a peak value on the SiC substrate side than the bottom well.

8. The gate trench further includes a second conductive bottom well located at the bottom of the gate trench, The semiconductor device according to claim 5, wherein the first carrier inhibiting portion is located on the SiC substrate side of the bottom well and on the device structure side of the center in the thickness direction of the SiC epitaxial layer.

9. The semiconductor device according to claim 3, wherein the element structure includes a planar gate structure comprising a gate insulating film formed on the main surface and a gate electrode formed on the gate insulating film.

10. The thickness of the SiC epitaxial layer is 5 μm or more and 15 μm or less. The semiconductor device according to any one of claims 1 to 9, wherein the thickness of the first carrier inhibiting portion is 2 μm or more and 3 μm or less.

11. The semiconductor device according to any one of claims 1 to 9, wherein the carrier lifetime killer is a proton or helium.

12. The semiconductor device according to any one of claims 1 to 9, further comprising a second carrier inhibition portion formed at the boundary between the SiC substrate and the SiC epitaxial layer, and consisting of crystal defects formed by the distribution of carrier lifetime killers.

13. The semiconductor device according to claim 12, wherein the second carrier inhibiting portion is uniformly distributed across the entire surface of the SiC epitaxial layer.

14. The semiconductor device according to claim 12, wherein the first carrier inhibiting portion and the second carrier inhibiting portion overlap each other in the thickness direction of the SiC epitaxial layer.

15. The semiconductor device according to claim 12, wherein the second carrier inhibitor is selectively disposed on the SiC epitaxial layer among the SiC substrate and the SiC epitaxial layer.

16. The semiconductor device according to claim 12, wherein the second carrier inhibitor is arranged across the SiC substrate and the SiC epitaxial layer.

17. The semiconductor device according to claim 12, wherein the carrier lifetime killer constituting the first carrier inhibiting portion and the second carrier inhibiting portion is a proton or helium.

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