Manufacturing method for multilayer substrates and semiconductor devices

Abstract

To minimize damage to the support substrate when peeling it off. [Solution] The laminated substrate of the embodiment is a laminated substrate for peeling using thermal expansion by laser light, comprising: a semiconductor substrate; a first insulating layer disposed above the semiconductor substrate; a first polysilicon layer disposed in contact with the first insulating layer and doped with phosphorus; and a second polysilicon layer extending through the first insulating layer and directly connecting the first polysilicon layer and the semiconductor substrate, and doped with phosphorus.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a laminated substrate and a semiconductor device.

Background Art

[0002] A semiconductor device such as a three-dimensional nonvolatile memory may be manufactured by bonding a support substrate on which a plurality of memory pillars are formed and a semiconductor substrate on which a peripheral circuit is formed. After bonding to the semiconductor substrate, the support substrate is peeled off and reused.

[0003] An insulating layer or the like for protecting the support substrate is formed on the support substrate, and the support substrate on the insulating layer side is thermally expanded by irradiation with laser light or the like. Thereby, the support substrate and the insulating layer can be cleaved to peel off the support substrate. At this time, damage such as lattice defects may occur in the support substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a method for manufacturing a laminated substrate and a semiconductor device capable of suppressing damage to the support substrate when peeling off the support substrate.

Means for Solving the Problems

[0006] The laminated substrate of the embodiment is a laminated substrate for peeling using thermal expansion by laser light, comprising: a semiconductor substrate; a first insulating layer disposed above the semiconductor substrate; a first polysilicon layer disposed in contact with the first insulating layer and doped with phosphorus; and a second polysilicon layer extending through the first insulating layer and directly connecting the first polysilicon layer and the semiconductor substrate, and doped with phosphorus. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example configuration of a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 3] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 4] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 5] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 6] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 7] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 8] A diagram illustrating, in order, some of the steps of a semiconductor device manufacturing method according to an embodiment. [Figure 9] A cross-sectional view illustrating a part of the procedure for the regeneration process of the support substrate according to the embodiment. [Figure 10] A cross-sectional view illustrating a part of the procedure for the regeneration process of the support substrate according to the embodiment. [Figure 11] A cross-sectional view showing an example of the configuration of a support substrate according to a modified embodiment. [Figure 12] A schematic cross-sectional view showing an example of how the support substrate peels off in a modified embodiment. [Figure 13] A schematic cross-sectional view showing another example of how the support substrate peels off in a modified application configuration. [Figure 14] A schematic diagram showing the measurement substrate and absorption rate measurement method according to the example. [Figure 15] A schematic diagram illustrating a method for calculating the absorption rate of the polysilicon layer in a measurement substrate according to the embodiment. [Figure 16] A schematic diagram illustrating a method for calculating the absorption rate of the polysilicon layer in a measurement substrate according to the embodiment. [Figure 17] A graph showing the absorption rate of the polysilicon layer in the measurement substrate according to the example. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0009] (Example of semiconductor device configuration) Figure 1 is a cross-sectional view showing an example configuration of the semiconductor device 1 according to an embodiment. However, hatching is omitted in Figure 1 for the sake of readability.

[0010] As shown in Figure 1, the semiconductor device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, and a laminate LM in which multiple word lines WL are stacked. The semiconductor device 1 also includes a peripheral circuit CBA provided on a semiconductor substrate SB above the laminate LM.

[0011] A source wire SL is arranged on the electrode film EL via an insulating layer 60. The source wire SL is, for example, a polysilicon layer.

[0012] Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film EL via the plugs PG. This allows a source potential to be applied to the source wire SL from outside the semiconductor device 1 via the electrode film EL and the plugs PG.

[0013] A stacked structure LM, consisting of multiple word lines WL stacked on top of each other, is arranged on the source line SL. A memory area MR is located in the center of the stacked structure LM, and contact areas ER are located at both ends of the stacked structure LM.

[0014] In the memory region MR, multiple pillars PL, which serve as memory pillars, are arranged, penetrating the word line WL in the stacking direction. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. As a result, the semiconductor device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells are arranged three-dimensionally in the memory region MR.

[0015] Multiple contacts CC are arranged in the contact region ER, each connected to a multiple word line WL. In this specification, in the extending direction of the contact CC, the end of the contact CC that connects to the word line WL is considered to be on the lower side of the semiconductor device 1.

[0016] From the contact CC, write voltage and read voltage are applied to memory cells contained in the memory area MR in the center of the stacked LM, via word lines WL located at the same height as the memory cells. In this way, these contact CCs individually draw out the word lines WL that are stacked in multiple layers.

[0017] Multiple word wires WL, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around the multiple word wires WL.

[0018] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0019] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with the insulating layer 50 covering the laminate LM, a semiconductor device 1 is formed that includes multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0020] (Method of manufacturing semiconductor devices) Next, a method for manufacturing the semiconductor device 1 of the embodiment will be described with reference to Figures 2 to 10. The method for manufacturing the semiconductor device 1 may include, in part, a method for manufacturing the support substrate SS, a method for peeling off the support substrate SS, and a method for regenerating the support substrate SS.

[0021] Figures 2 to 9 illustrate, in order, a part of the procedure for manufacturing the semiconductor device 1 according to an embodiment. Unless otherwise specified, Figures 2 to 9 are cross-sectional views of the semiconductor device 1 during the manufacturing process.

[0022] As shown in Figure 2(a), a semiconductor substrate 30 such as a silicon substrate is prepared. After cleaning both sides of the semiconductor substrate 30, an insulating layer 91 such as a silicon nitride layer is formed.

[0023] The insulating layer 91 is formed on both sides of the semiconductor substrate 30 using, for example, CVD (Chemical Vapor Deposition), with a thickness of 50 nm to 100 nm, for example, 70 nm. However, as will be described later, in this embodiment, damage to the semiconductor substrate 30 during the peeling process of the support substrate SS, which will be described later, is suppressed. Therefore, the insulating layer 91 used for surface protection does not need to be formed.

[0024] Furthermore, an insulating layer 92, such as a silicon oxide layer, is formed on the semiconductor substrate 30 covered with the insulating layer 91, for example, with a layer thickness of 20 nm to 50 nm. The insulating layer 92 functions as an insulating layer that insulates the semiconductor substrate 30 from the heat of the polysilicon layer 93, which is a heat source, during the peeling process of the support substrate SS described later.

[0025] Furthermore, multiple recesses 92r and 91r having a predetermined pattern are formed, penetrating the insulating layers 92 and 91, respectively. As a result, the semiconductor substrate 30 is exposed from the bottom surface of the recesses 92r and 91r. A polysilicon layer 93 is also formed, filling these recesses 92r and 91r and covering the upper surface of the insulating layer 92. As a result, the polysilicon layer 93 has protrusions 931 that penetrate the insulating layers 92 and 91 and reach the semiconductor substrate 30.

[0026] The main body of the polysilicon layer 93 on the upper surface of the insulating layer 92 is formed to be thicker than the insulating layer 92, for example, having a layer thickness of 100 nm to 300 nm. In addition, the polysilicon layer 93 is doped with phosphorus. By doping the polysilicon layer 93 with phosphorus, the absorption rate of light with wavelengths of 9 μm to 10 μm can be increased, and in the peeling process of the support substrate SS described later, the polysilicon layer 93 can be thermally expanded, causing the insulating layer 92 and the polysilicon layer 93 to cleave apart.

[0027] The phosphorus concentration in the polysilicon layer 93 is, for example, 1.5 × 10⁻⁶. 20 atom / cm 3 The above is more preferable, 3.0 × 10 20 atom / cm 3 This concludes the explanation. As a result, while the absorption rate of light with wavelengths between 9 μm and 10 μm is 0% in the undoped polysilicon layer, the absorption rate of the polysilicon layer 93 with the above phosphorus concentration can be increased to, for example, 50% or more, more preferably to 75%.

[0028] As a result, the polysilicon layer 93 can be heated and thermally expanded by light of the above wavelength. The thermal conductivity of the polysilicon layer 93 is more than 10 times that of the insulating layer 92, which is a silicon oxide layer or the like. In addition, when comparing the thermal conductivity of each layer of the support substrate SS, the thermal conductivity of the insulating layer 91, which is a silicon nitride layer or the like, and the thermal conductivity of the semiconductor substrate 30, which is a silicon substrate or the like, are both more than 10 times that of the insulating layer 92, which is a silicon oxide layer or the like.

[0029] Furthermore, the protrusions 931 of the polysilicon layer 93 can be doped with phosphorus at the same concentration as that of the main body of the polysilicon layer 93, more preferably at a lower concentration than that of the main body of the polysilicon layer 93. At this time, the phosphorus concentration is adjusted to maintain a level that does not impair the conductivity of the protrusions 931.

[0030] The method for adjusting the phosphorus concentration of the polysilicon layer 93 will be described in more detail. When the raw material gas for the polysilicon layer 93 is supplied to the insulating layer 92, the filling of the polysilicon layer 93 into the recesses 92r of the insulating layer 92 and the formation of the polysilicon layer 93 on the upper surface of the insulating layer 92 proceed in parallel.

[0031] When the phosphorus concentration of the protruding portion 931 is made equal to that of the main body portion of the polysilicon layer 93, the filling of the polysilicon layer 93 into the recesses 91r and 92r and the formation of the polysilicon layer 93 on the upper surface of the insulating layer 92 can be carried out continuously while maintaining a constant phosphorus concentration mixed into the raw material gas of the polysilicon layer 93.

[0032] When the phosphorus concentration of the protrusion 931 is to be lower than that of the main body portion of the polysilicon layer 93, the recesses 91r and 92r are filled with the polysilicon layer to form the protrusion 931. After the polysilicon layer with a low phosphorus concentration on the upper surface of the insulating layer 92 is removed, a polysilicon layer 93 doped with a predetermined concentration of phosphorus is formed on the insulating layer 92.

[0033] As a result, a polysilicon layer 93 is formed, each containing protrusions 931 doped with a predetermined concentration of phosphorus. The main body portion of the polysilicon layer 93 on the upper surface of the insulating layer 92 is electrically connected to the semiconductor substrate 30 by the protrusions 931 that penetrate the insulating layers 92 and 91.

[0034] Furthermore, as described above, a support substrate SS is manufactured in which a multilayer structure 90 including insulating layers 91, 92 and a polysilicon layer 93 is formed on the semiconductor substrate 30. In this way, the support substrate SS is configured as a laminated substrate in which multiple layers are formed on the semiconductor substrate 30.

[0035] The main body portion of the polysilicon layer 93 covering the upper surface of the insulating layer 92 is an example of a first polysilicon layer, and the protruding portion 931 that electrically connects the main body portion of the polysilicon layer 93 to the semiconductor substrate 30 is an example of a second polysilicon layer.

[0036] Here, the pattern of the protrusions 931 of the polysilicon layer 93 will be explained in more detail using the schematic layout diagrams in Figures 2(b) and 2(c).

[0037] Figure 2(b) is a schematic top view showing the shot regions SH and chip regions CH that will be present on the support substrate SS after the semiconductor device 1 is formed on the support substrate SS. As shown in Figure 2(b), the multiple shot regions SH each have, for example, a rectangular shape and are arranged in a grid pattern on the support substrate SS.

[0038] These shot regions SH will serve as processing units in at least some of the manufacturing processes for the semiconductor device 1, which will be described later. For example, exposure using lithography technology and pattern transfer using imprint technology will be performed for each individual shot region SH.

[0039] Each shot region SH contains one or more chip regions CH. In the example in Figure 2(b), there are eight chip regions CH contained in one shot region SH. Each chip region CH consists of one semiconductor device 1. In the final stage of the manufacturing process for the semiconductor device 1, the chip regions CH are cut into individual chips, and individual semiconductor devices 1 are manufactured.

[0040] These tip regions CH are separated from each other by calf regions CR. The calf regions CR are the parts that are cut by the dicing saw when individual tip regions CH are separated into individual pieces. When tip regions CH are separated into individual pieces, some or all of the calf regions CR disappear.

[0041] Figure 2(c) is a schematic top view showing the pattern of the protrusions 931 of the polysilicon layer 93. As shown in Figure 2(c), the protrusions 931 of the polysilicon layer 93 are positioned to overlap the individual chip regions CH in the vertical direction.

[0042] More specifically, the protrusions 931 are positioned such that their vertical positional relationship with the chip region CH is within each individual chip region CH and along the outer edge of the chip region CH. Therefore, the protrusions 931 are provided in a rectangular shape, similar to the chip region CH, and are arranged to surround the central portion of the chip region CH when viewed from above.

[0043] One or more of these rectangular protrusions 931 may be provided within a single chip region CH. In the example shown in Figure 2(c), three protrusions 931 are provided within a single chip region CH. That is, the protrusions 931 shown in Figure 2(c) surround the central part of the chip region CH in a triple layer when viewed from above.

[0044] From this point forward, a part of the semiconductor device 1 will be formed on the support substrate SS configured as described above.

[0045] As shown in Figure 3(a), a conductive layer SLb is formed on the multilayer structure 90 of the support substrate SS. The conductive layer SLb is, for example, a polysilicon layer, and later becomes the source line SL of the semiconductor device 1. However, when forming the conductive layer SLb on the multilayer structure 90, the conductive layer SLb may be formed via other layers such as a silicon oxide layer or a polysilicon layer. The layer interposed between the multilayer structure 90 and the conductive layer SLb may be a single-layer structure, a multilayer structure of the same type of layer, or a multilayer structure of different types of layers.

[0046] As shown in Figure 3(b), multiple laminates LM are formed on the conductive layer SLb by stacking multiple word lines WL spaced apart from each other. As shown in the enlarged cross-sectional view in Figure 3(c), multiple pillars PL and multiple contacts CC are formed on each individual laminate LM.

[0047] The laminate LM on which pillars PL and contacts CC are formed is formed as follows: On a conductive layer SLb formed on a support substrate SS, a laminate is formed in which multiple silicon nitride layers and multiple silicon oxide layers are alternately stacked one layer at a time.

[0048] Furthermore, multiple contact holes reaching individual silicon nitride layers are formed in a portion of this laminate. Memory holes are also formed that penetrate the laminate and reach the conductive layer SLb, and memory layers and semiconductor layers are filled into these memory holes. At this time, a portion of the memory layer on the side of the semiconductor layer is removed to electrically connect the semiconductor layer and the conductive layer SLb.

[0049] Subsequently, a process called replacement is performed to replace multiple silicon nitride layers of the laminate with conductive layers to form word lines (WL). In addition, multiple contact holes are filled with conductive layers to form contacts (CC), and upper layer wiring is formed on the upper layer of the laminate (LM).

[0050] As shown in Figure 3(c), an insulating layer 50 is formed to cover multiple laminates LM, each having multiple pillars PL and multiple contacts CC formed as described above. Electrode pads are formed on the surface of the insulating layer 50, which are electrically connected to the pillars PL and contacts CC of the laminates LM.

[0051] The insulating layer 50, which includes multiple laminates LM on which multiple pillars PL are formed, is an example of a device layer that includes at least a part of the configuration of the semiconductor device 1.

[0052] Here, the processes shown in Figure 3 include the formation of various types of layers using methods such as plasma-enhanced chemical vapor deposition (PECVD), exposure and development using lithography techniques, pattern transfer using imprint techniques, and processing of each layer using methods such as Reactive Ion Etching (RIE). In this case, for example, in plasma processing using PECVD and RIE, the insulating layer 50, which is a device layer, may become charged, causing arcing.

[0053] As described above, the support substrate SS of the embodiment has a protruding portion 931 that electrically connects the main body portion of the polysilicon layer 93 to the semiconductor substrate 30. This allows the electricity accumulated in the insulating layer 50 to be released to the semiconductor substrate 30, thereby suppressing arcing.

[0054] In this case, as described above, by forming the protrusions 931 to surround each chip region CH (see Figure 2(c)) when viewed from above, the influence of arcing on the semiconductor device 1 being manufactured and placed within the chip region CH can be suppressed more reliably. Furthermore, as described above, by forming the protrusions 931 to surround the chip region CH in multiple layers, the influence of arcing on the semiconductor device 1 can be suppressed even further.

[0055] However, as described above, there may be only one protrusion 931 provided in a single chip region CH, that is, the protrusion 931 may surround the chip region CH in a single layer.

[0056] As shown in Figure 4(a), multiple peripheral circuits CBA, including transistors TR, are formed on a semiconductor substrate SB, which is separate from the support substrate SS. The multiple peripheral circuits CBA are formed to correspond to, for example, each of the multiple laminates LM. An insulating layer 40 is also formed to cover the peripheral circuits CBA. Electrode pads are formed on the surface of the insulating layer 40 that are electrically connected to the transistors TR and other components of the peripheral circuits CBA.

[0057] As shown in Figure 4(b), the side of the support substrate SS on which the laminate LM etc. is formed is placed opposite the side of the semiconductor substrate SB on which the peripheral circuit CBA etc. is formed, and the insulating layer 50 on the support substrate SS side and the insulating layer 40 on the semiconductor substrate SB side are joined together to bond the support substrate SS and the semiconductor substrate SB.

[0058] These insulating layers 50 and 40 can be joined by, for example, activating their surfaces in advance through plasma treatment. When joining the insulating layers 50 and 40, the support substrate SS and the semiconductor substrate SB are aligned so that the electrode pads formed on the insulating layer 50 and the electrode pads formed on the insulating layer 40 overlap.

[0059] After bonding the insulating layers 50 and 40, an annealing process is performed to bond the two electrode pads together, for example, by a Cu-Cu bond. This electrically connects the corresponding laminate LM and peripheral circuit CBA, and also bonds the support substrate SS and semiconductor substrate SB together.

[0060] As shown in Figure 5, a laser beam having a wavelength of, for example, 9 μm to 10 μm is irradiated onto the bonded material of the support substrate SS and the semiconductor substrate SB from the support substrate SS side. For example, a carbon dioxide (CO2) laser with a wavelength of 9.6 μm can be used as the laser beam. However, the wavelength of the laser beam may also be, for example, 9.25 μm or 10.6 μm. Furthermore, it is preferable to irradiate the laser beam in a pulsed manner. This allows the entire surface of the support substrate SS to be irradiated with laser light.

[0061] As shown in the top view of Figure 6, when irradiating the entire surface of the support substrate SS with a pulsed laser, for example, the bonded material of the support substrate SS and the semiconductor substrate SB can be placed on a stage RT that is capable of rotational and horizontal drive, and while rotating the stage RT, the laser beam can be sequentially irradiated in a pulsed manner from the laser oscillator OSC.

[0062] In other words, by rotating the stage RT once to irradiate the support substrate SS with laser light in a circular pattern, and then moving the stage RT horizontally to shift the irradiation position, and then rotating the stage RT again, the entire surface of the support substrate SS can be irradiated with laser light in a concentric pattern.

[0063] In this case, the laser light may be irradiated in a concentric circle from the outer periphery of the support substrate SS toward the center, as shown in the example in Figure 6, or, not according to the example in Figure 6, the laser light may be irradiated in a concentric circle from the center toward the outer periphery of the support substrate SS.

[0064] The pitch of the laser beam irradiation positions can be, for example, several tens of micrometers apart, and the pulse frequency can be, for example, between 10 kHz and 100 kHz.

[0065] As described above, when the support substrate SS is irradiated with laser light, the polysilicon layer 93 of the multilayer structure 90 formed on the semiconductor substrate 30 undergoes thermal expansion, causing the polysilicon layer 93 and the insulating layer 92 to cleave apart. This process is shown in Figure 7.

[0066] As shown in Figure 7(a), when irradiated with laser light, the phosphorus-doped polysilicon layer 93, which has a higher laser light absorption rate than the insulating layer 92, absorbs the laser light and generates heat.

[0067] As shown in Figure 7(b), the insulating layer 92 also generates some heat when irradiated with laser light, but the amount of heat generated by the insulating layer 92 is lower than that of the polysilicon layer 93. Furthermore, as mentioned above, the thermal conductivity of the insulating layer 92 is less than one-tenth that of the polysilicon layer 93. For this reason, the insulating layer 92 can function as an insulating layer that suppresses the transfer of heat from the polysilicon layer 93 to the semiconductor substrate 30.

[0068] Furthermore, when the insulating layer 92 is to function as a heat insulating layer, it is preferable that the insulating layer 92 has a thickness of, for example, 20 nm to 50 nm, as described above. If the insulating layer 92 is too thick, the insulating layer 92 itself becomes a heat source, weakening its heat insulating effect, and heat may be transferred to the semiconductor substrate 30. When heat is transferred to the semiconductor substrate 30, the semiconductor substrate 30 itself expands due to heat, which may cause damage such as lattice defects in the crystal of the semiconductor substrate 30.

[0069] On the other hand, if an insulating layer 92 is not provided on the support substrate SS, the heat from the polysilicon layer 93 is transferred to the semiconductor substrate 30 and dissipated, so the stress generated by the thermal expansion of the polysilicon layer 93, as described later, is dispersed, making it difficult to peel off the support substrate SS.

[0070] As shown in Figure 7(c), the polysilicon layer 93 undergoes thermal expansion. This creates stress between the polysilicon layer 93 and the insulating layer 92.

[0071] As shown in Figure 7(d), the stress on the thermally expanded polysilicon layer 93 pushes up the insulating layer 92, causing the interface between the polysilicon layer 93 and the insulating layer 92 to crack.

[0072] As shown in Figure 7(e), the support substrate SS is peeled off with the insulating layers 92 and 91 attached to the semiconductor substrate 30 due to a crack that occurs at the interface between the polysilicon layer 93 and the insulating layer 92. At this time, the portion of the polysilicon layer 93 that has expanded due to heat peels off together with the insulating layer 92 and 91.

[0073] In this way, by utilizing the thermal expansion of the polysilicon layer 93 to cleave the polysilicon layer 93 and the insulating layer 92, the support substrate SS can be peeled off at a relatively low temperature. Therefore, the support substrate SS is removed without thermal spraying or melting the polysilicon layer 93 and the insulating layer 92, or causing any chemical changes to the components that serve as the starting point for the cleavage.

[0074] As described above, when laser light is pulsed and irradiated over the entire surface of the support substrate SS, the laser light may irradiate the protrusions 931 of the polysilicon layer 93. In this case, the tip of the protrusion 931 connected to the semiconductor substrate 30 may heat up, and there is a risk that heat will be transferred to the semiconductor substrate 30. However, as described above, by keeping the phosphorus concentration of the protrusion 931 lower than that of the main body of the polysilicon layer 93, the amount of heat generated by the protrusion 931 can be suppressed, and damage to the semiconductor substrate 30 due to heat transfer from the protrusion 931 can be prevented.

[0075] As shown in Figure 8, when the support substrate SS, which has become a semiconductor substrate 30 having only a part of the multilayer structure 90 such as insulating layers 92 and 91, is peeled off, the semiconductor substrate SB side will be left with peripheral circuits CBA including transistors TR etc. formed on the semiconductor substrate SB, and a laminate LM which is bonded above the peripheral circuits CBA via insulating layers 40 and 50 and includes pillars PL etc.

[0076] As shown in Figure 9(a), the multilayer structure 90 remaining on the conductive layer SLb side of the laminate LM bonded to the semiconductor substrate SB is removed by polishing using a polishing pad PD with CMP (Chemical Mechanical Polishing) or the like.

[0077] As shown in Figure 9(b), the multilayer structure 90 is removed, exposing the conductive layer SLb on the upper surface of the semiconductor substrate SB.

[0078] As shown in Figure 9(c), a resist pattern 21 having a pattern that matches the arrangement of each laminate LM is formed on the conductive layer SLb.

[0079] As shown in Figure 9(d), the conductive layer SLb is etched through the resist pattern 21 to form a pattern of multiple source lines SL separated for each individual laminate LM.

[0080] As shown in the top view of Figure 9(e), the source line SL is also formed in a grid-like pattern, for example, to match the arrangement of multiple laminates LM arranged in a grid pattern within the plane of the semiconductor substrate SB.

[0081] After the source line SL is formed in multiple patterns, the resist pattern 21 is removed by ashing using oxygen plasma or the like.

[0082] Subsequently, an electrode film EL is formed that connects to a source wire SL via a plug PG formed in the insulating layer 60, and the semiconductor substrate SB is sectionalized to include at least one laminate LM, thereby manufacturing the semiconductor device 1 of the embodiment.

[0083] On the other hand, the support substrate SS, which is peeled off from the semiconductor substrate SB, undergoes the regeneration process described below and is reused as a support substrate SS for the manufacture of a new semiconductor device 1.

[0084] Figure 10 is a cross-sectional view illustrating a part of the procedure for the regeneration process of the support substrate SS according to the embodiment.

[0085] As shown in Figure 10(a), the multilayer structure 90 remaining on the support substrate SS side due to the cracking is removed by grinding with a polishing pad PD. The multilayer structure 90 may also be removed by wet etching or the like.

[0086] As shown in Figure 10(b), the multilayer structure 90 is removed, and the semiconductor substrate 30 is obtained in approximately its original state.

[0087] From this point onward, the semiconductor substrate 30 is subjected to the process shown in Figure 2(a) above.

[0088] Specifically, as shown in Figure 10(c), after cleaning the semiconductor substrate 30, both sides of the semiconductor substrate 30 are covered with, for example, an insulating layer 91. Furthermore, an insulating layer 92 and a phosphorus-doped polysilicon layer 93 are formed on the semiconductor substrate 30 in this order, starting from the semiconductor substrate 30 side.

[0089] As described above, a support substrate SS is regenerated from a used semiconductor substrate 30. The regeneration process for the support substrate SS shown in Figure 10 above may also be included in the method for manufacturing the support substrate SS.

[0090] (Overview) Semiconductor devices such as three-dimensional non-volatile memory may be manufactured by forming a laminate containing multiple pillars on a support substrate, and then bonding it to a semiconductor substrate on which peripheral circuits are formed separately. The support substrate is peeled off after being bonded to the semiconductor substrate and reused repeatedly.

[0091] The support substrate is detached by, for example, irradiating it with laser light, causing thermal expansion of the semiconductor substrate that constitutes the support substrate, which in turn causes separation from other components on the surface of the semiconductor substrate. However, if the support substrate is detached using the thermal expansion of the semiconductor substrate itself, damage such as lattice defects will occur in the thermally expanded semiconductor substrate. In addition, the thermally expanded portion of the semiconductor substrate may remain on the insulating layer side that covers the surrounding circuits, etc., causing further damage such as irregularities on the surface of the semiconductor substrate.

[0092] When damage such as lattice defects and irregularities occurs in the semiconductor substrate, the damaged portion of the semiconductor substrate must also be removed during the regeneration of the support substrate. As a result, the semiconductor substrate becomes thinner with each regeneration, and the number of times the support substrate can be regenerated decreases.

[0093] According to the support substrate SS of the embodiment, it comprises an insulating layer 92 disposed above the semiconductor substrate 30, and a phosphorus-doped polysilicon layer 93 disposed above the insulating layer 92.

[0094] As described above, the phosphorus-doped polysilicon layer 93 has the property of absorbing laser light and acts as a starting point for cleavage in the multilayer structure 90. The insulating layer 92 absorbs laser light less readily than the polysilicon layer 93 and suppresses the transfer of heat generated in the polysilicon layer 93 to the semiconductor substrate 30. This makes it possible to suppress damage to the semiconductor substrate 30 when peeling off the support substrate SS.

[0095] According to the support substrate SS of this embodiment, a phosphorus-doped protrusion 931 extends through the insulating layer 92, connecting the main body portion of the polysilicon layer 93 to the semiconductor substrate 30. This makes it possible to suppress the occurrence of arcing, which occurs when the insulating layer 50 and the like become charged during plasma processing when forming a part of the semiconductor device 1 on the support substrate SS.

[0096] According to the support substrate SS of the embodiment, the polysilicon layer 93 is 1.5 × 10 20 atom / cm 3 More preferably, 3.0 × 10 20 atom / cm 3 The above phosphorus concentration is achieved. This makes it possible to increase the absorption rate of light with wavelengths between 9 μm and 10 μm in the polysilicon layer 93.

[0097] According to the support substrate SS of the embodiment, the protruding portion 931 of the polysilicon layer 93 has a lower phosphorus concentration than the main body portion of the polysilicon layer 93. As a result, even if the laser light strikes the protruding portion 931 when, for example, pulsed laser light is irradiated, the heat generation of the protruding portion 931 can be suppressed, and heat transfer from the protruding portion 931 to the semiconductor substrate 30 can be suppressed. Therefore, damage to the semiconductor substrate 30 can be further suppressed.

[0098] In the support substrate SS of this embodiment, the thickness of the insulating layer 92 is 20 nm to 50 nm. By appropriately adjusting the thickness of the insulating layer 92 in this way, it is possible to suppress the insulating layer 92 itself from becoming a heat source, while suppressing heat transfer to the semiconductor substrate 30 through the heat insulation effect of the insulating layer 92, thereby suppressing damage to the semiconductor substrate 30.

[0099] In the support substrate SS of this embodiment, the thickness of the main body portion of the polysilicon layer 93 is 100 nm to 300 nm. By forming the polysilicon layer 93 sufficiently thick relative to the insulating layer 92 in this way, stress is generated by the thermal expansion of the polysilicon layer 93, causing the interface with the insulating layer 92 to crack.

[0100] In the support substrate SS of this embodiment, the protruding portion 931 of the polysilicon layer 93 is positioned on the outer edge of the plurality of semiconductor devices 1 so as to surround the central portion of each semiconductor device 1 formed on the support substrate SS, when viewed from the stacking direction of the insulating layer 92, the main body portion of the polysilicon layer 93, and the insulating layer 50. This further suppresses the occurrence of arcing caused by the insulating layer 50 and the like becoming charged during the plasma treatment when forming the semiconductor devices 1.

[0101] (modified version) Next, a modified support substrate Ssa of the embodiment will be described with reference to Figures 11 to 13. The modified support substrate Ssa differs from the above-described embodiment in that it further comprises a polysilicon layer 932 around the protruding portion 931 of the polysilicon layer 93.

[0102] Figure 11 is a cross-sectional view showing an example of the configuration of a support substrate SSa according to a modified embodiment. In the following drawings, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions may be omitted.

[0103] As shown in Figure 11, the modified support substrate SSa has a configuration in which a multilayer structure 90a is formed on a semiconductor substrate 30. The multilayer structure 90a includes a polysilicon layer 94 in addition to the insulating layer 92 and polysilicon layer 93 of the above-described embodiment.

[0104] The support substrate SSa may also have an insulating layer 91, such as a silicon nitride layer, covering both sides of the semiconductor substrate 30, similar to the embodiment described above. In other words, the modified multilayer structure 90a may further include an insulating layer 91.

[0105] The polysilicon layer 94 penetrates the insulating layer 92 and is provided on the side wall of the recess 92r that reaches the semiconductor substrate 30, covering the periphery of the protrusion 931 of the polysilicon layer 93. At this time, the volume of the polysilicon layer 94 is larger than the volume of the protrusion 931.

[0106] Also, the phosphorus concentration in the main body portion of the polysilicon layer 93 is, as described above, for example, 1.5×10 20 atom / cm 3 or higher, more preferably 3.0×10 20 atom / cm 3 or higher. The phosphorus concentration in the protruding portion 931 is not higher than that of the polysilicon layer 93. In contrast, the polysilicon layer 94 has a phosphorus concentration even lower than these, and more preferably, the polysilicon layer 94 is an undoped polysilicon layer.

[0107] Thereby, the polysilicon layer 94 has a lower absorption rate of laser light than the protruding portion 931 of the polysilicon layer 93 and has a thermal conductivity equal to or higher than that of the semiconductor substrate 30. Therefore, even when the laser light hits the protruding portion 931 of the polysilicon layer 93 during the peeling of the support substrate SSa, the polysilicon layer 94 can function as a heat absorption layer, and the heat generated in the protruding portion 931 can be absorbed by the polysilicon layer 94. Thus, damage to the semiconductor substrate 30 is further suppressed.

[0108] Such a support substrate SSa can be manufactured, for example, as follows.

[0109] An insulating layer 92 is formed on the semiconductor substrate 30, and a recess 92r penetrating the insulating layer 92 is further formed. Next, when the raw material gas of the polysilicon layer is supplied to the insulating layer 92, initially, the side wall of the recess 92r of the insulating layer 92 and the upper surface of the insulating layer 92 are covered with the polysilicon layer. Also, the polysilicon layer gradually increases in thickness toward the center of the recess 92r, and the recess 92r is filled with the polysilicon layer.

[0110] In this process, initially, a polysilicon layer 94 is formed on the sidewall of the recess 92r of the insulating layer 92 by doping with a low concentration of phosphorus, or without doping with phosphorus. When filling the central part of the recess 92r, the phosphorus concentration is increased to form the protruding portion 931 of the polysilicon layer 93. In this case, for example, after forming an undoped polysilicon layer 94 using SiH4 gas, a mixed gas is used by adding Si2H6 gas or PH3 gas to SiH4 gas to form the phosphorus-doped polysilicon layer, which is the protruding portion 931.

[0111] Alternatively, after forming an undoped polysilicon layer 94, phosphorus can be doped into the portion that will become the protrusion 931 by ion implantation or the like. In this case, phosphorus can be ion implanted while masking the positions other than those corresponding to the protrusion 931.

[0112] In either method, phosphorus diffuses during the annealing process in manufacturing, so the phosphorus concentration in the polysilicon layer 94 and the protrusions 931 may have a concentration gradient.

[0113] Subsequently, the low-phosphorus polysilicon layer 94 formed on the insulating layer 92 is removed, and a new polysilicon layer 93 doped with a predetermined phosphorus concentration is formed.

[0114] Based on the above, the modified support substrate SSa is manufactured.

[0115] Here, the manner of cracking during delamination of the support substrate SSa may differ depending on the phosphorus concentration of the protrusions 931 of the polysilicon layer 93. Examples of these are shown in Figures 12 and 13.

[0116] Figure 12 is a schematic cross-sectional view showing an example of the peeling of the support substrate SSa according to a modified embodiment. More specifically, Figure 12 shows an example where the phosphorus concentration of the protrusion 931 is about the same as the phosphorus concentration of the main body portion of the polysilicon layer 93.

[0117] As shown in Figure 12(a), when irradiated with laser light, the phosphorus-doped polysilicon layer 93, which has a higher laser light absorption rate than the insulating layer 92, absorbs the laser light and generates heat. At this time, if the protrusions 931 of the polysilicon layer 93 are also irradiated with laser light, the protrusions 931 also absorb the laser light and generate heat.

[0118] As shown in Figure 12(b), in the portion where an insulating layer 92 is interposed between the polysilicon layer 93 and the semiconductor substrate 30, the insulating layer 92 functions as a heat insulating layer, suppressing the transfer of heat from the polysilicon layer 93 to the semiconductor substrate 30. On the other hand, the protrusions 931 of the polysilicon layer 93 are in direct contact with the semiconductor substrate 30. However, a polysilicon layer 94 with a low phosphorus concentration, which functions as a heat-absorbing layer, is arranged around the protrusions 931. Therefore, the heat from the protrusions 931 is absorbed by the polysilicon layer 94, and its transfer to the semiconductor substrate 30 is suppressed.

[0119] In this case, since the volume of the polysilicon layer 94 is larger than the volume of the protrusion 931, it can sufficiently absorb the heat from the protrusion 931.

[0120] As shown in Figure 12(c), the polysilicon layer 93 in the area irradiated with laser light undergoes thermal expansion. This creates stress between the polysilicon layer 93 and the insulating layer 92.

[0121] As shown in Figure 12(d), the stress of the thermally expanded polysilicon layer 93 pushes up the insulating layer 92, causing the interface between the polysilicon layer 93 and the insulating layer 92 to cleave. At this time, the protruding portion 931, which is heated by the laser light irradiation, and the polysilicon layer 94, which absorbs that heat, cleave together with the semiconductor substrate 30, along with the insulating layer 92, from the main body portion of the polysilicon layer 93.

[0122] As shown in Figure 12(e), the support substrate SSa is peeled off with the insulating layer 92 attached to the semiconductor substrate 30 due to a crack that occurs at the interface between the polysilicon layer 93 and the insulating layer 92. At this time, the thermally expanded portion of the main body of the polysilicon layer 93, the protruding portion 931 of the polysilicon layer 93, and the polysilicon layer 94 are peeled off together with the insulating layer 92.

[0123] Figure 13 is a schematic cross-sectional view showing another example of the peeling of the support substrate SSa according to a modified embodiment. More specifically, Figure 13 is an example where the phosphorus concentration of the protrusion 931 is lower than the phosphorus concentration of the main body portion of the polysilicon layer 93.

[0124] As shown in Figure 13(a), when irradiated with laser light, the phosphorus-doped polysilicon layer 93, which has a higher laser light absorption rate than the insulating layer 92, absorbs the laser light and generates heat. At this time, if the protrusions 931 of the polysilicon layer 93 are also irradiated with laser light, the protrusions 931 also absorb the laser light and generate heat. However, the amount of heat generated by the protrusions 931, which have a low phosphorus concentration, is less than in the example in Figure 12.

[0125] As shown in Figure 13(b), in the portion where the insulating layer 92 is interposed between the polysilicon layer 93 and the semiconductor substrate 30, the insulating layer 92 functions as a heat insulating layer, suppressing the transfer of heat from the polysilicon layer 93 to the semiconductor substrate 30. On the other hand, since the protrusions 931 of the polysilicon layer 93 have a higher thermal conductivity than the polysilicon layer 93, some of the heat from the protrusions 931 is transferred to the polysilicon layer 93, and the other part is absorbed by the polysilicon layer 94. As a result, heat transfer from the protrusions 931 to the semiconductor substrate 30 is further suppressed.

[0126] As shown in Figure 13(c), the polysilicon layer 93 in the area irradiated with laser light undergoes thermal expansion. This creates stress between the polysilicon layer 93 and the insulating layer 92.

[0127] As shown in Figure 13(d), the stress of the thermally expanded polysilicon layer 93 pushes up the insulating layer 92, causing the interface between the polysilicon layer 93 and the insulating layer 92 to rupture. In addition, the portion of the main body of the polysilicon layer 93 that receives heat from the protrusion 931 also expands due to thermal expansion, pushing the protrusion 931 upward. At this time, the polysilicon layer 94 that absorbed the heat from the protrusion 931 becomes attached to the main body of the polysilicon layer 93.

[0128] As shown in Figure 13(e), the support substrate SSa is peeled off with the insulating layer 92 attached to the semiconductor substrate 30 due to a cleavage that occurs at the interface between the polysilicon layer 93 and the insulating layer 92. At this time, the thermally expanded portion of the main body of the polysilicon layer 93 peels off together with the insulating layer 92. The protruding portion 931 of the polysilicon layer 93 and the polysilicon layer 94 remain on the semiconductor substrate SB side having the insulating layer 50, etc.

[0129] In the modified support substrate SSa, a polysilicon layer 94 with a lower phosphorus concentration than the polysilicon layer 93 is provided to cover the sidewall of the protrusion 931 of the polysilicon layer 93 extending through the insulating layer 92. As a result, even if the protrusion 931 generates heat when struck by laser light, the heat from the protrusion 931 can be absorbed by the polysilicon layer 94. Therefore, damage to the semiconductor substrate 30 can be further suppressed.

[0130] The modified support substrate SSa also provides the same effects as the support substrate SS of the above-described embodiment. [Examples]

[0131] The following describes the embodiments in detail with reference to the drawings. The embodiments show the method and results for measuring the absorption rate of light at each wavelength in the polysilicon layer, which functions as a thermal expansion layer.

[0132] Figure 14 is a schematic diagram showing the measurement substrate SSex and the absorption rate measurement method according to the embodiment.

[0133] As shown in Figure 14, the measurement substrate SSex is a semiconductor substrate 30e with an anti-reflective layer AR formed on its back surface and a polysilicon layer 93e, etc., which is the target of absorption rate measurement, formed on its front surface.

[0134] Light is obliquely incident on the measurement substrate SSex from the light emitter PR, and the light reflected from the measurement target, such as the polysilicon layer 93e, is detected by the light receiver RC.

[0135] The wavelength of the light emitted from the light emitter PR can be changed, for example, within the range of 3.0 μm to 11 μm. The light is multiple-reflected by the upper and lower surfaces of the polysilicon layer 93e, etc., and the light reflected back to the light receiver RC is detected. At this time, by obliquely incidenting the light onto the measurement substrate SSex, these multiple-reflected lights can be separated and detected individually.

[0136] Figures 15 and 16 are schematic diagrams illustrating the method for calculating the absorption rate of the polysilicon layer 93e in the measurement substrate SSex according to the embodiment.

[0137] As shown in Figure 15, light of wavelength λ is obliquely incident on the measurement substrate SSex from the light source PR. The angle of incidence at this time is assumed to be φ0 with respect to a perpendicular line drawn from the upper surface of the polysilicon layer 93e on the measurement substrate SSex.

[0138] A portion of the light that reaches the polysilicon layer 93e from the light source PR is reflected from the upper surface of the polysilicon layer 93e and detected by the light receiver RC. The incident light from the light source PR and the reflected light from the polysilicon layer 93e each contain p-polarized and s-polarized components, respectively.

[0139] The p-polarization component is the polarization component parallel to the incident plane from the light source PR, and the s-polarization component is the polarization component perpendicular to the incident plane of light from the light source PR. The incident plane of light is the plane that includes both the incident light from the light source PR and the reflected light from the polysilicon layer 93e. The p-polarization component and the s-polarization component affect the reflectance of light of wavelength λ in the polysilicon layer 93e.

[0140] A portion of the light that reaches the polysilicon layer 93e from the floodlight PR is incident into the polysilicon layer 93e at an angle φ1 with respect to the thickness direction of the polysilicon layer 93e. A portion of the light incident into the polysilicon layer 93e is reflected by the lower surface of the polysilicon layer 93e, and another portion is transmitted to the semiconductor substrate 30e side at an angle φ2 with respect to the thickness direction of the polysilicon layer 93e.

[0141] A portion of the light reflected from the lower surface of the polysilicon layer 93e is transmitted through the upper surface of the polysilicon layer 93e and detected by the photodetector RC. Another portion of the light reflected from the lower surface of the polysilicon layer 93e is further reflected from the upper surface of the polysilicon layer 93e. A portion of the light reflected from the upper surface of the polysilicon layer 93e is reflected from the lower surface of the polysilicon layer 93e, and another portion is transmitted to the semiconductor substrate 30e.

[0142] In this way, the light reflected from the surface of the polysilicon layer 93e, and the light that undergoes multiple reflections within the polysilicon layer 93e and is finally transmitted to the photodetector RC are detected by the photodetector RC. Furthermore, based on the information about this light detected by the photodetector RC, the n / k value is determined using the following equations (1) to (8). n is the refractive index of the polysilicon layer 93e, and k is the extinction coefficient of the polysilicon layer 93e.

[0143] The intensity reflectance of the p-polarization component Rp = r p ·r p ...(1) The intensity reflectance of the s-polarization component Rs = r s ·r s ...(2) r p : Amplitude reflectance of the p-polarization component r s :s polarization component amplitude reflectance

[0144] r p =(r 1p +r 2p ×e -iδ ) / (1+r 1p ·r 2p ×e -iδ)···(3) r s =(r 1s +r 2s ×e -iδ ) / (1+r 1s ·r 2s ×e -iδ )···(4) δ=(4π / λ)nd·cosφ1···(5) i: Imaginary number δ: Phase difference when light of wavelength λ makes one round trip within the polysilicon layer 93e. n: Refractive index of polysilicon layer 93e d: Thickness of polysilicon layer 93e

[0145] Reflection Fresnel coefficient r of the p-polarized component ip = (n i · cosφ i-1 -n i-1 · cosφ i ) / (n i · cosφ i―1 +n i-1 · cosφ i )···(6) r of the reflection Fresnel coefficient of the s-polarization component is = (n i-1 · cosφ i -n i · cosφ i-1 ) / (n i-1 · cosφ i +n i · cosφ i-1 )···(7) n i : Complex refractive index of polysilicon layer 93e

[0146] n=n i -ik···(8)

[0147] Here, the refractive index and thickness of the polysilicon layer 93e are known. Therefore, the n / k value can be determined using equations (1) to (8) above.

[0148] As shown in Figure 16, when light of wavelength λ is incident on the polysilicon layer 93e with intensity I0, the wavelength of the light in the polysilicon layer 93e becomes wavelength λ / n1 depending on the refractive index n1 of the polysilicon layer 93e, and the intensity I of the light transmitted through the polysilicon layer 93e with thickness d is expressed by the following equation (9).

[0149] I=I0×exp((-4πk / λ)·d)···(9)

[0150] Furthermore, the absorption rate A of light with wavelength λ in the polysilicon layer 93e can be obtained from the following equation (10).

[0151] Absorption rate A = (I0 - I) / I0 = 1 - e -αx ...(10) α: Absorption coefficient

[0152] Figure 17 is a graph showing the absorption rate of the polysilicon layer 93e of the measurement substrate SSex according to the embodiment. In the graph of Figure 17, the horizontal axis represents the wavelength λ (nm) of light irradiated onto the polysilicon layer 93e, and the vertical axis represents the absorption rate (%) of light at each wavelength λ in the polysilicon layer 93e.

[0153] Furthermore, as shown in Figure 14, the polysilicon layer 93e consists of an undoped polysilicon layer and a 1.5 × 10⁻¹⁰ layer. 20 atom / cm 3 A phosphorus-doped polysilicon layer and 3.0 × 10 20 atom / cm 3 The phosphorus-doped polysilicon layers were used as the measurement targets. The thickness of these polysilicon layers was set to 200 nm. For comparison, the absorption rate of a silicon oxide layer with a thickness of 200 nm, which was used in the aforementioned insulating layer 92, was also measured.

[0154] Furthermore, for reference, the graph in Figure 17 shows a dashed line representing the wavelength of the carbon dioxide laser light, 9.6 μm, which was used when peeling off the support substrate SS in the above-described embodiment.

[0155] As shown in Figure 17, the light absorption rate in the silicon oxide layer with a thickness of 200 nm was approximately 45% at a wavelength λ of around 9 μm, while the light absorption rate in the undoped polysilicon layer 93e was consistently 0% over wavelengths from 3.0 μm to 12 μm.

[0156] In contrast, the absorption rate in the phosphorus-doped polysilicon layer 93e increased as the wavelength λ of light increased up to around 7.0 μm, and the increase in absorption rate was greater with increasing phosphorus concentration.

[0157] More details: 3.0×10 20 atom / cm 3 In the phosphorus-doped polysilicon layer, the absorption rate at wavelengths λ of 9 μm or greater is 75% or greater, and 1.5 × 10⁻⁶ 20 atom / cm 3 The phosphorus content was also over 50% in the phosphorus-doped polysilicon layer.

[0158] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0159] 1... Semiconductor device, 30, SB... Semiconductor substrate, 40, 50, 60, 91, 92... Insulating layer, 90, 90a... Multilayer structure, 93, 94... Polysilicon layer, 931... Protrusion, CBA... Peripheral circuit, LM... Laminate, PL... Pillar, SS, SSa... Support substrate, WL... Word line.

Claims

1. A laminated substrate for delamination using thermal expansion by laser light, Semiconductor substrate and A first insulating layer is disposed above the semiconductor substrate, A first polysilicon layer, which is doped with phosphorus and is placed in contact with the first insulating layer, The present invention comprises a second polysilicon layer, which extends through the first insulating layer and directly connects the first polysilicon layer and the semiconductor substrate, and is doped with phosphorus. Multilayer substrate.

2. The present invention further comprises a third polysilicon layer that covers the sidewall of the second polysilicon layer extending through the first insulating layer and has a lower phosphorus concentration than the first polysilicon layer. The laminated substrate according to claim 1.

3. The second polysilicon layer is Having the same phosphorus concentration as the first polysilicon layer, The laminated substrate according to claim 2.

4. The second polysilicon layer is Having a phosphorus concentration lower than that of the first polysilicon layer and higher than that of the third polysilicon layer, The laminated substrate according to claim 2.

5. The first polysilicon layer further comprises a device layer including at least a portion of the components of each of a plurality of semiconductor devices. The laminated substrate according to claim 1.

6. The second polysilicon layer is Viewed from the stacking direction of the first insulating layer, the first polysilicon layer, and the device layer, the following are arranged on the outer edges of the plurality of semiconductor devices, surrounding the central portion of each of the plurality of semiconductor devices: The laminated substrate according to claim 5.

7. A first insulating layer is formed on top of the first semiconductor substrate. A recess is formed that penetrates the first insulating layer, A first polysilicon layer covered with phosphorus and a second polysilicon layer extending within the recess and reaching the first semiconductor substrate and also doped with phosphorus are formed. A device layer is formed above the first polysilicon layer, which includes at least a portion of the components of each of the multiple semiconductor devices. The first polysilicon layer is irradiated with laser light to cleave the first insulating layer and the first polysilicon layer and remove the first semiconductor substrate. A method for manufacturing a semiconductor device.

8. The formation of the device layer is A laminate is formed on top of the first polysilicon layer, in which a plurality of conductive layers are stacked spaced apart from each other. This includes forming a memory pillar that penetrates the laminate, The method for manufacturing a semiconductor device according to claim 7.

9. Before removing the first semiconductor substrate, Forming peripheral circuits including transistors on a second semiconductor substrate, The method further includes bonding the surface of the first semiconductor substrate on which the device layer is formed with the surface of the second semiconductor substrate on which the peripheral circuit is formed. The method for manufacturing a semiconductor device according to claim 8.

10. The formation of the second polysilicon layer is This includes forming the first insulating layer, the first polysilicon layer, and the device layer on the outer edges of the plurality of semiconductor devices so as to surround the central portion of each of the plurality of semiconductor devices when viewed from the stacking direction of the plurality of semiconductor devices. The method for manufacturing a semiconductor device according to claim 7.

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