Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Solution] The semiconductor device comprises a substrate having a first surface and a second surface opposite to the first surface, a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, and a second nitride semiconductor layer provided in the recess, the substrate and the first nitride semiconductor layer having an opening that penetrates the substrate and the first nitride semiconductor layer and reaches the second nitride semiconductor layer, with an opening having a bottom surface formed in the second nitride semiconductor layer, the first metal layer covering the first surface and the inner wall surface of the opening, and contacting the second nitride semiconductor layer at its bottom surface, the second nitride semiconductor layer having 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor device is known in which a metal layer is formed on a semiconductor layer containing a high concentration of carriers, and a metal layer that is in ohmic contact with the semiconductor layer is formed as an etching stopper. Through holes are formed in the semiconductor layer that reach the etching stopper, and electrodes that contact the etching stopper are formed within the through holes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2011-077434 [Patent Document 2] Japanese Patent Publication No. 2020-017647 [Patent Document 3] Japanese Patent Publication No. 2024-092747 [Overview of the project] [Problems that the invention aims to solve]

[0004] In conventional semiconductor devices, the contact resistance between the electrode and the semiconductor layer can increase, leading to a decrease in yield.

[0005] This disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Means for solving the problem]

[0006] The semiconductor device of this disclosure comprises a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface; and a second nitride semiconductor layer provided in the recess. The substrate and the first nitride semiconductor layer have a first metal layer that penetrates the substrate and the first nitride semiconductor layer, reaches the second nitride semiconductor layer, and has an opening with a bottom surface formed in the second nitride semiconductor layer, covering the first surface and the inner wall surface of the opening, and contacting the second nitride semiconductor layer at its bottom surface. The second nitride semiconductor layer has a thickness of 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations. [Effects of the Invention]

[0007] According to this disclosure, yield can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the layout of the gate electrode and drain wiring in the semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 shows the band structure of the semiconductor layer (regrowth layer). [Figure 4] Figure 4 is a cross-sectional view (part 1) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 2) showing a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 3) showing a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 4) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8]FIG. 8 is a cross-sectional view (part 5) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 8) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 9) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 10) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 1) showing a second example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 2) showing a second example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 17] FIG. 17 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 18] FIG. 18 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 19] FIG. 19 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 20] FIG. 20 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 21] FIG. 21 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 22] FIG. 22 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 23]Figure 23 is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to a reference example. [Figure 24] Figure 24 shows the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device according to the second embodiment. [Figure 25] Figure 25 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A semiconductor device according to one aspect of the present disclosure comprises a substrate having a first surface and a second surface opposite to the first surface, a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, and a second nitride semiconductor layer provided in the recess, wherein the substrate and the first nitride semiconductor layer have an opening that penetrates the substrate and the first nitride semiconductor layer, reaches the second nitride semiconductor layer, and has a bottom surface, covers the first surface and the inner wall surface of the opening, and has a first metal layer that contacts the second nitride semiconductor layer at its bottom surface, and the second nitride semiconductor layer has a thickness of 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations.

[0011] A second nitride semiconductor layer is formed in a recess formed on the fourth surface of the first nitride semiconductor layer, and the second nitride semiconductor layer is 1.0 × 10 18 cm -3The material contains impurity atoms at the above concentrations. Furthermore, the first metal layer contacts the second nitride semiconductor layer at the bottom surface of the opening, resulting in ohmic contact between the first metal layer and the second nitride semiconductor layer. As a result, the electrical resistance between the first nitride semiconductor layer and the first metal layer is low. Consequently, compared to cases where there is another metal layer in the current path between the first metal layer and the first nitride semiconductor layer, the stability of the electrical resistance between the first metal layer and the first nitride semiconductor layer is good, and the yield can be improved.

[0012] [2] In [1], the thickness of the second nitride semiconductor layer may be 20 nm or more and 1000 nm or less. When the thickness of the second nitride semiconductor layer is 20 nm or more, etching of the first nitride semiconductor layer and the second nitride semiconductor layer can be easily stopped before the opening penetrates the second nitride semiconductor layer when forming the opening. When the thickness of the second nitride semiconductor layer is 1000 nm or less, the time required for forming the recess and the second nitride semiconductor layer can be easily shortened.

[0013] [3] In [1] or [2], the second nitride semiconductor layer may be a gallium nitride layer. In this case, it is easier to obtain a low electrical resistance in the second nitride semiconductor layer.

[0014] [4] In any of [1] to [3], the Fermi level in the second nitride semiconductor layer may be higher than the energy of the lower end of the conduction band. In this case, ohmic contact is easily obtained between the second nitride semiconductor layer and the first metal layer.

[0015] [5] In any of [1] to [4], the carrier density in the second nitride semiconductor layer may be higher than the carrier density in the first nitride semiconductor layer. In this case, the electrical resistance of the second nitride semiconductor layer is easily reduced.

[0016] [6] In any of [1] to [5], a second metal layer is provided on the second nitride semiconductor layer, and the second nitride semiconductor layer may be located between the first metal layer and the second metal layer. In this case, characteristic testing can be performed using the second metal layer.

[0017] 〔7〕 A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes forming a first nitride semiconductor layer having a third surface contacting the second surface and a fourth surface opposite to the third surface on a substrate having a first surface and a second surface opposite to the first surface; forming a recess in the fourth surface; forming a second nitride semiconductor layer in the recess; forming an opening penetrating the substrate and the first nitride semiconductor layer and reaching the second nitride semiconductor layer and having a bottom surface in the second nitride semiconductor layer; and forming a first metal layer covering the first surface and the inner wall surface of the opening and contacting the second nitride semiconductor layer at the bottom surface. The second nitride semiconductor layer contains impurity atoms at a concentration of 1.0×10 18 cm -3 or more.

[0018] A recess is formed in the fourth surface of the first nitride semiconductor layer, a second nitride semiconductor layer is formed in the recess, and the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0×10 18 cm -3 or more. Further, the first metal layer contacts the second nitride semiconductor layer at the bottom surface of the opening, and the first metal layer and the second nitride semiconductor layer form an ohmic contact. Therefore, the electrical resistance between the first nitride semiconductor layer and the first metal layer is low. Accordingly, the stability of the electrical resistance between the first metal layer and the first nitride semiconductor layer is better than in the case where there is another metal layer in the current path between the first metal layer and the first nitride semiconductor layer, and the yield can be improved.

[0019] [Details of Embodiments of the Present Disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In the following description, the XYZ Cartesian coordinate system will be used, but this coordinate system is defined for illustrative purposes only and is not limited to the orientation of the semiconductor device. Also, from any point, the +Z side may be referred to as up, upper, or top, and the -Z side may be referred to as down, lower, or bottom.

[0020] (First Embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT).

[0021] [Structure of a semiconductor device] The structure of the semiconductor device according to the first embodiment will now be described. Figure 1 is a diagram showing the layout of the gate electrode and drain wiring in the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0022] As shown in Figures 1 and 2, the semiconductor device 100 according to the first embodiment includes a substrate 11, a semiconductor layer 12, a semiconductor layer 21S, a semiconductor layer 21D, a gate electrode 22, a drain electrode 30D, a drain wiring 52D, and a back electrode 51.

[0023] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B is located above (on the +Z side of) the first surface 11A.

[0024] The semiconductor layer 12 is provided on the substrate 11. The semiconductor layer 12 has a third surface 12C that is in contact with the second surface 11B, and a fourth surface 12D opposite to the third surface 12C. The fourth surface 12D is above (on the +Z side of) the third surface 12C. The semiconductor layer 12 is, for example, a nitride semiconductor layer containing gallium (Ga). The nitride semiconductor layer constitutes part of a high electron mobility transistor, such as an electron transport layer (channel layer) and an electron supply layer (barrier layer), and contains a two-dimensional electron gas (2DEG). The semiconductor layer 12 is an example of a first nitride semiconductor layer.

[0025] Multiple recesses 13S and multiple recesses 13D are formed on the fourth surface 12D. The recesses 13S and 13D extend parallel to the Y-axis and are arranged alternately along the X-axis. For example, the recesses 13S and 13D reach the electron transport layer (channel layer). The bottom surfaces of the recesses 13S and 13D may be in the electron transport layer.

[0026] The semiconductor device 100 has an insulating film 61. The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12. For example, the insulating film 61 is a nitride film such as a silicon nitride (SiN) film. Multiple openings 61S, multiple openings 61D, and multiple openings 61G are formed in the insulating film 61. The openings 61S, 61D, and 61G extend parallel to the Y axis. The openings 61S and 61D are connected to the recesses 13S and 13D, respectively. The openings 61G are provided between adjacent openings 61S and 61D along the X axis.

[0027] The semiconductor layer 21S is provided in the recess 13S, and the semiconductor layer 21D is provided in the recess 13D. A portion of the semiconductor layer 21S may be inside the opening 61S, and a portion of the semiconductor layer 21D may be inside the opening 61D. For example, the semiconductor layers 21S and 21D are n-type gallium nitride (GaN) layers. The semiconductor layers 21S and 21D are regrowth layers. The carrier density in the semiconductor layers 21S and 21D is higher than the carrier density in the semiconductor layer 12. The semiconductor layers 21S and 21D have a carrier density of 1.0 × 10⁻⁶ 18 cm -3The above concentrations contain n-type impurity atoms. Semiconductor layers 21S and 21D are, for example, degenerate semiconductor layers. The n-type impurities are, for example, silicon (Si) or germanium (Ge). Semiconductor layer 21S is an example of a second nitride semiconductor layer.

[0028] The gate electrode 22 extends parallel to the Y-axis. The gate electrode 22 covers the opening 61G of the insulating film 61 and makes Schottky contact with the semiconductor layer 12 through the opening 61G. The gate electrode 22 has, for example, nickel (Ni) layers and gold (Au) layers stacked sequentially upwards. As shown in Figure 1, a plurality of gate electrode 22s are connected to the gate common connection 15.

[0029] The drain electrode 30D extends parallel to the Y-axis. In a plan view, the drain electrode 30D has a Ni layer 31D and an Au layer 32D inside the opening 61D. The Ni layer 31D is provided on the semiconductor layer 21D, and the Au layer 32D is provided on the Ni layer 31D. The Ni layer 31D is in direct contact with the semiconductor layer 21D.

[0030] The semiconductor device 100 has an insulating film 62. The insulating film 62 covers the drain electrode 30D, the gate electrode 22, the insulating film 61, the semiconductor layer 21S, and the semiconductor layer 21D. For example, the insulating film 62 is a nitride film such as a SiN film. Multiple openings 62D are formed in the insulating film 62. The openings 62D extend parallel to the Y axis. The openings 62D reach the drain electrode 30D.

[0031] The drain wiring 52D is located above the drain electrode 30D. The drain wiring 52D is provided on an insulating film 62. The drain wiring 52D is in contact with the drain electrode 30D through an opening 62D. The drain wiring 52D has, for example, a seed layer and a plating layer on top of the seed layer. For example, the seed layer includes a titanium (Ti) layer and the plating layer includes a gold (Au) layer. As shown in Figure 1, multiple drain wirings 52D may be connected to the drain pad 55.

[0032] The semiconductor device 100 has an insulating film 63. The insulating film 63 covers the drain wiring 52D and the insulating film 62. For example, the insulating film 63 is a nitride film such as a SiN film.

[0033] Although not shown in the diagram, an opening reaching the gate common connection portion 15 is formed in the insulating film 62, and a gate pad is formed on the insulating film 62 that contacts the gate common connection portion 15 through this opening. In addition, an opening reaching the gate pad and an opening reaching the drain pad 55 are formed in the insulating film 63.

[0034] An opening 50 is formed in the substrate 11 and the semiconductor layer 12, penetrating both the substrate 11 and the semiconductor layer 12. The opening 50 reaches the semiconductor layer 21S. The opening 50 has a bottom surface 71 and an inner wall surface 72. The inner wall surface 72 is connected to the bottom surface (first surface 11A) of the substrate 11, and the bottom surface 71 is connected to the inner wall surface 72. The bottom surface 71 is located in the semiconductor layer 21S. The opening 50 may extend into the semiconductor layer 21S. At least one opening 50 is formed for each of the semiconductor layers 21S. Multiple openings 50 may be formed for each of the semiconductor layers 21S.

[0035] The back electrode 51 is formed on the lower surface of the semiconductor layer 21S, the inner wall surface 72 of the opening 50, and the lower surface (first surface 11A) of the substrate 11. The back electrode 51 covers the first surface 11A and the inner wall surface 72 and contacts the semiconductor layer 21S at its bottom surface 71. The back electrode 51 has, for example, a seed layer and a plating layer. For example, the seed layer includes a titanium (Ti) layer, a nickel (Ni) layer, a nickel-chromium (NiCr) alloy layer, or a tantalum (Ta) layer, and the plating layer includes a gold (Au) layer. The back electrode 51 is an example of a first metal layer.

[0036] In the semiconductor device 100, a semiconductor layer 21S is formed in the recess 13S of the semiconductor layer 12, and the semiconductor layer 21S is 1.0 × 10 18 cm -3 The semiconductor layer 21S contains impurity atoms at the above concentration. In such a semiconductor layer 21S, the distance between impurity atoms is short, and as shown in Figure 3, the impurity level (E DA binding band is formed between the interacting elements, connecting to the conduction band 26. At this time, the Fermi level (E F ) exists within the conduction band, that is, the Fermi level (E F ) is the energy at the lower end of the conduction band (E C Because it is higher than ), the semiconductor layer 21S exhibits properties similar to those of a metal. In other words, the semiconductor layer 21S functions as a degenerate semiconductor layer. Therefore, ohmic contact is obtained between the semiconductor layer 21S and the back electrode 51. Figure 3 shows the band structure of the semiconductor layer 21S. E in Figure 3 V This indicates the energy at the upper end of the valence band 27.

[0037] [First example of a semiconductor device manufacturing method] Next, a first example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 13 are cross-sectional views showing a first example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0038] In the first example, as shown in Figure 4, a semiconductor layer 12 is formed on a substrate 11, for example, by metal-organic chemical vapor deposition (MOCVD). The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The semiconductor layer 12 has a third surface 12C that is in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. Next, an insulating film 61 is formed on the semiconductor layer 12. The insulating film 61 can be formed, for example, by plasma CVD. The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12.

[0039] Next, as shown in Figure 5, openings 61S and 61D are formed in the insulating film 61, and recesses 13S and 13D are formed in the semiconductor layer 12. For the formation of the openings 61S and 61D, reactive ion etching (RIE) of the insulating film 61 is performed, for example, using a resist pattern as a mask. For the RIE of the insulating film 61, a reactive gas containing fluorine (F), for example, is used. For the formation of the recesses 13S and 13D, RIE of the semiconductor layer 12 is performed, using the resist pattern used to form the openings 61S and 61D as a mask. For the RIE of the semiconductor layer 12, a reactive gas containing chlorine (Cl), for example, is used.

[0040] Next, as shown in Figure 6, a semiconductor layer 21S is formed in the recess 13S and a semiconductor layer 21D is formed in the recess 13D. In the formation of semiconductor layers 21S and 21D, for example, crystal growth of the semiconductor layer is performed by MOCVD, molecular beam epitaxy (MBE), or sputtering using a growth mask, and then the growth mask is removed. Semiconductor layers 21S and 21D are so-called regrowth layers.

[0041] Next, as shown in Figure 7, a drain electrode 30D is formed on the semiconductor layer 21D. In the formation of the drain electrode 30D, the Ni layer and Au layer are grown by a vapor deposition method using a growth mask, and then the growth mask is removed. In other words, the drain electrode 30D can be formed, for example, by vapor deposition and lift-off.

[0042] Next, as shown in Figure 8, an opening 61G is formed in the insulating film 61. For the formation of the opening 61G, for example, RIE is performed using a resist pattern as a mask. For etching the insulating film 61, for example, a reactive gas containing F is used. Next, a gate electrode 22 is formed on the insulating film 61. For the formation of the gate electrode 22, the Ni layer and Au layer are grown by a vapor deposition method using a growth mask, and then the growth mask is removed. In other words, the gate electrode 22 can be formed by vapor deposition and lift-off, for example. The gate electrode 22 makes Schottky contact with the semiconductor layer 12 through the opening 61G.

[0043] Next, as shown in Figure 9, an insulating film 62 is formed on the drain electrode 30D, gate electrode 22, insulating film 61, semiconductor layer 21S, and insulating film 61. The insulating film 62 can be formed, for example, by plasma CVD. The insulating film 62 covers the drain electrode 30D, gate electrode 22, insulating film 61, semiconductor layer 21S, and semiconductor layer 21D.

[0044] Next, as shown in Figure 10, an opening 62D is formed in the insulating film 62. For the formation of the opening 62D, for example, a resist pattern is used as a mask during the RIE of the insulating film 62. During the RIE of the insulating film 62, a reactive gas containing, for example, F is used. Next, a drain wiring 52D that contacts the drain electrode 30D through the opening 62D is formed on the insulating film 62.

[0045] Next, as shown in Figure 11, an insulating film 63 is formed on top of the insulating film 62. The insulating film 63 can be formed, for example, by plasma CVD. The insulating film 63 covers the drain wiring 52D and the insulating film 62.

[0046] Next, as shown in Figure 12, an opening 81 is formed in the substrate 11, penetrating the substrate 11. The opening 81 is formed so as to reach the semiconductor layer 12. The lower surface of the semiconductor layer 12 is exposed through the opening 81. For example, the substrate 11 is subjected to RIE (Reactive Emission) to form the opening 81. For example, a reactive gas containing F is used for the RIE of the substrate 11. During the RIE of the substrate 11 to form the opening 81, a mask is formed on the first surface 11A, and the mask is removed after etching of the substrate 11.

[0047] Next, as shown in Figure 13, RIE of the semiconductor layer 12 and semiconductor layer 21S is performed through the opening 81 to form an opening 50 in the substrate 11 and semiconductor layer 12 that penetrates the substrate 11 and semiconductor layer 12. The opening 50 includes the opening 81. The opening 50 is formed to reach the semiconductor layer 21S. The opening 50 has a bottom surface 71 and an inner wall surface 72. The inner wall surface 72 is connected to the bottom surface (first surface 11A) of the substrate 11, and the bottom surface 71 is connected to the inner wall surface 72. The bottom surface 71 is in the semiconductor layer 21S. The opening 50 may penetrate into the semiconductor layer 21S. During RIE of the semiconductor layer 12 and semiconductor layer 21S, a reactive gas containing Cl, for example, is used. The RIE of the semiconductor layer 12 and semiconductor layer 21S is stopped before the opening 50 penetrates the semiconductor layer 21S, for example, based on time control. After the formation of the opening 50, cleaning of the opening 50 is performed.

[0048] Next, the back electrode 51 is formed (see Figure 2). The back electrode 51 covers the first surface 11A and the inner wall surface 72, and contacts the semiconductor layer 21S at its bottom surface 71. In forming the back electrode 51, for example, a seed layer is formed by sputtering, and then a plating layer is formed on top of the seed layer.

[0049] In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

[0050] [Second example of a semiconductor device manufacturing method] Next, a second example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 14 to 15 are cross-sectional views showing a second example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0051] In the second example, the same procedure as in the first example is followed to form the semiconductor layers 21S and 21D (see Figures 4 to 6). Next, as shown in Figure 14, an opening 61G is formed in the insulating film 61.

[0052] Next, as shown in Figure 15, a drain electrode 30D is formed on the semiconductor layer 21D, and a gate electrode 22 is formed on the insulating film 61. For the formation of the drain electrode 30D and the gate electrode 22, the Ni layer and Au layer are grown by evaporation using a growth mask, and then the growth mask is removed. The drain electrode 30D and the gate electrode 22 may be formed simultaneously.

[0053] Subsequently, the same procedure as in the first example is followed for the formation of the insulating film 62 and subsequent processes (see Figures 9 to 13 and Figure 2).

[0054] In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

[0055] In the first embodiment, in both the first and second examples, the mask used for RIE of the substrate 11 may be removed after the removal of the opening 50. Alternatively, the opening 50 may be formed by performing RIE of the substrate 11 and RIE of the semiconductor layer 12 consecutively using a reactive gas containing F, and then the mask may be removed.

[0056] In the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, and the back electrode 51 and the semiconductor layer 21S are in ohmic contact. As a result, the electrical resistance between the semiconductor layer 12 containing 2DEG and the back electrode 51 is low. Crystal defects may be present in the semiconductor layer 21S, but the increase in electrical resistance between the back electrode 51 and the semiconductor layer 21S due to the crystal defects is slight. Therefore, the semiconductor device 100 has good stability in electrical resistance between the back electrode 51 and the semiconductor layer 12, and yield can be improved.

[0057] Here, the electrical resistance between the back electrode 51 and the semiconductor layer 12 will be further explained, in comparison with the reference example. Figure 16 is a cross-sectional view showing a semiconductor device according to the reference example. Figures 17 to 23 are cross-sectional views showing a method for manufacturing the semiconductor device according to the reference example.

[0058] As shown in Figure 16, the semiconductor device 100X according to the reference example has a source electrode 30S and a source wiring 52S. In a plan view, the source electrode 30S has a Ni layer 31S and an Au layer 32S inside the opening 61S. The Ni layer 31S is provided on the semiconductor layer 21S, and the Au layer 32S is provided on the Ni layer 31S. The Ni layer 31S is in direct contact with the semiconductor layer 21S. The insulating film 62 covers the source electrode 30S, and a plurality of openings 62S are formed in the insulating film 62. The openings 62S reach the source electrode 30S.

[0059] The source wiring 52S is located above the source electrode 30S. The source wiring 52S is provided on the insulating film 62. The source wiring 52S is in contact with the source electrode 30S through the opening 62S. The insulating film 63 covers the source wiring 52S.

[0060] Instead of an opening 50, through holes 50X are formed in the substrate 11, semiconductor layer 12, and semiconductor layer 21S, penetrating the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The through holes 50X reach the source electrode 30S. The back electrode 51 is formed on the lower surface of the source electrode 30S, the inner wall surface of the through holes 50X, and the lower surface (first surface 11A) of the substrate 11. The back electrode 51 contacts the source electrode 30S and covers the first surface 11A and the inner wall surface of the through holes 50X. The back electrode 51 and the source electrode 30S are electrically connected to each other, and the source electrode 30S and the semiconductor layer 21S are in ohmic contact.

[0061] The other components of semiconductor device 100X are the same as those of semiconductor device 100.

[0062] In the manufacturing method of semiconductor device 100X, the process up to the formation of semiconductor layers 21S and 21D is carried out using the same procedure as in the first example (see Figures 4 to 6). Next, as shown in Figure 17, the source electrode 30S is formed simultaneously with the formation of the drain electrode 30D.

[0063] Next, as shown in Figure 18, the process from forming the opening 61G to forming the insulating film 62 is carried out using the same procedure as in the first example.

[0064] Next, as shown in Figure 19, the opening 62S is formed simultaneously with the formation of the opening 62D, and the source wiring 52S is formed simultaneously with the formation of the drain wiring 52D.

[0065] Next, as shown in Figure 20, the process from forming the insulating film 63 to forming the opening 81 is carried out using the same procedure as in the first example.

[0066] Next, as shown in Figure 21, RIE is performed on the semiconductor layer 12 and semiconductor layer 21S through the opening 81 to form through-holes 50X in the substrate 11, semiconductor layer 12, and semiconductor layer 21S. In forming the through-holes 50X, the source electrode 30S is used as an etching stopper, and the through-holes 50X are formed so as to reach the source electrode 30S. The through-holes 50X may also penetrate into the source electrode 30S. During RIE of the semiconductor layer 12 and semiconductor layer 21S, a reactive gas containing Cl, for example, is used. After forming the through-holes 50X, the inside of the through-holes 50X is cleaned.

[0067] Next, the back electrode 51 is formed (see Figure 16). In this way, the semiconductor device 100X according to the reference example can be manufactured.

[0068] In semiconductor device 100X, the through-hole 50X reaches the source electrode 30S, and the source electrode 30S and the semiconductor layer 21S make ohmic contact. However, as shown in Figure 22, if crystal defects 89 exist in the semiconductor layer 12 and the semiconductor layer 21S, when the mask used for RIE of the substrate 11 is removed, the material used to remove the mask may reach the source electrode 30S through the crystal defects 89, causing a portion of the source electrode 30S to be lost. A portion of the source electrode 30S may also be lost during cleaning after the formation of the through-hole 50X. Therefore, as shown in Figure 23, a gap 30X may exist between the source electrode 30S and the semiconductor layer 21S even after the formation of the back electrode 51. If a gap 30X exists, the contact resistance between the source electrode 30S and the semiconductor layer 21S increases, and the yield decreases. On the other hand, in the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, and the back electrode 51 and the semiconductor layer 21S make ohmic contact. Therefore, even if crystal defects 89 are present, the increase in contact resistance as in the reference example does not occur, and the yield can be improved.

[0069] Although the back electrode 51 may contact the semiconductor layer 21S on the inner wall surface of the through-hole 50X of the semiconductor device 100X, the contact area is extremely small. Furthermore, etching residue generated during the etching of the semiconductor layer 12 and semiconductor layer 21S may be present on the inner wall surface of the through-hole 50X. Therefore, even if the back electrode 51 contacts the semiconductor layer 21S on the inner wall surface of the through-hole 50X, this contact does not contribute much to reducing contact resistance. Similarly, in the semiconductor device 100, even if the back electrode 51 contacts the semiconductor layer 21S on the inner wall surface 72 of the opening 50, this contact does not contribute much to reducing contact resistance. However, in the semiconductor device 100, the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, thus reducing contact resistance.

[0070] The thickness of the semiconductor layer 21S is, for example, 20 nm to 1000 nm, and may be 150 nm to 400 nm. If the thickness of the semiconductor layer 21S is 20 nm or more, the RIE of the semiconductor layer 12 and semiconductor layer 21S is more likely to stop before the aperture 50 penetrates the semiconductor layer 21S. If the thickness of the semiconductor layer 21S is 150 nm or more, the RIE of the semiconductor layer 12 and semiconductor layer 21S is more likely to stop before the aperture 50 penetrates the semiconductor layer 21S. If the thickness of the semiconductor layer 21S is 1000 nm or less, the time required for the formation of the recess 13S and the semiconductor layer 21S is more likely to be shortened. If the thickness of the semiconductor layer 21S is 400 nm or less, the time required for the formation of the recess 13S and the semiconductor layer 21S is more likely to be shortened. The thickness of the semiconductor layer 21S can be measured using a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0071] Because the semiconductor layer 21S is a GaN layer, it is easy to obtain low electrical resistance in the semiconductor layer 21S.

[0072] The higher carrier density in semiconductor layers 21S and 21D compared to semiconductor layer 12 makes it easier to reduce the electrical resistance of the semiconductor device 100. Specifically, it makes it easier to reduce the electrical resistance between the back electrode 51 and the drain wiring 52D.

[0073] The semiconductor layer 21S is 1.0 × 10 19 cm -3 It may contain n-type impurity atoms at the above concentrations, 1.0 × 10 20 cm -3 The semiconductor layer 21S may contain n-type impurity atoms at the above concentrations. The higher the concentration of n-type impurity atoms in the semiconductor layer 21S, the easier it is to obtain ohmic contact with the back electrode 51. Similarly, the semiconductor layer 21D may contain 1.0 × 10⁻⁶ impurity atoms. 19 cm -3 It may contain n-type impurity atoms at the above concentrations, 1.0 × 10 20 cm -3The semiconductor layer 21D may contain n-type impurity atoms at the above concentrations. The higher the concentration of n-type impurity atoms in the semiconductor layer 21D, the easier it is to obtain ohmic contact with the drain electrode 30D. The concentration of impurity atoms can be measured by secondary ion mass spectrometry (SIMS).

[0074] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in that it has a source electrode and source wiring.

[0075] [Structure of a semiconductor device] The structure of the semiconductor device according to the second embodiment will now be described. Figure 24 is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device according to the second embodiment. Figure 25 is a cross-sectional view showing the semiconductor device according to the second embodiment. Figure 25 corresponds to a cross-sectional view along the line XXV-XXV in Figure 24.

[0076] As shown in Figures 24 and 25, the semiconductor device 200 according to the second embodiment has, in addition to the configuration of the semiconductor device 100, a source electrode 30S and a source wiring 52S. Multiple source wirings 52S may be connected to each other. The configuration of the source electrode 30S, insulating film 62 and source wiring 52S is the same as that of the semiconductor device 100X according to the reference example. The source electrode 30S is an example of a second metal layer.

[0077] The other components of the semiconductor device 200 are the same as those of the semiconductor device 100.

[0078] [Manufacturing method for semiconductor devices] When manufacturing the semiconductor device 200 according to the second embodiment, the source electrode 30S and source wiring 52S are formed using the same procedure as in the reference example. Furthermore, the opening 81 and the opening 50 are formed using the same procedure as in the first embodiment. In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

[0079] The yield can be improved in the second embodiment as in the first embodiment. As in the reference example, defects in the source electrode 30S may occur, but defects in the source electrode 30S do not affect the contact resistance. This is because the back electrode 51 contacts the semiconductor layer 21S at the bottom surface 71 of the opening 50, and the back electrode 51 and the semiconductor layer 21S make ohmic contact.

[0080] Furthermore, in the semiconductor device 200 according to the second embodiment, characteristic testing can be performed using the source wiring 52S. For example, characteristic testing can be performed before the formation of the back surface electrode 51.

[0081] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0082] 11 circuit boards 11A 1st page 11B 2nd side 12 Semiconductor Layers 12C 3rd page 12D 4th side 13D, 13S recess 15 Gate Common Connection Section 21D, 21S semiconductor layer 22 Grid cells 26 Conduction band 27 valence band 30D drain electrode 30S Source Electrode 30X gap 31D, 31S Ni layer 32D, 32S Au layer 50, 61D, 61G, 61S, 62D, 62S, 81 opening 50X through hole 51 Backside electrode 52D Drain Wiring 52S Source Wiring 55 Drain Pad 61, 62, 63 Insulating film 71 Bottom 72 Interior wall surface 89 Crystal defects 100, 100X, 200 Semiconductor Equipment

Claims

1. A substrate having a first surface and a second surface opposite to the first surface, A first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, A second nitride semiconductor layer provided in the recess, It has, An opening is formed in the substrate and the first nitride semiconductor layer, penetrating the substrate and the first nitride semiconductor layer, reaching the second nitride semiconductor layer, and having a bottom surface in the second nitride semiconductor layer. The first metal layer covers the first surface and the inner wall surface of the opening, and has a bottom surface that contacts the second nitride semiconductor layer. The second nitride semiconductor layer is 1.0 × 10 １８ cm －３ A semiconductor device containing impurity atoms at the above concentration.

2. The semiconductor device according to claim 1, wherein the thickness of the second nitride semiconductor layer is 20 nm or more and 1000 nm or less.

3. The semiconductor device according to claim 1 or claim 2, wherein the second nitride semiconductor layer is a gallium nitride layer.

4. The semiconductor device according to claim 1 or claim 2, wherein in the second nitride semiconductor layer, the Fermi level is higher than the energy of the lower end of the conduction band.

5. The semiconductor device according to claim 1 or claim 2, wherein the carrier density in the second nitride semiconductor layer is higher than the carrier density in the first nitride semiconductor layer.

6. The second metal layer is provided on the second nitride semiconductor layer, The semiconductor device according to claim 1 or claim 2, wherein the second nitride semiconductor layer is located between the first metal layer and the second metal layer.

7. A step of forming a first nitride semiconductor layer on a substrate having a first surface and a second surface opposite to the first surface, the layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface. The process of forming a recess on the aforementioned fourth surface, The process of forming a second nitride semiconductor layer in the recess, A step of forming an opening in the substrate and the first nitride semiconductor layer that penetrates the substrate and the first nitride semiconductor layer, reaches the second nitride semiconductor layer, and has a bottom surface in the second nitride semiconductor layer, A step of forming a first metal layer that covers the first surface and the inner wall surface of the opening and contacts the second nitride semiconductor layer at the bottom surface, It has, The second nitride semiconductor layer is 1.0 × 10 １８ cm －３ A method for manufacturing a semiconductor device containing impurity atoms at the above concentration.

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